H EE GEN FR ALO CAT93C86 (Die Rev. C) 16K-Bit Microwire Serial EEPROM LE A D F R E ETM FEATURES ■ High speed operation: 3MHz ■ 1,000,000 Program/erase cycles ■ Low power CMOS technology ■ 100 year data retention ■ 1.8 to 6.0 volt operation ■ Commercial, industrial and automotive temperature ranges ■ Selectable x8 or x16 memory organization ■ Self-timed write cycle with auto-clear ■ Sequential read ■ Hardware and software write protection ■ Program enable (PE) pin ■ Power-up inadvertant write protection ■ “Green” package option available DESCRIPTION The CAT93C86 is a 16K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C86 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8-pad TDFN packages. PIN CONFIGURATION FUNCTIONAL SYMBOL CS SK DI DO 1 2 3 4 8 7 6 5 VCC SOIC Package (J,W) DIP Package (P, L) VCC PE ORG GND 1 2 3 4 PE VCC CS SK 8 7 6 5 ORG GND DO DI ORG DI CS DO SK PE SOIC Package (S,V) CS SK DI DO 1 2 3 4 8 7 6 5 SOIC Package (K,X) VCC PE ORG GND CS SK DI DO 1 2 3 4 TDFN Package (RD4, ZD4) CS SK DI DO 1 8 2 7 3 6 4 5 Top View VCC PE ORG GND 8 7 6 5 GND VCC PE ORG GND PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +1.8 to 5.5V Power Supply GND Ground ORG Memory Organization PE Program Enable Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice. Doc. No. 1091, Rev. M CAT93C86 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias .................. -55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ........................ -65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............. -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min NEND(3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Typ Max Cycles/Byte Units TDR(3) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(3)(4) Latch-Up JEDEC Standard 17 100 mA D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Symbol Parameter Test Conditions ICC1 Power Supply Current (Write) ICC2 Min Typ Max Units fSK = 1MHz VCC = 5.0V 3 mA Power Supply Current (Read) fSK = 1MHz VCC = 5.0V 500 µA ISB1 Power Supply Current (Standby) (x8 Mode) CS = 0V ORG=GND 10 µA ISB2 Power Supply Current (Standby) (x16Mode) CS=0V ORG=Float or VCC 10 µA ILI Input Leakage Current VIN = 0V to VCC 1 µA ILO Output Leakage Current (Including ORG pin) VOUT = 0V to VCC, CS = 0V 1 µA VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V VIH2 Input High Voltage 1.8V ≤ VCC < 4.5V VCC x 0.7 VCC+1 V VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V IOL = 2.1mA 0.4 V VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V IOH = -400µA VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V IOL = 1mA VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V IOH = -100µA 0 2.4 V 0.2 VCC - 0.2 V V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Doc. No. 1091, Rev. M 2 CAT93C86 PIN CAPACITANCE Symbol COUT Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) (1) CIN(1) Min Typ Max Units VOUT=0V 5 pF VIN=0V 5 pF INSTRUCTION SET Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A10-A0 A9-A0 Read Address AN– A0 ERASE 1 11 A10-A0 A9-A0 Clear Address AN– A0 WRITE 1 01 A10-A0 A9-A0 EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write Enable EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Write Disable ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Clear All Addresses WRAL 1 00 01XXXXXXXXX 01XXXXXXXX x8 x16 D7-D0 Comments D15-D0 Write Address AN– A0 D7-D0 D15-D0 Write All Addresses A.C. CHARACTERISTICS Limits VCC = 1.8V-6V Test Conditions Min Max VCC = 2.5V-6V Min Max VCC = 4.5V-5.5V Symbol Parameter Min Max Units tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns tDIS DI Setup Time 200 100 50 ns tDIH DI Hold Time 200 100 50 ns tPD1 Output Delay to 1 tPD0 Output Delay to 0 tHZ(1) Output Delay to High-Z tEW Program/Erase Pulse Width tCSMIN Minimum CS Low Time 1 0.5 0.15 µs tSKHI Minimum SK High Time 1 0.5 0.15 µs tSKLOW Minimum SK Low Time 1 0.5 0.15 µs tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 1 0.5 0.15 µs CL = 100pF 1 0.5 0.15 µs (3) 400 200 100 ns 5 5 5 ms 1 DC 3 500 0.5 DC 1000 DC 0.1 µs 3000 kHz Doc. No. 1091, Rev. M CAT93C86 POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Max 1 1 ≤ 50ns 0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC Units ms ms 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 4.5V 1.8V ≤ VCC ≤ 4.5V NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in “AC Test Conditions” table. DEVICE OPERATION The CAT93C86 is a 16,384-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C86 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 14-bit instructions control the reading, writing and erase operations of the device. The CAT93C86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Enabled mode. For Write Enable and Write Disable instruction PE=don’t care. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Since this device features AutoClear before write, it is NOT necessary to erase a memory location before it is written into. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Note: The Write, Erase, Write all and Erase all instructions require PE=1. If PE is left floating, 93C86 is in Program Doc. No. 1091, Rev. M 4 CAT93C86 Figure 1. Sychronous Data Timing tSKLOW tSKHI tCSH SK tDIS tDIH VALID DI VALID tCSS CS tDIS tPD0,tPD1 DO tCSMIN DATA VALID Figure 2. Read Instruction Timing SK 1 1 1 1 1 AN AN–1 1 1 1 1 1 1 1 1 1 1 CS Don't Care DI 1 1 A0 0 HIGH-Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D 7 . . . D0 Address + 2 D15 . . . D0 or D 7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Write Instruction Timing SK tCSMIN AN DI 1 0 AN-1 A0 DN D0 1 tSV DO STANDBY STATUS VERIFY CS tHZ BUSY HIGH-Z READY HIGH-Z tEW 5 Doc. No. 1091, Rev. M CAT93C86 Erase Erase All Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Erase/Write Enable and Disable Write All The CAT93C86 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C86 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Figure 4. Erase Instruction Timing SK STATUS VERIFY CS AN DI 1 1 tCS A0 AN-1 STANDBY 1 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW Doc. No. 1091, Rev. M 6 CAT93C86 Figure 5. EWEN/EWDS Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE=11 DISABLE=00 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCS DI 1 0 0 0 1 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY STANDBY tCSMIN DI 1 0 0 0 DN 1 D0 tSV tHZ DO BUSY READY HIGH-Z tEW 7 Doc. No. 1091, Rev. M CAT93C86 ORDERING INFORMATION Prefix CAT Device # 93C86 Optional Company ID Product Number Suffix S I Temperature Range Blank = Commercial (0°C - 70°C) I = Industrial (-40°C - 85°C) A = Automotive (-40°C - 105°C) E = Extended (-40°C to + 125°C) Package P = PDIP S = SOIC (JEDEC) J = SOIC (JEDEC) K = SOIC (EIAJ) U = TSSOP RD4 = TDFN (3x3mm) ZD4 = TDFN (3x3mm, Lead free, Halogen free) L = PDIP (Lead free, Halogen free) V = SOIC, JEDEC (Lead free, Halogen free) W= SOIC, JEDEC (Lead free, Halogen free) X = SOIC, EIAJ (Lead free, Halogen free) Y = TSSOP (Lead free, Halogen free) -1.8 TE13 Rev C (2) Tape & Reel Die Revision Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V) Notes: (1) The device used in the above example is a 93C86SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWC.) For additional information, please contact your Catalyst sales office. Doc. No. 1091, Rev. M 8 REVISION HISTORY Date 05/14/04 Revision Comments L New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and CAT93C86 have been separtated into single data sheets Add Die Revision ID Letter Update Features Update Description Update Pin Condition Add Functional Diagram Update Pin Function Update D.C. Operating Characteristics Update Pin Capacitance Update Instruction Set Update Device Operation Update Ordering Information 08/10/04 M Added TDFN Package pin out Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1091 M 8/10/04