Cypress CY2SSTU877LFI-XXT 1.8v, 500-mhz, 10-output jedec-compliant zero delay buffer Datasheet

CY2SSTU877
PRELIMINARY
1.8V, 500-MHz, 10-Output JEDEC-Compliant
Zero Delay Buffer
Features
• Operating frequency: 125 MHz to 500 MHz
• Supports DDRII SDRAM
• Ten differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 40 ps
• Very low skew: < 40 ps
This phase-locked loop (PLL) clock buffer is designed for a
VDD of 1.8V, an AVDD of 1.8V and differential data input and
output levels. Package options include a plastic 52-ball
VFBGA and a 40-pin MLF (QFN). The device is a zero delay
buffer that distributes a differential clock input pair (CK, CK#)
to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one
differential pair feedback clock outputs (FBOUT, FBOUT#).
The input clocks (CK, CK#), the feedback clocks (FBIN,
FBIN#), the LVCMOS (OE, OS), and the analog power input
(AVDD) control the clock outputs.
The PLL in the CY2SSTU877 clock driver uses the input
clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to
provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able
to track Spread Spectrum Clocking (SSC) for reduced EMI.
• Power management control input
• 1.8V operation
• Fully JEDEC-compliant
• 52-ball BGA and a 40-pin MLF (QFN)
Functional Description
The CY2SSTU877 is a high-performance, low-skew, low-jitter
zero delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTU877 generates ten
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTU877 features differential
feedback clock outputs and inputs. This allows the
CY2SSTU877 to be used as a zero delay buffer. When used
as a zero delay buffer in nested clock trees, the CY2SSTU877
locks onto the input reference and translates with near zero
delay to low-skew outputs.
When AVDD is grounded, the PLL is turned off and bypassed
for test purposes. When both clock signals (CK, CK#) are logic
low, the device will enter a low-power mode. An input logic
detection circuit on the differential inputs, independent from
the input buffers, will detect the logic low level and perform a
low-power state where all outputs, the feedback, and the PLL
are OFF. When the inputs transition from both being logic low
to being differential signals, the PLL will be turned back on, the
inputs and outputs will be enabled and the PLL will obtain
phase lock between the feedback clock pair (FBIN, FBIN#)
and the input clock pair (CK, CK#) within the specified stabilization time tL.
Pin Configuration
Block Diagram
52 BGA
1
2
3
4
5
6
A
Y1
Y0
Y0#
Y5#
Y5
Y6
B
Y1#
GND
GND
GND
GND
Y6#
C
Y2#
GND
NB
NB
GND
Y7#
D
Y2
VDDQ
VDDQ
VDDQ
OS
Y7
E
CK
VDDQ
NB
NB
VDDQ
FBIN
AVDD
GND
NB
NB
GND
FBOUT
J
Y3
GND
GND
GND
GND
Y8
K
Y3#
Y4#
Y4
Y9
Y5#
Y8#
40 39 38
•
3901 North First Street
35
34
33 32
31
Y0#
37 36
30
Y7#
29
Y7
28
VD D Q
27
FB IN
26
FB IN #
6
25
FB O U T#
AG N D
7
24
FB O U T
A VD D
8
23
VD D Q
VD DQ
GND
9
22
OE
18 19 20 21
OS
VD DQ
•
Y4#
Y3#
10 11 12 13
14 15
16
17
VDDQ
5
Y8
C LK #
40 Q FN
C Y 2S S T U 877
Y8#
4
Y9#
C LK
Y9
Y2
2
3
VDDQ
1
Y2#
Y4
VD DQ
Y3
Cypress Semiconductor Corporation
Document #: 38-07575 Rev. *B
VDDQ
H
Y6#
FBOUT#
Y6
FBIN#
VDDQ
Y5
OE
VDDQ
Y5#
NB
VDDQ
VDDQ
NB
VDDQ
Y0
VDDQ
Y1
CK#
AGND
Y1#
F
G
San Jose, CA 95134
•
408-943-2600
Revised January 19, 2005
PRELIMINARY
CY2SSTU877
Pin Description
Pin No.
(BGA)
QFN
Name
Description
G1
7
AGND
Ground for 1.8V analog supply
H1
8
AVDD
1.8V analog supply
E1, F1
4, 5
CLK, CLK#
Differential clock input with a (10K–100KΩ) pull-down resistor
E6, F6
27, 26
FBIN, FBIN#
Feedback differential clock input
H6, G6
24, 25
FBOUT, FBOUT#
Feedback differential clock output
B2, B3, B4, B5, C2, 10
C5, H2, H5, J2, J3,
J4, J5
GND
Ground
F5
22
OE
Output enable (ASYNC) for Y[0:9] and Y# [0:9]
D5
21
OS
Output Select (Tied to GND or VCC)
D2, D3, D4, E2, E5, 1, 6, 9, 15, 20, 23, 28, VDDQ
F2, G2, G3, G4, G5 31, 36
1.8V supply
A2, A1, D1, J1, K3,
A5, A6, D6, J6, K4,
Buffered output of input clock, CLK
38, 39, 3, 11, 14, 34, Y [0:9]
33, 29, 19, 16
A3, B1, C1, K1, K2, 37, 40, 2, 12, 13, 35, Y# [0:9]
A4, B6, C6, K6, K5 32, 30, 18, 17
Buffered output of input clock, CLK
Table 1. Function Table
Inputs
AVDD
OE
OS
GND
H
GND
H
GND
L
GND
L
VDD
L
VDD
L
VDD
H
VDD
H
VDD
X
X
X
X
X
Outputs
CLK
CLK#
Y
Y#
FBOUT
FBOUT#
X
L
X
H
H
L
L
H
H
L
H
Lz
L
H
L
Lz,Y7 Active
H
L
H
Lz
L
H
L
Lz,Y7 Active
X
L
H
L
X
H
L
H
L
L
Lz
Lz
H
H
PLL
H
L
H
Bypassed/Off
L
H
L
Bypassed/Off
Lz
L
H
Bypassed/Off
Lz,Y7# Active
H
L
Bypassed/Off
Lz
L
H
On
Lz,Y7# Active
H
L
On
H
L
H
On
L
H
L
On
Lz
Lz
Off
Reserved
Recommended Operating Conditions
Parameter
Description
Condition
Min.
Max.
Unit
TA (Ind.)
Ambient Operating Temp
–40
85
°C
TA (Com.)
Ambient Operating Temp
0
70
°C
VDD
Operating Voltage
1.7
1.9
V
Document #: 38-07575 Rev. *B
Page 2 of 9
PRELIMINARY
CY2SSTU877
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VIN
Input Voltage Range
–0.5
VDDQ + 0.5
V
VOUT
Output Voltage Range
–0.5
VDDQ + 0.5
V
TS
Storage Temperature
–65
150
°C
VCC
Supply Voltage Range
–0.5
2.5
V
IIK
Input Clamp Current
–50
50
mA
IOK
Output Clamp Current
–50
50
mA
IO
Continuous Output Current
–50
50
mA
Continuous Current through VDD/GND
–100
100
mA
DC Electrical Specifications
Parameter
Description
Conditions
VIX
Input Differential Crossing Voltage
VID DC
Input Differential Voltage (DC Values)
VID AC
Input Differential Voltage (AC Values)
VIL
Input Low Voltage
VIH
Input High Voltage
(OE, OS, CK, CK#)
VOL
Output Low Voltage
IOL = 100 µA
VOH
Output High Voltage
IOH = –100 µA
IOH
Output High Current
IOL
Output Low Current
VIK
Input Clamping Voltage
VOD
Output Differential Voltage
VOX
Output Differential Crossing Voltage
Min.
Max.
Unit
(VDDQ/2) – 0.15
(VDDQ/2) + 0.15
V
0.3
VDDQ + 0.4
V
0.6
(OE, OS, CK, CK#)
VDDQ + 0.4
V
0.35 * VDDQ
V
0.1
V
0.6
V
0.65 * VDDQ
V
IOL = 9 mA
VDDQ – 0.2
IOH = –9 mA
V
1.1
V
II = –18 mA
–9
mA
9
mA
–1.2
V
0.5
V
VDDQ/2 – 0.08
VDDQ/2 + 0.08
V
AC Electrical Specifications
Parameter
Description
SLR(O)
Output Slew Rate
SLR(I)
Input Slew Rate
Conditions
Y[0:9], Y#[0:9], FBOUT,
FBOUT#
CLK, CLK#, FBIN, FBIN#
OE
CIN
Input Capacitance
COUT
CIN(DELTA)
Min.
Max.
Unit
1.5
3
V/ns
1
4
0.5
(Input Capacitance of CK, CK#,
FBIN, FBIN#) Vi = VDDQ or
GND
Ci(delta) (CK, CK#, FBIN,
FBIN#) Vi = VDDQ or GND
2
V/ns
V/ns
3
pF
pF
–0.25
0.25
pF
AC Timing Specifications
Min.
Max.
Unit
FCLK
Parameter
Clock Frequency
Description
125
500
MHz
TDC
Duty Cycle
40
60
%
TLOCK
PLL Lock Time
–
10
µs
Tjitt (cc)
Cycle-to-cycle jitter
–30
30
ps
Tjit (Period)
Period Cycle-to-cycle jitter
–40
20
ps
Document #: 38-07575 Rev. *B
Conditions
Page 3 of 9
PRELIMINARY
CY2SSTU877
AC Timing Specifications (continued)
Parameter
Description
Conditions
Min.
Max.
Unit
–45
45
ps
Tjit (H-Period)
Half Period Cycle-to-cycle jitter
Above 270 MHz
Below 270 MHz
–70
70
ps
Td(0)
Static Phase Offset
Average 1000 cycles
–50
50
ps
Td(0)
Dynamic Phase Offset
TSKEW
Clock Skew
TR/TF
Rise/Fall Time
TODC
Output Duty Cycle
TOENB
Output Enable Time
OE to any Y/Y#
–
8
ns
TODIS
Output Disable Time
OE to any Y/Y#
–
8
ns
TPLH
Propagation Delay
(Y[0:9], Y#[0:9] @ 500 MHz)
–30
30
ps
–
25
ps
–
300
ps
49
51
%
8
ns
Figure 1. Test Loads for Timing Measurement #1
Figure 2. Test Loads for Timing Measurement #2
Document #: 38-07575 Rev. *B
Page 4 of 9
PRELIMINARY
CY2SSTU877
Figure 3. Cycle to Cycle Jitter
Figure 4. Period Jitter
Figure 5. Half Period Jitter
Document #: 38-07575 Rev. *B
Page 5 of 9
PRELIMINARY
CY2SSTU877
Figure 6. Static Phase Offset
Figure 7. Dynamic Phase Offset
Figure 8. Output Skew
Document #: 38-07575 Rev. *B
Page 6 of 9
PRELIMINARY
CY2SSTU877
Figure 9. Time Delay Between OE and Clock Output (Y, Y)
Figure 10. Input/Output Slew Rates
Ordering Information
Part Number
Package Type
Product Flow
Standard
CY2SSTU877LFC-XX
40-pin QFN
Commercial, 0° to 70°C
CY2SSTU877LFC-XXT
40-pin QFN – Tape and Reel
Commercial, 0° to 70°CC
CY2SSTU877BVC-XX
52-pin VFBGA
Commercial, 0° to 70°C
CY2SSTU877BVC-XXT
52-pin VFBGA– Tape and Reel
Commercial, 0° to 70°C
CY2SSTU877LFI-XX
40-pin QFN
Industrial, –40° to 85°C
CY2SSTU877LFI-XXT
40-pin QFN – Tape and Reel
Industrial, –40° to 85°C
CY2SSTU877BVI-XX
52-pin VFBGA
Industrial, –40° to 85°C
CY2SSTU877BVI-XXT
52-pin VFBGA– Tape and Reel
Industrial, –40° to 85°C
CY2SSTU877LFXC-XX
40-pin QFN
Commercial, 0° to 70°C
CY2SSTU877LFXC-XXT
40-pin QFN – Tape and Reel
Commercial, 0° to 70°CC
Lead-free
CY2SSTU877BVXC-XX
52-pin VFBGA
Commercial, 0° to 70°C
CY2SSTU877BVXC-XXT
52-pin VFBGA– Tape and Reel
Commercial, 0° to 70°C
CY2SSTU877LFXI-XX
40-pin QFN
Industrial, –40° to 85°C
CY2SSTU877LFXI-XXT
40-pin QFN – Tape and Reel
Industrial, –40° to 85°C
CY2SSTU877BVXI-XX
52-pin VFBGA
Industrial, –40° to 85°C
CY2SSTU877BVXI-XXT
52-pin VFBGA– Tape and Reel
Industrial, –40° to 85°C
Document #: 38-07575 Rev. *B
Page 7 of 9
PRELIMINARY
CY2SSTU877
Package Drawing
52 VFBGA 4.5 × 7.0 × 1.0 MM BV52A
TOP VIEW
BOTTOM VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(52X)
A1 CORNER
1
2
3
4
5
6
6
3
2
1
B
C
C
0.65
A
B
7.00±0.10
E
F
F
G
2.925
G
D
E
5.85
D
7.00±0.10
4
5
A
H
J
H
J
K
K
1.625
A
A
B
4.50±0.10
0.65
3.25
DIMENSION IN MM
REFERENCE JEDEC MO-225
SEATING PLANE
C
1.00 MAX
0.26 MAX.
4.50±0.10
0.15 C
0.21±0.05
0.25 C
0.55 MAX.
B
0.15(4X)
51-85192-**
40-lead QFN 6 x 6 MM LF40A
BOTTOM VIEW
SIDE VIEW
TOP VIEW
0.08[0.003]
C
1.00[0.039] MAX.
5.90[0.232]
6.10[0.240]
A
0.05[0.002] MAX.
0.80[0.031] MAX.
5.70[0.224]
5.80[0.228]
0.18[0.007]
0.28[0.011]
0.20[0.008] REF.
0.60[0.024]
DIA.
PIN1 ID
0.20[0.008] R.
N
N
1
1
2
2
0.45[0.018]
0.30[0.012]
0.50[0.020]
4.45[0.175]
4.55[0.179]
5.90[0.232]
6.10[0.240]
5.70[0.224]
5.80[0.228]
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
0°-12°
0.50[0.020]
C
SEATING
PLANE
0.24[0.009]
0.60[0.024]
(4X)
4.45[0.175]
4.55[0.179]
51-85190-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07575 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY2SSTU877
Document History Page
Document Title:CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
Document Number: 38-07575
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
129198
08/22/03
RGL
New Data Sheet
*A
204389
See ECN
RGL
Added more Information. Deleted 4 rows from the bottom of the Pin
description.
*B
310414
See ECN
RGL
Changed Advance Info. to Preliminary status
Added Lead-free devices
Document #: 38-07575 Rev. *B
Page 9 of 9
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