ICST ICS8304 Low skew, 1-to-4 lvcmos / lvttl fanout buffer Datasheet

ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8304 is a low skew, 1-to-4 Fanout
Buffer and a member of the HiPerClockS ™
HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8304 is characterized at
full 3.3V for input VDD, and mixed 3.3V and 2.5V
for output operating supply modes (VDDO). Guaranteed output and par t-to-par t skew character istics make the
ICS8304 ideal for those clock distribution applications
demanding well defined performance and repeatability.
• 4 LVCMOS / LVTTL outputs
ICS
• LVCMOS / LVTTL clock input
• Maximum output frequency: 200MHz
• Output skew: 45ps (maximum at 3.3V supply)
• Part-to-part skew: 500ps (maximum)
• Small 8 lead SOIC package saves board space
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• Lead-Free package available
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
VDDO
VDD
CLK
GND
Q1
1
2
3
4
8
7
6
5
Q3
Q2
Q1
Q0
CLK
8304AM
Q2
ICS8304
Q3
8-Lead SOIC, 150mil
3.9mm x 4.9mm, x 1.63mm package body
M Package
Top View
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1
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VDDO
Power
Type
Description
Output supply pin.
2
VDD
Power
3
CLK
Input
4
GND
Power
Power supply ground.
5
Q0
Output
Single clock output. LVCMOS / LVTTL interface levels.
6
Q1
Output
Single clock output. LVCMOS / LVTTL interface levels.
7
Q2
Output
Single clock output. LVCMOS / LVTTL interface levels.
8
Q3
Output
Single clock output. LVCMOS / LVTTL interface levels.
Core supply pin.
Pulldown
LVCMOS / LVTTL clock input.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
RPULLDOWN
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
ROUT
Output Impedance
CPD
8304AM
Test Conditions
Minimum
Typical
Maximum
4
VDD, VDDO = 3.465V
pF
15
51
5
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2
7
Units
pF
KΩ
12
Ω
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
VDDO
Output Supply Voltage
3.465
V
IDD
Power Supply Current
15
mA
IDDO
Output Supply Current
8
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
Test Conditions
Minimum
Typical
2
Units
VDD + 0.3
V
VIL
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
µA
Refer to NOTE 1
2. 6
V
IOH = -16mA
2.9
V
IOH = -100uA
3
VOH
VOL
Output High Voltage
Output Low Voltage
-0.3
Maximum
1.3
V
150
µA
V
Refer to NOTE 1
0.5
V
IOL = 16mA
0.25
V
IOL = 100uA
0.15
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit".
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
15
mA
IDDO
Output Supply Current
8
mA
8304AM
Test Conditions
Minimum
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3
Typical
Maximum
Units
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
Test Conditions
Minimum
Typical
Maximum
Units
VDD + 0.3
V
2
VIL
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V
-0.3
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
VOH
Output High Voltage; NOTE 1
1.3
V
150
µA
-5
µA
2.1
V
Output Low Voltage; NOTE 1
VOL
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section,
"3.3V/2.5V Output Load Test Circuit".
0.5
V
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
Test Conditions
Minimum
IJ 166MHz
2.0
166MHz < f ≤ 189.5MHz
2.0
Typical
Maximum Output Frequency
Propagation Delay, Low-to-High; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR
Output Rise Time
30% to 70%
tF
Output Fall Time
30% to 70%
ƒ = 133MHz
Maximum
Units
200
MHz
3.3
ns
3.4
ns
45
ps
500
ps
250
500
ps
250
500
ps
60
%
Maximum
Units
odc
Output Duty Cycle
f ≤ 189.5MHz
40
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
Test Conditions
Minimum
Typical
189.5
MHz
IJ 166MHz
2.3
3.7
ns
166MHz < f ≤ 189.5MHz
2.15
3.55
ns
Maximum Output Frequency
Propagation Delay, Low-to-High; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR
Output Rise Time
30% to 70%
tF
Output Fall Time
30% to 70%
ƒ = 133MHz
60
ps
500
ps
250
500
ps
250
500
ps
60
%
odc
Output Duty Cycle
f ≤ 189.5MHz
40
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM
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4
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
2.05V±5% 1.25V±5%
SCOPE
VDD,
VDDO
VDDO
Qx
LVCMOS
SCOPE
VDD
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1
V
DD
Qx
Qx
2
PART 2
V
DD
2
V
DD
DD
Qy
V
Qy
2
t sk(o)
OUTPUT SKEW
2
t sk(pp)
PART-TO-PART SKEW
V
70%
DDO
70%
2
Q0:Q3
Clock
Outputs
Pulse Width
30%
30%
tR
t
tF
odc =
PERIOD
t PW
t PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
2
CLK
VDDO
2
Q0:Q3
t
PD
PROPAGATION DELAY
8304AM
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5
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 5.
θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
200
500
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8304 is: 416
8304AM
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6
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - SUFFIX M
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
FOR
8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
SYMBOL
Millimeters
MINIMUN
N
MAXIMUM
8
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
e
H
4.00
1.27 BASIC
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
8304AM
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7
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
Marking
Package
ICS8304AM
8304AM
8 lead SOIC
ICS8304AMT
8304AM
8 lead SOIC on Tape and Reel
ICS8304AMLN
8304AMLN
ICS8304AMLNT
8304AMLN
ICS8304AMLF
8304AMLF
ICS8304AMLFT
8304AMLF
8 lead SOIC, "Lead Free/Annealed"
8 lead SOIC, "Lead Free/Annealed"
on Tape and Reel
8 lead SOIC, "Lead Free"
8 lead SOIC, "Lead Free"
on Tape and Reel
Count
Temperature
96 per tube
2500
0°C to 70°C
96 per tube
2500
0°C to 70°C
0°C to 70°C
96 per tube
2500
0°C to 70°C
0°C to 70°C
0°C to 70°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8304AM
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8
REV. F SEPTEMBER 13, 2004
ICS8304
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
LVCMOS / LVTTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
B
C
C
D
Table
T4A
Page
3
T4B
4
T4A
3
T4B
4
T7
10
T3B
3
T1
T2
1
2
2
E
T3A & T3C
T7
3&4
8
1
T4A
4
F
F
8304AM
T4B
4
T7
8
•
•
•
•
•
Description of Change
Revised tpLH (Propagation Delay) row from 2.3 Min. to 2 Min.
Deleted tpHL row.
Revised tsk(o) (Output Skew) row from 35 Max. to 80 Max.
Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max.
General note changed from "...measured at 166MHz..." to
" ...measured at 150MHz..."
Date
12/4/01
• Revised tpLH (Propagation Delay) row from 2.6 Min. to 2.3 Min.
• Deleted tpHL row.
• Revised tsk(o) (Output Skew) row from 35 Max. to 85 Max.
• Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max.
• General note changed from "...measured at 166MHz..." to
" ...measured at 150MHz..."
• In AC table, revised tsk(o) row from 80ps Max. to 45ps Max.
Added f = 133MHz in Test Conditions column.
• In odc row, deleted test conditions.
• In notes, changed 150MHz to fMAX.
• In AC table, revised tsk(o) row from 80ps Max. to 60ps Max.
Added f = 133MHz in Test Conditions column.
• In odc row, deleted test conditions
• In notes, changed 150MHz to fMAX.
In the Ordering Information table, Marking column, revised marking to read
8304AM from ICS8304AM.
LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions
to VOH and VOL rows.
• Pin Assignment - adjusted dimensions.
• Pin Descriptions - changed VDD description to Core supply pin.
• Pin Characteristics - changed CIN max 4pF to typical 4pF.
Deleted RPULLUP row.
Added 5Ω min. and 12Ω max. to ROUT.
• Power Supply tables - changed VDD parameter from Power to Core.
• Ordering Information table - added "Lead Free/Annealed" marking.
Updated format throughout the data sheet.
Featues section, changed Maximum output frequency bullet from 166MHz to
200MHz.
3.3V AC Table - changed 166MHz max. to 200MHz max.
Added another line for Propagation Delay.
Changed test conditions in Output Duty Cycle from 166MHz to 189.5MHz.
3.3V AC Table - changed 166MHz max. to 189.5MHz max.
Added another line for Propagation Delay.
Changed test conditions in Output Duty Cycle from 166MHz to 189.5MH
• Ordering Information table - added "Lead Free" marking.
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9
12/11/01
3/11/02
4/4/02
4/13/04
6/1/04
9/13/04
REV. F SEPTEMBER 13, 2004