DG444, DG445 ® Data Sheet November 20, 2006 Monolithic, Quad SPST, CMOS Analog Switches The DG444 and DG445 monolithic CMOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole single throw (SPST) analog switches and TTL and CMOS compatible digital inputs. FN3586.9 Features • ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 85Ω • Low Power Consumption (PD) . . . . . . . . . . . . . . . <35μW • Fast Switching Action - tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns - tOFF (Max, DG444) . . . . . . . . . . . . . . . . . . . . . . . 140ns These switches feature lower analog ON resistance (<85Ω) and faster switch time (tON <250ns) compared to the DG211 and DG212. Charge injection has been reduced, simplifying sample and hold applications. • Low Charge Injection The improvements in the DG444 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling ±20V signals when operating with ±20V power supplies. • Single or Split Supply Operation The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. The switches in the DG444 and DG445 are identical, differing only in the polarity of the selection logic. • Upgrade from DG211, DG212 • TTL, CMOS Compatible • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Audio Switching • Battery Operated Systems • Data Acquisition • Hi-Rel Systems • Sample and Hold Circuits • Communication Systems Pinout • Automatic Test Equipment DG444, DG445 (16 LD SOIC, TSSOP) TOP VIEW Ordering Information PART NUMBER PART TEMP. MARKING RANGE (°C) PKG. DWG. # IN1 1 16 IN2 D1 2 15 D2 DG444DY* DG444DY -40 to 85 16 Ld SOIC M16.15 S1 3 14 S2 -40 to 85 V- 16 Ld SOIC (Pb-free) M16.15 13 V+ DG444DYZ* (Note) DG444DYZ 4 GND 5 12 VL DG444DVZ* (Note) DG444DVZ -40 to 85 16 Ld TSSOP M16.173 (Pb-free) S4 6 11 S3 DG445DY* DG445DY -40 to 85 16 Ld SOIC M16.15 D4 7 10 D3 -40 to 85 9 IN3 16 Ld SOIC (Pb-free) M16.15 8 DG445DYZ* (Note) DG445DYZ IN4 DG445DVZ* (Note) DG445DVZ -40 to 85 16 Ld TSSOP M16.173 (Pb-free) PACKAGE *Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 1999, 2003, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. DG444, DG445 Functional Diagrams Pin Descriptions DG444 DG445 S1 IN1 S1 IN1 D1 S2 IN2 D1 S2 IN2 D2 S3 IN3 D2 S3 IN3 D3 S4 IN4 D3 S4 IN4 D4 D4 SWITCHES SHOWN FOR LOGIC “1” INPUT TRUTH TABLE LOGIC VIN DG444 DG445 0 ≤0.8V ON OFF 1 ≥2.4V OFF ON Schematic Diagram PIN SYMBOL DESCRIPTION 1 IN1 Logic Control for Switch 1 2 D1 Drain (Output) Terminal for Switch 1 3 S1 Source (Input) Terminal for Switch 1 4 V- Negative Power Supply Terminal 5 GND 6 S4 Source (Input) Terminal for Switch 4 7 D4 Drain (Output) Terminal for Switch 4 8 IN4 Logic Control for Switch 4 9 IN3 Logic Control for Switch 3 10 D3 Drain (Output) Terminal for Switch 3 11 S3 Source (Input) Terminal for Switch 3 12 VL Logic Reference Voltage 13 V+ Positive Power Supply Terminal (Substrate) 14 S2 Source (Input) Terminal for Switch 2 15 D2 Drain (Output) Terminal for Switch 2 16 IN2 Logic Control for Switch 2 Ground Terminal (Logic Common) (One Channel) V+ S VL VV+ INX D GND V- 2 FN3586.9 November 20, 2006 DG444, DG445 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) + 0.3V Digital Inputs, VS , VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA Thermal Resistance (Typical, Note 2) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Packages). . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C (SOIC and TSSOP- Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max) Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min) Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX , DX , or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) (NOTE 4) (NOTE 5) (NOTE 4) MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS RL = 1kΩ, CL = 35pF, VS = ±10V (Figure 1) Turn-ON Time, tON +25 - 120 250 ns DG444 +25 - 110 140 ns DG445 +25 - 160 210 ns Turn-OFF Time, tOFF Charge Injection, Q (Figure 2) CL = 1nF, VG = 0V, RG = 0Ω +25 - -1 - pC OFF Isolation (Figure 4) RL = 50Ω, CL = 5pF, f = 1MHz +25 - 60 - dB +25 - -100 - dB +25 - 4 - pF Drain OFF Capacitance, CD(OFF) +25 - 4 - pF Channel ON Capacitance, CD(ON) + CS(ON) +25 - 16 - pF Crosstalk (Channel-to-Channel) (Figure 3) Source OFF Capacitance, CS(OFF) f = 1MHz, VANALOG = 0 (Figure 5) DIGITAL INPUT CHARACTERISTICS Input Current VIN Low, IIL VIN Under Test = 0.8V, All Others = 2.4V Full -0.5 -0.00001 0.5 μA Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -0.5 0.00001 0.5 μA Full -15 - 15 V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) IS = 10mA, VD = ±8.5V, V+ = 13.5V, V- = -13.5V +25 - 50 85 Ω Full - - 100 Ω Source OFF Leakage Current, IS(OFF) V+ = 16.5V, V- = -16.5V, VD = ±15.5V, VS = 15.5V +25 -0.5 0.01 0.5 nA +85 -5 - 5 nA 3 FN3586.9 November 20, 2006 DG444, DG445 Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified (Continued) PARAMETER TEMP (°C) TEST CONDITIONS Drain OFF Leakage Current, ID(OFF) V+ = 16.5V, V- = -16.5V, VD = ±15.5V, VS = 15.5V Channel ON Leakage Current, ID(ON) + IS(ON) (NOTE 4) (NOTE 5) (NOTE 4) MIN TYP MAX UNITS +25 -0.5 0.01 0.5 nA +85 -5 - 5 nA V+ = 16.5V, V- = -16.5V, VS = VD , = ±15.5V +25 -0.5 0.08 0.5 nA +85 -10 - 10 nA V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V +25 - 0.001 1 μA +85 - - 5 μA +25 -1 -0.0001 - μA +85 -5 - - μA +25 - 0.001 1 μA +85 - - 5 μA +25 -1 -0.001 - μA +85 -5 - - μA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, I- Logic Supply Current, IL Ground Current, IGND Electrical Specifications (Single Supply) Test Conditions: V+ = 12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified TEMP (°C) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS RL = 1kΩ, CL = 35pF, VS = 8V (Figure 1) +25 - 300 450 ns +25 - 60 200 ns CL = 1nF, VG = 6V, RG = 0Ω +25 - 2 - pC Full 0 - 12 V IS = -10mA, VD = 3V, 8V V+ = 10.8V, VL = 5.25V +25 - 100 160 Ω Full - - 200 Ω V+ = 13.2V, VIN = 0V or 5V, VL = 5.25V +25 - 0.001 1 μA Full - - 5 μA +25 -1 -0.0001 - μA Full -5 - - μA +25 - 0.001 1 μA Full - - 5 μA +25 -1 -0.001 - μA Full -5 - - μA PARAMETER TEST CONDITIONS DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q (Figure 2) ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, I- Logic Supply Current, IL Ground Current, IGND NOTES: 3. VIN = input voltage to perform proper function. 4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. 4 FN3586.9 November 20, 2006 DG444, DG445 Test Circuits and Waveforms VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. VL tr < 20ns tf < 20ns 3V LOGIC INPUT 50% SWITCH INPUT 0V SWITCH INPUT VS VO D1 S1 VO IN1 tOFF SWITCH OUTPUT V+ 80% 80% CL RL LOGIC INPUT 3V GND V- 0V tON NOTE: Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for Channels 2, 3 and 4. For load conditions, see Specifications. CL includes fixture and stray capacitance. RL V O = V S -----------------------------------R L + r DS ( ON ) FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES SWITCH OUTPUT VL ΔVO INX (DG444) OFF RG OFF ON V+ D1 VO VG CL V- INX (DG445) VIN = 3V ON Q = ΔVO x CL OFF OFF GND FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ +15V +15V C C SIGNAL GENERATOR 10dBm SIGNAL GENERATOR 10dBm VS VD 50Ω 0V, 2.4V IN1 IN2 0V, 2.4V VD ANALYZER RL NC C GND V-15V FIGURE 3. CROSSTALK TEST CIRCUIT 5 V+ VS INX 0V, 2.4V VD ANALYZER RL GND V- C -15V FIGURE 4. OFF ISOLATION TEST CIRCUIT FN3586.9 November 20, 2006 DG444, DG445 Test Circuits and Waveforms (Continued) +15V C V+ VS INX 0V, 2.4V IMPEDANCE ANALYZER VD f = 1MHz C V- GND -15V FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT Application Information VIN FET INPUT OP AMP 3 2 +5V 12 2 +15V 7 6 4 +15V -15V 13 + VOUT - V+ VL +5V +15V VL +15V V+ 1/ DG444 4 +15V VOUT 3 +5V GAIN1 AV = 1 1 R1 90kΩ 15 GAIN2 AV = 10 0V 10kΩ GND V- 16 R2 5kΩ 11 9 R3 4kΩ FIGURE 7. LEVEL SHIFTER 6 7 GAIN4 AV = 100 VIN 14 10 GAIN3 AV = 20 0V 8 R4 1kΩ DG444 OR DG445 VGND 4 -15V 5 GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE, OP AMP OFFSET AND CMRR WILL LIMIT ACCURACY OF CIRCUIT R1 + R2 + R3 + R4 V OUT ---------------- = ------------------------------------------------ = 100 R4 V IN WITH SW4 CLOSED FIGURE 6. PRECISION WEIGHTED RESISTOR PROGRAMMABLE GAIN AMPLIFIER 6 FN3586.9 November 20, 2006 DG444, DG445 Typical Performance Curves 105 104 4 IL , I+, I-, IGND (nA) 103 VIN (V) 3 VL = 7V 2 VL = 5V I+, IGND 102 10 -(I-) 1 0.1 1 0.01 0 0 4 8 12 SUPPLY VOLTAGE (±V) 16 20 IL 0.001 -55 FIGURE 8. SWITCHING THRESHOLD vs SUPPLY VOLTAGE 0 50 TEMPERATURE (°C) 100 125 FIGURE 9. SUPPLY CURRENT vs TEMPERATURE 105 80 V+ = +15V V- = -15V 70 104 60 rDS(ON) (Ω) IIN (pA) 103 102 10 50 +85°C 40 +25°C 30 0°C -40°C 20 1 10 0.1 -55 0 50 100 0 -15 125 0 VD (V) TEMPERATURE (°C) FIGURE 10. INPUT CURRENT vs TEMPERATURE 15 FIGURE 11. rDS(ON) vs VD AND TEMPERATURE 50 140 120 40 CROSSTALK V+ = +15V V- = -15V 30 100 20 Q (pC) (dB) 80 OFF ISOLATION 60 10 CL = 10nF CL = 1nF 0 40 -10 20 0 100 V+ = +15V V- = -15V PGEN = 10dBm 1k -20 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 12. CROSSTALK REJECTION AND OFF ISOLATION vs FREQUENCY 7 -30 -10 0 VS (V) 10 FIGURE 13. CHARGE INJECTION vs SOURCE VOLTAGE FN3586.9 November 20, 2006 DG444, DG445 Typical Performance Curves (Continued) 25 20 V+ = +15V V- = -15V IS(OFF) , ID(OFF) 0 20 -20 IS , ID (pA) CS , D (pF) CS(ON) + CD(ON) 15 10 -40 IS(ON) + ID(ON) -60 V+ = +15V V- = -15V FOR I(OFF) , VD = -VS CS(OFF) , CD(OFF) 5 -80 0 -15 -10 -5 0 VA (V) 5 10 -100 -15 15 FIGURE 14. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE -10 -5 0 VS , VD (V) 5 10 15 FIGURE 15. LEAKAGE CURRENTS vs ANALOG VOLTAGE 150 V+ = +15V, V- = -15V VL = 5V 160 V+ = +15V V- = -15V 140 tON 100 tON tON, tOFF (ns) tON, tOFF (ns) 120 100 80 tOFF 50 tOFF 60 40 0 20 2 3 4 2 5 3 VIN (V) 4 5 VIN (V) FIGURE 16. SWITCHING TIME vs INPUT VOLTAGE (DG444) FIGURE 17. SWITCHING TIME vs INPUT VOLTAGE (DG445) 160 160 VL = 5V 140 140 tOFF tON 120 tON, tOFF (ns) tON, tOFF (ns) 120 100 80 60 100 80 tON 60 tOFF 40 40 20 20 10 12 14 16 18 SUPPLY VOLTAGE (±V) 20 22 FIGURE 18. SWITCHING TIME vs POWER SUPPLY VOLTAGE (DG444) 8 10 12 14 16 18 20 22 SUPPLY VOLTAGE (±V) FIGURE 19. SWITCHING TIME vs POWER SUPPLY VOLTAGE (DG445) FN3586.9 November 20, 2006 DG444, DG445 Typical Performance Curves (Continued) 400 500 V+ = +12V, V- = 0V VL = 5V 400 tON, tOFF (ns) 300 tON, tOFF (ns) V- = 0V, VL = 5V tON 200 100 tOFF tON (444) 300 tON (445) 200 tOFF (445) 100 tOFF (444) 0 0 2 3 4 8 5 VIN (V) FIGURE 20. SWITCHING TIME vs INPUT VOLTAGE (DG444) (SINGLE 12V SUPPLY) 10 12 14 16 18 POSITIVE SUPPLY (V) 20 22 FIGURE 21. SWITCHING TIMES vs SINGLE SUPPLY VOLTAGE 10 30 V+ = 12V V- = 0V IS(OFF) , ID(OFF) 0 20 IS , ID (pA) Q (pC) -10 10 CL = 10nF -20 CL = 1nF IS(ON) + ID(ON) V+ = +12V V- = 0V FOR ID , VS = 0 0 -30 FOR IS, VD = 0 -40 -10 0 4 0 8 6 VS , VD (V) VS (V) FIGURE 22. CHARGE INJECTION vs SOURCE VOLTAGE (SINGLE 12V SUPPLY) 12 FIGURE 23. SOURCE/DRAIN LEAKAGE CURRENTS (SINGLE 12V SUPPLY) 20 V+ = +12V V- = 0V CS(ON) + CD(ON) CS , D (pF) 15 10 CS(OFF) , CD(OFF) 5 0 0 6 VA (V) 12 FIGURE 24. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY) 9 FN3586.9 November 20, 2006 DG444, DG445 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2160μm x 1760μm x 485 Type: Nitride Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: SiAl Thickness: 12kÅ ±1kÅ 9.1 x 104 A/cm2 Metallization Mask Layout DG444, DG445 D1 (2) IN1 (1) IN2 (16) (15) D2 (14) S2 S1 (3) (13) V+ SUBSTRATE V- (4) GND (5) (12) VL S4 (6) (11) S3 (7) D4 10 (8) IN4 (9) IN3 (10) D3 FN3586.9 November 20, 2006 DG444, DG445 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M 2 INCHES E1 GAUGE PLANE -B1 B M L 0.05(0.002) -A- SYMBOL MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - A1 3 A D -C- e α c 0.10(0.004) C A M 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - B S 0.002 D 0.193 0.201 4.90 5.10 3 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 N α NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 0.006 E1 e A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 6.50 - 0.70 6 16 8o 0o 7 8o Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 11 FN3586.9 November 20, 2006 DG444, DG445 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M INCHES E -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B C 0.10(0.004) 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 16 0° 16 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN3586.9 November 20, 2006