ON NSS40300MDR2G Dual matched 40 v, 6.0 a, low vce(sat) pnp transistor Datasheet

NSS40300MDR2G,
NSV40300MDR2G
Dual Matched 40 V, 6.0 A,
Low VCE(sat) PNP Transistor
These transistors are part of the ON Semiconductor e2PowerEdge
family of Low VCE(sat) transistors. They are assembled to create a pair
of devices highly matched in all parameters, including ultra low
saturation voltage VCE(sat), high current gain and Base/Emitter turn on
voltage.
Typical applications are current mirrors, differential amplifiers,
DC−DC converters and power management in portable and battery
powered products such as cellular and cordless phones, PDAs,
computers, printers, digital cameras and MP3 players. Other
applications are low voltage motor controls in mass storage products
such as disc drives and tape drives. In the automotive industry they can
be used in air bag deployment and in the instrument cluster. The high
current gain allows e2PowerEdge devices to be driven directly from
PMU’s control outputs, and the Linear Gain (Beta) makes them ideal
components in analog amplifiers.
Features





Current Gain Matching to 10%
Base Emitter Voltage Matched to 2 mV
AEC−Q101 Qualified and PPAP Capable
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements
These are Pb−Free Devices*
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40 VOLTS
6.0 AMPS
PNP LOW VCE(sat) TRANSISTOR
EQUIVALENT RDS(on) 80 mW
SOIC−8
CASE 751
STYLE 29
COLLECTOR
7,8
1
BASE
COLLECTOR
5,6
3
BASE
2
EMITTER
4
EMITTER
MARKING DIAGRAM
8
MAXIMUM RATINGS (TA = 25C)
Symbol
Max
Unit
Collector-Emitter Voltage
VCEO
−40
Vdc
Collector-Base Voltage
VCBO
−40
Vdc
Emitter-Base Voltage
VEBO
−7.0
Vdc
IC
−3.0
A
Collector Current − Peak
ICM
−6.0
A
Electrostatic Discharge
ESD
Rating
Collector Current − Continuous
HBM Class 3B
MM Class C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 2
1
1
P40300
A
Y
WW
G
P40300
AYWWG
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Package
Shipping†
NSS40300MDR2G
SOIC−8
(Pb−Free)
2,500 /
Tape & Reel
NSV40300MDR2G
SOIC−8
(Pb−Free)
2,500 /
Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NSS40300MD/D
NSS40300MDR2G, NSV40300MDR2G
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
576
4.6
mW
mW/C
SINGLE HEATED
Total Device Dissipation (Note 1)
TA = 25C
Derate above 25C
PD
Thermal Resistance
Junction−to−Ambient (Note 1)
RqJA
Total Device Dissipation (Note 2)
TA = 25C
Derate above 25C
PD
Thermal Resistance
Junction−to−Ambient (Note 2)
RqJA
217
676
5.4
185
C/W
mW
mW/C
C/W
DUAL HEATED (Note 3)
Total Device Dissipation (Note 1)
TA = 25C
Derate above 25C
PD
Thermal Resistance
Junction−to−Ambient (Note 1)
RqJA
Total Device Dissipation (Note 2)
TA = 25C
Derate above 25C
PD
Thermal Resistance
Junction−to−Ambient (Note 2)
RqJA
Junction and Storage Temperature Range
TJ, Tstg
1. FR−4 @ 10 mm2, 1 oz. copper traces, still air.
2. FR−4 @ 100 mm2, 1 oz. copper traces, still air.
3. Dual heated values assume total power is the sum of two equally powered devices.
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2
653
5.2
191
783
6.3
160
−55 to +150
mW
mW/C
C/W
mW
mW/C
C/W
C
NSS40300MDR2G, NSV40300MDR2G
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
−40
−
−
−40
−
−
−7.0
−
−
−
−
−0.1
−
−
−0.1
250
220
180
150
0.9
380
340
300
230
0.99
−
−
−
−
−
−
−
−
−
−0.013
−0.075
−0.130
−0.135
−0.017
−0.095
−0.170
−0.170
−
−0.780
−0.900
−
−
−0.660
0.3
−0.750
2.0
100
−
−
Unit
OFF CHARACTERISTICS
Collector −Emitter Breakdown Voltage
(IC = −10 mAdc, IB = 0)
V(BR)CEO
Collector −Base Breakdown Voltage
(IC = −0.1 mAdc, IE = 0)
V(BR)CBO
Emitter −Base Breakdown Voltage
(IE = −0.1 mAdc, IC = 0)
V(BR)EBO
Collector Cutoff Current
(VCB = −40 Vdc, IE = 0)
ICBO
Emitter Cutoff Current
(VEB = −6.0 Vdc)
IEBO
Vdc
Vdc
Vdc
mAdc
mAdc
ON CHARACTERISTICS
DC Current Gain (Note 4)
(IC = −10 mA, VCE = −2.0 V)
(IC = −500 mA, VCE = −2.0 V)
(IC = −1.0 A, VCE = −2.0 V)
(IC = −2.0 A, VCE = −2.0 V)
(IC = −2.0 A, VCE = −2.0 V) (Note 5)
hFE
hFE(1)/hFE(2)
Collector −Emitter Saturation Voltage (Note 4)
(IC = −0.1 A, IB = −0.010 A)
(IC = −1.0 A, IB = −0.100 A)
(IC = −1.0 A, IB = −0.010 A)
(IC = −2.0 A, IB = −0.200 A)
VCE(sat)
Base −Emitter Saturation Voltage (Note 4)
(IC = −1.0 A, IB = −0.01 A)
VBE(sat)
Base −Emitter Turn−on Voltage (Note 4)
(IC = −0.1 A, VCE = −2.0 V)
(IC = −0.1 A, VCE = −2.0 V) (Note 6)
VBE(on)
VBE(1) − VBE(2)
V
V
V
mV
Cutoff Frequency
(IC = −100 mA, VCE = −5.0 V, f = 100 MHz)
fT
MHz
Input Capacitance (VEB = −0.5 V, f = 1.0 MHz)
Cibo
−
250
300
pF
Output Capacitance (VCB = −3.0 V, f = 1.0 MHz)
Cobo
−
50
65
pF
td
−
−
60
ns
Rise (VCC = −30 V, IC = −750 mA, IB1 = −15 mA)
tr
−
−
120
ns
Storage (VCC = −30 V, IC = −750 mA, IB1 = −15 mA)
ts
−
−
400
ns
Fall (VCC = −30 V, IC = −750 mA, IB1 = −15 mA)
tf
−
−
130
ns
SWITCHING CHARACTERISTICS
Delay (VCC = −30 V, IC = −750 mA, IB1 = −15 mA)
4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle  2%.
5. hFE(1)/hFE(2) is the ratio of one transistor compared to the other transistor within the same package. The smaller hFE is used as numerator.
6. VBE(1) − VBE(2) is the absolute difference of one transistor compared to the other transistor within the same package.
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3
NSS40300MDR2G, NSV40300MDR2G
TYPICAL CHARACTERISTICS
0.30
150C
0.20
−55C
0.15
25C
0.10
0.05
0
0.001
0.01
0.1
1
10
300 −55C (5.0 V)
200 −55C (2.0 V)
100
0
0.001
0.01
0.1
1
0
0.001
0.01
0.1
1
10
IC/IB = 10
1.0
0.9
−55C
0.8
25C
0.7
0.6
150C
0.5
0.4
0.001
0.01
0.1
1
IC, COLLECTOR CURRENT (A)
Figure 3. DC Current Gain vs. Collector
Current
Figure 4. Base Emitter Saturation Voltage vs.
Collector Current
10
2.0
VCE = −2.0 V
0.7
VCE(sat), COLLECTOR−EMITTER
VOLTAGE (V)
VBE(on), BASE−EMITTER TURN−ON
VOLTAGE (V)
0.05
IC, COLLECTOR CURRENT (A)
0.8
−55C
25C
0.6
0.5
150C
0.4
0.3
0.2
0.10
0.3
10
1.0
0.9
0.15
1.1
25C (2.0 V)
400
0.20
150C
Figure 2. Collector Emitter Saturation Voltage
vs. Collector Current
25C (5.0 V)
500
25C
Figure 1. Collector Emitter Saturation Voltage
vs. Collector Current
150C (2.0 V)
600
−55C
IC, COLLECTOR CURRENT (A)
150C (5.0 V)
700
IC/IB = 100
0.25
IC, COLLECTOR CURRENT (A)
800
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
IC/IB = 10
VBE(sat), BASE−EMITTER
SATURATION VOLTAGE (V)
VCE(sat), COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
0.25
0.001
0.01
0.1
1
10
1.8
100 mA
1.6
1A
3A
2A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.0001
0.001
0.01
IC, COLLECTOR CURRENT (A)
Ib, BASE CURRENT (A)
Figure 5. Base Emitter Turn−On Voltage vs.
Collector Current
Figure 6. Saturation Region
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4
0.1
NSS40300MDR2G, NSV40300MDR2G
TYPICAL CHARACTERISTICS
100
Cobo, OUTPUT CAPACITANCE (pF)
300
250
200
Cibo (pF)
150
100
0
1
2
3
4
5
90
80
70
60
50
Cobo (pF)
40
30
6
0
5
10
15
20
25
30
VEB, EMITTER BASE VOLTAGE (V)
Vcb, COLLECTOR BASE VOLTAGE (V)
Figure 7. Input Capacitance
Figure 8. Output Capacitance
10
1 ms
1s
10 ms
100 ms
1.0
IC (A)
Cibo, INPUT CAPACITANCE (pF)
350
0.1
Thermal Limit
0.01
0.001
Single Pulse Test at TA = 25C
0.01
0.1
1.0
10
VCE (Vdc)
Figure 9. Safe Operating Area
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5
100
35
40
NSS40300MDR2G, NSV40300MDR2G
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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NSS40300MD/D