March 2004 AS7C3513B ® 3.3V 32K×16 CMOS SRAM Features • Industrial and commercial temperature • Organization: 32,768 words × 16 bits • Center power and ground pins • High speed • 10/12/15/20 ns address access time • 5, 6, 7, 8 ns output enable access time • Low power consumption: ACTIVE • 288 mW / max @ 10 ns • Low power consumption: STANDBY • 18 mW / max CMOS • 6T 0.18m CMOS Technology • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • 44-pin JEDEC standard package • 400 mil SOJ • 400 mil TSOP 2 • ESD protection > 2000 volts • Latch-up current > 200 mA Pin arrangement A0 A2 A3 A4 A5 A6 44-Pin SOJ, TSOP 2 (400 mil) VCC Row decoder A1 32K × 16 Array GND NC A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A14 A13 A12 A11 NC A7 I/O buffer Control circuit A14 A13 A12 A11 A8 A9 Column decoder WE A10 I/O0–I/O7 I/O8–I/O15 UB OE LB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 AS7C3513B Logic block diagram A4 A5 A6 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A7 A8 A9 A10 NC CE Selection guide -10 -12 -15 -20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 80 75 70 65 mA Maximum CMOS standby current 5 5 5 5 mA 3/24/04, v.1.2 Alliance Semiconductor P. 1 of 10 Copyright © Alliance Semiconductor. All rights reserved. AS7C3513B ® Functional description The AS7C3513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is high, the device enters standby mode. If inputs are still toggling, the device consumes ISB power. If the bus is static, then the full standby power is reached (ISB1). The AS7C3513B is guaranteed not to exceed 18mW power consumption under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0 - I/O7, and/or I/O8 – I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 – I/O7, and UB controls the higher bits, I/O8 – I/O15. All chip inputs and outputs are TTL-compatible. The AS7C3513B is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 –0.50 +5.0 V Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 oC Ambient temperature with VCC applied Tbias –55 +125 oC DC current into outputs (low) IOUT – 20 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode H X X X X High Z High Z Standby (ISB, ISBI) L H L L H DOUT High Z Read I/O0–I/O7 (ICC) L H L H L High Z DOUT Read I/O8–I/O15 (ICC) L H L L L DOUT DOUT Read I/O0–I/O15 (ICC) L L X L L DIN DIN Write I/O0–I/O15 (ICC) L L X L H DIN High Z Write I/O0–I/O7 (ICC) L L X H L High Z DIN Write I/O8–I/O15 (ICC) L L H X H X X H X H High Z High Z Output disable (ICC) Key: X = Don’t care; L = Low; H = High 3/24/04, v.1.2 Alliance Semiconductor P. 2 of 10 AS7C3513B ® Recommended operating conditions Parameter Symbol Min Typical Max Unit VCC 3.0 3.3 3.6 V VIH 2.0 – VCC + 0.5 VIL –0.5 – 0.8 V commercial TA 0 – 70 °C industrial TA –40 – 85 °C Supply voltage Input voltage Ambient operating temperature VIL = -1.0V for pulse width less than 5ns VIH = VCC + 1.5V for pulse width less than 5ns DC operating characteristics (over the operating range)1 -10 Parameter Sym -12 -15 -20 Min Max Min Max Min Max Min Max Unit VCC = Max VIN = GND to VCC – 1 – 1 – 1 – 1 µA Output leakage | ILO | current VCC = Max VOUT = GND to VCC – 1 – 1 – 1 – 1 µA Operating power supply current ICC VCC = Max, CE ≤ VIL f = fMax , IOUT = 0mA – 80 – 75 – 70 – 65 mA ISB VCC = Max, CE ≥ VIH f = fMax – 30 – 25 – 20 – 20 mA – 5 – 5 – 5 – 5 mA – 0.4 – 0.4 – 0.4 – 0.4 V 2.4 – 2.4 – 2.4 – 2.4 – V Max Unit Input leakage current | ILI | Standby power supply current ISB1 Test conditions VCC = Max, CE ≥ VCC–0.2V VIN ≤ 0.2V or VIN ≥ VCC –0.2V, f=0 Output voltage VOL IOL = 8 mA, VCC = Min VOH IOH = –4 mA, VCC = Min Capacitance (f = 1MHz, Ta = 25o C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Input capacitance CIN A, CE, WE, OE, LB, UB Vin = 0V 5 pF I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF 3/24/04, v.1.2 Alliance Semiconductor P. 3 of 10 AS7C3513B ® Read cycle (over the operating range) 3,9 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Read cycle time tRC 10 – 12 – 15 – 20 – ns Address access time tAA – 10 – 12 – 15 – 20 ns 3 Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 3 Output enable (OE) access time tOE – 5 – 6 – 7 – 8 ns Output hold from address change tOH 3 – 3 – 3 – 3 – ns 5 CE low to output in low Z tCLZ 3 – 3 – 3 – 3 – ns 4,5 CE high to output in high Z tCHZ – 3 – 3 – 4 – 5 ns 4,5 OE low to output in low Z tOLZ 0 – 0 – 0 – 0 – ns 4,5 Byte select access time tBA – 5 – 6 – 7 – 8 ns Byte select Low to low Z tBLZ 0 – 0 – 0 – 0 – ns 4,5 Byte select High to high Z tBHZ – 5 – 6 – 6 – 8 ns 4,5 OE high to output in high Z tOHZ – 5 – 6 – 7 – 8 ns 4,5 Power up time tPU 0 – 0 – 0 – 0 – ns 4,5 Power down time tPD – 10 – 12 – 15 20 ns 4,5 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tOH Data OUT 3/24/04, v.1.2 tAA Previous data valid tOH Data valid Alliance Semiconductor P. 4 of 10 Notes AS7C3513B ® Read waveform 2 (CE, OE, UB, LB controlled)3,6,8,9 tRC Address tAA OE tOE tOH tOLZ CE tOHZ tACE tLZ tHZ LB, UB tBA tBHZ tBLZ Data OUT Data valid Write cycle (over the operating range)11 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Write cycle time tWC 10 – 12 – 15 – 20 – ns Chip enable (CE) to write end tCW 8 – 9 – 10 – 12 – ns Address setup to write end tAW 8 – 9 – 10 – 12 – ns Address setup time tAS 0 – 0 – 0 – 0 – ns Write pulse width tWP 7 – 8 – 9 – 12 – ns Write recovery time tWR 0 – 0 – 0 – 0 – ns Address hold from end of write tAH 0 – 0 – 0 – 0 – ns Data valid to write end tDW 5 – 6 – 8 – 10 – ns Data hold time tDH 0 – 0 – 0 – 0 – ns 5 Write enable to output in high Z tWZ – 5 – 6 – 7 – 8 ns 4,5 Output active from write end tOW 1 – 1 – 1 – 2 – ns 4,5 Byte select low to end of write tBW 7 – 8 – 9 – 9 – ns 3/24/04, v.1.2 Alliance Semiconductor Notes P. 5 of 10 AS7C3513B ® Write waveform 1(WE controlled)11 tWC Address tWR tBW LB, UB tAW tAS tWP WE tDW tDH Data valid Data IN tWZ tOW Data undefined Data OUT High-Z Write waveform 2 (CE controlled)11 tWC Address tAS tAH & tWR tCW CE tAW tBW LB, UB tWP WE tDH tDW Data valid Data IN tCLZ Data OUT 3/24/04, v.1.2 High-Z tWZ Data undefined Alliance Semiconductor tOW High-Z P. 6 of 10 AS7C3513B ® AC test conditions - Output load: see Figure B. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168Ω Dout +1.728V +3.3V 320Ω +3.0V GND 90% 10% Dout 350Ω 90% 2 ns 10% C13 GND Figure B: 3.3V Output load Figure A: Input pulse Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. These parameters are specified with CL = 5pF, as in Figure B. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. All write cycle timings are referenced from the last valid address to the first transitioning address. Not applicable. C=30pF, except on High Z and Low Z parameters, where C=5pF. 3/24/04, v.1.2 Alliance Semiconductor P. 7 of 10 AS7C3513B ® Package dimensions 44-pin TSOP 2 c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Min (mm) Max (mm) A1 0.05 0.15 A2 0.95 1.05 b 0.3 0.45 c 0.12 0.21 d 18.31 18.52 e 10.06 10.26 He 11.68 11.94 Symbol A e He 44-pin TSOP 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 d l A2 A 0–5° A1 E E b l D E1 E2 Pin 1 B c A A1 b 0.60 Seating Plane A2 Symbol Min Max A 0.128 0.148 A1 0.025 - A2 0.105 0.115 B 0.026 0.032 b 0.015 0.020 c 0.007 0.013 D 1.120 1.130 E E Alliance Semiconductor 0.370 NOM E1 0.395 0.405 E2 0.435 0.445 e 3/24/04, v.1.2 0.80 (typical) 0.40 44-pin SOJ 400 mil 44-pin SOJ e 1.2 0.050 NOM P. 8 of 10 AS7C3513B ® Ordering codes Package\Access time 10 ns 12 ns 15 ns 20 ns Plastic SOJ, 400 mil Commercial AS7C3513B-10JC AS7C3513B-12JC AS7C3513B-15JC AS7C3513B-20JC Industrial AS7C3513B-10JI AS7C3513B-12JI AS7C3513B-15JI AS7C3513B-20JI TSOP 2, 18.4×10.2 mm Commercial AS7C3513B-10TC AS7C3513B-12TC AS7C3513B-15TC AS7C3513B-20TC Industrial AS7C3513B-10TI AS7C3513B-12TI AS7C3513B-15TI AS7C3513B-20TI Note: Add suffix ‘N’ to the above part number for lead free parts (Ex. AS7C3513B-10JCN) Part numbering system AS7C 3 513B –XX SRAM prefix Voltage: Device number Access time 3/24/04, v.1.2 3.3V CMOS X C X Package: Temperature range: C = Commercial, 0°C to 70°C I = Industrial, -40°C to 85°C N=Lead Free Part J = SOJ 400 mil T =TSOP 2 18.4×10.2 mm Alliance Semiconductor P. 9 of 10 AS7C3513B ® ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C3513B Document Version: v.1.2 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. 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