HiPerClockS™ Application Note Integrated Circuit Systems, Inc. 3.3V LVPECL DRIVER TERMINATION TM TM This application note provides termination examples for HiPerClockS 3.3V LVPECL drivers. The HiPerClockS 3.3V LVPECL driver is an open source/emitter driver as shown in Figure 1. Proper termination is required to ensure proper function of the device and signal integrity. There are many different termination schemes for the LVPECL drivers. This application note includes standard direct termination and AC coupled termination. The following termination approaches are only general recommendations under ideal conditions. Board designers should consult with their signal integrity engineers or verify through simulations in their system environment. The trace length and physical location of the components can affect signal integrity. The 50-Ohm transmission lines in the following diagrams indicate whether the components should be located near the driver or near the receiver. VCCO VCCO R1 R2 P.C. Board Q Zo = 50 nQ Zo = 50 LVPECL Driver R4 50 R3 50 VEE VCCO-2V TM Figure 1 HiPerClockS LVPECL driver Direct LVPECL Termination The standard 3.3V LVPECL termination is shown in Figure 2. This termination scheme is used in characterization. The draw back of using this termination scheme in real applications is that it requires an additional power supply VCCO-2V = 1.3V. In actual applications, the terminations shown in Figure 3 and Figure 4 are commonly used. These termination approaches eliminate the need of 1.3V power supply. In Figure 5, R1 and R2 located near the driver serve as current paths for the LVPECL outputs. The R3=100 Ohm located near the receiving serves as matched load termination for the transmission lines. www.icst.com/products/hiperclocks.html 1 Aug 02, 2002 HiPerClockS™ Application Note Integrated Circuit Systems, Inc. 3.3V LVPECL DRIVER TERMINATION VCCO=VEE+3.3V Zo = 50 Td + Zo = 50 Td VEE R2 50 R1 50 VCCO-2V Figure 2 Standard 3.3V LVPECL Termination 3.3V VCCO =3.3V R1 125 Zo = 50 R3 125 Td + Zo = 50 Td - R2 84 R4 84 Figure 3 Equivalent 3.3V LVPECL Termination www.icst.com/products/hiperclocks.html 2 Aug 02, 2002 HiPerClockS™ Application Note Integrated Circuit Systems, Inc. 3.3V LVPECL DRIVER TERMINATION VCCO=3.3V Zo = 50 Td + Zo = 50 Td R2 50 R1 50 R3 50 Figure 4 Equivalent 3.3V LVPECL Termination VCCO=3.3V U1 Zo = 50 Td TL1 + 3v3 PECL Driver R3 100 Zo = 50 Td - nTL1 R2 100-180 R1 100-180 Figure 5 Termination with 100-Ohm resistor across the differential input www.icst.com/products/hiperclocks.html 3 Aug 02, 2002 HiPerClockS™ Application Note Integrated Circuit Systems, Inc. 3.3V LVPECL DRIVER TERMINATION AC Coupled Termination For AC termination, the offset level needs to be taken care of after the AC capacitors. A bias circuit might be required. The board design engineer needs to verify what type of receiver is being driven. A few examples of AC couple termination are shown in this section. In Figure 6, the R3 and R4 at the driver pins provide a current path for the LVPECL driver. R1 and R2 serve as matched load termination. The power supply VBB controls the offset level so that the signal offset fall within the VCMR input requirement of the receiver. Figure 7 and Figure 8 are equivalent to Figure 5. The Figure 7 is TM equivalent to VBB=VCC-2V. This offset is suitable for interfacing with HiPerClockS CLK/nCLK input. Figure 8 is TM equivalent to VBB=VCC-1.3V. This offset is suitable for interfacing with HiPerClockS PCLK/nPCLK input. Figure 9 shows AC termination with the offset bias voltage VBB provided at the receiving end. Figure 10 shows AC termination with the offset bias voltage VBB provided by the receiver device. In some cases, for the receiver with built-in bias resistors R1 and R2, the termination is shown in Figure 11. VCCO=3.3V U1 Zo = 50 Td C1 + TL1 3v3 PECL Driver Zo = 50 Td C2 nTL1 R3 100-180 R4 100-180 R2 50 R1 50 VBB Figure 6 AC Coupled with VBB power supply provided at the receiving end www.icst.com/products/hiperclocks.html 4 Aug 02, 2002 HiPerClockS™ Application Note Integrated Circuit Systems, Inc. 3.3V LVPECL DRIVER TERMINATION VCCO=3.3V 3.3V U1 Zo = 50 Td C1 R5 125 R3 125 TL1 3v3 PECL Driver + Zo = 50 Td C2 - nTL1 R2 100-180 R1 100-180 R6 84 R4 84 Figure 7 AC Coupled with bias offset at VCC - 2V (Suitable for interface with HiPerClockS CLK/nCLK input) VCCO=3.3V 3.3V U1 Zo = 50 Td C1 R5 84 R3 84 TL1 3v3 PECL Driver + Zo = 50 Td C2 - nTL1 R2 100-180 R1 100-180 R6 125 R4 125 Figure 8 AC coupled with bias offset at VCC - 1.3V (Suitable for AC Couple with ICS HiPerClockS PCLK/nPCLK input) www.icst.com/products/hiperclocks.html 5 Aug 02, 2002 HiPerClockS™ Application Note Integrated Circuit Systems, Inc. 3.3V LVPECL DRIVER TERMINATION VCCO=3.3V Zo = 50 C1 Td + Zo = 50 C2 Td R3 50 R2 1K R4 50 R1 1K VBB R5 50 Figure 9 AC Coupled Termination with VBB bias level provided at the receiver VCCO=3.3V Zo = 50 C1 Td + VBB Zo = 50 C2 Td R3 50 R4 50 R2 1K R1 1K VBB R5 50 Figure 10 AC Coupled Termination with VBB bias provided by the receiver www.icst.com/products/hiperclocks.html 6 Aug 02, 2002 HiPerClockS™ Application Note Integrated Circuit Systems, Inc. 3.3V LVPECL DRIVER TERMINATION VCCO=3.3V Receiver U1 3v3 PECL Driver Zo = 50 Td C1 Td C2 TL1 Zo = 50 R5 100 nTL1 R3 100-180 R4 100-180 R3 > 1K R4 > 1K VBB Figure 11 AC coupled for the receiver with built-in bias circuit www.icst.com/products/hiperclocks.html 7 Aug 02, 2002