OKI Semiconductor ML66525 Family FEDL66525-02 Issue Date: July 19, 2002 16-Bit Microcontroller GENERAL DESCRIPTION The ML66525 family devices are high-performance 16-bit CMOS microcontrollers that utilize the nX-8/500S, Oki’s proprietary CPU core. Data from a personal computer with a USB connector can be automatically, quickly written or read to and from NAND type Flash Memory via USB I/F and NAND Flash Memory I/F. The ML66525 family devices support clock gear functions, a sub-clock and HALT/STOP mode, which are suitable for low power applications. The ML66525 family devices are provided with interfaces to external devices such as a 4-channel multi-functional serial interface with internal 32-byte FIFO and a high-speed bus interface that has separate address and data buses and does not require external address latches. A wide variety of internal multi-functional timers enable various timing controls such as periodic and timed measurements. With a 16-bit CPU core that enables high-speed arithmetic computations and a variety of bit processing functions, these general-purpose microcontrollers are optimally suited for Digital Audio devices such as MP3 players, voice recorders, handy games, and PC peripheral control systems (to control devices that can be connected to USB and store data into memory). The ML66525 family devices also include the flash ROM version device (ML66Q525B) that is programmable with a single 3 V power supply (2.4 to 3.6 V). [ Note ] ML66525A/ML66Q525A are supplied as stock lasts. APPLICATIONS • Small-sized handy systems that require USB control and Storage control (Digital Audio players, etc) • PC Peripheral Control Systems ORDERING INFORMATION Order Code or Product Name Package Remark ML66525B-xxTB *1 100-pin plastic TQFP mask ROM version (2.4 to 3.6 V) ML66Q525B-NTB *2 (TQFP100-P-1414-0.50-K) ML66525B flash ROM version (2.4 to 3.6 V) ML66525B-xxLA *1 144-pin plastic LFBGA ML66525B BGA package version (2.4 to 3.6 V) (P-LFBGA144-1111-0.80) ML66Q525B-NLA *2 ML66Q525B BGA package version (2.4 to 3.6 V) *1 : The “xx” of “-xx” stands for the code number. *2 : The “N” of “-N” stands for the flash ROM blank version. When OKI programs and ship the flash ROM, the part number is changed from ”–N” to ”–XX” (code number ) , for example, ML66Q525B-999TB. 1/27 FEDL66525-02 OKI Semiconductor ML66525 Family FEATURES Parameter Operating temperature Power supply voltage/ ML66525B –30 to +70°C VDD = 2.4 to 3.6 V / f = 24 MHz Maximum operating frequency Minimum instruction execution time Internal ROM size (max. external) Internal RAM size (max. external) I/O ports Timers Serial port A/D converter External interrupts USB control NAND Flash Memory control Interrupt priority Others Flash ROM version 83 nsec@24 MHz 61 µ[email protected] kHz 128 KB (1 MB) 6 KB (1 MB) 64 I/O pins (with programmable pull-up resistors) 6 input-only pins 1 output-only pin 16-bit auto-reload timer × 2ch 8-bit auto-reload timer × 1ch 8-bit auto-reload timer 8-bit auto-reload timer (also functions as watchdog timer) × 1ch Watch timer × 1ch 8-bit PWM × 2ch (can also be used as 16-bit PWM × 1ch) Synchronous (with 32-byte FIFO) × 1ch Synchronous (Shift register type) × 1ch Synchronous/UART × 2ch 10-bit × 4ch Non-maskable × 1ch Maskable × 6ch Compliant with USB spec. version 1.1 High-speed transfer at 12 Mbps Internal PLL(x2 , x3 , x4) -> 48 MHz Internal transceiver Vbus detection circuit (connection to USB host : detect/non-detect) Bus power available EP0 (IN 32 bytes, OUT 32 bytes), control transfer EP1 (64 bytes × 2), bulk/interrupt transfer EP2 (64 bytes × 2), bulk/interrupt transfer EP3 (32 bytes), bulk/interrupt transfer EP4 (64 bytes × 2), bulk/isochronous/interrupt transfer EP5 (64 bytes × 2), bulk/isochronous/interrupt transfer Automatic, high-speed data transfer ECC circuit Automatic, high-speed 512-byte data transfer 3 levels External bus Interface (separate address and data buses) Dual clocks function Clock gear function Different power available among USB, CPU core, and I/O port ML66Q525B 2/27 FEDL66525-02 OKI Semiconductor ML66525 Family FUNCTIONAL DESCRIPTION 1. High-performance CPU The ML66525 family devices include the high-performance CPU, powerful bit manipulation instruction set, a variety of symmetrical addressing modes, and ROM WINDOW function, and also supports the best-optimized C compiler. 2. A variety of power saving modes Attaching a 32.768-kHz crystal produces a real time clock signal from the internal clock timer. A single clock can be used in place of dual clocks. Switching the CPU clock to the dual clocks (1/2 or 1/4 of the main clock) enables operation in a low power consumption mode. The clock gear function allows a 1/2 or 1/4 clock signal of the main clock to be selected as the CPU operating clock. The ML66525 family devices are provided with a wide range of standby control functions such as the STOP mode that stops the oscillation circuit, the quick restart STOP mode that stops the CPU and peripherals while the oscillation circuit is operating, and the HALT mode that shuts down the CPU while peripherals are operating. 3. USB control The family include USB controller which compliant with USB specification version 1.1 and can be transferred data with 12Mbps circuit. Also, USB controller have 6 kinds of endpoint and apply for control/bulk/isochronous/interrupt transfer. With NAND Flash Memory control circuit, high speed data transfer is possible. 4. NAND Flash Memory control The family include control circuit of NAND Flash Memory. Automatically data read from and write to outside NAND Flash Memory with 528 byte. Also, include ECC circuit which detect data error and correct data error. 5. ML66Q525B with flash memory programmable with single power supply In addition to mask ROM version devices, the ML66525 family devices include the ML66Q525B with internal 128 Kbytes of flash memory that can be programmed with a single power supply. The flash memory of the ML66Q525B can be programmed with a low power supply (2.4 to 3.6 V) using the internal voltage booster circuit. 6. Multifunctional, high-precision analog-to-digital converter The family devices include a high-precision 10-bit analog-to-digital converter with four channels and are ideal for such analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and controlling battery use in portable equipment. Each channel has its own result register readily accessible from the software. 3/27 FEDL66525-02 OKI Semiconductor ML66525 Family 7. Multifunctional PWM The family devices support both 8- and 16-bit PWM operations. Choosing between the time base counter output and the overflow from an 8-bit auto-reload time as the PWM counter clock source provides a great number of possibilities over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable for digital-to-analog applications. 8. Programmable pull-up resistors Building the pull-up resistors into the chip contributes overall design compactness. Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These programmable pull-up resistors are available for all I/O pins except ports that have specific functions such as oscillator connection pins. 9. High-speed bus interface The interface to external devices uses separate data and address buses. This arrangement permits a rapid bus access for controlling the system from the microcontroller. 10. A variety of external interrupts There are a total of seven interrupt channels for use in communicating with external devices; six channels for maskable interrupts and one channel for non-maskable interrupts. 4/27 FEDL66525-02 OKI Semiconductor ML66525 Family BLOCK DIAGRAM NMI EXINT0 to EXINT4 EXINT8/9 Interrupt CPU Core RESn System Control 16-bit Timer0 RXD1 TXD1 RXC1 TXC1 SIO1 (UART/SYNC) ALU Control Registers 8-bit Timer4/BRG RXD6 TXD6 RXC6 TXC6 OSC0 OSC1n XT0 XT1n SSP LRB ALU Control ACC SIO6 PSW PC DSR TSR CSR (UART/SYNC) 8-bit Timer3/BRG Memory Control Pointing Registers Local Registers SIO3 (SYNC) 8-bit Timer5/BRG SIOI4 SIOO4 SIOCK4 ROM 128 Kbyte RAM 4Kbyte SIO4 (32-byte FIFO SYNC) Instruction Decoder + 2Kbyte Also functions as transfer RAM 8-bit Timer6/WDT Bus Port Control SIOI3 SIOO3 SIOCK3 TBC 8-bit PWM0 8-bit PWM1 Port Control RTC 8-bit Timer9 VREF AGND AI0 to AI3 10-bit A/D Converter USB DMA transfer PUCTL USB D+/D– (Compliant with ver1.1) DMA (USB ↔ Transfer RAM) D0 to D7 A0 to A19 P0 (8 bit) P1 (8 bit) P2 (4 bit) P3 (3 bit) P4 (8 bit) P6 (4 bit) 16-bit Timer7 PWMOUT0 PWMOUT1 EAn PSENn RDn WRn FLASH media DMA transfer bus Transfer RAM (512 bytes × 4 banks) Flash media control DMA (Media ↔ Transfer RAM) P7 (2 bit) P8 (4 bit) P9 (1 bit) P10 (6 bit) P12 (4 bit) P13 (2 bit) P15 (4 bit) P20 (8 bit) P21 (5 bit) FD0 to FD7 FRDn FWRn FCLE FALE FRB 5/27 FEDL66525-02 OKI Semiconductor ML66525 Family 1 80 85 90 100 75 5 70 10 65 15 60 20 55 50 45 40 VDD_CORE P2_3/A19 P2_2/A18 P2_1/A17 P2_0/A16 VTM P1_7/A15 P1_6/A14 P1_5/A13 P1_4/A12 P1_3/A11 P1_2/A10 P1_1/A9 P1_0/A8 P4_7/A7 P4_6/A6 P4_5/A5 P4_4/A4 P4_3/A3 P4_2/A2 P4_1/A1 P4_0/A0 VDD_CORE GND VDD_IO VDD_CORE RESn NMI EAn VDD_IO XT0 XT1n GND TEST OSC0 OSC1n VDD_IO P13_0/EXINT8 P13_1/EXINT9 P0_0/D0 P0_1/D1 P0_2/D2 P0_3/D3 P0_4/D4 P0_5/D5 P0_6/D6 P0_7/D7 P3_1/PSENn P3_2/RDn P3_3/WRn 35 25 30 VBUS P9_0/VBUSIN P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P7_6/PWM0OUT P7_7/PWM1OUT FLAMOD P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 GND VDD_IO P10_0/SIOCK3 P10_1/SIOI3 P10_2/SIOO3 P10_3/SIOCK4 P10_4/SIOO4 P10_5/SIOI4 P15_0/RXD6 P15_1/TXD6 P15_2/RXC6 P15_3/TXC6 95 Dñ D+ PUCTL GND P20_7/FD7 P20_6/FD6 P20_5/FD5 P20_4/FD4 P20_3/FD3 P20_2/FD2 P20_1/FD1 P20_0/FD0 VDD_IO GND P21_4/FRB P21_3/FALE P21_2/FCLE P21_1/FWRn P21_0/FRDn AGND AI3/P12_3 AI2/P12_2 AI1/P12_1 AI0/P12_0 VREF PIN CONFIGURATION (TOP VIEW) 100-pin Plastic TQFP A symbol with “n” suffixed indicates an active Low pin. 6/27 FEDL66525-02 OKI Semiconductor ML66525 Family PIN CONFIGURATION (TOP VIEW) NC VDD_IO P3_2/ RDn NC P0_5/ D5 P0_3/ D3 P13_1/ OSC0 EXINT9 GND XT0 NMI VDD_ CORE NC N GND P3_3/ WRn P3_1/ PSENn P0_4/ D4 P0_2/ D2 P0_1/ D1 VDD_IO OSC1n TEST XT1n VDD_IO P15.2/ RXC6 P15_3/ TXC6 M P4_0/ A0 NC VDD_ CORE P0_7/ D7 P0_6/ D6 P0_0/ D0 P13_0/ EXINT8 NC NC EAn RESn P15_0/ P15_1/ RXD6 TXD6 L P4_2/ A2 NC P4_1/ A1 NC NC NC NC NC NC NC P10_4/ P10_2/ P10_5/ SIOO4 SIOO3 SIOI4 K P4_4/ A4 P4_5/ A5 P4_3/ A3 NC NC P10_3/ SIOCK4 J P4_6/ A6 P4_7/ A7 P1_0/ A8 NC NC VDD_IO NC P1_1/ A9 P1_2/ A10 NC NC P8_3/ TXC1 P8_2/ RXC1 GND G P1_5/ A13 P1_4/ A12 P1_3/ A11 NC NC P8_1/ TXD1 P8_0/ RXD1 NC F NC NC P1_7/ A15 NC NC P7_6/ P7_7/ FLAMO PWM0O PWM1O E D UT UT NC P1_6/ A14 VTM NC NC P6_2/ EXINT2 NC P6_3/ EXINT3 D P2_1/ A17 P2_0/ A16 VREF P12_1/ P12_3/ P21_4/ P20_1/ P20_7/ VDD_IO AI1 AI3 FRB FD1 FD7 NC P6_0/ EXINT0 NC P6_1/ EXINT1 C P2_3/ A19 P2_2/ A18 NC AGND P20_2/ P20_3/ P20_5/ PUCTL FD2 FD3 FD5 D- P9_0/ VBUSIN B NC VDD_ CORE 13 12 NC P21_1/ P21_3/ FWRn FALE P12_0/ P12_2/ P21_0/ AI0 AI2 FRDn 11 10 NC 9 NC GND P21_2 /FCLE P20_0 /FD0 8 7 NC NC P20_4/ P20_6/ FD4 FD6 6 5 NC NC P10_0/ P10_1/ SIOCK3 SIOI3 GND D+ VBUS NC 4 3 2 1 H A 144-pin Plastic LFBGA A symbol with “n” suffixed indicates an active Low pin. [Note] Don’t connect NC pins with others. 7/27 FEDL66525-02 OKI Semiconductor ML66525 Family PIN DESCRIPTIONS In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin. A symbol with “n” suffixed indicates an active Low pin. Classification Symbol Description Type Port P0_0/D0 to P0_7/D7 I/O P1_0/A8 to P1_7/A15 I/O P2_0/A16 to P2_3/A19 I/O P3_1/PSENn I/O Primary function 8-bit I/O port Type I/O External memory access data I/O port O External memory access address output port O External memory access address output port O External program memory access read strobe output pin Pull-up resistors can be specified for each bit. 8-bit I/O port Pull-up resistors can be specified for each bit. 4-bit I/O port Pull-up resistors can be specified for each bit. 1-bit I/O port Secondary function Pull-up resistors can be specified. P3_2/RDn O 1-bit output port O External data memory access read strobe output pin P3_3/WRn I/O 1-bit I/O port O External data memory access write strobe output pin O External memory access address output port 4-bit I/O port I External interrupt 0 input pin Pull-up resistors can be specified for each bit. I External interrupt 1 input pin Pull-up resistors can be specified. P4_0/A0 to P4_7/A7 I/O P6_0/EXINT0 I/O 8-bit I/O port Pull-up resistors can be specified for each bit. P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P7_6/PWM0OUT I/O P7_7/PWM1OUT P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 I/O I External interrupt 2 input pin I External interrupt 3 input pin 2-bit I/O port O PWM0 output pin Pull-up resistors can be specified for each bit. O PWM1 output pin 4-bit I/O port I SIO1 receive data input pin Pull-up resistors can be specified for each bit. O SIO1 transmit data output pin I/O SIO1 receive clock I/O pin I/O SIO1 transmit clock I/O pin 8/27 FEDL66525-02 OKI Semiconductor Classification Port ML66525 Family Symbol P9_0/VBUSIN Description Type I/O Primary function 1-bit I/O port Type I Pull-up resistors can be specified. P10_0/SIOCK3 I/O 6-bit I/O port Pull-up resistors can be specified for each bit. P10_1/SIOI3 P10_2/SIOO3 I/O I P10_5/SIOI4 P12_0/AI0 to SIO3 transmit-receive clock I/O pin SIO3 receive data input pin O SIO3 transmit data input pin I/O SIO4 (with internal 32-byte FIFO) transmit-receive clock I/O pin O SIO4 (with internal 32-byte FIFO) transmit data output pin I SIO4 (with internal 32-byte FIFO) receive data output pin P10_3/SIOCK4 P10_4/SIOO4 Secondary function Vbus detect external interrupt input pin (5V tolerant input) I 4-bit input port I A/D converter analog input port I 2-bit input port I External interrupt 8 input pin I External interrupt 9 input pin P12_3/AI3 P13_0/EXINT8 P13_1/EXINT9 P15_0/RXD6 I/O P15_1/TXD6 P15_2/RXC6 4-bit I/O port I SIO6 receive data input pin Pull-up resistors can be specified for each bit. O SIO6 transmit data output pin P15_3/TXC6 P20_0/FD0 to P20_7/FD7 P21_0/FRDn P21_1/FWRn P21_2/FCLE P21_3/FALE P21_4/FRB I/O 8-bit I/O port I/O SIO6 receive clock I/O pin I/O SIO6 transmit clock I/O pin I/O NAND Flash Memory access data I/O port Pull-up resistors can be specified for each bit. I/O 5-bit I/O port O I/O Pull-up resistors can be specified for each bit. NAND Flash Memory access read strobe output pin O NAND Flash Memory access write strobe output pin I/O O NAND Flash Memory access CLE strobe output pin I/O O NAND Flash Memory access ALE strobe output pin I/O I NAND Flash Memory access Ready/Busy input pin 9/27 FEDL66525-02 OKI Semiconductor ML66525 Family Classification Symbol Type Power supply VDD_IO I Description IO Power supply pin Connect all the VDD _IO pins.* VDD_CORE I Core Power supply pin Connect all the VDD _CORE pins.* VBUS I USB Power supply pin (Vbus input pin) GND I GND pin Connect all the GND pins to GND.* Oscillation VREF I Analog reference voltage pin (Connect to the VDD pin when A/D converter is not used.) AGND I Analog GND pin (Connect to the GND pin when A/D converter is not used.) XT0 I Sub-clock oscillation input pin Connect to a crystal of f = 32.768 kHz. XT1n O Sub-clock oscillation output pin Connect to a crystal of f = 32.768 kHz. The clock output is opposite in phase to XT0. OSC0 I Main clock oscillation input pin Connect to a crystal or ceramic oscillator. When an external clock is used, this pin is configured to be clock input. OSC1n O Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used. USB I/F D+ I/O D+ pin D– I/O D– pin PUCTL O External control output pin Reset RESn I Reset input pin Others NMI I Non-maskable interrupt input pin TEST I Test pin Connect to the GND pin for normal operation. VTM I Test pin Connect to the GND pin for normal operation. FLAMOD I Flash ROM programming mode input pin When the FLAMOD pin is set to “L”, the device enters a programming mode. Connect to the VDD_IO pin when using as normal operation. EAn I External program memory access input pin When the EA pin is enabled (low level), the internal program memory is masked and the CPU executes the program code in external program memory through all address space. * Connect all VDD_IO pins, all VDD_CORE pins and all GND pins. If a device has one or more VDD_IO, VDD_CORE, or GND pins to which the power supply or the ground potential is not connected, the family devices are not guaranteed to have normal operations. 10/27 FEDL66525-02 OKI Semiconductor ML66525 Family ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rated value Unit GND = AGND = 0 V Ta = 25°C –0.3 to +4.6 V Other than P9_0 –0.3 to VDD_IO + 0.3 V P9_0 (5 V tolerant input) –0.3 to +0.6 V VO –0.3 to VDD_IO + 0.3 V VREF –0.3 to +4.6 V VDD_CORE Digital power supply voltage Input voltage Output voltage Analog reference voltage Analog input voltage Power dissipation VDD_IO VBUS VI VAI PD Ta = 70°C 100-pin TQFP per package V 680 mW 595 mW — –50 to +150 °C Symbol Condition Range Unit VDD_CORE VDD_IO fOSC ≤ 24 MHz VDD_CORE ≤ VDD_IO 2.4 to 3.6 V VREF VDD_CORE ≤ VREF 2.4 to 3.6 V Analog input voltage VAI — AGND to VREF V VBUS input voltage VBUS — 3.0 to 3.6 V Memory hold voltage VDDH fOSC = 0 Hz 2.0 to 3.6 V USB is used 12, 16, 24 USB is unused 2 to 24 — 32.768 kHz — –30 to +70 °C MOS load 20 — 6 — 1 — Storage temperature TSTG 144-pin LFBGA –0.3 to VREF RECOMMENDED OPERATING CONDITIONS Parameter Digital power supply voltage Analog reference voltage Operating frequency fOSC fXT Ambient temperature Ta P7, P10_0 to P10_2 Fan out N MHz P0, P1, P2, P3, P4, TTL load P6, P8, P9, P10_3 to P10_5, P15, P20, P21 11/27 FEDL66525-02 OKI Semiconductor ML66525 Family ALLOWABLE OUTPUT CURRENT VALUES (VDD_IO = 2.4 to 3.6 V, Ta = –30 to +70°C) Parameter Pin “H” output pin (1 pin) All output pins “H” output pins (sum total) Sum total of all output pins “L” output pin (1 pin) Symbol Min. Typ. Max. IOH — — –10 ∑ IOH — — –70 IOL — — 10 All output pins Unit Sum total of P0, P3 Sum total of P1, P2, P4 “L” output pins (sum total) Sum total of P6, P7, P8, P9 Sum total of P10, P15 mA 35 ∑ IOL — — Sum total of P20, P21 70 Sum total of all output pins 160 [Note] Connect all VDD_CORE and VDD_IO pins to the power supply voltage and all GND pins to the ground voltage. If there is a pin or pins that are not connected to the power supply voltage on ground voltage, the device cannot be guaranteed for normal operation. INTERNAL FLASH ROM PROGRAMMING CONDITIONS Parameter Supply voltage Ambient temperature Symbol Condition Rating Unit VDD_CORE VDD_IO VDD_CORE ≤ VDD_IO 2.4 to 3.6 V During Read –30 to +70 °C Ta During Programming +0 to +50 °C Endurance CEP — 100 Cycles Blocks size — — 128 bytes 12/27 FEDL66525-02 OKI Semiconductor ML66525 Family ELECTRICAL CHARACTERISTICS DC Characteristics 1 (Except USB port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter “H” input voltage *1 “H” input voltage “L” input voltage “H” output voltage Symbol Condition Min. Typ. Max. VIH — 0.80 VDD — 5.5 VIL — 0.80 VDD — VDD + 0.3 –0.3 — 0.2VDD IO = –400 µA VDD – 0.4 — — IO = –2.0 mA VDD – 0.8 — — IO = –200 µA VDD – 0.4 — — IO = –1.0 mA VDD – 0.8 — — IO = 3.2 mA — — 0.5 IO = 5.0 mA — — 0.9 IO = 1.6 mA — — 0.5 IO = 2.5 mA — — 0.9 — — 1/–1 — — 1/–90 — — 15/–15 *2 VOH “H” output voltage “L” output voltage *3 *2 VOL “L” output voltage Input leakage current *3 *4, *6 Input current *5 Input current *7 IIH/IIL VI = VDD/0 V Unit V µA ILO VO = VDD/0 V — — ±10 µA Pull-up resistance Rpull VI = 0 V 40 100 200 kΩ Input capacitance CI — 5 — Output capacitance CO — 7 — Analog reference supply current IREF — 1.8 5 mA When A/D is stopped — — 5 VDD = VDD_IO *1. Applicable to P9_0 (5 V tolerant input) *2. Applicable to P7 and P10_0 to P10_2 *3. Applicable to P0, P1, P2, P3, P4, P6, P8, P9, P10_3 to P10_5, P15, P20 and P21 µA Output leakage current *2, *3 fOSC = 1 MHz, Ta = 25°C During A/D operation pF *4. Applicable to P12 and P13 *5. Applicable to RESn and FLAMOD *6. Applicable to EAn, NMI, and TEST *7. Applicable to OSC0 13/27 FEDL66525-02 OKI Semiconductor ML66525 Family Supply Current • Mask ROM version (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, VBUS = 3.0 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Mode Symbol Condition Min. Typ. Max. fosc = 24 MHz, No load — 28 60 18 50 — 100 300 µA fosc = 24 MHz, DMA/media CPU operation mode IDD control stopped. No load fXT = 32.768 kHz, DMA/media control stopped. No load *1 Unit mA Applicable power supply VDD_CORE + VDD_IO USB operation mode IBUS Setting of 48 MHz for multiplication selection. No Load — 25 45 mA VBUS HALT mode IDDH fosc = 24 MHz, DMA/media control stopped. No load — 9 18 mA VDD_CORE + VDD_IO STOP mode IDDS XT is used *2 — 15 160 XT is not used *2 — 10 150 µA VDD_CORE + VDD_IO — 1 100 µA VBUS Suspend current ISUSP OSC is stopped *1 Suspend state OSC is stopped, XT is not used * 1 The values in the Typ. Column indicate reference values at 25°C and 3.0 V (The VBUS currents indicate values at 3.3 V). *1: The temperature condition ranges from –30 to +50°C *2: The ports used as inputs are at VDD_IO or 0 V. Other ports are unloaded. • Flash ROM version (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, VBUS = 3.0 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Mode Symbol Condition Min. Typ. Max. fosc = 24 MHz, No load — 28 60 18 50 — 100 300 µA fosc = 24 MHz, DMA/media CPU operation mode IDD control stopped. No load fXT = 32.768 kHz, DMA/media control stopped. No load *1 Unit mA Applicable power supply VDD_CORE + VDD_IO USB operation mode IBUS Setting of 48 MHz for multiplication selection No Load — 25 45 mA VBUS HALT mode IDDH fosc = 24 MHz, DMA/media control stopped. No load — 10 20 mA VDD_CORE + VDD_IO STOP mode IDDS XT is used *2 — 15 160 XT is not used *2 — 10 150 µA VDD_CORE + VDD_IO Suspend current ISUSP — 1 100 µA VBUS OSC is stopped *1 Suspend state, D+/D– fixed OSC is stopped, XT is not used * 1 The values in the Typ. Column indicate reference values at 25°C and 3.0 V (The VBUS currents indicate values at 3.3 V). *1: The temperature condition ranges from –30 to +50°C *2: The ports used as inputs are at VDD_IO or 0 V. Other ports are unloaded. 14/27 FEDL66525-02 OKI Semiconductor ML66525 Family DC Characteristics 2 (USB port) (VBUS = 3.0 to 3.6V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Typ. Max. Differential input sensitivity VDI |(D+) – (D–)| 0.2 — — Differential common mode range VCM Includes VDI 0.8 — 2.5 Single ended receiver threshold VSE 0.8 — 2.0 15 kΩ to GND 2.8 — — IOH = –100 µA VBUS – 0.2 — — IOH = –4 mA 2.4 — — 1.5 kΩ to 3.6 V — — 0.3 — — ±10 — — ±10 “H” output voltage “L” output voltage VOH VOL VO = VBUS/0 Output leakage current ILO V VO = VBUS/0 V Unit Applicable pin V D+, D– V D+, D– V PUCTL V D+, D– D+, D– µA PUCTL 15/27 FEDL66525-02 OKI Semiconductor ML66525 Family AC Characteristics (Except USB port) (1) External program memory control (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Symbol Condition Cycle time tcyc fOSC = 24 MHz 41.67 — Clock pulse width (HIGH level) tφWH 16.25 — Clock pulse width (LOW level) tφWL 16.25 — PSENn pulse width tPW (2 + 2n)tφ – 25 — PSENn pulse delay time tPD — 55 Address setup time tAS 2tφ – 25 — Address hold time tAH Instruction setup time tIS Instruction hold time Read data access time Min. VDD_CORE = CL = 50 pF Max. –10 — 40 — tIH 0 — tACC — (3 + 2n)tφ – 50 Unit ns (Note) tφ = tcyc/2 n = 0 to 3 ( n wait cycles inserted) tcyc CPUCLK tφWH tφWL PSENn tPD tPW PC0 to 19 A0 to A19 tAS tAH INST0 to 7 D0 to D7 tACC tIS tIH Bus timing during no wait cycle time 16/27 FEDL66525-02 OKI Semiconductor ML66525 Family (2) External data memory control (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Symbol Condition Min. Max. Cycle time tcyc fOSC = 24 MHz 41.67 — Clock pulse width (HIGH level) tφWH 16.25 — Clock pulse width (LOW level) tφWL 16.25 — RDn pulse width tRW (2 + 2n)tφ – 25 — WRn pulse width tWW (2 + 2n)tφ – 25 — RDn pulse delay time tRD — 55 WRn pulse delay time tWD — 55 Address setup time tAS tφ – 20 — CL = 50 pF Address hold time tAH tφ – 20 — Read data setup time tRS 40 — Read data hold time tRH 0 — Read data access time tACC — (3 + 2n)tφ – 50 Write data setup time tWS 2tφ – 30 — Write data hold time tWH tφ – 6 — Unit ns (Note) tφ = tcyc/2 n = 0 to 7 ( n wait cycles inserted) tcyc CPUCLK tφWH tφWL RDn tRD tRW RAP0 to 19 A0 to A19 tAS tAH DIN0 to 7 D0 to D7 tACC tRS tRH WRn tWD tWW RAP0 to 19 A0 to A19 tAS D0 to D7 tAH DOUT0 to 7 tWS tWH Bus timing during no wait cycle time 17/27 FEDL66525-02 OKI Semiconductor ML66525 Family (3) Serial port control 1. Serial port 1, 6 (SIO1, 6) Master mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 24 MHz 41.67 — Serial clock cycle time tSCKC 4 tcyc — Output data setup time tSTMXS 2tφ – 10 — Output data hold time tSTMXH 5tφ – 20 — CL = 50 pF Input data setup time tSRMXS 21 — Input data hold time tSRMXH 0 — Unit ns (Note) tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH 18/27 FEDL66525-02 OKI Semiconductor ML66525 Family Slave mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 24 MHz 41.67 — Serial clock cycle time tSCKC 4tcyc — Output data setup time tSTMXS 2tφ – 30 — Output data hold time tSTMXH 4tφ – 20 — CL = 50 pF Input data setup time tSRMXS 21 — Input data hold time tSRMXH 7 — Unit ns (Note) tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXS tSTMXH SDIN (RXD) tSRMXS tSRMXH 19/27 FEDL66525-02 OKI Semiconductor ML66525 Family 2. Serial port 4 (SIO4) Master mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. tcyc fOSC = 24 MHz Max. 41.67 — Serial clock cycle time tSCKC 400 — Output data setup time tSTMXS 190 — Output data hold time tSTMXH 130 — Input data setup time tSRMXS 21 — Input data hold time tSRMXH 0 — CL = 50 pF Unit ns tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH 20/27 FEDL66525-02 OKI Semiconductor ML66525 Family Slave mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Symbol Condition Min. Max. tcyc fOSC = 24 MHz 41.67 — Serial clock cycle time tSCKC 400 — Output data setup time tSTMXS 70 — Output data hold time tSTMXH 180 — CL = 50 pF Input data setup time tSRMXS 21 — Input data hold time tSRMXH 7 — Unit ns tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) tSRMXS tSRMXH Measurement points for AC timing (except the serial port) VDD_IO 0V 0.44VDD_IO 0.44VDD_IO 0.16VDD_IO 0.16VDD_IO Measurement points for AC timing (the serial port) VDD_IO 0V 0.8VDD_IO 0.8VDD_IO 0.2VDD_IO 0.2VDD_IO 21/27 FEDL66525-02 OKI Semiconductor ML66525 Family A/D Converter Characteristics (Ta = –30 to +70°C, VREF = 2.4 to 3.6 V, AGND = GND = 0 V) Parameter Symbol Condition Min. Typ. Max. Unit n Refer to measurement circuit 1 — 10 — Bit — Resolution Linearity error EL Differential Linearity error ED Zero scale error EZS — ±3 Analog input source impedance — — ±2 — — +3 — — –3 LSB Full-scale error EFS RI ≤ 5 kΩ Cross talk ECT Refer to measurement circuit 2 — — ±1 tCONV Set according to ADTM set data 16 — 3906.3 Conversion time Reference voltage VREF 0.1 µF – + 47 µF VDD_IO µs/ch +3 V + + 0.1 µF RI AI0 to AI3 AGND GND 47 µF 0V Analog input CI RI (impedance of analog input source) ≤ 5 kΩ CI ≅ 0.1 µF Measurement Circuit 1 22/27 FEDL66525-02 OKI Semiconductor – + ML66525 Family 5 kΩ AI0 AI1 Analog input 0.1 µF to Cross talk is the difference between the A/D conversion results when the same analog input is applied to AI0 through AI3 and the A/D conversion results of the circuit to the left. AI3 VREF or AGND Measurement Circuit 2 Definition of Terminology 1. Resolution Resolution is the value of minimum discernible analog input. With 10 bits, since 210 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible. 2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit A/D converter (not including quantization error). Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024 equal steps. 3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF – AGND) ÷ 1024. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000H to 001H. 5. Full-scale error Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3FEH to 3FFH. 23/27 FEDL66525-02 OKI Semiconductor ML66525 Family PACKAGE DIMENSIONS (Unit: mm) TQFP100-P-1414-0.50-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.55 TYP. 4/Oct. 28, 1996 Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/27 FEDL66525-02 OKI Semiconductor ML66525 Family PACKAGE DIMENSIONS (Unit: mm) P-LFBGA144-1111-0.80 5 Package material Ball material Package weight (g) Rev. No./Last Revised Epoxy resin Sn/Pb 0.30 TYP. 1/Aug. 25, 1999 Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/27 FEDL66525-02 OKI Semiconductor ML66525 Family REVISION HISTORY Document No. PEDL66525-01 PEDL66525-02 Date Oct. 2000 Mar. 2001 Page Previous Current Edition Edition – – Description – Preliminary edition 1 – - Modified contents of P3_2 and P3_3 in the table on Page 8. - Added contents of P9_0 in the table on Page 9. - Modified contents of PUCTL in the table on Page 10. - Partially added contents of “ABSOLUTE MAXIMUM RATINGS”. - Partially added contents of “RECOMMENDED OPERATING CONDITIONS”. - Partially added contents of “ALLOWABLE OUTPUT CURRENT VALUES”. - Partially added contents of “INTERNAL FLASH ROM PROGRAMMING CONDITIONS”. - Partially added contents of “ELECTRICAL CHARACTERISTICS”. FEDL66525-01 Oct. 2001 – – FEDL66525-02 Jul. 19, 2002 – – - Changed the name from ML66525 to ML66525A. - Changed the name from ML66Q525 to ML66Q525A. - Modified supply current values for ML66Q525 on Page 14. - Modified contents of the table on Page 21. - Changed the name from ML66525A to ML66525B. - Changed the name from ML66Q525A to ML66Q525B. 26/27 FEDL66525-02 OKI Semiconductor ML66525 Family NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 27/27