IDT7164S IDT7164L CMOS STATIC RAM 64K (8K x 8-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High-speed address/chip select access time — Military: 20/25/30/35/45/55/70/85ns (max.) — Commercial: 15/20/25/35/70ns (max.) • Low power consumption • Battery backup operation — 2V data retention voltage (L Version only) • Produced with advanced CMOS high-performance technology • Inputs and outputs directly TTL-compatible • Three-state outputs • Available in: — 28-pin DIP and SOJ • Military product compliant to MIL-STD-883, Class B The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K x 8. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. Address access times as fast as 15ns are available and the circuit offers a reduced power standby mode. When CS1 goes HIGH or CS2 goes LOW, the circuit will automatically go to, and remain in, a low-power stand by mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ; and 28-pin 600 mil DIP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM A0 V CC GND 65,536 BIT ADDRESS DECODER MEMORY ARRAY A12 7 0 I/O 0 I/O CONTROL I/O 7 CS 1 CS 2 CONTROL OE LOGIC 2967 drw 01 WE The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. MAY 1996 2967/8 6.1 1 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS NC A 12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GND 1 28 2 27 3 26 4 25 5 24 D28-1 6 23 V CC WE CS2 A8 A9 A 11 7 D28-3 22 OE 8 P28-1 21 A 10 P28-2 20 9 10 19 SO28-5 11 12 18 17 13 16 14 15 TRUTH TABLE(1,2,3) WE CS1 CS1 Function X H X X High-Z Deselected – Standby (ISB) X L X High-Z Deselected – Standby (ISB) X High-Z Deselected –Standby (ISB1) High-Z Deselected –Standby (ISB1) Output Disabled VHC VHC or VLC X X VLC X H L H H High-Z H L H L DataOUT Read Data L L H X DataIN Write Data NOTES: 1. CS2 will power-down CS1, but CS1 will not power-down CS2. 2. H = VIH, L = VIL, X = don't care. 3. VLC = 0.2V, VHC = VCC - 0.2V 2967 drw 02 DIP/SOJ TOP VIEW I/O X X I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 OE CS2 2967 tbl 02 PIN DESCRIPTIONS Name Description A0–A12 Address I/O0–I/O7 Data Input/Output CS1 Chip Select CS2 Chip Select WE OE RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Write Enable Output Enable GND VCC Ground Grade Temperature GND VCC Power Military –55°C to +125°C 0V 5V ± 10% Commercial 0°C to +70°C 0V 5V ± 10% 2967 tbl 01 2967 tbl 04 ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Com’l. Mil. Unit Terminal Voltage with Respect to GND –0.5 to +7.0 –0.5 to +7.0 V TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C Symbol TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.0 1.0 W VIH Input HIGH Voltage 2.2 VIL Input LOW Voltage –0.5(1) (2) VTERM IOUT DC Output Current 50 50 RECOMMENDED DC OPERATING CONDITIONS mA Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V — VCC + 0.5 V — 0.8 V NOTE: 2967 tbl 05 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. NOTES: 2967 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. 6.1 2 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 0V 8 pF VOUT = 0V 8 pF NOTE: 2967 tbl 06 1. This parameter is determined by device characterization, but is not production tested. DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) Symbol Parameter 7164S15 7164S20 7164S25 7164S30 7164L15 7164L20 7164L25 7164L30 Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit 100 110 90 110 — 100 mA — 90 100 80 100 — 90 — 170 180 170 180 — 170 150 — 150 160 150 160 — 150 20 — 20 20 20 20 — 20 ICC1 Operating Power Supply Current, CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = 0(3) S 110 — L 100 ICC2 Dynamic Operating Current CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = fMAX(3) S 180 L ISB Standby Power Supply Current (TTL Level), CS1 ≥ VIH or CS2 ≤ VIL VCC = Max., Outputs Open, f = fMAX(3) S L 3 — 3 5 3 5 — 5 ISB1 Full Standby Power Supply Current (CMOS Level), f = 0(3), VCC = Max. 1. CS1 ≥ V HC and CS2 ≥ V HC, or 2. CS2 ≤ VLC S 15 — 15 20 15 20 — 20 L 0.2 — 0.2 1 0.2 1 — 1 mA mA mA DC ELECTRICAL CHARACTERISTICS(1) (Continued) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 7164S35 7164L35 Symbol ICC1 ICC2 ISB ISB1 Parameter Power Com’l. Mil. 7164S45 7164L45 7164S55 7164L55 7164S70(2)/85(4) 7164L70(2)/85(4) Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit mA Operating Power Supply Current, CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = 0(3) S 90 100 — 100 — 100 90 100 L 80 90 — 90 — 90 80 90 Dynamic Operating Current CS1 = VIL, CS2 = VIH, Outputs Open, VCC = Max., f = fMAX(3) S 150 160 — 160 — 160 150 160 L 130 140 — 130 — 125 130 120 Standby Power Supply Current (TTL Level), CS1 ≥ V IH, or CS2 ≤ VIL VCC = Max., Outputs Open, f = fMAX(3) S 20 20 — 20 — 20 20 20 L 3 5 — 5 — 5 3 5 Full Standby Power Supply Current (CMOS Level), f = 0(3), VCC = Max. 1. CS1 ≥ VHC and CS2 ≥ VHC, or 2. CS2 ≤ VLC S 15 20 — 20 — 20 15 20 L 0.2 1 — 1 — 1 0.2 1 NOTES: 1. All values are maximum guaranteed values. 2. 70 ns available in both military and commercial devices. 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 4. Also available: 100ns military devices. 6.1 mA mA mA 2967 tbl 07 3 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%) IDT7164S Symbol Parameter Min. Max. Min. Max. Unit VCC = Max., VIN = GND to VCC MIL. COM’L. — — 10 5 — — 5 2 µA Output Leakage Current VCC = Max., CS1 = VIH, VOUT = GND to VCC MIL. COM’L. — — 10 5 — — 5 2 µA Output Low Voltage IOL = 8mA, VCC = Min. 0.4 — 0.4 V |ILI| Input Leakage Current |ILO| VOL VOH Test Condition IDT7164L Output High Voltage IOL = 10mA, VCC = Min. — 0.5 — 0.5 IOH = –4mA, VCC = Min. 2.4 — 2.4 — V 2967 tbl 08 DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V) Typ. (1) VCC @ Symbol Parameter Test Condition VDR VCC for Data Retention ICCDR Data Retention Current tCDR(3) Chip Deselect to Data Retention Time 1. CS1 ≥ VHC CS2 ≥ VHC, or tR(3) Operation Recovery Time 2. CS2 ≤ VLC (3) |ILI| — MIL. COM’L. Input Leakage Current Max. VCC @ Min. 2.0v 3.0V 2.0V 3.0V Unit 2.0 — — — — V — — 10 10 15 15 200 60 300 90 µA 0 — — — — ns tRC(2) — — — — ns — — — 2 2 NOTES: 1. TA = +25°C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. µA 2967 tbl 09 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2967 tbl 10 5V 5V 480Ω 480Ω DATA OUT DATA OUT 255Ω 255Ω 30pF* 2967 drw 03 5pF* 2967 drw 04 Figure 2. AC Test Load (for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ) Figure 1. AC Test Load *Includes scope and jig capacitances 6.1 4 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 7164S15(1) 7164L15(1) Symbol Parameter 7164S20 7164L20 7164S25 7164L25 7164S30(2) 7164L30 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle Time 15 — 20 — 25 — 30 — ns Read Cycle tRC tAA Address Access Time — 15 — 19 — 25 — 29 ns tACS1 (3) Chip Select-1 Access Tim — 15 — 20 — 25 — 30 ns tACS2 (3) Chip Select-2 Access Time — 20 — 25 — 30 — 35 ns Chip Select-1, 2 to Output in Low-Z 5 — 5 — 5 — 5 — ns tOE Output Enable to Output Valid — 7 — 8 — 12 — 15 ns tOLZ(4) Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns Chip Select-1, 2 to Output in High-Z — 8 — 9 — 13 — 13 ns Output Disable to Output in High-Z — 7 — 8 — 10 — 12 ns tCLZ1,2 (4) tCHZ1,2 tOHZ (4) (4) tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns tPU (4) Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns tPD (4) Chip Deselect to Power Down Time — 15 — 20 — 25 — 30 ns Write Cycle tWC Write Cycle Time 15 — 20 — 25 — 30 — ns tCW1, 2 Chip Select to End-of-Write 14 — 15 — 18 — 22 — ns tAW Address Valid to End-of-Write 14 — 15 — 18 — 22 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 14 — 15 — 21 — 23 — ns tWR1 Write Recovery Time (CS1, WE) 0 — 0 — 0 — 0 — ns tWR2 Write Recovery Time (CS2) 5 — 5 — 5 — 5 — ns tWHZ(4) Write Enable to Output in High-Z — 6 — 8 — 10 — 12 ns tDW Data to Write Time Overlap 8 — 10 — 13 — 13 — ns tDH1 Data Hold from Write Time (CS1, WE) 0 — 0 — 0 — 0 — ns tDH2 Data Hold from Write Time (CS2) 5 — 5 — 5 — 5 — ns tOW(4) Output Active from End-of-Write 4 — 4 — 4 — 4 — NOTES: 1. 0° to +70°C temperature range only. 2. –55°C to +125°C temperature range only. Also available: 100ns military devices. 3. Both chip selects must be active for the device to be selected. 4. This parameter is guaranteed by device characterization, but is not production tested. 6.1 ns 2967 tbl 11 5 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Continued) (VCC = 5.0V ± 10%, All Temperature Ranges) 7164S35 7164L35 Symbol Parameter 7164S45(2) 7164L45(2) 7164S55(2) 7164L55(2) 7164S70/85(2) 7164L70/85(2) Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle Time 35 — 45 — 55 — 70/85 — ns Read Cycle tRC tAA Address Access Time — 35 — 45 — 55 — 70/85 ns tACS1 (3) Chip Select-1 Access Time — 35 — 45 — 55 — 70/85 ns tACS2 (3) Chip Select-2 Access Time — 40 — 45 — 55 — 70/85 ns Chip Select-1, 2 to Output in Low-Z 5 — 5 — 5 — 5 — ns Output Enable to Output Valid — 18 — 25 — 30 — 35/40 ns Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns Chip Select-1, 2 to Output in High-Z — 15 — 20 — 25 — 30/35 ns Output Disable to Output in High-Z — 15 — 20 — 25 — 30/35 ns tCLZ1,2 (4) tOE tOLZ (4) tCHZ1,2 tOHZ (4) (4) tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns tPU (4) Chip Select to Power Up Time 0 — 0 — 0 — 0 — ns tPD (4) Chip Deselect to Power Down Time — 35 — 45 — 55 — 70/85 ns Write Cycle tWC Write Cycle Time 35 — 45 — 55 — 70/85 — ns tCW1, 2 Chip Select to End-of-Write 25 — 33 — 50 — 60/75 — ns tAW Address Valid to End-of-Write 25 — 33 — 50 — 60/75 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 25 — 25 — 50 — 60/75 — ns tWR1 Write Recovery Time (CS1, WE) 0 — 0 — 0 — 0 — ns tWR2 Write Recovery Time (CS2) 5 — 5 — 5 — 5 — ns tWHZ(4) Write Enable to Output in High-Z — 14 — 18 — 25 — 30/35 ns tDW Data to Write Time Overlap 15 — 20 — 25 — 30/35 — ns tDH1 Data Hold from Write Time (CS1, WE) 0 — 0 — 0 — 0 — ns tDH2 Data Hold from Write Time (CS2) 5 — 5 — 5 — 5 — ns tOW(4) Output Active from End-of-Write 4 — 4 — 4 — 4 — NOTES: 1. 0° to +70°C temperature range only. 2. –55°C to +125°C temperature range only. Also available: 100ns military devices. 3. Both chip selects must be active for the device to be selected. 4. This parameter is guaranteed by device characterization, but is not production tested. 6.1 ns 2967 tbl 11 6 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1(1) tRC ADDRESS tAA tOH OE tOE tOLZ (5) CS2 tACS2 tCHZ2 tCLZ2 (5) (5) CS1 tCLZ1 tOHZ (5) tACS1 (5) tCHZ1 DATA OUT (5) DATA VALID 2967 drw 05 (1, 2, 4) TIMING WAVEFORM OF READ CYCLE NO. 2 tRC ADDRESS tAA tOH tOH DATA OUT DATA VALID 2967 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 3 (1, 3, 4) CS1 CS2 tACS2 tCLZ2 (5) tACS1 tCLZ1 (5) DATA OUT tCHZ2 (5) tCHZ1 (5) DATA VALID tPU ICC POWER SUPPLY CURRENT ISB NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.1 tPD 2967 drw 07 7 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 6) tWC ADDRESS CS2 CS1 tWR1(3) tAW tAS WE (6) (4) tOW(7) tWP DATA OUT tDW tWHZ (7) tDH1, 2 DATA IN DATA VALID 2967 drw 08 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2) tWC ADDRESS tAS tWR2 (3) tWR1 (3) CS2 tCW CS1 (5) tAW WE tDW DATA IN tDH1,2 DATA VALID 2967 drw 09 NOTES: 1. WE, CS1 or CS2 must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2. 3. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals must not be applied. 5. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified tWP. 7. Transition is measured ±200mV from steady state. 6.1 8 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE V CC 4.5V 4.5V V DR ≥ 2V tCDR CS V IH tR V IH V DR 2967 drw 10 ORDERING INFORMATION IDT 7164 Device Type X XX XXX X Power Speed Package Process/ Temperature Range 6.1 Blank Commercial (0°C to +70°C) B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B Y TD D P TP 300 mil 300 mil 600 mil 600 mil 300 mil 15 20 25 30 35 45 55 70 85 Commercial Only S L Standard Power Low Power SOJ (SO28-5) CERDIP (D28-3) CERDIP (D28-1) Plastic DIP (P28-1) Plastic DIP (P28-2) Military Only Speed in nanoseconds Military Only Military Only Military Only 2967 drw 11 9