AD AD9071 10-bit, 100 msps a/d converter Datasheet

a
FEATURES
10-Bit, 100 MSPS ADC
Low Power: 450 mW at 100 MSPS
On-Chip Track/Hold
280 MHz Analog Bandwidth
SINAD = 54 dB @ 41 MHz
On-Chip Reference
1 V p-p Analog Input Range
Single +5 V Supply Operation
+5 V/+3.3 V Outputs
APPLICATIONS
Digital Communications
Signal Intelligence
Digital Oscilloscopes
Spectrum Analyzers
Medical Imaging
Sonar
HDTV
GENERAL DESCRIPTION
The AD9071 is a monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and TTL/CMOS
digital interfaces. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full
operating range.
The ADC requires only a single 5 V supply and an encode clock
for full performance operation. The digital outputs are TTL
compatible. Separate output power supply pins support
10-Bit, 100 MSPS
A/D Converter
AD9071
FUNCTIONAL BLOCK DIAGRAM
VREF
OUT
VREF
IN
VCC – 2.5V
AD9071
VDD
AIN
ADC
T/H
AIN
SUM
AMP
DAC
10
D0–D9
ENCODE
LOGIC
OR
ADC
ENCODE
TIMING
VCC
GND
interfacing with 3.3 V or 5 V logic. An out-of-range output
(OR) is available that indicates a conversion result is outside the
operating range. The output data are held at saturation levels
during an out-of-range condition.
The input amplifier supports differential or single-ended interfaces. An internal reference is included.
Fabricated on an advanced BiCMOS process, the AD9071 is
available in a plastic SOIC package specified over the industrial
temperature range (–40°C to +85°C).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
(VCC = +5 V, VDD = +3.3 V, Differential Analog Input, ENCODE = 100 MSPS unless
AD9071–SPECIFICATIONS otherwise noted)
Parameter
Temp
Test
Level
Min
AD9071BR
Typ
RESOLUTION
DC ACCURACY
Differential Nonlinearity1
10
± 0.8
± 1.0
± 0.8
± 1.25
Guaranteed
±1
±2
150
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
Full
I
VI
I
VI
I
I
VI
V
Full
Full
+25°C
Full
Full
+25°C
+25°C
Full
+25°C
V
V
I
VI
VI
V
I
VI
V
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Full
Full
VI
V
VCC – 2.6
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (tEH)
Encode Pulsewidth Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)3
Output Propagation Delay (tPD)3
Output Rise Time (tR)
Output Fall Time (tF)
Full
Full
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
VI
IV
IV
IV
V
V
VI
VI
V
V
100
DIGITAL INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
+25°C
VI
VI
VI
VI
V
2.0
Full
Full
VI
VI
VDD – 0.5
Integral Nonlinearity1
No Missing Codes1
Gain Error2
Gain Tempco2
ANALOG INPUT
Input Voltage Range
(With Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
Input Resistance
Input Capacitance
Input Bias Current
Analog Bandwidth, Full Power
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
POWER SUPPLY
VCC Supply Current (VCC = 5 V)4
VDD Supply Current (VDD = 3.3 V)4
Power Dissipation4
Power Supply Sensitivity5
Max
␣␣␣␣␣␣
15
Bits
+1.5/–1.0
+1.75/–1.0
± 1.5
± 1.75
␣␣␣
±4
±8
LSB
LSB
LSB
LSB
% FS
% FS
ppm/°C
± 512
–2.5 ± 0.2
±4
± 18
±5
± 20
35
3
55
90
65
115
280
mV p-p
V
mV
mV
kΩ
pF
µA
µA
MHz
VCC – 2.5
130
V
ppm/°C
VCC – 2.4
40
13
13
4.5
4.5
1.1
3.0
4.0
5.0
1.4
1.0
2.0
Units
7.0
0.8
± 10
–500
3
MSPS
MSPS
ns
ns
ns
ps, rms
ns
ns
ns
ns
V
V
µA
µA
pF
0.05
V
V
115
14
620
0.010
mA
mA
mW
V/V
Offset Binary
Full
Full
Full
+25°C
VI
VI
VI
I
–2–
85
7.5
450
0.002
REV. B
AD9071
Parameter
Temp
Test
Level
+25°C
+25°C
V
V
+25°C
Full
+25°C
Full
I
V
I
V
54
+25°C
Full
+25°C
Full
I
V
I
V
54
+25°C
+25°C
I
I
+25°C
+25°C
Min
AD9071BR
Typ
Max
Units
6
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = 41 MHz
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz
fIN = 41 MHz
Effective Number of Bits
fIN = 10.3 MHz
fIN = 41 MHz
2nd Harmonic Distortion
fIN = 10.3 MHz
fIN = 41 MHz
3rd Harmonic Distortion
fIN = 10.3 MHz
fIN = 41 MHz
Two-Tone Intermodulation (IMD)
fIN = 10.3 MHz
fIN = 41 MHz
4
5
ns
ns
56
55
55
54
dB
dB
dB
dB
56
55
54
53
dB
dB
dB
dB
8.8
8.5
9.2
8.8
Bits
Bits
I
I
63
60
75
66
dBc
dBc
+25°C
+25°C
I
I
65
57
75
65
dBc
dBc
+25°C
+25°C
V
V
70
60
dBc
dBc
53
52
NOTES
1
Differential and integral nonlinearity based on F S = 80 MSPS.
2
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
3
tV and tPD are measured from the threshold crossing of the ENCODE input to the 50% levels of the digital outputs. The output ac load during test is 5 pF.
4
Power dissipation is measured under the following conditions: F S @ 100 MSPS, analog input is –1 dBFS at 10.3 MHz.
5
A change in input offset voltage with respect to a change in V CC.
6
SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range.
Typical thermal impedance for the R style (SOIC) 28-lead package: θJC = 23°C/W, θCA = 48°C/W, θJA = 71°C/W.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Test Level
VCC␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150°C
I.
100% production tested.
II. 100% production tested at +25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
VI. 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature range.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9071 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
WARNING!
ESD SENSITIVE DEVICE
AD9071
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9071BR
AD9071/PCB
–40°C to +85°C
+25°C
28-Lead Wide Body (SOIC)
Evaluation Board
R-28
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1, 7, 12, 21, 23
2, 8, 11
3
4
5, 6
9
10
13
14
GND
VCC
VREF OUT
VREF IN
DNC
AIN
AIN
ENCODE
OR
15–19, 24–28
20, 22
D9–D0
VDD
Ground.
Analog Power Supply. Nominally 5.0 V. (Tie together to prevent a possible latch-up condition.)
Internal Reference Output (VCC – 2.5 V typical); Bypass with 0.1 µF to VCC.
Reference Input for ADC (VCC – 2.5 V typical).
Do Not Connect.
Analog Input – Complementary.
Analog Input – True.
Encode clock for ADC. (ADC Samples on Rising Edge of ENCODE.)
Out-of-Range Output. Goes HIGH when the converted sample is more positive than
3FFH or more negative than 000H (offset binary coding).
Digital outputs of ADC. D9 is the MSB. Data is offset binary.
Digital Output Power Supply. User selectable range from 3 V to 5 V.
PIN CONFIGURATION
GND 1
28 D0
VCC 2
27 D1
VREF OUT
3
26 D2
VREF IN
4
25 D3
DNC
5
24 D4
DNC
6
AD9071BR 23 GND
GND
7
TOP VIEW 22 VDD
(Not to Scale)
21 GND
VCC 8
AIN 9
20 VDD
AIN 10
19 D5
VCC 11
18 D6
GND 12
17 D7
ENCODE 13
16 D8
OR 14
Table I. Output Coding
15 D9 (MSB)
DNC = DO NOT CONNECT
–4–
Code
AIN–AIN
Offset
Binary
OR
1023
1023
1022
•
•
•
513
512
511
•
•
•
1
0
0
≥ 0.512 V
0.511 V
0.510 V
•
•
•
0.001 V
0.000 V
–0.001 V
•
•
•
–0.511 V
–0.512 V
≤–0.513 V
11 1111 1111
11 1111 1111
11 1111 1110
•
•
•
10 0000 0001
10 0000 0000
01 1111 1111
•
•
•
00 0000 0001
00 0000 0000
00 0000 0000
1
0
0
•
•
•
0
0
0
•
•
•
0
0
1
REV. B
AD9071
SAMPLE N–1
SAMPLE N
SAMPLE N+3
SAMPLE N+4
AIN
SAMPLE N+1
tA
tEH
tEL
SAMPLE N+2
1/f s
ENCODE
tPD
D9–D0
DATA N–4
DATA N–3
DATA N–2
DATA N–1
tV
DATA N
DATA N+1
Figure 1. Timing Diagram
VDD
VCC
AIN
AIN
D9–0, OR
Figure 2. Equivalent Analog Input Circuit
Figure 5. Equivalent Digital Output Circuit
VCC
VCC
VREF
OUT
VREF IN
Figure 3. Equivalent Reference Input Circuit
Figure 6. Equivalent Reference Output Circuit
VCC
ENCODE
Figure 4. Equivalent Encode Input Circuit
REV. B
–5–
AD9071–Typical Performance Characteristics
0
0
FUNDAMENTAL = –1.0dBFS
SNR = 56.75dB
SINAD = 56.56dB
2ND HARMONIC = –71.88dB
3RD HARMONIC = –77.28dB
–10
–20
–30
–30
–40
–40
dB
dB
–20
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
F1 = 41.1MHz
F2 = 42.1MHz
F1 = F2 = –7.0dBFS
–10
50
0
50
MHz
MHz
Figure 7. Spectrum: FS = 100 MSPS, fIN = 10.3 MHz
Figure 10. Two-Tone Intermodulation Distortion
0
60
FUNDAMENTAL = –1.0dBFS
SNR = 55.23dB
SINAD = 54.35dB
2ND HARMONIC = –68.28dB
3RD HARMONIC = –62.83dB
–10
58
56
–30
54
–40
52
dB
dB
–20
–50
50
–60
48
–70
46
–80
44
–90
42
–100
40
0
SNR
50
SINAD
10
20
40
MHz
120
140
58
0
57
F1 = 9.63MHz
F2 = 10.63MHz
F1 = F2 = –7.0dBFS
–10
–20
56
SNR
55
–30
54
dB
–40
dB
100
Figure 11. SINAD/SNR vs. f IN: FS = 100 MSPS
Figure 8. Spectrum: FS = 100 MSPS, fIN = 41 MHz
–50
SINAD
53
52
–60
51
–70
50
–80
49
–90
–100
60
80
fIN – MHz
0
48
10
50
MHz
20
40
60
80
F S – MSPS
100
120
140
Figure 12. SINAD/SNR vs. FS: fIN = 10.3 MHz
Figure 9. Two-Tone Intermodulation Distortion
–6–
REV. B
AD9071
60
60
58
SNR
SNR
56
SINAD
SINAD
55
54
dB
dB
52
50
50
48
46
45
44
42
40
–40
–15
5
55
25
40
2.5
85
3.5
4.5
5.5
ENCODE PULSEWIDTH – ns
TC
Figure 13. Differential SNR vs. TC: fIN = 10.3 MHz
6.5
7.5
Figure 15. SNR vs. Clock Pulsewidth (tEH): fIN = 10.3 MHz
0
60
SNR
58
–1
56
SINAD
–2
54
–3dB ROLLOFF POINT
–3
dB
dB
52
50
–4
48
46
–5
44
–6
42
40
–40
–15
5
55
25
–7
85
15
60
105
150
TC
Figure 14. Single-Ended SNR vs. TC: fIN = 10.3 MHz
80
DIFFERENTIAL INPUT
70
dBc
60
SINGLE-ENDED
50
40
30
20
10
20
30
40
fIN – MHz
Figure 17. Second Harmonic Performance: SingleEnded vs. Differential Input
REV. B
285
330
Figure 16. Frequency Response
90
0
10
195
240
fIN – MHz
–7–
375
420
AD9071
APPLICATION NOTES
comparators detect when the analog input signal is out of this
range, and set the OR output signal HIGH. The digital outputs
are locked at plus or minus full scale (3FFH or 200H) for voltages that are out of range, but between 1 V and 5 V. Input voltages outside of this range may result in invalid codes at the
ADC’s output.
THEORY OF OPERATION
The AD9071 employs a two-step subranging architecture with
digital error correction.
The sampling and conversion process is initiated by a rising edge
at the ENCODE input. The analog input signal is buffered by a
high speed differential amplifier and applied to a track-and-hold
(T/H) circuit, which captures the value of the input at the sampling instant and maintains it for the duration of the conversion.
VREF (+2.5V)
100V
AIN
50V
AD9071
0.1mF
AIN
25V
Figure 19. Single-Ended Analog Input Configuration
Data are strobed to the output on the rising edge of the ENCODE
input, with the data from sample N appearing on the output
following ENCODE rising edge N+3.
When the analog input signal returns to the nominal range, the
out-of-range comparators return the ADC to its active mode
and the device recovers in the overvoltage recovery time.
Voltage Reference
USING THE AD9071
ENCODE Input
A stable and accurate 2.5 V voltage reference (VCC – 2.5 V) is
built into the AD9071 (VREF OUT). In normal operation, the
internal reference is used by strapping Pins 3 and 4 of the AD9071
together. The internal reference can provide 100 µA of extra
drive current that may be used for other circuits.
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the ENCODE input of the AD9071, and
the user is advised to give commensurate thought to the clock
source. The lowest jitter clock source is a crystal oscillator producing a pure sine wave.
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9071, which cannot be obtained by using the internal reference. For these applications, an external 2.5 V reference can be
connected to VREF IN, which requires 5 µA of drive current
(see Figure 20).
The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs
+5V
The digital outputs are CMOS compatible for lower power
consumption. 200 Ω series resistors are recommended between
the AD9071 and the receiving logic to reduce transients and
improve SNR.
AD780
+5V
+VIN
Analog Input
1MV
TRIM
NC = NO CONNECT
Figure 20. Using the AD780 Voltage Reference
The input range can be adjusted by varying the reference voltage applied to the AD9071. No appreciable degradation in
performance occurs when the reference is adjusted ± 4%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
100V
0.1mF
AIN
0.1mF
25kV
NC
VREF (+2.5V)
50V
AD9071
VREF IN
O/P SELECT
The analog input has been optimized for differential signal
input.
100V
0.1mF
VOUT
1mF
GND
T1A
T1 - 1T
100V
0.1mF
The coarse quantizer (ADC) produces a 5-bit estimate of the
input value. Its digital output is reconverted to analog form by
the reconstruction DAC and subtracted from the input signal in
the SUM AMP. The second stage quantizer generates a 6-bit
representation of the difference signal. The eleven bits are presented to the ENCODE LOGIC, which corrects for range overlap errors and produces an accurate 10-bit result.
AD9071
AIN
Timing
The performance of the AD9071 is insensitive to the duty
cycle of the clock over a wide range of operating conditions
(see Figure 15).
Figure 18. Differential Analog Input Configuration
If driven single-endedly, the AIN should be connected to a
clean reference and bypassed to ground. For best dynamic
performance, impedances at AIN and AIN should match.
The AD9071 provides latched data outputs, with three pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Figure 1). The
length of the output data lines, and loads placed on them, should
be minimized to reduce transients within the AD9071; these
transients can detract from the converter’s dynamic performance.
Special care was taken in the design of the analog input section
of the AD9071 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +1.988 V to
+3.012 V (1.024 V p-p centered at +2.5 V). Out-of-range
–8–
REV. B
AD9071
resistor on Data Ready (R33), normally 0 ohms, is provided to
support various user output impedance configurations. The
AD9760 DAC supports viewing reconstructed A/D data at J4.
The minimum guaranteed conversion rate of the AD9071 is
40 MSPS. At clock rates below 40 MSPS, dynamic performance
may degrade. The AD9070 will operate in bursts, but the user
must flush the internal pipeline each time the clock restarts.
Valid data will be produced on the fourth rising edge of the
ENCODE signal after the clock is restarted.
Voltage Reference
The AD9071 can be operated using its internal voltage reference (connect E2 to E3) or an optional external reference (connect E1 to E2). The board is shipped utilizing the internal
voltage reference.
EVALUATION BOARD
The AD9071 evaluation board is a convenient and easy way to
evaluate the performance of the AD9071 in the SOIC package.
The board consists of an internal voltage reference or an optional external reference, two 74LCX574 latches for capturing
data from the A/D converter, and an AD9760 DAC for viewing
reconstructed A/D data. The AD9071 output logic can be driven
at 5 V and 3.3 V levels. The latches are set up at 3.3 V but are
5 V tolerant. Test points are provided at Encode, DB9, DB0,
Data Ready, and Data Clock. All are clearly labeled.
Layout
The AD9071 is not layout sensitive if some important guidelines
are met. The evaluation board layout provides an example where
these guidelines have been followed to optimize performance.
• Provide a good ground plane connecting the analog and
digital sections.
• Excellent bypassing is essential. Chip capacitors with 0.1 µF
values and 0803 dimensions are placed flush against the pins.
Placing any of the capacitors on the bottom of the board can
degrade performance. These techniques reduce the amount
of parasitic inductance that can impact the bypassing ability
of the caps.
Analog Input
The evaluation board can be driven single-ended or differentially. Differential input requires using a 1:1 transformer. For
single-ended operation (J2), Jumper S5 is connected to S8 and
S6 is connected to S7. For differential input operation (J3), S5
is connected to S3 and S4 is connected to S6. The board is
shipped in the differential configuration.
• Separate power planes and supplies for the analog and digital
sections are recommended.
The AD9071 evaluation board is provided as a design example
for customers of Analog Devices. ADI makes no warranties
express, statutory, or implied regarding merchantability or fitness for a particular purpose.
Encode
The AD9071 encode inputs are driven single-ended into J1 and
are at TTL logic levels.
Data Out
The data delivered out of the AD9071 is in offset binary format
at TTL levels. The Data Ready signal can be inverted by opening the S1 and S2 connections. An optional series termination
Figure 21. Printed Circuit Board Top Side Silkscreen
REV. B
Figure 22. Printed Circuit Board Bottom Side Silkscreen
–9–
AD9071
Figure 23. Printed Circuit Board Top Side Copper
Figure 25. Printed Circuit Board “Split” Power Layer
Figure 24. Printed Circuit Board Ground Layer
Figure 26. Printed Circuit Board Bottom Side Copper
–10–
REV. B
REV. B
R5
50V
Figure 27. Printed Circuit Board Schematic
–11–
TB6
TB1
C1
0.1mF
5
4
C8
0.1mF
C15
0.1mF
C21
10mF
C17
0.1mF
6
8
9
10
3
DATA CLK
ENCODE
R32
25V
C3
0.1mF
C11
0.1mF
C6
0.1mF
TP4
C2
0.1mF
C12
0.1mF
C18
10mF
VCC
13
10
9
6
5
4
3
+VD
VDD
VCC
TP5
OR
+VD
28
9
14
27
26
25
24
19
18
17
16
15
28
8
7
R3
200V
6
TP2
R18
200V
5
R17
200V
R16
200V
R15
200V
R14
200V
R13
200V
R12
200V
R11
200V
R10
200V
4
3
2
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
Q7
1
+VD
AD9760
C14
0.1mF
C9
0.1mF
R2
2kV
C10
0.1mF
11
12
13
14
15
16
17
18
19
11
12
13
14
15
16
17
18
19
21
22
S12
S13
IOUTB
IOUTA
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
R34
150V
GND : 10
+VD : 20
CLOCK
Q6
D7
Q5
D6
D5
Q4
Q3
D3
D4
Q2
Q1
Q0
D2
D1
D0
OUT EN
U2
74LCX574
GND : 10
+VD : 20
DVDD AVDD COMP2 COMP1 FSADJ REFIO REFLO SLEEP
19
17
16
18
27
23
24
15
CLK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLOCK
D7
D6
D5
D4
D3
D2
D1
D0
OUT EN
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9
10
VCC : 2, 8, 11
VDD : 20, 22
GND : 1, 7 12, 21, 23
ENCODE
AIN
AIN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
TP3
U3
AD9071
DNC
DNC
VREF IN
VREF OUT
C13
0.1mF
TP1
ANALOG IN
R19
100V
ANALOG IN
VREF
VREF INT
DATA READY
C22
0.1mF
GND
11
+ VD : 14
GND : 7
U5
74LCX86
S7
S6
S10
R1
S5 100V
S8
1
1
12
13
1
2
C4
0.1mF
S4
S9
C5
0.1mF S3
VREF EXT
C17
0.1mF
C20
10mF
+VD
VDD
VCC
GND
+VD
R31
4.99kV
S2
S1
R6
50V
ENCODE IN
C19
10mF
6
5
4
3
2
1
J1
2, 3, 4,
5 - GND
SMB
1
T1 – 1T
6
SMB A IN DIF
T1
J3
3
4
R4
2, 3, 4,
50V
2
5 - GND
SMB
A IN
J2
2, 3, 4,
5 - GND
C7
0.1mF
VREF EXT
E2
E1
1
E3
R9
200V
U1
74LCX574
S11
R7
50V
+VD
DATABIT 0
R30
100V
R28
100V
R29
100V
R20
100V
R21
100V
R22
100V
R23
100V
R24
100V
R25
100V
R8
50V
SNS
J4
2, 3, 4,
5, - GND
J5
+VD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R36
150V
R33
0V
OVERRANGE
DATABIT 9
DATABIT 8
DATABIT 7
DATABIT 6
DATABIT 5
DATABIT 4
DATABIT 3
DATABIT 2
R26
100V DATABIT 1
R27
100V
DATA READY
OR
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DAC OUT
R35
150V
OR
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 P2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
DATABIT 0
DATABIT 1
DATABIT 2
DATABIT 3
DATABIT 4
DATABIT 5
DATABIT 6
DATABIT 7
DATABIT 8
DATABIT 9
OVERRANGE
DATA READY
GND
R37
150V
GND
GND
C37DPPF
AD9071
AD9071
Table II.␣ Printed Circuit Board Bill of Materials
Item #
Quantity
Reference
Description
1
18
Ceramic Chip Capacitor, 0603, 0.1 µF
2
3
4
5
6
7
4
3
4
1
1
13
8
9
1
11
10
11
12
13
14
15
5
1
1
1
4
13
16
17
1
1
C1, C2, C3, C4, C5, C6, C7, C8, C9, C10,
C11, C12, C13, C14, C15, C16, C17, C22
C18, C19, C20, C21
E1, E2, E3
J1, J2, J3, J4
J5
P2
R1, R19, R20, R21, R22, R23, R24, R25,
R26, R27, R28, R29, R30
R2
R3, R9, R10, R11, R12, R13, R14, R15,
R16, R17, R18
R4, R5, R6, R7, R8
R31
R32
R33
R34, R35, R36, R37
S1, S2, S3, S4, S5, S6, S7, S8, S9, S10,
S11, S12, S13
T1
TB1
18
19
20
21
22
5
2
1
1
1
TP1, TP2, TP3, TP4, TP5
U1, U2
U3
U4
U5
C3331b–0–5/99
Tantalum Chip Capacitor, 10 µF
Jumpers
SMB-P Connector
20-Pin Male Header
37-Pin Connector (Amp 747462-4)
Surface Mount Resistor, 1206, 100 Ω
Surface Mount Resistor, 1206, 2000 Ω
Surface Mount Resistor, 1206, 200 Ω
Surface Mount Resistor, 1206, 50 Ω
Surface Mount Resistor, 1206, 5000 Ω
Surface Mount Resistor, 1206, 25 Ω
Surface Mount Resistor, 1206, 0 Ω
Surface Mount Resistor, 1206, 150 Ω
Jumpers
Surface Mount Transformer Mini-Circuit T1-T1, 1:1 Ratio
6-Pin Wieland Connector (P/N # 25,602, 2653.0; 25.530
3625.0)
Test Points
74LCX574 Octal Latch
AD9071BR, 10-Bit, 100 MSPS, ADC
AD9760AR, 10-Bit, 125 MSPS, DAC
74LCX86, XOR
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide Body SOIC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
0.0138 (0.35)
PLANE
–12–
0.0125 (0.32)
0.0091 (0.23)
PRINTED IN U.S.A.
14
0.0291 (0.74)
3 458
0.0098 (0.25)
8°
0°
0.0500 (1.27)
0.0157 (0.40)
REV. B