NM93C06L/C46L/C56L/C66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) (MICROWIRE TM Bus Interface) General Description Features The NM93C06L/C46L/C56L/C66L devices are 256/1024/2048/4096 bits, respectively, of non-volatile electrically erasable memory divided into 16/64/128/256 x 16-bit registers (addresses). The NM93CxxL Family functions in an extended voltage operating range, requires only a single power supply and is fabricated using National Semiconductor’s floating gate CMOS technology for high reliability, high endurance and low power consumption. These devices are available in both SO and TSSOP packages for small space considerations. The EEPROM Interfacing is MICROWIRE compatible for simple interface to standard microcontrollers and microprocessors. There are 7 instructions that control these devices: Read, Erase/Write Enable, Erase, Erase All, Write, Write All, and Erase/Write Disable. The ready/busy status is available on the DO pin during programming. Y Y Y Y Y Y Y Y Y Y 2.7V to 5.5V operation in all modes Typical active current of 100 mA; Typical standby current of 1 mA No erase required before write Reliable CMOS floating gate technology MICROWIRE compatible serial I/O Self-timed programming cycle Device status during programming mode 40 years data retention Endurance: 106 data changes Packages available: 8-pin SO, 8-pin DIP, and 8-pin TSSOP Block Diagram TL/D/10045 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM is a trademark of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/D/10045 RRD-B30M126/Printed in U. S. A. http://www.national.com NM93C06L/C46L/C56L/C66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) (MICROWIRE Bus Interface) November 1996 Connection Diagrams Dual-In-Line Package (N) 8-Pin SO (M8) and 8-Pin TSSOP (MT8) Pin Names TL/D/10045–2 CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground VCC Power Supply Top View NS Package Number N08E, M08A or MTC08 Ordering Information Commercial Temp. Range (0§ C to a 70§ C) Order Number NM93C06LN/NM93C46LN NM93C56LN/NM93C66LN NM93C06LM8/NM93C46LM8 NM93C56LM8/NM93C66LM8 NM93C06LMT8/NM93C46LMT8 NM93C56LMT8/NM93C66LMT8 Extended Temp. Range (b40§ C to a 85§ C) Order Number NM93C06LEN/NM93C46LEN NM93C56LEN/NM93C66LEN NM93C06LEM8/NM93C46LEM8 NM93C56LEM8/NM93C66LEM8 NM93C06LEMT8/NM93C46LEMT8 NM93C56LEMT8/NM93C66LEMT8 Automotive Temp. Range (b40§ C to a 125§ C) Order Number NM93C06LVN/NM93C46LVN NM93C56LVN/NM93C66TLVN NM93C06LVM8/NM93C46LVM8 NM93C56LVM8/NM93C66LVM8 NM93C06LVMT8/NM93C46LVMT8 NM93C56LVMT8/NM93C66LVMT8 http://www.national.com 2 Absolute Maximum Ratings (Note 1) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Ambient Operating Temperature NM93C06L – NM93C66L NM93C06LE – NM93C66LE NM93C06LV – NM93C66LV Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating b 65§ C to a 150§ C 0§ C to a 70§ C b 40§ C to a 85§ C b 40§ C to a 125§ C Power Supply (VCC) Range a 6.5V to b 0.3V 2.7V to 5.5V a 300§ C 2000V DC and AC Electrical Characteristics: 2.7 V k VCC k 4.5V Symbol Max Units Operating Current CS e VIH, SK e 250 kHz 1 mA ICCS Standby Current CS e VIL 10 mA IIL IOL Input Leakage Output Leakage VIN e 0V to VCC g1 mA VIL VIH Input Low Voltage Input High Voltage 0.15 VCC VCC a 1 V VOL VOH Output Low Voltage Output High Voltage fSK SK Clock Frequency 0 tSKH SK High Time 1 ms tSKL SK Low Time 1 ms tSKS SK Setup Time SK Must Be at VIL for tSKS before CS goes high 0.2 ms tCS Minimum CS Low Time (Note 2) 1 ms tCSS CS Setup Time 0.2 ms tDH DO Hold Time 70 ns tDIS DI Setup Time 0.4 ms tCSH CS Hold Time 0 ms tDIH DI Hold Time 0.4 ms tPD1 Output Delay to ‘‘1’’ 2 ms tPD0 Output Delay to ‘‘0’’ 2 ms tSV CS to Status Valid 1 ms tDF CS to DO in TRI-STATEÉ 0.4 ms tWP Write Cycle Time 15 ms ICCA Parameter Part Number Conditions Min b 0.1 0.8 VCC IOL e 10 mA IOH e b10 mA CS e VIL 3 0.1 VCC V 250 kHz 0.9 VCC http://www.national.com DC and AC Electrical Characteristics: 4.5V k VCC k 5.5V Max Units ICCA Symbol Operating Current CS e VIH, SK e 1 MHz 1 mA ICCS Standby Current CS e VIL 50 mA IIL IOL Input Leakage Output Leakage VIN e 0V to VCC (Note 4) g1 mA VIL VIH Input Low Voltage Input High Voltage 0.8 VCC a 1 V VOL1 VOH1 Output Low Voltage Output High Voltage IOL e 2.1 mA IOH e b400 mA VOL2 VOH2 Output Low Voltage Output High Voltage IOL e 10 mA IOL e b10mA fSK SK Clock Frequency tSKH SK High Time tSKL SK Low Time tSKS SK Setup TIme SK Must Be at VIL for tSKS before CS goes high tCS Minimum CS Low Time (Note 2) tCSS tDH tDIS DI Setup Time tCSH tDIH tPD1 Output Delay to ‘‘1’’ 500 ns tPD0 Output Delay to ‘‘0’’ 500 ns tSV CS to Status Valid 500 ns tDF CS to DO in TRI-STATE 100 ns 10 ms tWP Parameter Part Number Conditions Min b 0.1 2 (Note 5) NM93C06L-NM93C66L NM93C06LE-NM93C66LE 0.4 2.4 0.2 VCC b 0.2 0 1 V V MHz 250 300 ns 250 ns 50 ns 250 ns CS Setup Time 50 ns DO Hold Time 70 ns 100 200 ns CS Hold Time 0 ns DI Hold Time 20 NM93C06L-NM93C66L NM93C06LE-NM93C66LE CS e VIL Write Cycle Time http://www.national.com 4 ns Capacitance (Note 3) TA e 25§ C, f e 1 MHz Max Units COUT Symbol Output Capacitance Test Typ 5 pF CIN Input Capacitance 5 pF Note 1: Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle (this is shown in the opcode diagrams in the following pages). Note 3: This parameter is periodically sampled and not 100% tested. Note 4: Typical leakage values are in the 20 nA range. Note 5: The shortest allowable SK clock period e 1/fSK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/tSK e tSKH (minimum) a tSKL (minimum) for shorter SK cycle time operation. AC Test Conditions VIL/VIH Input Levels VIL/VIH Timing Levels VOL/VOH Timing Levels IOL/IOH 2.7V s VCC k 4.5V (Extended Voltage Levels) 0.3V/1.8V 1.0V 0.8V/1.5V g 10 mA 4.5V s VCC s 5.5V (TTL Levels) 0.4V/2.4V 1.0V/2.0V 0.4V/2.4V b 2.1 mA/0.4 mA VCC Range Output Load: 1 TTL Gate (CL e 100 pF) Functional Description instruction. Once an Erase/Write Enable instruction is executed, programming remains enabled until an Erase/Write Disable (WDS) instruction is executed or VCC is completely removed from the part. The NM93C06L/C46L/C56L/C66L device have 7 instructions as described below. Note that the MSB of any instruction is a ‘‘1’’ and is viewed as a start bit in the interface sequence. For the C06 and C46 the next 8 bits carry the op code and the 6-bit address for register selection. For the C56 and C66 the next 10-bits carry the op code and the 8bit address for register selection. Erase (ERASE): The ERASE instruction will program all bits in the selected register to the logical ‘‘1’’ state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip if CS is brought high after the tCS interval. DO e logical ‘‘0’’ indicates that programming is still in progress. DO e logical ‘‘1’’ indicates that the register, at the address specified in the instruction, has been erased, and the part is ready for another instruction. Read (READ): The READ instruction outputs serial data on the DO pin. After a READ instruction is received, the instruction and address are decoded, followed by data transfer from the selected memory register into a 16-bit serial-out shift register. A dummy bit (logical 0) precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. Erase/Write Enable (WEN): When VCC is applied to the part, it powers up in the Erase/ Write Disable (WDS) state. Therefore, all programming modes must be preceded by an Erase/Write Enable WEN 5 http://www.national.com Functional Description (Continued) state. The Erase All cycle is identical to the ERASE cycle except for the different op-code. As in the ERASE mode, the DO pin indicates the READY/BUSY status of the chip if CS is brought high after the tCS interval. Write (WRITE): The WRITE instruction is followed by 16 bits of data to be written into the specificed address. After the last bit of data is put on the data-in (DI) pin, CS must be brought low before the next rising edge of the SK clock. This falling edge of CS initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the chip if CS is brought high after the tCS interval. DO e logical 0 indicates that programming is still in progress. DO e logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction. Write All (WRALL): The WRALL instruction will simultaneously program all registers with the data pattern specified in the instruction. As in the WRITE mode, the DO pin indicates the READY/BUSY status of the chip if CS is brought high after the tCS interval. Write Disable (WDS): To protect against accidental data distrub, the WDS instruction disables all programming modes and should follow all programming operations. Execution of a READ instruction is independent of both the WEN and WDS instructions. Erase All (ERAL): The ERAL instruction will simultaneously program all registers in the memory array and set each bit to the logical ‘‘1’’ Note: NSC CMOS EEPROMs do not require an ‘‘ERASE’’ or ‘‘ERASE ALL’’ operation prior to the ‘‘WRITE’’ and ‘‘WRITE ALL’’ instructions. The ‘‘ERASE’’ and ‘‘ERASE ALL’’ instructions are included to maintain compatibility with earlier technology EEPROMs. Instruction Set for the NM93C06L and NM93C46L SB Op Code Address READ Instruction 1 10 A5–A0 Data Reads data stored in memory at specified address. Comments WEN 1 00 11XXXX Enable all programming modes. ERASE 1 11 A5–A0 WRITE 1 01 A5–A0 ERAL 1 00 10XXXX WRALL 1 00 01XXXX WDS 1 00 00XXXX Erase selected register. D15 – D0 Writes selected register. Erases all registers. D15 – D0 Writes all registers. Disables all programming modes. Note: Address bits A5 and A4 become ‘‘Don’t Care’’ for the NM93C06L. Instruction Set for the NM93C56L and NM93C66L SB Op Code Address READ Instruction 1 10 A7–A0 WEN 1 00 11XXXXXX ERASE 1 11 A7–A0 WRITE 1 01 A7–A0 ERAL 1 00 10XXXXXX WRALL 1 00 01XXXXXX WDS 1 00 00XXXXXX Data Enable all programming modes. Erase selected register. D15 – D0 Writes selected register. Erases all registers. D15 – D0 Writes all registers. Disables all programming modes. Note: Address bit A7 is ‘‘Don’t Care’’ for the NM93C56L. http://www.national.com Comments Reads data stored in memory at specified address. 6 Timing Diagrams Synchronous Data Timing TL/D/10045 – 13 READ TL/D/10045 – 5 WEN TL/D/10045 – 6 7 http://www.national.com Timing Diagrams (Continued) WDS TL/D/10045 – 7 WRITE TL/D/10045 – 8 WRALL TL/D/10045 – 9 http://www.national.com 8 Timing Diagrams (Continued) ERASE TL/D/10045 – 10 ERAL TL/D/10045 – 11 9 http://www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Out-Line Package (M8) NS Package Number M08A http://www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Notes: Unless otherwise specified. 1. Reference JEDEC Registration M0-153, Variation AA. Dated 7/93. 8-Pin Molded TSSOP, JEDEC (MT8) NS Package Number MTC08 11 http://www.national.com NM93C06L/C46L/C56L/C66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage (2.7V to 5.5V) (MICROWIRE Bus Interface) Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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