Revised August 2000 CD4066BC Quad Bilateral Switch ■ High degree linearity General Description The CD4066BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4016BC, but has a much lower “ON” resistance, and “ON” resistance is relatively constant over the input-signal range. High degree linearity High degree linearity ■ Extremely low “OFF” 0.1% distortion (typ.) @ fis = 1 kHz, Vis = 5Vp-p, VDD−VSS = 10V, RL = 10 kΩ 0.1 nA (typ.) switch leakage: @ VDD−VSS = 10V, TA = 25°C ■ Extremely high control input impedance Features ■ Low crosstalk ■ Wide supply voltage range ■ High noise immunity between switches 3V to 15V 0.45 VDD (typ.) ■ Wide range of digital and @ fis = 0.9 MHz, RL = 1 kΩ ■ Frequency response, switch “ON” 40 MHz (typ.) ±7.5 VPEAK Applications analog switching • Analog signal switching/multiplexing ■ “ON” resistance for 15V operation 80Ω ■ Matched “ON” resistance • Signal gating ∆RON = 5Ω (typ.) • Squelch control over 15V signal input ■ “ON” resistance flat over peak-to-peak signal range • Chopper ■ High “ON”/“OFF” • Modulator/Demodulator 65 dB (typ.) output voltage ratio 1012Ω(typ.) −50 dB (typ.) @ fis = 10 kHz, RL = 10 kΩ • Commutating switch • Digital signal switching/multiplexing • CMOS logic implementation • Analog-to-digital/digital-to-analog conversion • Digital control of frequency, impedance, phase, and analog-signal-gain Ordering Code: Order Number Package Number Package Description CD4066BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow CD4066BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4066BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Schematic Diagram DS005665 www.fairchildsemi.com CD4066BC Quad Bilateral Switch November 1983 CD4066BC Absolute Maximum Ratings Recommended Operating Conditions (Note 2) (Note 1) (Note 2) −0.5V to +18V Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) −0.5V to VCC+0.5V Power Dissipation (PD) 700 mW Small Outline 500 mW Symbol IDD Parameter Quiescent Device Current −40°C to +85°C Note 2: VSS = 0V unless otherwise specified. 300°C DC Electrical Characteristics 0V to VDD Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 3V to 15V Input Voltage (VIN) Operating Temperature Range (TA) −65°C to +150 °C Dual-In-Line Supply Voltage (VDD) (Note 2) −40°C Conditions Min Max +25°C Min +85°C Typ Max Min Max Units VDD = 5V 1.0 0.01 1.0 7.5 µA VDD = 10V 2.0 0.01 2.0 15 µA VDD = 15V 4.0 0.01 4.0 30 µA SIGNAL INPUTS AND OUTPUTS RON “ON” Resistance RL = 10 kΩ to (VDD − VSS/2) VC = VDD, V SS to VDD ∆RON ∆“ON” Resistance Between Any 2 of 4 Switches IIS Input or Output Leakage VDD = 5V 850 270 1050 1200 Ω VDD = 10V 330 120 400 520 Ω VDD = 15V 210 80 240 300 Ω RL = 10 kΩ to (VDD − VSS/2) VCC = V DD, VIS = VSS to VDD VDD = 10V 10 VDD = 15V 5 VC = 0 Ω Ω ±50 ±0.1 ±50 ±200 VDD = 5V 1.5 2.25 1.5 1.5 V VDD = 10V 3.0 4.5 3.0 3.0 V 6.75 4.0 4.0 V nA Switch “OFF” CONTROL INPUTS VILC LOW Level Input VIS = V SS and VDD Voltage VOS = V DD and VSS IIS = ± 10µA VDD = 15V VIHC IIN 4.0 HIGH Level Input VDD = 5V 3.5 3.5 2.75 3.5 V Voltage VDD = 10V (Note 7) 7.0 7.0 5.5 7.0 V VDD = 15V 11.0 Input Current VDD−VSS = 15V VDD≥VIS≥V SS VDD≥VC≥V SS www.fairchildsemi.com 11.0 ± 0.3 2 8.25 ± 10−5 11.0 ± 0.3 V ± 1.0 µA (Note 3) TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise noted Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Parameter Conditions Typ Max Units VDD = 5V 25 55 ns VDD = 10V 15 35 ns VDD = 15V 10 25 ns Propagation Delay Time Signal VC = VDD, CL = 50 pF, (Figure 1) Input to Signal Output RL = 200k Propagation Delay Time Min RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3) Control Input to Signal VDD = 5V 125 ns Output High Impedance to VDD = 10V 60 ns Logical Level VDD = 15V 50 ns Propagation Delay Time RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3) Control Input to Signal VDD = 5V 125 ns Output Logical Level to VDD = 10V 60 ns High Impedance VDD = 15V 50 Sine Wave Distortion VC = VDD = 5V, VSS = −5V Frequency Response-Switch VC = VDD = 5V, VSS = −5V, “ON” (Frequency at −3 dB) RL = 1 kΩ, VIS = 5Vp-p, ns 0.1 % 40 MHz RL = 10 kΩ, VIS = 5Vp-p, f= 1 kHz, (Figure 4) 20 Log10 VOS/VOS (1 kHz)−dB, (Figure 4) Feedthrough — Switch “OFF” VDD = 5.0V, VCC = VSS = −5.0V, (Frequency at −50 dB) RL = 1 kΩ, VIS = 5.0Vp-p, 20 Log10, Crosstalk Between Any Two VDD = VC(A) = 5.0V; VSS = VC(B) = 5.0V, Switches (Frequency at −50 dB) RL1 kΩ, VIS(A) = 5.0 Vp-p, 20 Log10, Crosstalk; Control Input to VDD = 10V, RL = 10 kΩ, RIN = 1.0 kΩ, Signal Output VCC = 10V Square Wave, CL = 50 pF Maximum Control Input RL = 1.0 kΩ, CL = 50 pF, (Figure 7) 1.25 VOS/VIS = −50 dB, (Figure 4) 0.9 MHz 150 mVp-p VOS(B)/VIS(A) = −50 dB (Figure 5) (Figure 6) VOS(f) = ½ VOS(1.0 kHz) VDD = 5.0V 6.0 MHz VDD = 10V 8.0 MHz 8.5 MHz VDD = 15V CIS Signal Input Capacitance COS Signal Output Capacitance CIOS Feedthrough Capacitance CIN Control Input Capacitance 8.0 pF VDD = 10V 8.0 pF VC = 0V 0.5 5.0 pF 7.5 pF Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: These devices should not be connected to circuits with the power “ON”. Note 5: In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in CL wherever it is specified. Note 6: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input. Note 7: Conditions for VIHC: a) VIS = VDD, IOS = standard B series IOH b) VIS = 0V, IOL = standard B series IOL. 3 www.fairchildsemi.com CD4066BC AC Electrical Characteristics CD4066BC Typical Performance Characteristics “ON” Resistance vs Signal Voltage for TA = 25°C “ON” Resistance as a Function of Temperature for VDD−VSS = 15V “ON” Resistance as a Function of Temperature for VDD−VSS = 10V “ON” Resistance as a Function of Temperature for VDD−VSS = 5V Special Considerations avoid drawing VDD current when switch current flows into terminals 1, 4, 8 or 11, the voltage drop across the bidirectional switch must not exceed 0.6V at TA ≤ 25°C, or 0.4V at TA > 25°C (calculated from RON values shown). In applications where separate power sources are used to drive VDD and the signal input, the VDD current capability should exceed VDD/RL (RL = effective external load of the 4 CD4066BC bilateral switches). This provision avoids any permanent current flow or clamp action of the VDD supply when power is applied or removed from CD4066BC. No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9 or 10. In certain applications, the external load-resistor current may include both VDD and signal-line components. To www.fairchildsemi.com 4 CD4066BC AC Test Circuits and Switching Time Waveforms FIGURE 1. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output FIGURE 2. tPZH, tPHZ Propagation Delay Time Control to Signal Output FIGURE 3. tPZL, tPLZ Propagation Delay Time Control to Signal Output VC = VDD for distortion and frequency response tests VC = VSS for feedthrough test FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough 5 www.fairchildsemi.com CD4066BC AC Test Circuits and Switching Time Waveforms (Continued) FIGURE 5. Crosstalk Between Any Two Switches FIGURE 6. Crosstalk: Control Input to Signal Output FIGURE 7. Maximum Control Input Frequency www.fairchildsemi.com 6 CD4066BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 7 www.fairchildsemi.com CD4066BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 8 CD4066BC Quad Bilateral Switch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com