TI1 DRV8808DCAR Combination motor driver with dc-dc converter Datasheet

DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
COMBINATION MOTOR DRIVER WITH DC-DC CONVERTER
Check for Samples: DRV8808
FEATURES
1
•
2
•
Three DC Motor Drivers
– Up to 2.5-A Current Chopping
– Low Typical ON Resistance (RDSON = 0.5 Ω
at TJ = 25°C)
Three Integrated DC-DC Converters
– ON/OFF Selectable Using CSELECT Pin
and Serial Interface
– Outputs Configurable With External
Resistor Network From 1 V to 90% of VM
Capability for All Three Channels
– 1.35-A Output Capability for All Three
Channels
•
•
•
•
•
•
•
One Integrated LDO Regulator
– Output Configurable With External Resistor
Network from 1 V to 2.5 V
– 550-mA Output Capability
7-V to 40-V Operating Range
Serial Interface for Communications
Thermally-Enhanced Surface-Mount Package
48-Pin HTSSOP With PowerPAD™
(Eco-Friendly: RoHS and No Sb/Br )
Power-Down Function (Deep-Sleep Mode)
Reset Signal Output (Active Low)
Reset (All Clear) Control Input
DESCRIPTION
The DRV8808 provides the integrated motor driver solution for printers. The chip has three full H-bridges and
three buck DC-DC converters.
The output driver block for each consists of N-channel power MOSFETs configured as full H-bridges to drive the
motor windings. The device can be configured to utilize internal or external current sense for winding current
control.
The SPI input pins are 3.3-V compatible and have 5-V-tolerant inputs.
The DRV8808 has three dc-dc switch-mode buck converters to generate a programmable output voltage from
1 V up to 90% of VM, with up to 1.35-A load current capability.
The device is configured using the CSELECT terminal at start up, and serial interface during run time.
An internal shutdown function is provided for overcurrent protection, short-circuit protection, undervoltage lockout,
and thermal shutdown. Also, the device has the reset function at power on, and the input on nReset pin.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
BLOCK DIAGRAM
VM
Cstorage
VM
A_CONT
0.1 µF
VCP
Temperature
Sensor:
Pre-TSD or
Tsens (Analog)
OD_A
Vout1
CSELECT Th_out
DC-DC
Converter
Ch-A
0.1 µF
Cbkt
CP2
CP1
To High-Side
Gate Drive
Voltage
Charge
Pump
VM
A+
Motor Drive
Output
Control A
Thermal
Shut Down
VM
DC
Motor
A–
FB_A
RSA
Optional
VM
OD_B
Vout2
B+
DC-DC
Converter
Ch-B
FB_B
Voltage
Supervisory
Motor Drive
Output
Control B
VM
DC
Motor
B–
Regulator
Internal
Supply
RSB
Predrive,
Latch Registers,
and
Control
Circuitry
OD_C
Vout3
VM
DC-DC
Converter
Ch-C
Optional
VM
C+
Motor Drive
Output
Control C
FB_C
nReset
VM
DC
Motor
C–
nORT
RSC
LOGIC_OUT
Optional
LDO IN
LDO OUT
LDO
Regulator
LDO FB
nSLEEP
nWAKEUP
Serial Interface
V3p3
GND
0.1 µF
Enable_A
STROBE
2
Enable_B Enable_C
Phase_A
CLK
Phase_B
Phase_C
DATA
GND
GND
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
DCA PACKAGE
(TOP VIEW)
OD_A
OD_C
GND
FB_C
CSELECT
TH_OUT
LOGIC_OUT
nORT
ENABLE_A/STROBE
PHASE_A/CLK
ENABLE_B
PHASE_B
ENABLE_C
PHASE_C/DATA
A_CONT
NC
V3P3
nSLEEP
nRESET
nWAKEUP
VLDO_OUT
VLDO_FB
VLDO_IN
FB_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FB_A
GND
COA
CP2
VCP
VM
C–
RSC/GND
RSC/GND
C+
VM
VM
B–
RSB/GND
RSB/GND
B+
VM
A+
RSA/GND
RSA/GND
A–
VM
GND
OD_B
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
I/O
PU/PD
SHUNT
R
DESCRIPTION
1
OD_A
O
Output for DC-DC switch mode regulator A
2
OD_C
O
Output for DC-DC switch mode regulator C
3
GND
-
Ground
4
FB_C
I
5
CSELECT
I
6
TH_OUT
O
Temperature warning output (open drain)
7
LOGIC_OUT
O
Information monitoring output (open drain)
8
nORT
O
9
ENA / STB
I
Down
100k
Enable input for DC motor A control / SPI STROBE
10
PHA / CLK
I
Down
100k
Phase input for DC motor A control / SPI CLOCK
11
ENB
I
Down
100k
Enable input for DC motor B control
12
PHB
I
Down
100k
Phase input for DC motor B control
13
ENC
I
Down
100k
Enable input for DC motor C control
14
PHC / DATA
I
Down
100k
Phase input for DC motor C control / SPI DATA
15
A_CONT
I
Down
100k
DC-DC A converter control (L = Enable)
16
NC
NC
17
V3p3
O
18
nSLEEP
I
Down
100k
Enable/disable, SPI selector
19
nReset
I
Up
200k
Reset input (L: reset, H/open: normal operation)
20
nWAKEUP
I
Up
200k
Wake-up pin for DeepSleep mode (L = WAKEUP)
21
VLDO_OUT
O
Feedback signal for DC-DC converter C
Up
200k
DC-DC converter startup selector
Reset output (open drain)
Do not connect
Bypass for internal 3.3-V regulator
Copyright © 2009–2011, Texas Instruments Incorporated
LDO voltage regulator output
3
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
4
I/O
PU/PD
SHUNT
R
DESCRIPTION
NO.
NAME
22
VLDO_FB
I
LDO voltage regulator feed back
23
VLDO_IN
I
LDO voltage regulator input
24
FB_B
I
Feedback signal for DC-DC converter B
25
OD_B
O
Output for DC-DC switch mode regulator B
26
GND
-
Ground
27
VM
-
Voltage supply for motors and regulators
28
A-
O
Motor drive output for winding A-
29
RSKA / GND
I
Motor drive current sensing resistor A / GND Kelvin
30
RSA / GND
O
Motor drive current sensing resistor A / GND power
31
A+
O
Motor drive output for winding A+
32
VM
-
Voltage supply for motors and regulators
33
B+
O
Motor drive output for winding B+
34
RSKB / GND
I
Motor drive current sensing resistor B / GND Kelvin
35
RSB / GND
O
Motor drive current sensing resistor B / GND power
36
B-
O
Motor drive output for winding B-
37
VM
-
Voltage supply for motors and regulators
38
VM
-
Voltage supply for motors and regulators
39
C+
O
Motor drive output for winding C+
40
RSKC / GND
I
Motor drive current sensing resistor C / GND Kelvin
41
RSC / GND
O
Motor drive current sensing resistor C / GND power
42
C-
O
Motor drive output for winding C-
43
VM
-
Voltage supply for motors and regulators
44
VCP
O
Charge pump output
45
CP2
O
Charge pump bucket capacitor output (high side)
46
CP1
O
Charge pump bucket capacitor output (low side)
47
GND
-
Ground
48
FB_A
I
Feedback signal for DC-DC converter A
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
Internal
3.3-V
Supply
200 kW
(±40%)
1) Pin open, 3 V to 3.3 V
A /OFF, B /ON, C /ON
2) External R to GND (200 kW ± 10%)
1.3 V to 2 V
A /OFF, B /ON, C /OFF
3) GND, 0 V to 0.3 V
A /OFF, B /OFF, C /OFF
# CSELECT
Soft-Start
Control
GND
# Enable_X
# Phase _X
Hysteresis
# nSLEEP
# A_CONT
Serial Interface
100 kW
(±30%)
GND GND
Internal
3.3-V
Supply
200 kW
(±40%)
# nWAKEUP
Hysteresis
Deglitch
# nReset
GND
Reset Control
Deglitch is for nReset only.
nReset pulled up to 3.3 V internal.
nWAKEUP pulled up to 8 V internal.
Figure 1. Input Pin Configuration
External
3.3-V
Supply
# TH_OUT
1 kW
(External)
# LOGIC_OUT
# nORT
GND
Figure 2. Open-Drain Output Pin Configuration
Copyright © 2009–2011, Texas Instruments Incorporated
5
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VM
MAX
UNIT
Supply voltage
Logic input voltage range, serial I/F, A_CONT, nReset, etc.
(2)
TH_OUT, nORT, LOGIC_OUT, CSELECT
nWAKEUP
40
V
–0.3 to 5.5
V
–0.3 to 3.6
V
–0.3 to 8
V
Continuous total power dissipation (in case θJA = 20°C/W)
4
W
Continuous motor-drive output current for each H-bridge (100 ms)
2.5
A
Continuous dc-dc converter output current (3)
1.35
A
TJ
Operating junction temperature (1 hour)
Tstg
Storage temperature range
190
°C
–65 to 150
°C
260
°C
2
kV
Lead temperature 1.6 mm (1/16 in) from case for 10 s
ESD levels on every pin, Human-Body Model (HBM)
(1)
(2)
(3)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The negative spike less than –5 V and narrower than 50-ns width should not cause any problem.
May shut down due to regulator OCP.
RECOMMENDED OPERATING CONDITIONS
Supply voltage range, VM for motor control
Supply voltage range for dc-dc converter (VM)
MIN
TYP
MAX
18
27
38
UNIT
V
7
27
38
V
Operating ambient temperature range
–10
85
°C
Operating junction temperature range
0
135
°C
ELECTRICAL CHARACTERISTICS
TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply (Sleep) Current
ISLEEP1
Supply (sleep) current 1
nSLEEP = L,
dc-dc all off
3
5.5
mA
ISLEEP2
Supply (sleep) current 2
nSLEEP = L,
Regulators enabled
VM = 8 V,
No load
6
8
mA
ISLEEP3
Supply (sleep) current 3
nSLEEP = L,
Regulators enabled
VM = 38 V,
No load
6
8
mA
IDEEP_SL
Supply (deep sleep) current (1)
VM = 38 V
0.7
1
mA
Digital Interface Circuit
VIH
Digital high-level input voltage
Digital inputs
IIH
Digital high-level input current
Digital inputs
2
3.6
V
100
μA
VIL
Digital low-level input voltage
Digital inputs
0.8
V
IIL
Digital low-level input current
Digital inputs
100
μA
Vhys
Digital input hysteresis
Digital inputs
Tdeg_nReset
nReset input deglitch time
2.5
7.5
μs
Tfilt_ACONT
A_CONT filter time (2)
30
70
μs
0.45
V
Charge-pump VCP (CP = 0.1 μF to 0.47 μF, Cblk = 0.01 μF ±20%)
VO(CP)
Output voltage
f(CP)
Switching frequency
(1)
(2)
6
ILOAD = 0 mA,
VM > 15 V
VM + 10
VM + 13
1.6
V
MHz
Deep Sleep shuts down majority of the device and runs minimal circuits (internal bias circuits and the nWAKEUP pin). Deep Sleep is
entered by writing 1 to Setup Register, Bank 1, Bit 11. Device is restarted by pulling nWAKEUP pin low or power cycling VM. Deep
Sleep functionality only available for VM > VthVM+.
A_CONT is filtered for both high and low levels.
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER
tstart
Start-up time
TEST CONDITIONS
CStorage = 0.1 μF,
MIN
VM ≥ 15 V
TYP
MAX
0.5
2
UNIT
ms
V3p3 Output
V3p3
Output voltage (3)
3
3.3
3.6
V
Cbypass
Output capacitor
0.08
0.1
10
μF
5.76
6.4
7.04
MHz
Internal Clock OSCi
fOSCi
System clock rrequency
CSELECT for DC-DC Startup Selection
VCS0
dc-dc all off
VCS1
Turn ON ODB
Pull down by external 200-kΩ resistor
VCS2
Turn ON ODB then ODC
As pin open
VLDO Regulator
LDO input voltage
VLDOFB
Feedback voltage
VLDOOUT
Output voltage range
IOUT
Load capability
IOCP
OCP current
tIdeg
OCP deglitch
V
2
V
3
3.6
V
3.6
V
3
1
V
1 V ≤ VLDOOUT ≤ 1.8 V
±5
%
1.8 V ≤ VLDOOUT ≤ 2.5 V
±3
Vovp
Overvoltage protection
% to nominal Voutx detected at VFB
(VFB increasing)
Vuvp
Undervoltage protection
% to nominal Voutx detected at VFB
(VFB decreasing)
tVdeg
UVP/OVP deglitch time
CL1
Electrolytic load capacitance
Load bypass configuration 1
ESR of load capacitance
CC1
Ceramic load capacitance
CL2
Electrolytic load capacitance
CESR2
0.3
(4) (5) (6)
VLDOIN
CESR1
0
1.3
Load bypass configuration 2
CC2
500
mA
725
1100
mA
3
8
13
μs
25
30
35
%
–25
–30
–35
%
3
8
27
13
μs
120
μF
0.05
2
Ω
0
0.4
μF
120
μF
80
100
0.05
0.2
Ω
0
3
μF
Vth VM- < VM < 7 V
0.8 x
VM
V
20 V < VM < 38 V
0.9 x
VM
ESR of load capacitance
Ceramic load capacitance
Three, DC-DC Converter
VM
OPE_X
ODx
Operating supply voltage range
ratio to VOUT
Regulator output voltage
IO < 0.6 A
20 V < VM < 40 V
0℃ < TJ < 125℃
-3
VO
3
125℃ < TJ < 135℃
-4
VO
4
6.5 V < VM < 20 V
-5
VO
5
VM = 7 V, VO = 5.5 V
-5
VO
5
0℃ < TJ < 125℃
-3
VO
3
125℃ < TJ < 135℃
-4
VO
4
-5
VO
5
VM = 7 V, VO = 1 V
VthVM- < VM < 6.5 V , VO ≤ 3.3 V
FBx
FBx pin voltage
IO
ODx
Output current (DC)
VM > 15 V
ODx2
Output current (DC) at low VM
VM = 7 V, VO = 5.5 V
IO
(3)
(4)
(5)
(6)
1
%
V
1.35
A
0.6
A
V3p3 bypass pin is not meant to be used as a supply.
LDO can be bypassed by either load configuration 1 or 2.
Typical values for external components should be chosen such that when the tolerance is added to the typical, the values remain
between the maximum and minimum specifications listed.
When LDO is not used, recommend connecting VLDO_IN to GND, VLDO_OUT to GND, and VLDO_FB to FB_B.
Copyright © 2009–2011, Texas Instruments Incorporated
7
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER
IO
TEST CONDITIONS
Output current (DC) at low VM
VM = 7 V, VO = 3.3 V
RDSON (7)
FET on-resistance at 0.8 A for
OD_x VM > 15 V
TJ = 70 °C
L
Inductor
VOUT = 1.0 V
C
Capacitor
ODx3
MIN
TJ = 135 °C
TYP
MAX
1.2
A
0.85
1.05
Ω
1
1.2
μH
150
VOUT ≥ 3.3 V
UNIT
330
VOUT = 1.0 V
270
VOUT ≥ 3.3 V
330
μF
2.7
A
400
ns
220
Three DC-DC Converter Protection
IO DD ODx
Overcurrent detect for OD_x
source
tODXdeg
Cycle by cycle Idetect deglitch
tODXSD
dc-dc shutdown filter
Number of consecutive cycles with Idetect
Vovpx
Overvoltage protection
% to nominal Voutx detected at VFB
(VFB increasing)
25
30
35
%
Vuvpx
Undervoltage protection
% to nominal Voutx detected at VFB
(VFB decreasing)
–25
–30
–35
%
tVXdeg
UVP/OVP deglitch time
3
8
13
μs
tsst
Start-up time with soft start
56
ms
Vstover
Start-up overshoot
3
%
VM Supervisory (8)
Peak current in each ON cycle
1.35
100
200
4
Ratio to Vo
chop
cycles
(9)
VthVM–
nORT, for VM low threshold
VM decreasing
4.5
5
6
V
VthVM+
nORT, for VM high threshold
VM increasing
5.5
6
6.79
V
VthVMh
nORT, for VM detect hysteresis
VthVM+ – VthVM–
0.5
1
(10)
V
VthVM2
For motor driver off
15
V
tVMfilt
Vth VM monitor filtering time
For Vth VM detect
4
30
μs
tVM2filt
Vth VM2 monitor filtering time
For Vth VM2 detect
30
60
ms
Thermal Shutdown: TSD
(11) (12)
TTSD
Thermal shutdown set points
tTSDdeg
TSD deglitch time
Temperature Warning: Pre-TSD (13)
PreTSD
Temperature warning
150
170
190
°C
30
60
90
μs
115
135
155
°C
(12)
Assert at TH_OUT pin
Open-drain outputs (nORT, Logic_OUT, TH_OUT)
VOH
(14)
VOL
High-state voltage
RL = 1 kΩ to 3.3 V
3
V
Low-state voltage
RL = 1 kΩ to 3.3 V
IOL (14)
Low-state sink current
Vo = 0.25 V
tr (15)
Rise time
10% to 90%
1
μs
tf (15)
Fall time
90% to 10%
50
ns
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
8
0.3
2
V
mA
RDSON at T = 135°C guaranteed by characterization. Production test will be done at T = 25°C/70°C.
VM must be VM > VthVM+ to start up internal dc-dc converter.
When VM goes down below VthVM+, the VUVPx (undervoltage protection in dc-dc) are masked. The dc-dc converter is shut off by nORT
assertion at VthVM –.
No nORT assertion to VthVM2 detection.
TSD does not need thermal hysteresis.
Parametric guaranteed by characterization. Not tested in production.
PreTSD does not need thermal hysteresis.
Production test only measures Vol and Iol to ensure timing.
tr and tf dominated by external capacitance, pullup resistance, and open-drain NMOS RDSON.
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER
nORT Delay: Startup Sequence
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
300
390
ms
5
10
15
ms
60
120
180
ms
5
10
μs
6.8
A
(16) (17)
Tord1
nORT delay 1
Reset deassertion from VthVM+ < VM, for
DC/DC wake up failing
Tord3
dc-dc turn on delay
From one dc-dc wake up to following dc-dc to
go soft-start sequence
Tord4
nORT delay 4
Reset deassertion from 2nd dc-dc wake up
nReset Input (16)
Treset
nReset assertion to nORT
assertion delay
nReset falling to nORT failing
H-Bridge Drivers (OUTX+ and OUTX–) Condition: VM = 15 V to 38 V
(18)
IOUT1(max)
Peak output current 1
Less than 500-ns period
IOUT2(max)
Peak output current 2
Less than 100-ms period
2.42
A
RDSON
FET ON resistance at 0.8 A
TJ = 70°C
0.55
0.65
Ω
TJ = 135°C
0.7
0.85
ICEX
Output leakage current
IOC
Motor overcurrent threshold for
each H-bridge (18)
Motor
Fchop
VOUTX = 0 V or 10
3
Motor chopping frequency =
FOSCM/8
90
100
10
μA
8
A
110
kHz
DC Motor Drivers
tr
Rise time
VM = 35 V
20% to 80%
50
200
nS
tf
Fall time
VM = 35 V
20% to 80%
50
200
nS
tPDOFF
Enable or strobe detection
to sink or source gate OFF delay
tCOD
Crossover delay time to prevent
shoot through
tPDON
Enable or strobe detection
to sink or source gate ON delay
tIdeg
MISD BLANK
[00] (20)
[10]
[11]
TBLANK
400
nS
100 (19)
600
1000
nS
nS
1.80
2.25
2.95
(21)
1.20
1.50
2.30
(22)
2.35
3.00
3.65
2.95
3.75
4.30
(23)
[00]
(24)
3.05
3.45
5.50
[01]
(25)
1.90
2.20
4.15
[10]
(26)
4.15
4.70
6.75
5.30
5.95
8.25
[11] (27)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
150
750
[01]
Tblank
50
μs
μs
This includes asynchronous timing deviation between the event to the timer clock.
nORT assertion delay is configurable and defined in the serial register section.
When the overcurrent is detected, all the H-bridges are shut down and assert nORT per shutdown configuration.
tCOD, Pminp, and Pmine not production tested.
3 to 4 periods Fosc/4 + 1 Fosc
2 to 3 periods Fosc/4 + 1 Fosc
4 to 5 periods Fosc/4 + 1 Fosc
5 to 6 periods Fosc/4 + 1 Fosc
3 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
2 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
4 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
5 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
Copyright © 2009–2011, Texas Instruments Incorporated
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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER
VRSTRIP
TEST CONDITIONS
Internal current trip
External resistor sense voltage
trip threshold
MIN
TYP
MAX
UNIT
00
1.18
1.4
1.62
A
01
1.48
1.7
1.92
10
1.68
1.9
2.12
11
1.98
2.2
2.42
00
165
185
205
01
190
210
230
10
240
260
280
11
290
310
330
mV
Pminp
Minimum pulse width (phase)
(19)
1
μs
Pmine
Minimum pulse width (enable)
(19)
1
μs
25
MHz
Serial Interface
(28)
f(CLK)
Clock frequency
twh(CLK)
Minimum high-level pulse width
10
ns
twl(CLK)
Minimum low-level pulse width
10
ns
tdcs
Setup time, DATA to CLK↓
10
ns
tdch
Hold time, CLK↓ to DATA
10
ns
tdss
Setup time, DATA to STROBE↑
10
ns
tdsh
Hold time, STROBE↑ to DATA
10
ns
tcss
Setup time, CLK↓ to STROBE↑
20 (29)
ns
tcsh
Hold time, STROBE↑ to CLK↓
20 (29)
ns
(30)
μs
10
ns
20
ns
tnss
Setup time, nSLEEP↓ to
STROBE↑
tnsh
Hold time, STROBE↑ to
nSLEEP↑
tw(STRB)
Minimum strobe pulse width
4
Serial Interface: ID Monitor Function at Logic_out Pin, Extended Setup Mode
tODL
0 data output delay bit 3 to 0
(ext-setup) = (1100)
tODH
1 data output delay bit 3 to 0
(ext-setup) = (1111)
(31)
From strobe rise to Logic_out
(1 kΩ to external 3.3 V)
4000
ns
4000
ns
(28) Serial interface timing will not be tested parametrically in production.
(29) DATA value at STROBE is address bit for Setup and Extended Setup register so setup and hold times apply to DATA relative to
STROBE. CLK and DATA also require setup and hold times relative to each other. Therefore, CLK and STROBE setup and hold timing
is the summation of both.
(30) Internal filter on nSLEEP to STROBE drives this specification.
(31) Serial interface timing will not be tested parametrically in production.
Serial Interface
The device has a serial interface port (SIP) circuit block to control dc motor H-bridges, dc-dc regulators, and
other functions, such as blanking time, OFF time, etc. Since the SIP shares its three lines with three of the motor
control signals, the SIP is only available when nSLEEP is low.
Table 1. Serial Interface
nSLEEP
10
PIN 9
PIN 10
PIN 14
SIP FUNCTIONALITY
L
STB
CLK
DATA
Yes
H
ENA
PHA
PHC
No
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
Sixteen-bit serial data is shifted least significant bit (LSB) first into the serial data input (DATA) shift register on
the falling edge of the serial clock (CLK). After 16-bit data transfer, the strobe signal (Strobe) rising edge latches
all the shifted data. During the data transferring, Strobe voltage level is ok with L level or H level.
DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
Strobe
NOTE
During startup (VM rising), nSLEEP input is set HI, suppressing false data latching caused
by a rising edge on the STB signal. nSLEEP will remain HI until nORT is released (120 ms
after dc-dc regulators come up).
Setup Mode, Extended Setup Mode, Power-Down Mode
The motor output mode is configured through the SIP (DATA, CLK and STROBE) when nSLEEP = L. After set
up, the nSLEEP pin must be pulled high for normal motor drive control. The value on the DATA line at the
positive edge of STROBE when nSLEEP is low, selects whether the data is written to the Setup or Extended
Setup registers. Setup is selected for DATA = L; Extended Setup is selected for DATA = H.
The condition, which the device requires for set up (initialize), is after the nORT (Reset) output goes H level from
L level (power on, recovery from VM < 7 V). During nSLEEP in L level, all the motor-drive functions are shut
down and their outputs are high-impedance state. This device forces motor-driver functions to shut down for the
power-down mode, and is not damaged even if nSLEEP is asserted during motor driving.
Data is shifted at all times, regardless of nSLEEP. Care must be taken to ensure valid data has been shifted into
the internal shift register, before the STROBE rising edge, occurs while nSLEEP is LO.
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nSLEEP = L (Bit 16 = L): Setup Mode
Data
Bit 0
tsu
Bit 16 = L
Bit 16
Bit 1
th
Clock
tcs
twl(clk)
Strobe
twh(clk)
tw(STRB)
tss_min
nSLEEP
Don’t Care (see Note A)
nSLEEP = L (Bit 16 = H): Extended Setup Mode
Data
Bit 0
tsu
Bit 1
Bit 16
Bit 16 = H
th
Clock
tcs
twl(clk)
twh(clk)
Strobe
tw(STRB)
tss_min
nSLEEP
A.
Don’t Care (see Note A)
For initial setup, nSleep state can be "Don't care" before the tss_min timing prior to the strobe.
Figure 3. Serial Interface Timing
12
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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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SETUP REGISTER
nSLEEP
EXTENDED SETUP REGISTER
ENABLEA /
STROBE
When STROBE goes HI
SDATA
DATA SHIFT REGISTER
Register is initialized after power up reset
SCLK
Register isNOT initialized after power up reset
.
An SPI write command is recommended
.
A.
It is recommended that after initial power up sequence, a serial command be performed to clear undefined data in the
internal shift register. This will help avoid latching undefined data into SETUP and EXTENDED SETUP registers.
SETUP and EXTENDED SETUP registers are properly initialized during power up, but internal shift register is not
initialized.
Figure 4. Serial Peripheral Interface Block Diagram
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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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VM
nPUC
(internal)
nORT
nSLEEP_ext
nSLEEP_int is forced HI until nORT is HI.
Once nORT is HI, nSLEEP_int follows nSLEEP_ext.
nSLEEP_int
[internal only]
STB (or) ENA
STB (or) ENA going high when nSLEEP_int is LO causes
data transfer from shift registers to set up registers
???
???
Valid Data
Valid Data
Set Up regs
Undefined
???
Valid Data
Shift Regs
Shift Register data is valid and defined only
after a serial command
A.
During startup (VM rising), internally nSLEEP de-asserted to HI, suppressing false data latching caused by a rising
edge on the STB signal. nSLEEP will remain HI until nORT is released (120 ms after dc-dc regulators come up).
Figure 5. Serial Peripheral Interface STROBE Blocking During Power Up
14
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
Operation Setup Register Bit Assignment
BANK
0
Table 2. Setup Registers
(1) (2) (3)
BIT
FUNCTION
DEFAULT
COMMENT
0
Tblank A 0
0
1
Tblank A 1
0
00: 3.75 μs, 01: 2.50 μs
10: 5.00 μs, 11: 6.25 μs
2
Tblank B 0
0
3
Tblank B 1
0
4
Tblank C 0
0
5
Tblank C 1
0
00: 3.75 μs, 01: 2.50 μs
10: 5.00 μs, 11: 6.25 μs
6
DC-DC A Minoff Time
0
0: 2.2 μs, 1: 6.6 μs
7
DC-DC A SW
1
8
DC-DC B SW
CSELECT
9
DC-DC C SW
CSELECT
10
MOTOR CHOPPING 0
0
11
MOTOR CHOPPING 1
0
00: 100 kHz, 01: 50 kHz
10: 133 kHz, 11: 200 kHz
12
RESET DELAY CONTROL
0
0: Disable, 1: Enable
13
LDO ENABLE
Note 1
0: On, 1: Off
14
DC-DC B Minoff Time
0
0: 2.2 μs, 1: 6.6 μs
15
Bank Change
0
0: Bank0, 1: Bank1
0
MISD BLANK AB 0
0
1
MISD BLANK AB 1
0
00: 2.25 μs, 01: 1.50 μs
10: 3.00 μs, 11: 3.75 μs
2
MISD BLANK C 0
0
3
MISD BLANK C 1
0
4
VRS A
0
00: 3.75 μs, 01: 2.50 μs
10: 5.00 μs, 11: 6.25 μs
0: On
1: Off
00: 2.25 μs, 01: 1.50 μs
10: 3.00 μs, 11: 3.75 μs
0: Disable, 1: Enable
VRSA = 0:
5
VRS A Level 0
0
6
VRS A Level 1
0
7
DC-DC C Minoff Time
0
0: 2.2 μs, 1: 6.6 μs
8
VRS B
0
0: Disable, 1: Enable
9
VRS B Level 0
0
10
VRS B Level 1
0
00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
11
DEEP SLEEP
0
0: Disable, 1: Enable
12
VRS C
0
0: Disable, 1: Enable
13
VRS C Level 0
0
14
VRS C Level 1
0
00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
15
Bank Change
0
0: Bank0, 1: Bank1
00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSA = 1:
00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
VRSB = 0:
1
00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSB = 1:
VRSC = 0:
00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSC = 1:
(1)
(2)
(3)
The LDO default follows the DC/DC B default value based on CSELECT.
All bits go to default for VM < VthVM, nReset = L.
RESET DELAY CONTROL set to 1 delays nORT assertion by 100 us typical. Range is 85 us to 125 us.
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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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Operation Extended Setup Register Bit Assignment
Table 3. Extended Setup Register
(1)
(2)
(1) (2)
BANK
BIT
FUNCTION
DEFAULT
COMMENT
NA
0
Signal Select 0
0
See Logic_Out Table
1
Signal Select 1
0
2
Signal Select 2
0
3
Signal Select 3
0
4
DCDC/LDO ISD Mask
0
0: Disable, 1: Enable
5
DCDC/LDO VSD Mask
0
0: Disable, 1: Enable
6
Motor ISD Mask
0
0: Disable, 1: Enable
7
TSD Mask
0
0: Disable, 1: Enable
8
Reset Mask C
0
0: Disable, 1: Enable
9
Reset Mask B
0
0: Disable, 1: Enable
10
Reset Mask A
0
0: Disable, 1: Enable
11
Reset Mask SR
0
0: Disable, 1: Enable
12
Pre TSD
0
0: TSD-20C, 1: Analog output
13
TSD Cont0
0
See TSD Control Table
14
TSD Cont1
0
15
MISD Cont
0
See MISD Control Table
All bits go to default for VM < VthVM–, nReset = L.
Bits [11:8] are selective shutdown bits. Setting to a 1 makes faults on the associated regulator only shutdown that regulator and allows
restart on an nSLEEP L > H transition. Setting to 0 shuts everything down and restarts only for VM < VthVM– or nReset = L.
Table 4. TSD Control – Operation After Detected TSD
TSD Cont1
TSD Cont0
DC-DC
MOTORS
nORT
LDO
0
0
OFF
0
1
ON
1
0
1
1
RELEASED BY
OFF
LOW
OFF
VM < VthVM– or nReset = L
OFF
HIGH
ON
VM < VthVM– or nReset = L or nSLEEP L > H transition
ON
OFF
PULSE
ON
VM < VthVM– or nReset = L or nSLEEP L > H transition
OFF
OFF
LOW
OFF
VM < VthVM– or nReset = L
Table 5. MISD Control – Operation After Detected Motor OCP
MISD Cont
DC-DC
MOTORS
0
ON
OFF
PULSE
1
OFF
OFF
LOW
(1)
16
nORT
(1)
LDO
RELEASED BY
ON
VM < VthVM– or nReset = L or nSLEEP L > H transition
OFF
VM < VthVM– or nReset = L
PULSE in Control Tables is 40-ms duration.
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
Table 6. Logic_Out
SIGNAL SELECT
FUNCTION (Logic_out OUTPUT)
0000
Detect OCP/UVP/OVP on A, output L
0001
Detect OCP/UVP/OVP on B, output L
0010
Detect OCP/UVP/OVP on C, output L
0011
Detect OCP on DC-DC/LDO regulator, output L
0100
Detect UVP, output L
0101
Detect OVP, output L
0110
Detect OCP on motor, output L
0111
Detect TSD, output L
1000
Revision code bit 0
1001
Revision code bit 1
1010
Revision code bit 2
1011
Device code bit 0
1100
Device code bit 1
1101
N/A
1110
Detect OCP/UVP/OVP on LDO regulator, output L
1111
Fix, output H
Deep Sleep Mode
Deep sleep mode can be entered by setting the deep sleep bit (bit 11) on the Setup register to HI. Once deep
sleep mode is entered, every single subsystem is disabled, except the block necessary to regain power by
making the nWAKEUP input pin LO.
DEEP SLEEP Bit (SETUP
REGISTER) = 0
Normal
Operation /
Idle State
nWAKEUP = LO
DEEP SLEEP Bit (SETUP
REGISTER) = 1
Deep Sleep
nWAKEUP = HI
Figure 6. Deep Sleep Mode
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DC Motor Drive
H-bridges A, B, and C can be controlled by using the ENABLE_X and PHASE_X control lines.
The H-bridge driver operation is available for VM > 15 V.
Internal current sense functionality is present by default. External sensing can be enabled through the serial
interface. If enabled, the sense resistor must be placed externally.
NOTE
A capacitor, not larger than 2200 pF, can be placed between each H-bridge output to
GND for EMI suppression purposes. It will increase the peak current but will have no
impact on the operation.
Enable or Phase Reversal
or Trip Reduction
tPDON
Sink or Source Gate
OFF to ON
tPDOFF
tCOD
Sink or Source Gate
ON to OFF
tBLANK: DC Motor
Current Sense
Blanking Time
Figure 7. Crossover and Blanking Timing for H-Bridge
The dc motor H-bridges include a tBLANK period to ignore huge current spike due to rush current to varistor
capacitance.
Short/Open for Motor Outputs
When a short/open situation happens, the protection circuit prevents device damage under certain conditions
(short at start-up, etc).
Shutdown is released based on MISD Control in the Extended Setup register.
Table 7. DC Motor-Drive Truth Table
FAULT
CONDITION
nSleep
Enablex
Phasex
+ HIGH SIDE
+ LOW SIDE
– HIGH SIDE
– LOW SIDE
0
0
X
X
OFF
OFF
OFF
OFF
0
1
0
X
OFF
OFF
OFF
OFF
0
1
1
0
OFF
ON
ON
OFF
0
1
1
1
ON
OFF
OFF
ON
Motor OCP
X
X
X
OFF
OFF
OFF
OFF
TSD
X
X
X
OFF
OFF
OFF
OFF
(1)
18
(1)
X = Don't care
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
Charge Pump
The charge-pump voltage generator circuit utilizes, external storage, and bucket capacitors. It provides the
necessary voltage to drive the high-side switches, for both dc-dc regulators and motor driver. The charge-pump
circuit is driven at a frequency of 1.6 MHz (nom). Recommended bucket capacitance (connected from CP1 to
CP2) is 10 nF, rated at 55 V (minimum), and storage capacitance is 0.1 μF, at 16 V (minimum). The
charge-pump storage capacitor, Cstorage, should be connected from the CP output to VM.
For power save in sleep mode, the charge pump is stopped when N_SLEEP = L and all three regulators are
turned OFF. When the part is powered up, the charge pump is started first after the CSELECT capture and, 10
ms later from the CP startup, the first regulator is started up.
Table 8. Charge Pump
(1) (2)
FAULT CONDITION
DC-DC Ch-A
DC-DC Ch-B
DC-DC Ch-C
X
OFF
OFF
X
ON
X
X
X
X
0
(1)
(2)
nSleep
CHARGE PUMP
OFF
0
OFF
X
X
ON
ON
X
X
ON
X
X
ON
X
ON
X
X
X
1
ON
Motor OCP
X
X
X
1
ON
TSD
OFF
OFF
OFF
X
OFF
X = Don't care
DC=DC status in fault condition is determined by serial register settings, TSD Control table, and MISD Control table. These tables define
status of charge pump.
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VM
Charge
Pump
A_CONT
(Regulator A Only)
Overcurrent
Sense
OD_x
Vref
1V
Output
Voltage
Supervisor
Disable
(Mask)
Control Logic
and
Predriver
Current Limit
FBx
Overcurrent Protect
Detect
Disable
UVP
OVP
(–30%) (+30%)
C_SELECT
Soft Start,
Protection Control,
and
nORT Assertion
External catch diode
Vf < 1.2 V at peak current,
(1.25 ´ Iout) assuming
330-µH inductor
Setup/Extended Setup
Register
Figure 8. DC-DC Converter
This is a switch-mode regulator with integrated switches, to provide a programmed output set by the feedback
terminal. The dc-dc converter has a variable duty cycle topology. External filtering (inductor and capacitor) and
external catch diode are required. The output voltage is short circuit protected.
The regulator has a soft-start function to limit the rush current during start-up. It is achieved by using VFB ramp
during soft start.
For unused dc-dc converter channels, the external components can be removed if the channel is set to inactive
by the CSELECT pin and register bits. Recommend connecting unused FB pin to GND or V3p3 (pin 17).
20
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3.3V
LDO_IN
LDO_OUT
NC
LDO Regulator
LDO_FB
FB_B
Figure 9. Unused LDO Recommended Connections
For proper termination, it is recommended that, if left unused, the LDO terminals be connected in the following
fashion:
1. LDO IN must be powered by an input voltage greater than 1 V.
2. LDO OUT must be left disconnected.
LDO Feed Back must be connected to the DC/DC Converter Channel B Feed Back terminal.
Table 9. CSELECT for Start-Up
(1)
(2)
(3)
(1) (2) (3)
CSELECT
PIN VOLTAGE
DCDC_A
DCDC_B
DCDC_C
Gnd
0 V to 0.3 V
OFF
OFF
OFF
Pull down (by external 200 kΩ)
1.3 V to 2.0 V
OFF
ON
OFF
OPEN
3.0 V to 3.3 V
OFF
ON
ON
The CSELECT pin is connected to internal 3.3-V supply through 200-kΩ resister.
This CSELECT pin control is valid after the PowerON Reset is initiated. Once the Setup Register is set, the dc-dc control follows the bits
7 to 9 on the Setup Register, bank 0, until the next PowerON Reset event occurred.
For OPEN case, B starts up 1st and C follows after 10-ms delay.
Table 10. Regulator A Control
SETUP REGISTER BANK 0, BIT 7
A_CONT
0
0
DCDC_A
ON
0
1
OFF
1
0
OFF
1
1
OFF
nReset: Input for System Reset
nReset pin assertion stops all the dc-dc converters and H-bridges. It also resets all the register contents to
default values. After deassertion of input, device follows the initial start-up sequence. The CSELECT state is
captured after the nReset deassertion (L > H).
The input is pulled up to internal 3.3 V by a 200-kΩ resistor. When the pin is H or left open, the reset function is
released. Also it has deglitch filter of 2.5 μs to 7.5 μs.
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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
VM
(CSELECT = Open)
www.ti.com
VthVM+
(VM = 6 V)
VthVM–
(VM = 5 V)
Capture CSELECT
Then Start Charge Pump
VCP
CP Start to DC-DC Delay
DCDC_A
10 ms
(Note A)
DCDC_B
DCDC_C
120 ms
DLY
(10 ms)
nORT
Protection Mask
(UVP, OVP)
L
H
A.
Charge-pump wakeup delay, from 10 ms to 20 ms due to asynchronous event capture.
B.
When VM crosses the VthVM+ (about 6.0 V), the CSELECT state is captured. In case of the CSELECT being open
(pulled up to internal 3.3 V), dc-dc regulator channels B and C are turned on.
C.
LDO OCP is masked during protection M\mask time.
D.
In order to avoid false SPI data latching caused by a rising edge on the STB signal, nSLEEP will remain high during
the power up stage (VM rising) and until nORT is released.
E.
DC/DC Channel A follows the Regulator A Control table. During power up, DC/DC Channel A starts up disabled
(SETUP BANK 0 [7] = 1).
Figure 10. Power-up Timing (Power up With DC-DC Turn on by CSELECT)
22
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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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VthVM+
(VM = 6 V)
VthVM–
(VM = 5 V)
VM
(CSELECT = 200k to GND)
Capture CSELECT
Then Start Charge Pump
CP Start to DC-DC Delay
VCP
10 ms
(Note A)
DCDC_B
(3.3 V to LDO_IN)
LDO
(1.2 V)
120 ms
(20 ms + 100 ms)
nORT
Protection Mask
(OVP, UVP for Ch-A/B/C and LDO)
L
H
A.
Charge-pump wakeup delay, from 10 ms to 20 ms due to asynchronous event capture.
B.
LDO Enable follows DC/DC B Enable during power up and can be controlled using the SETUP register after power
up.
Figure 11. Power-up Timing (Power up With LDO, Supplied by DCDC_B)
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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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VthVM+
(VM = 6 V)
VthVM–
(VM = 5 V)
VM
(CSELECT = Open)
VCP
Capture CSELECT
Then Start Charge Pump
CP Start to DC-DC Delay
10 ms
(Note A)
DCDC_B
40 ms
DCDC_C
(3.3 V to LDO_IN)
LDO
(1.2 V)
120 ms
(20 ms + 100 ms)
nORT
Protection Mask
(OVP, UVP for Ch-A/B/C and LDO)
L
H
A.
Charge-pump wakeup delay, from 10 ms to 20 ms due to asynchronous event capture.
B.
LDO Enable follows DC/DC B Enable during power up and can be controlled using the SETUP register after power
up. In this case, since LDO_IN is driven by DC/DC Channel C, LDO_OUT will follow DC/DC Channel C.
Figure 12. Power-up Timing (Power up With LDO, Supplied by DCDC_C)
24
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VM
(CSELECT = GND)
VthVM+
(VM = 6 V)
VthVM–
(VM = 5 V)
300 ms
DCDC_B
(Off)
DCDC_C
(Off)
nORT
L
Protection Mask
(UVP, OVP)
H
A.
When VM crosses the VthVM+ (about 6 V) with CSELECT = GND, none of three regulators are turned ON. The nORT
output is released to H after 300 ms from VthVM+ crossing.
B.
LDO OCP is masked during protection mask time.
Figure 13. Power-up Timing (Power up Without DC-DC Turn on, CSELECT = GND)
Copyright © 2009–2011, Texas Instruments Incorporated
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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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VM
(CSELECT = GND)
VthVM+
VM = 6 V
VM + 11 V
VCP
VM – 0.7 V
DCDC_A
(Off®On)
Note B
DCDC_B
(Off)
DCDC_C
(Off)
120 ms
(Note A)
Setup
(9, 8, 7) = (1, 1, 0)
Setup Register
Strobe
nORT
Protection Mask
H
L
A.
The regulator is started from the strobe input, same as the charge pump. No 10-ms waiting, because the VCP pin
already reached to VM – 0.7 V.
B.
LDO OCP is masked during protection mask time.
C.
A_CONT must be LOW or OPEN for regulator A to turn on.
Figure 14. Power-up Timing (DC-DC Regulator Wakeup by Setup Register)
26
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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VM
(CSELECT = GND)
VthVM+
VM = 6 V
DCDC_B
(Off)
10 ms
DCDC_C
(Off)
10 ms
DCDC_A
(Off®On)
Note A
120 ms
Setup
(9, 8, 7) = (0, 0, 0)
Setup Register
Strobe
nORT
H
Protection Mask
(UVP, OVP)
L
A.
A_CONT must be LOW or OPEN for regulator A to turn on.
B.
LDO OCP is masked during protection mask time.
Figure 15. Power-up Timing (DC-DC Regulator Wakeup by Setup Register, All Three Channels ON)
Copyright © 2009–2011, Texas Instruments Incorporated
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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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VM Start-up/Power-Down and Glitch Condition
1. Start up with VM glitch (not below VthVM–)
VM
(CSELECT = Open)
VthVM+
VM = 6 V
VM = 5 V
VthVM–
DCDC_B
DCDC_C
10 ms
(Note A)
120 ms
10 ms
nORT
Protection Mask
(UVP, OVP)
A.
LDO OCP is masked during protection mask time.
Figure 16.
28
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
2. Start up with VM glitch (below VthVM–)
VM
(CSELECT = Open)
VthVM+
VM = 6 V
VM = 5 V
VthVM–
Restart
Shut Down
10 ms
(Note A)
DCDC_B
10 ms
(Note A)
DCDC_C
120 ms
10 ms
nORT
Protection Mask
(UVP, OVP)
A.
t
(in Case
t < 120 ms)
10 ms
L
H
LDO OCP is masked during protection mask time.
Figure 17.
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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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3. Power down (normal)
VM
VthVM+
VM = 6 V
VthVM–
VM = 5 V
Mask
Shut Down
DCDC_B
DCDC_C
nORT
Protection Mask
(UVP, OVP)
Masks UVP, OVP on All DC-DC.
Masks UVP, OVP, and OCP on LDO.
Figure 18.
4. Power down (glitch on VM)
VM
VthVM+
VM = 6 V
VthVM–
VM = 5 V
Mask
DCDC_B
DCDC_C
nORT
Masks UVP, OVP on All DC-DC.
Masks UVP, OVP, and OCP on LDO.
Protection Mask
(UVP, OVP)
Figure 19.
30
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
5. Power down (glitch on VM below VthVM–)
VM
(CSELECT = Open)
VthVM+
VthVM+
VM = 6 V
VthVM–
Restart
Shut Down
10 ms
(Note A)
DCDC_B
10 ms
DCDC_C
nORT
Protection Mask
(UVP, OVP)
A.
LDO OCP is masked during protection mask time.
Figure 20.
nReset
nORT
See Note A
A.
2.5 μs < (nReset Deglitch + Output Delay) < 10 μs
Figure 21. Shut Down by nReset
Copyright © 2009–2011, Texas Instruments Incorporated
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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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Blanking Time Insertion Timing for DC Motor Driving
For the dc motor-driving H-bridge, tBlank is inserted at each phase reversal and following each chopping cycle
(once in every eight OSCM clocks).
For a large n number (5 or 6), tBlank setup may decrease the Itrip detect window. Care must be taken when
optimizing this in the system.
Case A: Phase duty = 25%
•
•
A*1 for setup bit = (1,0)
A*2 for setup bit = (0,1)
OSCM
Phase
Resync
Resync
Resync
Resync
fChop
8 ´ OSCM Clocks
tBlank (0,1)
(see Note A)
tBlank (1,0)
(see Note B)
2.5 µs
2.5 µs
5 µs
2.5 µs
5 µs
2.5 µs
<5 µs
5 µs
A.
Setup register bit <1:0> = (1,0), tBlank = 5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
B.
Setup register bit <1:0> = (0,1), tBlank = 2.5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
2.5 µs
5 µs
Case B: Phase duty = 40%
•
•
B*1 for setup bit = (1,0)
B*2 for setup bit = (0,1)
OSCM
Phase
Resync
Resync
Resync
Resync
2.5 µs
2.5 µs
fChop
8 ´ OSCM Clocks
tBlank (0,1)
(see Note A)
tBlank (1,0)
(see Note B)
32
8 ´ OSCM Clocks
2.5 µs
2.5 µs
5 µs
5 µs
<2.5 µs
<5 µs
A.
Setup register bit <1:0> = (1,0), tBlank = 5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
B.
Setup register bit <1:0> = (0,1), tBlank = 2.5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
5 µs
5 µs
Copyright © 2009–2011, Texas Instruments Incorporated
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
Function Table in nORT, Power Down, VM Conditions
The following is valid only when the protection control bits (in Extended Setup register) are all 0.
Table 11.
DEVICE STATUS
CHARGE PUMP
OSCM
nORT
MODE SETTING
nSleep
Active
Active
Inactive
Available
nORT
Inactive
Active
Active
Depend on power down
VM < 6 V during power down
Active
Active
See timing chart
Depend on power down
4.5 V < VM
Inactive
Inactive
Active
Unavailable
Table 12. Shutdown Functions
•
•
•
•
•
FAULT CONDITION
DCDC_A
DCDC_B
DCDC_C
MOTOR
nORT
DCDC_A UVP/OVP/OCP
Shut down
Shut down
Shut down
Shut down
Asserted (low)
DCDC_B UVP/OVP/OCP
Shut down
Shut down
Shut down
Shut down
Asserted (low)
DCDC_C UVP/OVP/OCP
Shut down
Shut down
Shut down
Shut down
Asserted (low)
Motor OCP
See MISD Control
Table
See MISD Control
Table
See MISD Control
Table
See MISD Control
Table
See MISD Control
Table
TSD
See TSD Control
Table
See TSD Control
Table
See TSD Control
Table
See TSD Control
Table
See TSD Control
Table
Table is valid when the Protection and Reset Mask bits in the Extended Setup register are all 0.
If Reset Mask (selective shutdown) bits are set, shutdown and release description is in the note following the
Extended Setup register definition.
DC-DC regulators are released at VM > VthVM+ when VM increasing. When VM decreasing, regulators are shut
down when VM < VthVM–. When VthVM+ > VM > VthVM–, OVP and UVP are masked.
Motor OCP shutdown release is specified in MISD Control Table.
TSD shutdown release is specified in TSD Control Table.
Copyright © 2009–2011, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DRV8808DCA
ACTIVE
HTSSOP
DCA
48
DRV8808DCAR
ACTIVE
HTSSOP
DCA
48
40
TBD
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
Call TI
CU NIPDAU
MSL Peak Temp (3)
Call TI
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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