Renesas ISL9506 Multiphase pwm controller with programmable output voltage Datasheet

DATASHEET
ISL9506
FN6722
Rev 0.00
August 13, 2008
Multiphase PWM Controller with Programmable Output Voltage
The ISL9506 is a multiphase PWM buck controller for high
performance digital processor core. This multiphase buck
controller uses interleaved channels to reduce the total output
voltage ripple with each channel carrying a portion of total load
current. The multiple phase implementation results in better
system performance, superior thermal management, lower
component cost, reduced power dissipation, and smaller
implementation area. The ISL9506 multiphase controller
together with ISL6208 external gate drivers provide a complete
solution to power the processor core. The PWM modulator of
ISL9506 is based on Intersil's Robust Ripple Regulator
technology (R3). Compared with the traditional multiphase buck
regulator, the R3 modulator commands variable switching
frequency during load transients, which achieves faster
transient response. With the same modulator, the switching
frequency is reduced at light load conditions resulting higher
operation efficiency.
Features
ISL9506 responds to LP (Low Power) signal by adding or
dropping PWM2 and adjusting overcurrent protection
accordingly. ISL9506 enables diode emulation and stretches
switching period at light load conditions to improve efficiency.
The diode emulation feature is programmed by DE_EN (Diode
Emulation Enable) and DE_ENN pins.
• Excellent Dynamic Current Balance between Channels
The ISL9506 has several other key features. ISL9506 reports
output power through a power monitor pin (PMON). Current
sense can be achieved by using either inductor DCR or discrete
precision resistor. In the case of DCR current sensing, a single NTC
thermistor is used to thermally compensate the inductor DCR
variation with temperature. A unity gain, differential amplifier is
available for remote voltage sensing. This allows the voltage at the
load point to be accurately measured and regulated per voltage
selection pins.
• High Performance Point-of-Load Power Supply
FN6722 Rev 0.00
August 13, 2008
• Small Footprint 40 Ld 6x6 QFN Package
• Pb-Free (RoHS compliant)
Applications
• Mobile Laptop Computers
Pinout
PGOOD
3V3
PGD_N
DE_ENN
DE_EN
VR_EN
VSEL6
VSEL5
VSEL4
VSEL3
ISL9506
(40 LD QFN)
TOP VIEW
40
39
38
37
36
35
34
33
32
31
LP 1
30 VSEL2
PMON 2
29 VSEL1
RBIAS 3
28 VSEL0
VRHOT# 4
27 PWM1
NTC 5
26 PWM2
GND PAD
(BOTTOM)
SOFT 6
25 PWM3
VW 8
23 ISEN1
COMP 9
22 ISEN2
FB 10
21 ISEN3
11
12
13
14
15
16
17
18
19
20
VDD
24 FCCM
VSS
OCSET 7
VIN
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
• Programmable 1, 2 or 3 Power Channels
VSUM
ISL9506HRZ-T ISL9506 HRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
Tape and Reel
• Differential Remote Voltage Sensing
VO
ISL9506 HRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
• Power Monitor and Thermal Monitor
DFB
PKG.
DWG. #
• Superior Noise Immunity and Transient Response
DROOP
PACKAGE
(Pb-Free)
• Optimized Efficiency across Overall Load Range
RTN
ISL9506HRZ
PART
MARKING
TEMP.
RANGE
(°C)
• Multiple Current Sensing Approaches Supported
- Lossless DCR Current Sensing
- Precision Resistive Current Sensing
VSEN
PART
NUMBER
(Note)
• Voltage Selection Input
- 7-Bit VSEL (Voltage Selection) Input
- 0.300V to 1.500V in 12.5mV Steps
- Supports VSEL Changes On-The-Fly
VDIFF
Ordering Information
• Precision Multiphase Voltage Regulation
- 0.5% System Accuracy Over Temperature
- Enhanced Droop Impedance Accuracy
Page 1 of 28
ISL9506
Functional Pin Description
PGOOD
3V3
PGD_N
DE_ENN
DE_EN
VR_EN
VSEL6
VSEL5
VSEL4
VSEL3
VW (Pin 8)
40
39
38
37
36
35
34
33
32
31
A resistor from this pin to COMP programs the switching
frequency. (7k gives approximately 300kHz). VW pin
sources current.
COMP (Pin 9)
LP 1
30 VSEL2
PMON 2
29 VSEL1
RBIAS 3
28 VSEL0
VRHOT# 4
27 PWM1
NTC 5
FB (Pin 10)
This pin is the inverting input of error amplifier.
VDIFF (Pin 11)
This pin is the output of the differential amplifier.
26 PWM2
GND PAD
(BOTTOM)
SOFT 6
This pin is the output of the error amplifier.
25 PWM3
VSEN (Pin 12)
OCSET 7
24 FCCM
Remote output voltage sense input. Connect to the point of
load.
VW 8
23 ISEN1
RTN (Pin 13)
COMP 9
22 ISEN2
FB 10
21 ISEN3
Remote voltage sensing return. Connect to ground at the
point of load.
12
13
14
15
16
17
18
19
20
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
DROOP (Pin 14)
11
LP (Pin 1)
Low power indicator input. When asserted low, indicates a
reduced load-current condition. For ISL9506, when LP is
asserted low, PWM2 will be disabled.
PMON (Pin 2)
An analog output. PMON sends out an analog signal
proportional to the product of VSEN voltage and the droop
voltage.
Output of droop amplifier. Output = VO + DROOP.
DFB (Pin 15)
Inverting input to droop amplifier.
VO (Pin 16)
An input to the IC that reports the local output voltage.
VSUM (Pin 17)
This pin is connected to the current summation junction.
VIN (Pin 18)
Battery supply voltage, used for feed forward.
VSS (Pin 19)
RBIAS (Pin 3)
Connect a 147k Resistor to VSS, sets the internal current
reference.
VRHOT# (Pin 4)
Thermal overload output indicator.
NTC (Pin 5)
Thermistor input to VRHOT# circuit.
SOFT (Pin 6)
A capacitor from this pin to VSS sets the maximum slew rate
of the output voltage. It affects both soft start and VSEL
transitioning slew rate. SOFT pin is the non-inverting input of
the error amplifier.
OCSET (Pin 7)
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
FN6722 Rev 0.00
August 13, 2008
Signal ground; Connect to local controller ground.
VDD (Pin 20)
5V bias power.
ISEN3 (Pin 21)
Individual current sensing for Channel 3.
ISEN2 (Pin 22)
Individual current sensing for Channel 2.
ISEN1 (Pin 23)
Individual current sensing for Channel 1.
FCCM (Pin 24)
Forced Continuous Conduction Mode (FCCM) enable pin to
MOSFET drivers. It will disable diode emulation.
PWM3 (Pin 25)
PWM output for Channel 3. When PWM3 is pulled to 5V
VDD, PWM3 will be disabled and allow other channels to
operate.
Page 2 of 28
ISL9506
PWM2 (Pin 26)
DE_ENN (Pin 37)
PWM output for Channel 2. For ISL9506, LP low will make
this output tri-state. When PWM2 is pulled to 5V VDD,
PWM2 will be disabled and allow other channels to operate.
DE_EN and DE_ENN work together for diode emulation.
Generally a reversed logic signal of DE_EN should be
applied to DE_ENN.
PWM1 (Pin 27)
PGD_N (Pin 38)
PWM output for channel 1.
Digital output prior to PGOOD high. Goes nominal (logic 0)
after 13 switching cycles after VOUT is within 10% of 1.2V
voltage at start-up.
VSEL0:6 (Pin28:Pin34)
Voltage Selection input with VSEL0 = LSB and VSEL6
= MSB.
VR_EN (Pin 35)
Voltage Regulator Enable input. A high level logic signal on
this pin enables the regulator.
DE_EN (Pin 36)
Diode Emulation Enable signal. A high level logic signal on
this pin will allow diode emulation operation. Only if the
current is low enough, the diode emulation will actually be
entered. DE_EN logic high also affects the output voltage
transition from one voltage selection to anther programmed
by voltage select.
FN6722 Rev 0.00
August 13, 2008
3V3 (Pin 39)
3.3V supply voltage for PGD_N logic, such an
implementation will increase power consumption from 3.3V
compared to open drain circuit other wise.
PGOOD (Pin 40)
Power Good open-drain output. Will be pulled up externally
by a 1.9k resistor to 3.3V.
Page 3 of 28
ISL9506
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Open Drain Outputs, PGOOD, VRHOT# . . . . . . . . . . . . -0.3 to +7V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Thermal Resistance (Notes 1, 2)
JA (°C/W) JC (°C/W)
40 Ld QFN Package. . . . . . . . . . . . . . .
30
5.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . +5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Limits established by characterization and are not production tested.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.6
4.2
mA
VR_EN = 0V
1
µA
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_EN = 3.3V
+3.3V Supply Current
I3V3
No load on PGD_N
1
µA
Battery Supply Current
IVIN
VR_EN = 0V
1
µA
VIN Input Resistance
RVIN
VR_EN = 3.3V
900
Power-On-Reset Threshold
PORr
VDD rising
4.35
PORf
VDD falling
4.00
k
4.5
4.15
V
V
SYSTEM AND REFERENCES
System Accuracy
%Error (VOUT) No load; closed loop, nominal mode range
VSEL = 0.75V to 1.50V
-0.5
+0.5
%
VSEL = 0.5V to 0.7375V
-8
+8
mV
VSEL = 0.3 to 0.4875V
-15
+15
mV
1.224
V
VSTART
1.176
1.200
Maximum Output Voltage
VOUT(max)
VSEL = [0000000]
1.500
V
Minimum Output Voltage
VOUT(min)
VSEL = [1100000]
0.300
V
VSEL Off State
VSEL = [1111111]
0.0
V
RBIAS Voltage
RBIAS = 147k
1.45
1.47
1.49
V
RFSET = 7k, 3 channel operation,
VCOMP = 2V
285
300
315
kHz
See Equation 6 RFSET selection
200
500
kHz
-0.3
+0.3
mV
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW(nom)
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
Av0
Error Amp Gain-Bandwidth Product
GBW
FB Input Current
IIN(FB)
FN6722 Rev 0.00
August 13, 2008
(Note 3)
90
dB
CL= 20pF (Note 3)
18
MHz
10
150
nA
Page 4 of 28
ISL9506
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
2
mV
ISEN
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
Input Bias Current
20
nA
SOFT CURRENT
Soft-start Current
ISS
SOFT Geyserville Current
IGV
|SOFT-VDAC| >100mV
SOFT DIODE EMULATION Entry
Current
IC4
SOFT DIODE EMULATION Exit
Current
SOFT DIODE EMULATION Exit
Current
-47
-42
-37
µA
180
205
230
µA
DE_EN = 3.3V
-47
-42
-37
µA
IC4EA
DE_EN = 3.3V
37
42
47
µA
IC4EB
DE_EN = 0V
180
205
230
µA
0.26
0.4
V
1
µA
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD= 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
PGOOD Delay
tpgd
PGD_N LOW to PGOOD HIGH
6.3
7.6
8.9
ms
Overvoltage Threshold
OVH
VO rising above setpoint for >1ms
160
200
240
mV
Severe Overvoltage Threshold
OVHS
VO rising for >2µs
1.675
1.7
1.725
V
10
10.2
µA
4
mV
OCSET Reference Current
I(RBIAS) = 10µA
9.8
OC Threshold Offset
DROOP rising above OCSET for >150µs
-2
Current Imbalance Threshold
One ISEN above another ISEN for >1.2ms
Undervoltage Threshold
(VDIFF/SOFT)
UVf
VO falling below setpoint for >1.2ms
9
-355
-295
mV
-235
mV
1.0
V
LOGIC THRESHOLDS
VR_EN and DE_EN Input Low
VIL(3.3V)
VR_EN and DE_EN Input High
VIH(3.3V)
VSEL0: VSEL6, LP, DE_ENN Input
Low
VIL(1.0V)
VSEL0: VSEL6, LP, DE_ENN Input
High
VIH(1.0V)
2.3
V
0.3
0.7
V
V
PWM
PWM (PWM1 to PWM3) Output Low
VOL(5.0V)
Sinking 5mA
1.0
V
FCCM Output Low
VOL_FCCM
Sinking 3mA
1.0
V
PWM (PWM1 to PWM3) and FCCM
Output High
VOH(5.0V)
Sourcing 5mA
3.5
PWM = 2.5V
-1
NTC Source Current
NTC = 1.3V
53
Over-Temperature Threshold
V (NTC) falling
1.18
PWM Tri-State Leakage
V
1
µA
60
67
µA
1.2
1.22
V
6.5
9

THERMAL MONITOR
VRHOT# Low Output Resistance
FN6722 Rev 0.00
August 13, 2008
RTT
I = 20mA
Page 5 of 28
ISL9506
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
2.9
3.1
MAX
UNITS
PGD_N OUTPUT LEVELS
PGD_N High Output Voltage
VOH
3V3 = 3.3V, I = -4mA
PGD_N Low Output Voltage
VOL
I = 4mA
V
0.26
0.4
V
POWER MONITOR
PMON Output Voltage
VPMON
PMON Maximum Voltage
VSEN = 1.2V, Droop - Vo = 80mV
1.638
1.68
1.722
V
VSEN = 1.0V, Droop - Vo = 20mV
0.308
0.35
0.392
V
2.8
3
VPMONMAX
V
PMON Sourcing Current
VSEN = 1.0V, Droop - Vo = 50mV
2.0
mA
PMON Sinking Current
VSEN = 1.0V, Droop-Vo = 50mV
2.0
mA
Maximum Current Sinking Capability
See Figure 36
PMON Impedance
When PMON is within its sourcing/sinking
current range (Note 3)
VPMON/ VPMON/ VPMON/
250
180
130
A
7

Typical Operating Performance 3-Phase, DCR Sense, HS one IRF7821, LS two IRF7832 per phase, 300kHz, 0.5µH
100
1.46
VIN = 12.6V
VIN = 12.6V
1.44
VIN = 8.0V
VIN = 8.0V
1.42
VIN = 19.0V
80
V OUT (V)
EFFICIENCY (%)
90
70
1.40
VIN = 19.0V
1.38
1.36
60
1.34
50
1
1.32
100
10
0
10
20
IOUT (A)
40
50
FIGURE 2. DROOP IMPEDANCE, 3 PHASE, CCM, LP = HIGH
FIGURE 1. NOMINAL MODE EFFICIENCY, 3 PHASE, CCM,
VSEL = 1.435V
LP = HIGH, VSEL = 1.4375V
100
1.44
VIN = 8.0V
90
1.43
VIN = 12.6V
VIN = 8.0V
1.42
VIN = 19.0V
80
VOUT (V)
EFFICIENCY (%)
30
IOUT (A)
70
1.41
VIN = 12.6V
1.40
1.39
VIN = 19.0V
1.38
60
1.37
50
10
1
100
IOUT (A)
FIGURE 3. DIODE EMULATION MODE EFFICIENCY, 3 PHASE,
DCM OPERATION, LP = LOW, VSEL = 1.4375V
FN6722 Rev 0.00
August 13, 2008
1.36
0
10
20
30
IOUT (A)
FIGURE 4. DIODE EMULATION MODE DROOP IMPEDANCE,
3 PHASE, CCM, LP = LOW VSEL = 1.435V
Page 6 of 28
ISL9506
Typical Operating Performance 3-Phase, DCR Sense, HS one IRF7821, LS two IRF7832 per phase, 300kHz, 0.5µH
100
0.76
0.75
VIN = 12.6V
VIN = 8.0V
80
VIN = 19.0V
70
VIN = 8.0V
0.74
VOUT (V)
EFFICIENCY (%)
90
VIN = 12.6V
0.73
0.72
0.71
VIN = 19.0V
0.70
60
0.69
50
0.1
1.0
0.68
10.0
0
10
FIGURE 5. DIODE EMULATION MODE EFFICIENCY, 3 PHASE,
PHASE, DCM OPERATION, LP = LOW, VSEL = 0.75V
100
100
EFFICIENCY (%)
VIN = 8.0V
90
EFFICIENCY (%)
VIN = 12.6V
90
VIN = 19.0V
80
70
VIN = 12.6V
VIN = 8.0V
VIN = 19.0V
80
70
60
60
1
10
50
0.1
100
1.0
10.0
IOUT (A)
IOUT (A)
FIGURE 7. NOMINAL MODE EFFICIENCY, 2 PHASE, CCM,
FIGURE 8. DIODE EMULATION MODE EFFICIENCY, 2 PHASE,
LP = HIGH, VSEL = 1.4375V
DCM OPERATION, LP = LOW, VSEL = 1.4375V
1.44
100
1.42
90
VIN = 12.6V
1.40
80
VIN = 19.0V
70
VIN = 8.0V
VIN = 8.0V
VOUT (V)
EFFICIENCY (%)
30
FIGURE 6. DIODE EMULATION MODE DROOP IMPEDANCE, 3
DCM OPERATION, LP = LOW, VSEL = 0.75V
50
20
IOUT (A)
IOUT (A)
60
VIN = 12.6V
1.38
1.36
VIN = 19.0V
1.34
50
0.1
1.0
10.0
IOUT (A)
FIGURE 9. DIODE EMULATION MODE EFFICIENCY, 2 PHASE,
DCM OPERATION, LP = LOW, VSEL = 0.75V
FN6722 Rev 0.00
August 13, 2008
1.32
0
10
20
30
40
50
IOUT (A)
FIGURE 10. NOMINAL MODE DROOP IMPEDANCE, 2 PHASE,
CCM, LP = HIGH, VSEL = 1.435V
Page 7 of 28
ISL9506
Typical Operating Performance 3-Phase, DCR Sense, HS one IRF7821, LS two IRF7832 per phase, 300kHz, 0.5µH
0.76
1.44
VIN = 8.0V
1.43
1.41
1.40
1.39
VIN = 19.0V
0.72
0.71
0.70
1.37
0.69
0
10
20
30
VIN = 12.6V
0.73
1.38
1.36
VIN = 8.0V
0.74
VOUT (V)
VOUT (V)
0.75
VIN = 12.6V
1.42
0.68
VIN = 19.0V
0
10
IOUT (A)
20
30
IOUT (A)
FIGURE 11. DIODE EMULATION MODE DROOP IMPEDANCE,
2 PHASE, DCM OPERATION, LP = LOW, VSEL = 1.4375V
FIGURE 12. DIODE EMULATION MODE DROOP IMPEDANCE,
2 PHASE, DCM OPERATION, LP = LOW, VSEL = 0.75V
Typical Operating Performance
VSOFT (Green)
VOUT
VOUT (Brown)
PGOOD
PGD_N
VR_EN
FIGURE 13. SOFT-START WAVEFORM 0V TO 1.2V (START
VOLTAGE) AND PGD_N TIMING
VIN
VR_EN
FIGURE 14. SOFT-START WAVEFORM SHOWING PGOOD
VOUT
VOUT
FIGURE 15. 12V-18V INPUT LINE TRANSIENT RESPONSE
FN6722 Rev 0.00
August 13, 2008
FIGURE 16. SOFT-START INRUSH CURRENT, VIN = 8V
Page 8 of 28
ISL9506
Typical Operating Performance (Continued)
FIGURE 17. 3 PHASE CURRENT BALANCE, FULL LOAD = 50A
FIGURE 18. 2 PHASE CURRENT BALANCE, FULL LOAD = 50A
VOUT
COMP PIN
FIGURE 19. TRANSIENT LOAD RESPONSE, 40A LOAD STEP
@ 200A/µs, 3 PHASE
FIGURE 20. TRANSIENT LOAD 3 PHASE OPERATION CURRENT BALANCE
FIGURE 21. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM
OF RISING EDGE CURRENT BALANCE
FIGURE 22. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM
OF FALLING EDGE CURRENT BALANCE
FN6722 Rev 0.00
August 13, 2008
Page 9 of 28
ISL9506
Typical Operating Performance (Continued)
VSEL MSB
VSEL MSB
VOUT
VOUT
FIGURE 23. VSEL MSB BIT CHANGE FROM 1.4375V TO 0.65V
SHOWING 9mV/µs SLEW RATE, DE_EN = 0,
DE_ENN = 1
FIGURE 24. SLEW RATE ENTERING C4, VSEL MSB BIT
CHANGE FROM 1.4375V TO 0.65V SHOWING
2mV/µs SLEW RATE, DE_EN = 1, DE_ENN = 0
VOUT
VOUT @ 1.7V
PWM
DE_ENN AND LP
VOUT @ 0.85V
DE_EN AND MSB
FIGURE 25. C4 ENTRY AND EXIT SLEW RATES WITH DE_EN
AND DE_ENN
FIGURE 26. 1.7V OVP SHOWING OUTPUT PULLED LOW TO
0.85V AND PWM TRI_STATE
PWM
PWM
VOUT
IPHASE
PGOOD
VOUT
FIGURE 27. UNDERVOLTAGE RESPONSE SHOWING PWM
TRI-STATE, VOUT < VSEL - 300mV
FN6722 Rev 0.00
August 13, 2008
PGOOD
FIGURE 28. OCP - RESPONSE
Page 10 of 28
ISL9506
Typical Operating Performance (Continued)
PWM
LP
PGD_N
IPHASE
VOUT
PGOOD
VOUT
PHASE 2
FIGURE 29. WOCP - SHORT CIRCUIT PROTECTION
FIGURE 30. ISL9506, PHASE ADDING AND DROPPING IN
NOMINAL MODE, LOAD CURRENT = 15A
PHASE 3 CURRENT
LP
PGD_N
VOUT
PHASE 1 CURRENT
PHASE 2
CURRENT
PHASE 2
PHASE 2
FIGURE 31. ISL9506 PHASE ADDING AND DROPPING IN DIODE
EMULATION MODE, LOAD CURRENT = 4.35A
FN6722 Rev 0.00
August 13, 2008
FIGURE 32. ISL9506, INDUCTOR CURRENT WAVEFORM
WITH PHASE ADDING AND DROPPING IN DCM
OR DIODE EMULATION MODE
Page 11 of 28
ISL9506
Typical Operating Performance (Continued)
PHASE 3
CURRENT
PHASE 1 CURRENT
PHASE 2 CURRENT
PHASE 1 CURRENT
PGOOD
PHASE 2 CURRENT
FIGURE 33. ISL9506, INDUCTOR CURRENT WAVEFORM
WITH PHASE ADDING AND DROPPING IN CCM
OR NOMINAL MODE
FIGURE 34. ISL9506, OVERCURRENT DUE TO PHASE
DROPPING
1.8
PMON (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.8
VSEL = 1.15V, IOUT = 15A
0.7
7
19V, 1.15V, 40A
0.6
PMON (V)
1.6
19V, 1.15V, 30A
19V, 1.15V, 20A
0.5
VSEL = 1.15V, IOUT = 10A
0.4
180
0.3
VSEL = 1.15V, IOUT = 5A
0.2
19V, 1.15V, 10A
0.1
19V, 1.15V, 5A
1.0
2.0
3.0
4.0
5.0
CURRENT SOURCING (mA)
6.0
0.0
0.0
7.0
VSEL = 1.15V, IOUT = 2.5A
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
CURRENT SINKING (mA)
FIGURE 35. POWER MONITOR CURRENT SOURCING
CAPABILITY
FIGURE 36. POWER MONITOR CURRENT SINKING
CAPABILITY
60.0
25%
VIN = 19V
VSEL = 1.15V
50.0
POWER (W)
20%
15%
10%
5%
40.0
PMON
30.0
20.0
MEASURED OUTPUT POWER
10.0
0%
0.0
10.0
20.0
30.0
40.0
OUTPUT CURRENT (A)
FIGURE 37. POWER MONITOR ACCURACY
FN6722 Rev 0.00
August 13, 2008
50.0
0.0
0.0
10.0
20.0
30.0
40.0
50.0
CURRENT (A)
FIGURE 38. POWER MONITOR vs OUTPUT CURRENT
Page 12 of 28
ISL9506
Simplified Application Circuit for DCR Current Sensing
Figure 39 shows a simplified application circuit for the ISL9506 converter with inductor DCR current sensing. The ISL6208
MOSFET gate driver has a force-continuous-conduction-mode (FCCM) input, that when disabled, allows the regulator to operate in
Diode Emulation for improved light load efficiency. As shown in the circuit diagram, the FCCM pin is connected to ISL9506, which
programs the CCM or DCM mode.
V+5
VIN
V+3.3
VIN
3V3
VIN
VDD
V+5
RBIAS
VCC
NTC
VRHOT#
VRHOT#
PWM
PWM1
ISEN1
LO
UGATE
ISL6208
PHASE
SOFT
7
BOOT
RL
FCCM
VSEL<0:6>
VSELs
DE_ENN
DE_ENN
LGATE
GND
CL
ISEN1
VSUM
DE_EN
LP
VO
ISL9506
LP
V+5
PMON
PWR MONITOR
PGD_N
PGD_N
VCC
BOOT
PWM UGATE
PWM2
ISEN2
VR_EN
VR_EN
POWER GOOD
CO
LO
ISL6208
PHASE
PGOOD
RL
FCCM
Remote
Sense
at POL
LGATE
GND
VSEN
RTN
Ri
FCCM
VIN
VDIFF
C3
R3
C1
R1
VO'
VIN
DE_EN
CL
ISEN2
VSUM
VO'
V+5
VCC
FB
COMP
BOOT
PWM
PWM3
ISEN3
C2
RFSET
VW
ISL6208
VSUM
VSUM
PHASE
FCCM
LGATE
GND
OCSET
GND
LO
UGATE
DFB DROOP VO
RL
CL
ISEN3
VSUM
RN
CCS
VO'
VO'
FIGURE 39. TYPICAL APPLICATION CIRCUIT FOR DCR SENSING
FN6722 Rev 0.00
August 13, 2008
Page 13 of 28
ISL9506
Simplified Application Circuit for Resistive Current Sensing
Figure 40 shows a simplified application circuit for the ISL9506 converter with external resistor current sensing. A capacitor is
added in parallel with RL in order to improve the stability margin of the channel current balance loop. No NTC thermistor is needed
and the droop circuit is simplified.
V+5
V+3.3
VIN
VIN
VDD
3V3
VIN
V+5
RBIAS
VCC
NTC
VRHOT#
VRHOT#
PWM1
ISEN1
PWM
VSEL<0:6>
PHASE
VSELs
DE_EN
ISEN1
CL
ISL9506
VIN
VO
V+5
VCC
PGD_N
PWM2
ISEN2
PWM
VR_EN
POWER GOOD
CO
BOOT
LO
UGATE
PHASE
VSUM
FCCM
ISEN2
LGATE
GND
VSEN
FCCM
R3
C1
R1
CL
VIN
VDIFF
C3
RL
VO'
RTN
Ri
RSEN
ISL6208
PGOOD
Remote
Sense
at POL
RL
VO'
PMON
VR_EN
VSUM
LGATE
GND
LP
PGD_N
RSEN
FCCM
DE_ENN
PWR MONITOR
LO
UGATE
ISL6208
SOFT
7
BOOT
V+5
VCC
FB
COMP
BOOT
PWM3
ISEN3
PWM
C2
UGATE
LO
RSEN
ISL6208
RFSET
VW
VSUM
VSUM
VSUM
LGATE
GND
ISEN3
FCCM
OCSET
GND
PHASE
DFB DROOP VO
RL
CL
VO'
VO'
FIGURE 40. TYPICAL APPLICATION CIRCUIT FOR DISCRETE RESISTOR CURRENT SENSING
FN6722 Rev 0.00
August 13, 2008
Page 14 of 28
RBIAS
PMON PGOOD 3V3 PGD_N VIN
VO
ISEN1 ISEN2 ISEN3
ISL9506
FN6722 Rev 0.00
August 13, 2008
Functional Block Diagram
VDD
VIN
VSEL0
VSEL1
VSEL2
DACOUT
VSEL4
OC VIN VO
MULTIPLIER
54µA 6µA
PWM1
VOVSEN
OC
NUMBER OF
PHASES
10µA
GAIN SELECT)
OCSET
VRHOT#
FLT
MODULATOR
SOFT
DE_EN
DE_ENN
1.24V
+
2X
VO
MODE
CONTROL
1.20V
- +
MODE
CONTROL
FCCM
DFB
CURRENT
BALANCE
NTC
FAST_OC OR
WAY-OC
VSEL6
VSUM
IBAL
FLT
OC
IBAL VDIFF
VSEL5
LP
PGD_N
LOGIC
DAC
VSEL3
VR_EN
POWER
GOOD
MONITOR
PROTECTION
VIN VO
FLT
MODULATOR
+
PWM2
OC
OC
+
-
VIN VO
DROOP
DROOP
+ 1
VO
VSEN
+1
-
+
+
-
+
CLOCK
NUMBER OF
PHASES
MODE
CONTROL
VIN VO
Page 15 of 28
VO VSEN RTN
VDIFF SOFT FB
FLT
MODULATOR
E/A
COMP
VW
FIGURE 41. SIMPLIFIED BLOCK DIAGRAM
GND
PWM3
CHANNEL
SELECT
ISL9506
Theory of Operation
Operational Description
The ISL9506 is a multiphase regulator for digital processor
core power application. It can be programmed for 1-, 2- or 3channel operation. With ISL6208 gate driver capable of
diode emulation, the ISL9506 provides optimum efficiency in
both heavy and light load conditions.
VDD
10mV/µs
2mV/µs
VR_EN
120µs
1.2V
SOFT & VO
ISL9506 uses Intersil patented R3 (Robust Ripple
Regulator®) modulator. The R3® modulator combines the
best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. The ISL9506
modulator internally synthesizes analog signals inside the IC
emulating the inductor ripple currents and use hysteretic
comparators on those signals to determine switching pulse
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL9506 to achieve lower
output ripple and lower phase jitter than conventional
hysteretic and fixed PWM mode controllers. Unlike
conventional hysteretic converters, the ISL9506 has an error
amplifier that allows the controller to maintain a 0.5% output
voltage accuracy. At heavy load conditions, the ISL9506 is
switching at a relatively constant switching frequency similar
to fixed frequency PWM controller. At light load conditions,
the ISL9506 is switching at a frequency proportional to load
current similar to hysteretic mode controller.
The hysteresis window voltage rides on the error amplifier
output such that a load current transient results in an
increase in switching frequency to give the R3 regulator a
faster response than conventional fixed frequency PWM
controllers. The sharing of the hysteretic window voltage
also inherently shares the transient load current between the
phases. The individual average phase voltages are
monitored and controlled to equally share the static current
among the phases.
VSEL COMMANDED
VOLTAGE
90%
13 SWITCHING CYCLES
PGD_N
~7ms
PGOOD
FIGURE 42. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
the soft-start sequence starting 120µs after VDD crosses the
POR threshold.
Static Operation
VOLTAGE REGULATION AT ZERO LOAD CURRENT
After the start sequence, the output voltage will be regulated
to the value set by the VSEL inputs per Table 1. The ISL9506
will control the no-load output voltage to an accuracy of ±0.5%
over the range of 0.75V to 1.5V.
TABLE 1. VOLTAGE SELECTION TABLE
VSEL5 VSEL4 VSEL3 VSEL2 VSEL1 VSEL0 VSEL6=0 VSEL6=1
0
0
0
0
0
0
1.5000
0.7000
0
0
0
0
0
1
1.4875
0.6875
0
0
0
0
1
0
1.4750
0.6750
0
0
0
0
1
1
1.4625
0.6625
The ISL9506 disables PWM2 when LP is asserted low, and
the power monitor pin provides an analog signal
representing the output power of the converter.
0
0
0
1
0
0
1.4500
0.6500
0
0
0
1
0
1
1.4375
0.6375
0
0
0
1
1
0
1.4250
0.6250
Start-up Timing
0
0
0
1
1
1
1.4125
0.6125
0
0
1
0
0
0
1.4000
0.6000
0
0
1
0
0
1
1.3875
0.5875
0
0
1
0
1
0
1.3750
0.5750
0
0
1
0
1
1
1.3625
0.5625
0
0
1
1
0
0
1.3500
0.5500
0
0
1
1
0
1
1.3375
0.5375
0
0
1
1
1
0
1.3250
0.5250
0
0
1
1
1
1
1.3125
0.5125
0
1
0
0
0
0
1.3000
0.5000
0
1
0
0
0
1
1.2875
0.4875
0
1
0
0
1
0
1.2750
0.4750
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_EN
exceeds the 3.3V logic HIGH threshold. Approximately
120µs later SOFT and VOUT start ramping up to the start
voltage of 1.2V. During this interval, the SOFT capacitor is
charged with approximately 40µA. Therefore, if the SOFT
capacitor is selected to be 20nF, the SOFT ramp will be at
about 2mV/µs for a soft-start time of 600µs. Once VOUT is
within 10% of the start voltage for 13 PWM cycles (43µs for
frequency = 300kHz), then PGD_N is pulled LOW and the
SOFT capacitor is charged up with approximately 200µA.
Therefore, VOUT slews at +10mV/µs to the voltage set by
the VSEL pins. Approximately 7ms later, PGOOD is
asserted HIGH. A typical start-up timing is shown in
Figure 42. Similar results occur if VR_EN is tied to VDD, with
FN6722 Rev 0.00
August 13, 2008
Page 16 of 28
ISL9506
TABLE 1. VOLTAGE SELECTION TABLE (Continued)
TABLE 1. VOLTAGE SELECTION TABLE (Continued)
VSEL5 VSEL4 VSEL3 VSEL2 VSEL1 VSEL0 VSEL6=0 VSEL6=1
VSEL5 VSEL4 VSEL3 VSEL2 VSEL1 VSEL0 VSEL6=0 VSEL6=1
0
1
0
0
1
1
1.2625
0.4625
1
1
1
0
1
1
0.7625
OFF
0
1
0
1
0
0
1.2500
0.4500
1
1
1
1
0
0
0.7500
OFF
0
1
0
1
0
1
1.2375
0.4375
1
1
1
1
0
1
0.7375
OFF
0
1
0
1
1
0
1.2250
0.4250
1
1
1
1
1
0
0.7250
OFF
0
1
0
1
1
1
1.2125
0.4125
1
1
1
1
1
1
0.7125
OFF
0
1
1
0
0
0
1.2000
0.4000
0
1
1
0
0
1
1.1875
0.3875
0
1
1
0
1
0
1.1750
0.3750
A differential amplifier allows voltage sensing for precise
voltage regulation at the point of load. The inputs to the
amplifier are the VSEN and RTN pins.
0
1
1
0
1
1
1.1625
0.3625
DROOP IMPEDANCE OR DROOP ACCOMPLISHMENT
0
1
1
1
0
0
1.1500
0.3500
0
1
1
1
0
1
1.1375
0.3375
0
1
1
1
1
0
1.1250
0.3250
0
1
1
1
1
1
1.1125
0.3125
1
0
0
0
0
0
1.1000
0.3000
1
0
0
0
0
1
1.0875
OFF
1
0
0
0
1
0
1.0750
OFF
1
0
0
0
1
1
1.0625
OFF
1
0
0
1
0
0
1.0500
OFF
1
0
0
1
0
1
1.0375
OFF
1
0
0
1
1
0
1.0250
OFF
1
0
0
1
1
1
1.0125
OFF
As the load current increases from zero, the output voltage
will drop from the VSEL table value by an amount
proportional to load current to achieve certain droop
characteristics or droop impedance. The ISL9506 provides
for current to be sensed using resistors in series with the
channel inductors as shown in the application circuit of
Figure 40 or using the intrinsic series resistance of the
inductors as shown in the application circuit of Figure 39. In
both cases, signals representing the inductor currents are
summed at VSUM which is the non-inverting input to the
DROOP amplifier shown in the block diagram of Figure 41.
The voltage at the DROOP pin minus the output voltage at
VO pin is the total load current multiplied by a gain factor.
This value is used as an input to the differential amplifier to
achieve the desired droop impedance as well as the input of
the overcurrent circuit.
1
0
1
0
0
0
1.0000
OFF
1
0
1
0
0
1
0.9875
OFF
1
0
1
0
1
0
0.9750
OFF
1
0
1
0
1
1
0.9625
OFF
1
0
1
1
0
0
0.9500
OFF
1
0
1
1
0
1
0.9375
OFF
1
0
1
1
1
0
0.9250
OFF
1
0
1
1
1
1
0.9125
OFF
1
1
0
0
0
0
0.9000
OFF
1
1
0
0
0
1
0.8875
OFF
1
1
0
0
1
0
0.8750
OFF
1
1
0
0
1
1
0.8625
OFF
1
1
0
1
0
0
0.8500
OFF
1
1
0
1
0
1
0.8375
OFF
1
1
0
1
1
0
0.8250
OFF
1
1
0
1
1
1
0.8125
OFF
1
1
1
0
0
0
0.8000
OFF
1
1
1
0
0
1
0.7875
OFF
1
1
1
0
1
0
0.7750
OFF
FN6722 Rev 0.00
August 13, 2008
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load-line
accuracy with reduced cost.
PHASE CURRENT BALANCE
In addition to the total current which is used for DROOP and
OCP, the individual channel average currents are also
monitored by the phase node voltage. Channel current
differences are sensed by comparing ISEN1, ISEN2, and
ISEN3 voltage. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channels to
cause the voltages presented to the ISEN pins to be equal.
ENABLE AND DISABLE PHASES
The ISL9506 controller can be configured for three-, two- or
single-channel operation. To disable Channel 2 and/or
Channel 3, its PWM output pin should be tied to +5V and the
ISEN pins should be grounded. In three-channel operation,
the three-channel PWM's are phase shifted by 120°, and in
two-channel operation they are phase shifted by 180°.
Page 17 of 28
ISL9506
SWITCHING FREQUENCY IN CCM/DCM MODE
The switching frequency is adjusted by the resistor between
the error amplifier output and the VW pin. When ISL9506 is
in continuous conduction mode (CCM), the switching
frequency may not be as constant as that of a fixed
frequency PWM controllers. However, the switching
frequency variation will be kept small to maintain the output
voltage ripple within specification. In general, the switching
frequency will be very close to the set value at high input
voltage and heavy load conditions.
When DE_EN is high and DE_ENN is low, the FCCM pin will
become low, and discontinuous conduction mode (DCM)
operation will be allowed in the ISL6208 gate drive. In DCM,
ISL6208 turns off the lower FET after its channel current
across zero. As load is further reduced, channel switching
frequency will drop, providing optimized efficiency at light
load. FCCM logic low is the signal to enable, or to allow the
DCM operation. Only if the inductor current is really cross
zero, does the true DCM occur.
VOUT
-2m V/µS
DE_ENN
10m V/µS
2m V/µS
DE_EN
VSEL6
FIGURE 43. DIODE EMULATION TRANSITION SHOWING
DE_EN’s EFFECT ON EXIT SLEW RATE
Dynamic Operation
Refer to Figure 43. The ISL9506 responds to changes in
VSEL command voltage by slewing to new voltages with a
dV/dt set by the SOFT capacitor and by the state of DE_EN.
With CSOFT = 20nF and DE_EN is HIGH, the output voltage
will move at ±2mV/µs for large changes in voltage. For
DE_EN LOW, the large signal dV/dt will be ±10mV/µs. As
the output approaches the VSEL command voltage, the
dV/dt rate moderates to prevent overshoot. During
Geyserville III transitions where there is one LSB VSEL step
each 5µs, the controller will follow the VSEL command with
its dV/dt rate of ±2.5mV/µs.
Keeping DE_EN HIGH during VSEL transitions will result in
reduced dV/dt slew rate and lesser audio noise. For fastest
recovery from Diode Emulation to Nominal mode, DE_EN
LOW achieves higher dV/dt.
Intersil's R3 intrinsically has voltage-feed-forward. The
output voltage is insensitive to a fast slew input voltage
change. Refer to Figure 15 in the “Typical Operating
Performance” on page 8” section of this document for Input
Transient Performance.
FN6722 Rev 0.00
August 13, 2008
The hysteresis window voltage is constructed with a resistor on
the VW pin to the error amplifier outputs. The synthesized
inductor current ripple signal compares with the window voltage
and generates PWM signal. At load current step-up, the
switching frequency is increased resulting in a faster response
than conventional fixed frequency PWM controllers. As all the
phases shares the same hysteretic window voltage, it also
ensures excellent dynamic current balance between phases.
The individual average phase voltages are monitored and
controlled to achieve steady state current balance among the
phases with current balance loop.
Modes of Operation Programmed by Logic Signals
The operational modes of ISL9506 are programmed by the
control signals of DE_EN, DE_ENN, and LP. ISL9506
responds LP signal by adding or dropping PWM2 and
adjusting the overcurrent protection level accordingly. For
example, if the ISL9506 is initially used as 3-phase
controller, the LP signal will add or drop PWM2 and leave
PWM1 and PWM3 always in operation. Meanwhile, after
PWM2 is dropped, the phase shift between the PWM1 and
PWM3 is adjusted from 120° to 180° and the overcurrent
and the way-overcurrent protection level will be adjusted to
2/3 of the initial value. If the ISL9506 is initially used as
2-phase operation, it is suggested that PWM1 and PWM2
pair, not PWM1 and PWM3 pair, should be used such that
the LP signal will enable or disable PWM2 with PWM1 in
operation always. The overcurrent and way-overcurrent
protection level in two-to-one phase mode operation will be
adjusted as two-to-one as well.
The DCM mode operation is independent of LP for ISL9506.
It responds to the DE_EN and DE_ENN. Table 2 shows the
operation modes of ISL9506 with combinations of control
logic.
When LP is de-asserted low, ISEN2 pin is connected to the
ISEN pins of the operational phases internally to keep
proper current balance and minimize the inductor current
overshoot and undershoot when the disabled phase is
enabled again.
TABLE 2. ISL9506 MODE OF OPERATIONS
MODE OF
OPERATION
DE_EN
DE_ENN
LP
0
1
1
N phase CCM
Nominal
MODE
0
1
0
N-1 phase CCM
Low Power
1
0
1
N phase DCM
Diode
Emulation
1
0
0
N-1 phase DCM
Diode
Emulation
0
0
1
N phase CCM
0
0
0
N-1 phase CCM
1
1
1
N phase CCM
1
1
0
N-1phase CCM
Page 18 of 28
ISL9506
TABLE 3. THE FAULT PROTECTION AND RESET OPERATION OF ISL9506
FAULT DURATION
PRIOR TO
PROTECTION
PROTECTION
ACTIONS
FAULT RESET
Overcurrent
120µs
PWMs tri-state, PGOOD latched low
VR_EN toggle or VDD toggle
Way-Overcurrent (2.5 X
OC)
<2µs
PWMs tri-state, PGOOD latched low
VR_EN toggle or VDD toggle
Overvoltage 1.7V
Immediately
Low side MOSFET on until Vcore <0.85V, then PWM
tri-state, PGOOD latched low.
VDD toggle
Overvoltage +200mV
1ms
PWMs tri-state, PGOOD latched low
VR_EN toggle or VDD toggle
Undervoltage -300mV
1ms
PWMs tri-state, PGOOD latched low
VR_EN toggle or VDD toggle
Phase-Current Unbalance
1ms
PWMs tri-state, PGOOD latched low
VR_EN toggle or VDD toggle
Over-Temperature
Immediately
VRHOT# goes low
N/A
Protection
The ISL9506 provides overcurrent, overvoltage, and
undervoltage protection. Overcurrent protection is related to
the voltage droop which is determined by the droop
impedance requirement. After the load-line is set, the OCSET
resistor can be selected to detect overcurrent at any level of
droop voltage. For overcurrent less that 2.5x the OCSET
level, the overload condition must exist for 120µs in order to
trip the OC fault latch. This is shown in Figure 28.
For overload exceeding 2.5x the OCSET level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection due to hard short circuit. This protection
was referred to as way-overcurrent or fast over current, for
short-circuit protections.
In addition, excessive phase unbalance due to gate driver
failure will be detected and will shut down the controller. The
phase unbalance is detected by the voltage on the ISEN pin.
If the ISEN pin voltage difference is greater than 9mV for 1ms,
the controller will latch off.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VSEL set value by
300mV or more, a fault will latch after 1ms in that condition.
The PWM outputs will turn off and PGOOD will go low. This
is shown in Figure 27. Note that most practical core voltage
regulators will have the overcurrent set to trip before the
-300mV undervoltage limit.
There are two levels of overvoltage protection with different
responses. The first level of overvoltage protection is
referred to as PGOOD overvoltage protection. Basically, for
output voltage exceeding the set value by +200mV for 1ms,
a fault will be declared with PGOOD latched low.
All of the above faults have the same action taken: PGOOD
is latched low and the upper and lower power FETs are
turned off so that inductor current will decay through the
FETbody diodes. This condition can be reset by bringing
VR_EN low or by bringing VDD below POR threshold. When
FN6722 Rev 0.00
August 13, 2008
these inputs are returned to their high operating levels, a
soft-start will occur.
The second level of overvoltage protection behaves
differently. If the output exceeds 1.7V, an OV fault is
immediately declared, PGOOD is latched low and the
low-side FETs are turned on. The low-side FETs will remain
on until the output voltage is pulled down below 0.85V at
which time all FETs are turned off. If the output again rises
above 1.7V, the process is repeated. This affords the
maximum amount of protection against a shorted high-side
FET while preventing output ringing below ground. The 1.7V
OVP cannot be reset with VR_EN, but requires that VDD be
lowered to reset. The 1.7V OV detector is nominal at all
times when the controller is enabled including after one of
the other faults occurs. This ensures the load is protected
against high-side FET leakage while the FETs are
commanded off. The ISL9506 has a thermal throttling
feature. If the voltage on the NTC pin goes below the 1.18V
OT threshold, the VRHOT# pin is pulled low indicating the
need for thermal throttling to the system oversight load. No
other action is taken within the ISL9506 in response to NTC
pin voltage.
Fault protection is summarized in Table 3.
Power Monitor
The power monitor signal is an analog output. Its magnitude
is proportional to the product of VSEN and the voltage
difference between VDROOP and VO, which is the
programmed droop impedance multiplied by load current.
The output voltage of the PMON pin is given by:
V PMON = V SEN * (V
– V O *17.5 (Volt)
DROOP
(EQ. 1)
The power consumed by the load can be calculated by:
P LOAD = V PMON /(17.5*0.0021) (Watt)
(EQ. 2)
where the 0.0021 is the droop impedance.The power
monitor load regulation is about 7. Basically, within its
Page 19 of 28
ISL9506
sourcing/sinking current capability range, when the power
monitor loading changes 1mA, the output of the power
monitor will change 7mV. The 7 impedance is associated
with the layout and packaging resistance of PMON pin inside
the IC. Compared to the load resistance on the power
monitor pin in practical applications, 7output impedance
contributes no significance of error.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL9506 uses 2 slew rates for various modes of
operation. The first is a slow slew rate, used to reduce inrush
current on start-up. It is also used to reduce audible noise
when entering or exiting Diode Emulation Mode. A faster
slew rate is used to exit out of Diode Emulation and to
increase system performance by achieving nominal mode
regulation more quickly. Note that the SOFT capacitor
current is bidirectional and is flowing into the SOFT capacitor
when the output voltage is commanded to rise, and out of
the SOFT capacitor when the output voltage is commanded
to fall.
The two slew rates are determined by the currents into the
SOFT pin. As can be seen in Figure 44, the SOFT pin has a
capacitance to ground. Also, the SOFT pin is the input to the
error amplifier and is, therefore, the commanded system
voltage. Depending on the state of the system, i.e. Start-Up
or Nominal mode, and the state of the DE_EN pin, one of the
two currents shown in Figure 44 will be used to charge or
discharge this capacitor, thereby controlling the slew rate of
the commanded voltage. These currents can be found under
the Soft Current section of the Electrical Specifications Table
on page 4.
ISL9506
ISS
I2
ERROR
AMPLIFIER
+
SOFT
CSOFT
+
VREF
FIGURE 44. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
The first current, labeled ISS, is given in the specification
table as 42µA. This current is used during Soft-Start. The
second current, I2 sums with ISS to get the large current
labeled IGV in the Electrical Specifications Table on page 4
This total current is typically 205A with a minimum of
180µA.
FN6722 Rev 0.00
August 13, 2008
The desired VOUT slew rate will determine the choice of the
SOFT capacitor, CSOFT, by Equation 3:
I GV
C SOFT = -----------------------------------SLEWRATE
(EQ. 3)
Using a SLEWRATE of 10mV/µs, and the typical IGV value,
given in the Electrical Specification Table of 205µA, CSOFT is
calculated by using Equation 4:
205A
C SOFT = ------------------ = 0.0205F
10mV
---------------1s
(EQ. 4)
A choice of 0.015µF would guarantee a SLEWRATE of
10mV/µs is met for minimum IGV value, given in the
Electrical Specifications Table on page 4
Now this choice of CSOFT will then control the start-up
slewrate as well. One should expect the output voltage to
slew to the start value of 1.2V at a rate given by Equation 5:
I SS
42A
dV
mV
- = ----------------------- = 2.8 --------------- = -----------------0.015F
C SOFT
dt
s
(EQ. 5)
Generally, when output voltage is approaching its steady
state, its dv/dt will slow down to prevent overshoot. In order
to compensate the slow-down effect, faster initial dv/dt slew
rates can be used with small soft capacitors such as 10nF to
achieve the desired overall dv/dt in the allocated time
interval.
Selecting RBIAS
To properly bias the ISL9506, a reference current is
established by placing a 147k, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10µA current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin.
Capacitance on this pin would create instabilities and should
be avoided.
Start-up Operation - PGD_N and PGOOD
The ISL9506 provides a 3.3V logic output pin for PGD_N.
The 3V3 pin allows for a system 3.3V source to be
connected to separated circuitry inside the ISL9506, solely
devoted to the PGD_N function. The output is a 3.3V CMOS
signal with 4mA of source and sinking capability. This
implementation removes the need for an external pull-up
resistor on this pin, and due to the normal level of this signal
being a low, removes the leakage path from the 3.3V supply
to ground through the pull-up resistor. This reduces 3.3V
supply current, that would occur under normal operation with
a pull-up resistor, and prolongs battery life. The 3.3V supply
should be decoupled to digital ground, not to analog ground
for noise immunity.
Page 20 of 28
ISL9506
As mentioned in the ““Theory of Operation” on page 16
section of this data sheet, PGD_N is logic level high at startup. When the output voltage reaches 90% of start voltage, a
counter is enabled, it counts 13 switching cycles (about 43µs
for 300kHz operation) then PGD_N goes low. This in turn
triggers an internal timer for the PGOOD signal. This timer
allows PGOOD to go high approximately 7ms after PGD_N
goes low.
Static Mode of Operation - Remote Voltage
Sensing
Remote Voltage sensing allows the Voltage Regulator to
compensate for various resistive drops in the power path
and insure that the voltage seen at the point of load is the
correct level independent of load current.
The VSEN and RTN of the ISL9506 are the Kelvin
connection pins to the point of load. This allows the Voltage
Regulator to tightly control the output voltage at the point of
load, independent of layout inconsistencies and drops. This
Kelvin sense technique provides for extremely tight droop
impedance regulation.
These traces should be laid out as noise sensitive traces.
For optimum droop impedance regulation performance, the
traces connecting these two pins to the Kelvin sense point of
the load must be laid out in parallel and away from rapidly
rising voltage nodes (switching nodes) and other noisy
traces. To achieve optimum performance, place common
mode and differential mode RC filters to analog ground on
VSEN and RTN as shown in Figure 46. However, the filter
resistors should be in order of 10so that they do not
interact with the 50k input resistance of the differential
amplifier.
Due to the fact that the voltage feedback to the switching
regulator is sensed at the point of load, there exists the
potential of an overvoltage due to an open circuit feedback
signal, should the regulator be operated without the load
installed. Due to this fact, we recommend the use of the
ROPN1 and ROPN2 connected to VOUT and ground as
shown in Figure 46. These resistors will provide voltage
feedback in the event that the system is powered up without
the load installed. These resistors are typically 100.
following relationship, where RFSET is in k and the
switching period is in µs.
(EQ. 6)
Rfset  k  =  Period  s  – 0.29   2.33
In discontinuous conduction mode, (DCM), the ISL9506 runs
in period stretching mode. It should be noted that the
switching frequency in the Electrical Specification Table is
tested with the error amplifier output or Comp pin voltage at
2V. When Comp pin voltage is lower, the switching
frequency will not be at the tested value but can still maintain
the output voltage ripple within specification.
Voltage Regulator Thermal Throttling
The ISL9506 features a thermal monitor which senses the
voltage change across an externally placed negative
temperature coefficient (NTC) thermistor, see Figure 45.
Proper selection and placement of the NTC thermistor
allows for detection of a designated temperature rise by the
system.
Figure 45 shows the thermal throttling feature with
hysteresis. At low temperature, SW1 is on and SW2
connects to the 1.20V side. The total current going from NTC
pin is 60µA. The voltage on NTC pin is higher than threshold
voltage of 1.20V and the comparator output is low. VRHOT#
is pulling up high by the external resistor.
54µA
6µA
VRHOT#
SW1
NTC
+
VNTC
-
+
RNTC
Rs
1.24V
SW2
1.20V
INTERNAL TO
ISL9506
FIGURE 45. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE OF THE ISL9506
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM
architecture. The switching frequency can increase during
the application of a load to improve transient performance.
However, it also varies slightly due changes in input and
output voltage and output current, but this variation is
normally less than 10% in continuous conduction mode.
Refer to Figure 39. A resistor connected between the VW
and COMP pins of the ISL9506 adjusts the switching
window, and therefore adjusts the switching frequency. The
RFSET resistor that sets up the switching frequency of the
converter operating in CCM can be determined using the
FN6722 Rev 0.00
August 13, 2008
When temperature increases, the NTC thermistor resistance
on NTC pin decreases. The voltage on NTC pin decreases
to a level lower than 1.20V. The comparator changes polarity
and turns SW1 off and throws SW2 to 1.24V. This pulls
VRHOT# low and sends the signal to start thermal throttle.
There is a 6µA current reduction on NTC pin and 40mV
voltage increase on threshold voltage of the comparator in
this state. The VRHOT# signal will be used to change the
load operation and decrease the power consumption. When
the temperature goes down, the NTC thermistor voltage will
eventually go up. If NTC voltage increases to 1.24V, the
comparator will then be able to flip back. The external
Page 21 of 28
ISL9506
resistance difference in these two conditions as shown in
Equation 7:
1.24V 1.20V
---------------- – ---------------- = 2.96k
54A 60A
(EQ. 7)
Therefore, proper NTC thermistor has to be chosen such
that 2.96k resistor change will be corresponding to required
temperature hysteresis. Regular external resistor may need
to be in series with NTC resistors to meet the threshold
voltage values.
The following is an example.
For Panasonic NTC thermistor with B = 4700, its resistance
will drop to 0.03322 of its nominal at 105°C, and drop to
0.03956 of its nominal at 100 °C. If the requirement for the
temperature hysteresis is (105-100) °C, the required
resistance of NTC will be:
2.96k
------------------------------------------------------ = 467k
 0.03956 – 0.03322 
(EQ. 8)
Therefore a larger value thermistor, such as 470k NTC
should be used.
At 105°C, 470k NTC resistance becomes:
(0.03322*470k) = 15.6k. With 60µA on NTC pin, the voltage
is only (15.6k*60µA) = 0.937V. This value is much lower than
the threshold voltage of 1.20V. Therefore, a resistor is
needed to be in series with the NTC. The required resistance
can be calculated by using Equation 9:
1.20V
---------------- – 15.6k = 4.4k
60A
(EQ. 9)
4.42k is a standard resistor value. Therefore, the NTC
branch should have a 470k NTC and 4.42k resistor in series.
The part number for the NTC thermistor is ERTJ0EV474J. It
is a 0402 package. NTC thermistor will be placed in the hot
spot of the board.
Static Mode of Operation - Static Droop using DCR
Sensing
As previously mentioned, the ISL9506 has an internal
differential amplifier which provides for extremely accurate
voltage regulation at the point of load. The droop impedance
regulation is also very accurate, and the process of selecting
the components for the appropriate droop impedance is
explained here.
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired droop impedance
has several steps and is somewhat iterative.
inductor creates a small DC level of voltage. When this
voltage is summed with the other channels DC voltages, the
total DC load current can be derived.
RO is typically 5 to 10. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 47.
Figure 47 shows the simplified model of the droop circuitry.
Essentially one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by
Equation 10.
I OUT  DCR
Vdcr EQV = ---------------------------------N
(EQ. 10)
where N is the number of channels designed for nominal
operation. Another simplification was done by reducing the
NTC network comprised of RNTC, RSERIES and
RPARALLEL, given in Figure 46, to a single resistor given as
Rn as shown in Figure 47.
The first step in droop impedance compensation is to adjust
Rn, ROEQV and RSEQV such that sufficient droop voltage
exists even at light loads between the VSUM and VO’ nodes.
We recognize that these components form a voltage divider.
As a rule of thumb we start with the voltage drop across the
Rn network, VN, to be 0.57 x VDCR. This ratio provides for a
fairly reasonable amount of light load signal from which to
arrive at droop.
First we calculate the equivalent NTC network resistance,
Rn. Typical values that provide good performance are,
Rseries = 3.57k_1%, RPAR = 4.53k_1% and RNTC = 10k
NTC, ERT-J1VR103J from Panasonic. Rn is then given by
Equation 11.
 Rseries + Rntc   Rpar
Rn = -------------------------------------------------------------------- = 3.4k
Rseries + Rntc + Rpar
(EQ. 11)
In our second step, we calculate the series resistance from
each phase to the VSUM node, labeled RS1, RS2 and RS3
in Figure 46.
In Figure 46 we show a 3 phase solution using DCR
sensing. There are two resistors around the inductor of each
phase. These are labeled RS and RO. These resistors are
used to sense the DC voltage drop across each inductor.
Each inductor will have a certain level of DC current flowing
through it, this current when multiplied by the DCR of the
FN6722 Rev 0.00
August 13, 2008
Page 22 of 28
ISL9506
IS E N 1
IS E N 2
IS E N 2
IS E N 1
10µA
DROOP
VSEN
RTN
VO'
0.01µF
V D IF F
0 .2 2 µ F
VSUM
V DCR 1
RPAR
RS3
VO'
CL1
IS E N 1
L2
R OPN1
DCR
+V D C R 2 -
R L2
RO2
CL2
VO'
L3
+
V DCR 3
V OUT
-
DCR
R L3
CL3
RO3
C BU LK
VO'
to V O U T
VSS_SENSE
RO1
VO'
IS E N 3
10
-
DCR
IS E N 2
IPHASE3
VSUM
V C C _ S E NVSOEU T
R OPN2
RS2
RNTC
+
1 -
Cn
RDRP2
+
1 -
+
D FB
RDRP1

+
R L1
IPH A SE 2
VSUM
RSERIES
IN T E R N A L T O
ISISLL96520660
VSUM
VO'
VSUM
+
DROOP
-
+
L1
RS1
R OCSET
OCSET
+
OC
IPHASE1
IS E N 3
IS E N 3
ESR
T o P ro c e s s o r
T O P O IN T O F
S o c k e t K e lv in
L eOcAtio
D ns
C onn
FIGURE 46. EQUIVALENT MODEL FOR DROOP AND REMOTE SENSING USING DCR SENSING
10uA
OCSET
+
+
DRO OP
-
+
1
+
-
1
+
-
R TN
V D IF F
V dcr EQ V
DROOP
VSEN
VO'
 Io u t 
+
Cn
+
VSUM
RS
N
DFB
Rdrp1
In te r n a l to
IS
ISLL96520660

RS EQV 
VSUM
Rdrp2
OC
VN
Rn 
R n tc
R n tc
DCR
N
 R s e rie s   R p a r
 R s e rie s   R p a r
VO'
RO EQV 
RO
N
FIGURE 47. EQUIVALENT MODEL FOR DROOP AND REMOTE SENSING USING DCR SENSING
We do this using the assumption that we desire approximately
a 0.57 gain from the DCR voltage, VDCR, to the Rn network.
We call this gain, G1.
G1 = 0.57
(EQ. 12)
After simplification, then RSEQV is given by Equation 13:
1
RS EQV =  -------- – 1 Rn = 2.56k
 G1

(EQ. 13)
The individual resistors from each phase to the VSUM node,
labeled RS1, RS2 and RS3 in Figure 46, are then given by
Equation 14, where N is 3, for the number of channels in
nominal operation.
RS = N  RS EQV = 7.69k
(EQ. 14)
Choosing RS = 7.68k_1% is a good choice. Once we know the
attenuation of the RS and RN network, we can then determine
the Droop amplifier Gain required to achieve the droop
impedance. Setting Rdrp1 = 1k_1%, then Rdrp2 is can be
found using Equation 15.
N  Rdroop
Rdrp2 =  -------------------------------- – 1  Rdrp1
 DCR  G1

(EQ. 15)
Setting N = 3 for 3 channel operation, Droop Impedance
(Rdroop) = 0.0021 (V/A) as per the desired specification. DCR
FN6722 Rev 0.00
August 13, 2008
Page 23 of 28
ISL9506
= 0.0012 typical, Rdrp1 = 1k and the attenuation gain (G1)
= 0.57, Rdrp2 is then:
3  0.0021
Rdrp2 =  ------------------------------------ – 1  1K = 8.21k
 0.0012  0.57

(EQ. 16)
Rdrp2 is selected to be a 8.25k_1% resistor. Note, we choose
to ignore the RO resistors because they do not add significant
error.
These values are extremely sensitive to layout and coupling
factor of the NTC to the inductor. As only one NTC is required
in this application, this NTC should be placed as close to the
Channel 1 inductor as possible. And very importantly, the PCB
traces sensing the inductor voltage should be go directly to the
inductor pads.
Once the board has been laid out, some adjustments may be
required to adjust the full load droop voltage. This can be
accomplished by allowing the system to achieve thermal
equilibrium at full load, and then adjusting Rdrp2 to obtain the
appropriate droop impedance.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the output
voltage will deviate from the initial voltage reading. A good
NTC thermistor compensation can limit the output voltage drift
to 2mV. If the output voltage is decreasing with temperature
increase, that ratio between the NTC thermistor value and the
rest of the resistor divider network has to be increased. Users
should use the ISL9506 evaluation board component values
and follow the evaluation board layout of NTC as much as
possible to minimize engineering time.
The desired droop impedance should be adjusted by Rdrp2
based on maximum current steps, not based on small current
steps. Basically, if the max current is 40A, the required droop
voltage is 84mV with 2.1m droop impedance. The user should
have 40A load current on the converter and look for 84mV
droop. If the droop voltage is less than 84mV, for example,
80mV. The new value will be calculated by Equation 17:
Rdrp 2 _ new

84 mV
( Rdrp 1  Rdrp 2 )  Rdrp 1
80 mV
(EQ. 17)
For the best accuracy, the equivalent resistance on the DFB
and VSUM pins should be identical so that the bias current of
the droop amplifier does not cause an offset voltage. In the
example above, the resistance on the DFB pin is Rdrp1 in
parallel with Rdrop2, that is, 1k in parallel with 8.21k or 890.
The resistance on the VSUM pin is Rn in parallel with RSeqv or
3.4k in parallel with 2.56k or 1460. The mismatch in the
effective resistances is 1460 - 890 = 570. To reduce the
mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate
factor. The appropriate factor in the example is
1460/890 = 1.64.
FN6722 Rev 0.00
August 13, 2008
Dynamic Mode of Operation - Dynamic Droop using
DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage could
sag excessively upon load application and potentially create a
system failure. The output voltage could also take a long
period of time to settle to its final value.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in Equation 18:
 Rn  RS EQV
L
-  Cn
------------- =  ---------------------------------DCR
 Rn + RS EQV
(EQ. 18)
Solving for Cn we now have Equation 19:
L
------------DCR
---------------------------------------Cn =
 Rn  RS EQV
 -----------------------------------
 Rn + RS EQV
(EQ. 19)
Note, RO was neglected. As long as the inductor time constant
matches the droop circuit RC time constants as given above,
the transient performance will be optimum. The selection of Cn
may require a slight adjustment to correct for layout
inconsistencies and component tolerance. For the example of
L = 0.5H, Cn is calculated in Equation 20:
0.5H
-----------------0.0012
------------------------------------------------ = 28.5nF
Cn =
3.4k  2.56k
 ----------------------------------------- 3.4k + 2.56k
(EQ. 20)
The value of this capacitor is selected to be 27nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the transient
voltage. If the output voltage transient has an initial dip, lower
than the voltage required by the droop impedance, and is
slowly increasing back to the steady state, the capacitor should
be increased and vice versa. It is better to have the capacitor
value a little bigger to cover the tolerance of the inductor to
prevent the output voltage from going lower than the spec. This
capacitor needs to be a high grade capacitor like X7R with low
tolerance. There is another consideration in order to achieve
better time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those capacitors are only available
in small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10x to
reduce the capacitance by 10x. But attention has to be paid in
balancing the impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a voltage
source controlled by VSEL and a series impedance, in order to
achieve certain droop impedance, the series impedance inside
the black box needs to be this desired value. The
compensation design has to ensure the output impedance of
Page 24 of 28
ISL9506
the converter be lower than this desired value. There is a
mathematical calculation file available to the user. The power
stage parameters such as L and Cs are needed as the input to
calculate the compensation component values. Attention has
be paid to the input resistor to the FB pin. Too high of a resistor
will cause an error to the output voltage regulation because of
bias current flowing in the FB pin. It is better to keep this
resistor below 3k when using this file.
Static Mode of Operation - Current Balance using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL9506 through the
matching of the voltages present on the ISEN pins. The
ISL9506 adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used to
create a rather large time constant such that the ISEN voltages
have minimal ripple voltage and represent the DC current
flowing through each channel’s inductor. For optimum
performance, RL is chosen to be 10k and CL is selected to
be 0.22µF. When discrete resistor sensing is used, a capacitor
of 10nF should be placed in parallel with RL to properly
compensate the current balance circuit.
1. ISL9506 uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL9506 forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly the same. Take DCR
current sensing as example, two errors have to be added to
find the total current imbalance. 1) Mismatch of DCR: If the
DCR has a 5% tolerance, then the resistors could mismatch
by 10% worst case. If each phase is carrying 20A then the
phase currents mismatch by 20A*10% = 2A. 2) Mismatch of
phase voltages/offset voltage of ISEN pins. The phase
voltages are within 2mV of each other by current balance
circuit. The error current that results is given by 2mV/DCR.
If DCR = 1m then the error is 2A.
In the above example, the two errors add to 4A. For a two
phase DC/DC, the currents would be 22A in one phase and
18A in the other phase. In the above analysis, the current
balance can be calculated with 2A/20A = 10%. This is the
worst case calculation, for example, the actual tolerance of two
10% DCRs is 10%*sqrt(2) = 7%.
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for better
thermal management. Customer can put a resistor in parallel
with the current sensing capacitor on the phase of interest in
order to purposely increase the current in that phase. It is highly
recommended to use symmetrical layout in order to achieve
natural current balance.
In the case the PCB board trace resistance from the inductor to
the point of load are not the same on all three phases, the
current will not be balanced. On the phases that have too
much trace resistance a resistor can be added in parallel with
the ISEN capacitor that will correct for the poor layout.
FN6722 Rev 0.00
August 13, 2008
An estimate of the value of the resistor is:
Rtweak = Risen* [2*Rdcr - (Rtrace - Rmin)]/[2(Rtrace - Rmin)]
(EQ. 21)
where Risen is the resistance from the phase node to the ISEN
pin; usually 10k. Rdcr is the DCR resistance of the inductor.
Rtrace is the trace resistance from the inductor to the point of
load on the phase that needs to be tweaked. It should be
measured with a good micro meter. RMIN is the trace
resistance from the inductor to the load on the phase with the
least resistance.
For example, if the PC board trace on one phase is 0.5m and
on another trace is 0.3m; and if the DCR is 1.2m; then the
tweaking resistor is
Rtweak = 10kw* [2*1.2 - (0.5 - 0.3)]/[2*(0.5 - 0.3)] = 55k (EQ. 22)
For extremely unsymmetrical layout causing phase current
unbalance, ISL9506 applications schematics can be modified
to correct the problem.
Droop using Discrete Resistor Sensing - Static/
Dynamic Mode of Operation
When choosing current sense resistor, not only the tolerance
of the resistance is important, but also the TCR. Thus, its
combined tolerance at a wide temperature range should be
calculated.
Figure 48 shows the equivalent circuit of a discrete current
sense approach. Figure 40 shows the simplified schematic of
this approach.
For discrete resistor current sensing circuit, the droop circuit
parameters can be solved the same way as the DCR sensing
approach with a few slight modifications.
First, there is no NTC required for thermal compensation,
therefore, the Rn resistor network in the previous section is not
required. Secondly, there is no time constant matching
required, therefore, the Cn component is not needed to match
the L/DCR time constant, but this component does indeed
provide noise immunity, especially to noise voltage caused by
the ESL of the current sensing resistors. A 47pF capacitor can
be used for such purposes.
The Rs values in the previous section, Rs = 7.68k_1% are
sufficient for this approach.
Now, the input to the Droop amplifier is the VRSENSE voltage.
This voltage is given by Equation 23:
Rsense
Vrsense = --------------------  I OUT
N
(EQ. 23)
The gain of the Droop amplifier, G2, must be adjusted equal to
the droop impedance. See Equation 24:
Rdroop
G2 = ----------------------  N
Rsense
(EQ. 24)
Assuming N = 3, Rdroop = 0.0021(V/A) as per the desired
specification, Rsense = 0.001, we obtain G2 = 6.3.
Page 25 of 28
ISL9506
The values of Rdrp1 and Rdrp2 are selected to satisfy two
requirements. First, the ratio of Rdrp2 and Rdrp1 determine the
gain G2 = (Rdrp2/Rdrp1)+1. Second, the parallel combination
of Rdrp1 and Rdrp2 should equal the parallel combination of
the Rs resistors. Combining these requirements gives:
will cause 1% error. As shown in Figure 36, when the load is at
2.5A, PMON can still sink 0.6mA current. This allows the RC
filter capacitor to discharge when the load is at low current,
thus providing correct average power information on the
capacitor.
Rdrp1 = G2/(G2-1) * Rs/N
Fault Protection - Overcurrent Fault Setting
Rdrp2 = (G2-1) * Rdrp1
As previously described, the overcurrent protection of the
ISL9506 is related to the droop voltage. Previously we have
calculated that the Droop Voltage = ILOAD*Rdroop, where
Rdroop is the droop impedance. Knowing this relationship, the
overcurrent protection threshold can be set up as a voltage
droop level. Knowing this voltage droop level, one can program
in the appropriate drop across the Roc resistor. This voltage
drop will be referred to as Voc.
In the example above, Rs = 7.68k, N = 3, and G2 = 6.3 so Rdrp
3k and Rdrp2 is 15.8k.
These values are extremely sensitive to layout. Once the
board has been laid out, some tweaking may be required to
adjust the full load droop. This is fairly easy and can be
accomplished by allowing the system to achieve thermal
equilibrium at full load, and then adjusting Rdrp2 to obtain the
desired droop value.
Once the droop voltage is greater than Voc, the PWM drives will
turn off and PGOOD will go low. The selection of Roc is given in
Equation 25. Assuming we desire an overcurrent trip level, Ioc,
of 55A, and knowing from the desired specification that the
droop impedance, Rdroop is 0.0021 (V/A), we can then
calculate for ROC as shown in Equation 25:
Power Monitor
10µA
+
+
DROOP
-
VDIFF
1
DROOP
+
-
RTN
EQV
RS
N

DFB
+
VSEN
VO'
Cn
+
+
1 -
A capacitor may be added in parallel with ROC to improve
noise rejection but the Roc*capacitor time constant cannot
exceed 20µs. Do not remove ROC if overcurrent protection is
not desired. The maximum ROC is 30k.
VSUM
Rdrp1

+
Note, if the droop impedance is not -0.0021 (V/A) in the
application, the overcurrent setpoint will differ from predicted.
RS
VSUM
INTERNAL TO
ISL9506
(EQ. 25)
Roc
Rdrp2
OC
Voc
OCSET
Ioc  Rdroop
55  0.0021
Roc = ------------------------------------- = ------------------------------- = 11.5k
10A
10x10 – 6
-
+
The power monitor signal tracks the inductor current. Due to
the dynamic operation of the load, the inductor current is
pulsating and the power monitor signal needs to be filtered. If
the RC filter is followed by an A/D converter, the input
impedance of the A/D converter needs to be much larger than
the resistor used for the RC filter. Otherwise, the input
impedance of the A/D converter and the RC filter resistor will
construct a resistor divider causing the A/D converter reading
incorrect information. It is desirable to choose a small RC filter
resistor in order to reduce the resistor divider effect. The
ISL9506 comes with a very strong current sinking capability,
users can use k resistors for the RC filter. Some A/D
converters might have 100k input impedance, 1k resistor
Vrsense
EQV

Iout 

RO
N
Rsense
N
VN
RO
VO'
EQV
FIGURE 48. EQUIVALENT MODEL FOR DROOP AND REMOTE SENSING USING DISCRETE RESISTOR SENSING
FN6722 Rev 0.00
August 13, 2008
Page 26 of 28
ISL9506
© Copyright Intersil Americas LLC 2005-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6722 Rev 0.00
August 13, 2008
Page 27 of 28
ISL9506
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X 4.5
6.00
36X 0.50
A
B
31
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
30
1
6.00
4 . 10 ± 0 . 15
21
10
0.15
(4X)
11
20
TOP VIEW
0.10 M C A B
40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
(
C
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
C
0 . 2 REF
5
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6722 Rev 0.00
August 13, 2008
Page 28 of 28