ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com 12-, 14-, 16-Bit, Eight-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS Check for Samples: ADS8528, ADS8548, ADS8568 FEATURES DESCRIPTION • The ADS8528/48/68 contain eight low-power, 12-, 14-, or 16-bit, successive approximation register (SAR)-based analog-to-digital converters (ADCs) with true bipolar inputs. These channels are grouped in four pairs, thus allowing simultaneous high-speed signal acquisition of up to 650kSPS. 1 2 • • • • • • Family of 12-, 14-, 16-Bit, Pin- and Software-Compatible ADCs Maximum Data Rate Per Channel: – ADS8528: 650kSPS (PAR) or 480kSPS (SER) – ADS8548: 600kSPS (PAR) or 450kSPS (SER) – ADS8568: 510kSPS (PAR) or 400kSPS (SER) Excellent AC Performance: – Signal-to-Noise Ratio: ADS8528: 73.9dB ADS8548: 85dB ADS8568: 91.5dB – Total Harmonic Distortion: ADS8528: –89dB ADS8548: –91dB ADS8568: –94dB Programmable and Buffered Internal Reference: 0.5V to 2.5V or 0.5V to 3.0V Supports Input Voltage Ranges of Up to ±12V Selectable Parallel or Serial Interface Scalable Low-Power Operation Using Auto-Sleep Mode: Only 32mW at 10kSPS Fully Specified Over the Extended Industrial Temperature Range The devices support selectable parallel or serial interface with daisy-chain capability. The programmable reference allows handling of analog input signals with amplitudes up to ±12V. The ADS8528/48/68 family supports an auto-sleep mode for minimum power dissipation and is available in both QFN-64 and LQFP-64 packages. The entire family is specified over a temperature range of –40°C to +125°C. Clock Generator CH_A0 SAR ADC CH_A1 SAR ADC CH_B0 SAR ADC CH_B1 SAR ADC Control Logic Control Signal Bus Config Register CH_C0 SAR ADC CH_C1 SAR ADC CH_D0 SAR ADC CH_D1 SAR ADC REFIO String DAC APPLICATIONS • • • • • Protection Relays Power Quality Measurement Multi-Axis Motor Control Programmable Logic Controllers Industrial Data Acquisition I/O Parallel or Serial Data Bus 2.5/3V Reference 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FAMILY/ORDERING INFORMATION (1) (1) PRODUCT RESOLUTION (Bits) MAXIMUM DATA RATE: PAR/SER (kSPS/ch) SNR (dB, typ) THD (dB, typ) ADS8528 12 650/480 73.9 –89 ADS8548 14 600/450 85 –91 ADS8568 16 510/400 91.5 –94 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage VALUE UNIT HVDD to AGND –0.3 to 18 V HVSS to AGND –18 to 0.3 V AVDD to AGND –0.3 to 6 V –0.3 to 6 V Analog input voltage HVSS – 0.3 to HVDD + 0.3 V Reference input voltage with respect to AGND AGND – 0.3 to AVDD + 0.3 V Digital input voltage with respect to DGND DGND – 0.3 to DVDD + 0.3 V Ground voltage difference AGND to DGND ±0.3 V Input current to all pins except supply ±10 mA Maximum virtual junction temperature, TJ +150 °C Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins ±2500 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins ±500 V DVDD to DGND ESD ratings (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION ADS8528/48/68 THERMAL METRIC (1) RGC PM 64 PINS 64 PINS θJA Junction-to-ambient thermal resistance 22 48.5 θJCtop Junction-to-case (top) thermal resistance 9.0 9.4 θJB Junction-to-board thermal resistance 3.6 21.9 ψJT Junction-to-top characterization parameter 0.1 0.3 ψJB Junction-to-board characterization parameter 2.9 21.4 θJCbot Junction-to-case (bottom) thermal resistance 0.3 n/a (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8528 All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V. ADS8528 PARAMETER CONDITIONS MIN TYP MAX UNIT SAMPLING DYNAMICS Conversion time Throughput rate fDATA Internal conversion clock 1.33 μs Serial interface, all four SDOx active 480 kSPS Parallel interface 650 kSPS DC ACCURACY Resolution 12 No missing codes Bits 12 Bits Integral linearity error (1) INL –0.75 ±0.2 0.75 LSB Differential linearity error DNL –0.5 ±0.2 0.5 LSB –1.5 ±0.5 1.5 mV Offset error –0.65 Offset error matching 0.65 ±3.5 Offset error drift Gain error Gain error matching Gain error drift ±0.25 mV μV/°C Referenced to voltage at REFIO –0.5 0.5 % Between channels of any pair –0.2 0.2 % Between any two channels –0.4 0.4 ±6 Referenced to voltage at REFIO % ppm/°C AC ACCURACY Signal-to-noise ratio Signal-to-noise ratio + distortion Total harmonic distortion (2) SNR At fIN = 10kHz 73 73.9 dB SINAD At fIN = 10kHz 73 73.8 dB SFDR At fIN = 10kHz Channel-to-channel isolation At fIN = 10kHz –3dB small-signal bandwidth (1) (2) –89 THD At fIN = 10kHz Spurious-free dynamic range BW 84 92 –84 dB dB 120 dB In 4VREF mode 48 MHz In 2VREF mode 24 MHz Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range. Calculated on the first nine harmonics of the input frequency. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 3 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8548 All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V. ADS8548 PARAMETER CONDITIONS MIN TYP MAX UNIT SAMPLING DYNAMICS Conversion time Throughput rate fDATA Internal conversion clock 1.45 μs Serial interface, all four SDOx active 450 kSPS Parallel interface 600 kSPS DC ACCURACY Resolution 14 No missing codes Bits 14 Integral linearity error (1) INL Differential linearity error DNL Offset error Bits –1 ±0.5 –1 –1.5 1 LSB ±0.25 1 LSB ±0.5 1.5 mV –0.65 Offset error matching 0.65 ±3.5 Offset error drift Gain error Gain error matching Gain error drift Referenced to voltage at REFIO –0.5 0.5 % Between channels of any pair –0.2 0.2 % Between any two channels –0.4 0.4 Referenced to voltage at REFIO ±0.25 mV μV/°C % ±6 ppm/°C AC ACCURACY Signal-to-noise ratio Signal-to-noise ratio + distortion Total harmonic distortion (2) SNR At fIN = 10kHz 84 85 dB SINAD At fIN = 10kHz 83 84 dB SFDR At fIN = 10kHz Channel-to-channel isolation At fIN = 10kHz –3dB small-signal bandwidth (1) (2) 4 –91 THD At fIN = 10kHz Spurious-free dynamic range BW 86 92 –86 dB dB 120 dB In 4VREF mode 48 MHz In 2VREF mode 24 MHz Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range. Calculated on the first nine harmonics of the input frequency. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8568 All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V. ADS8568 PARAMETER CONDITIONS MIN TYP MAX UNIT SAMPLING DYNAMICS Conversion time Throughput rate fDATA Internal conversion clock 1.7 μs Serial interface, all four SDOx active 400 kSPS Parallel interface 510 kSPS DC ACCURACY Resolution 16 No missing codes Integral linearity error (1) INL DNL Bits At TA = –40°C to +85°C, QFN package (RGC) –3 ±1.5 3 LSB At TA = –40°C to +125°C, QFN package (RGC) –4 ±1.5 4 LSB At TA = –40°C to +85°C, LQFP package (PM) –4 ±1.5 4 LSB –4.5 ±1.5 4.5 LSB At TA = –40°C to +85°C –1 ±0.75 1.75 LSB At TA = –40°C to +125°C –1 ±0.75 2 LSB –1.5 ±0.5 1.5 mV At TA = –40°C to +125°C, LQFP package (PM) Differential linearity error Bits 16 Offset error –0.65 Offset error matching 0.65 ±3.5 Offset error drift Gain error Gain error matching Gain error drift ±0.25 mV μV/°C Referenced to voltage at REFIO –0.5 0.5 % Between channels of any pair –0.2 0.2 % Between any two channels –0.4 0.4 % ±6 Referenced to voltage at REFIO ppm/°C AC ACCURACY Signal-to-noise ratio Signal-to-noise ratio + distortion Total harmonic distortion (2) Spurious-free dynamic range SNR SINAD THD SFDR Channel-to-channel isolation –3dB small-signal bandwidth (1) (2) At fIN = 10kHz, TA = –40°C to +85°C 90 91.5 dB At fIN = 10kHz, TA = –40°C to +125°C 89 91.5 dB At fIN = 10kHz, TA = –40°C to +85°C 87 90 dB 86.5 90 At fIN = 10kHz, TA = –40°C to +125°C –94 –90 dB At fIN = 10kHz, TA = –40°C to +125°C –94 –89.5 dB At fIN = 10kHz, TA = –40°C to +85°C At fIN = 10kHz, TA = –40°C to +125°C At fIN = 10kHz BW dB At fIN = 10kHz, TA = –40°C to +85°C 90 95 dB 89.5 95 dB 120 dB In 4VREF mode 48 MHz In 2VREF mode 24 MHz Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as the number of LSBs or percentage of the specified full-scale range. Calculated on the first nine harmonics of the input frequency. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 5 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V. ADS8528, ADS8548, ADS8568 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Bipolar full-scale range CHXX RANGE pin/RANGE bit = 0 –4VREF 4VREF RANGE pin/RANGE bit = 1 –2VREF 2VREF Input range = ±4VREF Input capacitance 10 Input range = ±2VREF Input leakage current Aperture delay Aperture delay matching Common CONVST for all channels Aperture jitter Power-supply rejection ratio PSRR At output code FFFFh, related to HVDD and HVSS V pF 20 –1 No ongoing conversion V pF 1 μA 5 ns 100 ps 50 ps –78 dB REFERENCE VOLTAGE OUTPUT (REFOUT) Reference voltage Reference voltage drift Power-supply rejection ratio Output current VREF 2.485 2.5 2.515 V 2.5V operation, REFDAC = 3FFh at +25°C 2.496 2.5 2.504 V 3.0V operation, REFDAC = 3FFh 2.985 3.0 3.015 V 3.0V operation, REFDAC = 3FFh at +25°C 2.995 3.0 3.005 ±10 dVREF/dT –2 IREFSC Turn-on settling time tREFON External load capacitance V ppm/°C –77 PSRR At output code FFFFh, related to AVDD IREFOUT DC current Short-circuit current (1) Tuning range 2.5V operation, REFDAC = 3FFh dB 2 mA 50 mA 10 ms At REF_xP/N pins 4.7 10 μF At REFIO pin 100 470 REFDAC Internal reference output voltage range 0.2 VREF REFDAC resolution nF VREF 10 V Bits DNLDAC –1 ±0.1 1 LSB REFDAC integral nonlinearity INLDAC –2 ±0.1 2 LSB REFDAC offset error VOSDAC VREF = 0.5V (DAC = 0CDh) –4 ±0.65 4 LSB 2.5 3.025 REFDAC differential nonlinearity REFERENCE VOLTAGE INPUT (REFIN) Reference input voltage VREFIN 0.5 Input resistance 100 Input capacitance 5 Reference input current (1) 6 V MΩ pF 1 μA Reference output current is not limited internally. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V. ADS8528, ADS8548, ADS8568 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (2) Logic family CMOS with Schmitt-Trigger High-level input voltage 0.7 DVDD DVDD + 0.3 Low-level input voltage DGND – 0.3 0.3 DVDD V –50 50 nA Input current VI = DVDD to DGND Input capacitance 5 V pF DIGITAL OUTPUTS (2) Output capacitance 5 Load capacitance –50 High-impedance-state output current Logic family High-level output voltage Low-level output voltage pF 30 pF 50 nA CMOS VOH IOH = 100μA VOL DVDD – 0.6 V IOH = –100μA DGND + 0.4 V POWER-SUPPLY REQUIREMENTS Analog supply voltage AVDD 4.5 5.0 5.5 V Buffer I/O supply voltage DVDD 2.7 3.3 5.5 V Input positive supply voltage HVDD 5.0 15.0 16.5 V Input negative supply voltage HVSS –16.5 –15.0 –5.0 V ADS8528, fDATA = maximum 37.9 50.1 mA ADS8548, fDATA = maximum 37.3 49.3 mA ADS8568, fDATA = maximum 36.6 48.4 mA fDATA = 250kSPS, auto-sleep mode 20.3 30.0 mA fDATA = 200kSPS, auto-sleep mode 17 mA fDATA = 10kSPS, normal operation 30 mA fDATA = 10kSPS, auto-sleep mode 4.6 mA Analog supply current IAVDD Auto-sleep mode, no ongoing conversion, internal conversion clock Power-down mode Buffer I/O supply current 0.03 mA 0.5 2.0 mA fDATA = 250kSPS 0.5 1.4 mA fDATA = 200kSPS 0.5 mA 0.4 mA IDVDD fDATA = 10kSPS Power-down mode 0.35 mA 0.01 mA ADS8528, fDATA = maximum 3.0 4.2 mA ADS8548, fDATA = maximum 2.8 3.9 mA ADS8568, fDATA = maximum 2.3 3.2 mA fDATA = 250kSPS 1.8 2.4 mA IHVDD fDATA = 200kSPS 1.5 mA 0.4 mA fDATA = 10kSPS (2) mA fDATA = maximum Auto-sleep mode, no ongoing conversion, internal conversion clock Input positive supply current 7.0 Auto-sleep mode, no ongoing conversion, internal conversion clock 0.45 mA Power-down mode 0.01 mA Specified by design. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 7 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) All minimum/maximum specifications are at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal), VIN = ±10V, and fDATA = max, unless otherwise noted. Typical values are at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V. ADS8528, ADS8548, ADS8568 PARAMETER CONDITIONS MIN TYP MAX UNIT ADS8528, fDATA = maximum 3.4 4.5 mA ADS8548, fDATA = maximum 3.3 4.4 mA ADS8568, fDATA = maximum 2.7 3.6 mA fDATA = 250kSPS 2.1 2.6 mA IHVSS fDATA = 200kSPS 1.7 mA 0.4 mA POWER-SUPPLY REQUIREMENTS (continued) Input negative supply current fDATA = 10kSPS Auto-sleep mode, no ongoing conversion, internal conversion clock 0.35 Power-down mode Power dissipation (3) 0.01 mA ADS8528, fDATA = maximum 287.1 430.1 mW ADS8548, fDATA = maximum 279.7 419.1 mW ADS8568, fDATA = maximum 259.7 389.4 mW fDATA = 250kSPS, auto-sleep mode 161.7 255.2 mW fDATA = 200kSPS, auto-sleep mode 151.2 mW fDATA = 10kSPS, normal operation 163.3 mW fDATA = 10kSPS, auto-sleep mode 36.3 mW Auto-sleep mode, no ongoing conversion, internal conversion clock Power-down mode Operating ambient temperature range (3) 8 mA –40 TA 25 53.6 mW 0.6 mW +125 °C Maximum power dissipation values are specified with HVDD = 15V and HVSS = –15V. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION TIMING CHARACTERISTICS XCLK (C29 = 1) tSCVX tCVL tXCLK CONVST_x tACQ tCONV tDCVB BUSY (C27 = C26 = 0) tFSCV tBUFS FS tSCLK 32 1 SCLK tHDO tPDDO tDMSB CH_x0 MSB SDO_x CH_x1 D3 CH_x1 D2 tDTRI CH_x1 D1 tSUDI SDI or DCIN_x Don’t Care D31 D3 CH_x1 LSB tHDI D2 D1 D0 Don’t Care Figure 1. Serial Operation Timing Diagram (All Four SDO_x Active) Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 9 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Table 1. Serial Interface Timing Requirements (1) (2) TEST CONDITION PARAMETER tSCVX tXCLK CONVST_x high to XCLK rising edge setup time External conversion clock period External conversion clock frequency CLKSEL = 1 CONVST_x low time tACQ Acquisition time MIN TYP ADS8528 66.67 ns ADS8548 72.46 ns ADS8568 85.11 ADS8528 1 ADS8548 ADS8568 ns 15.0 MHz 1 13.8 MHz 1 11.75 MHz 40 60 20 tDCVB CONVST_x high to BUSY high delay tBUFS BUSY low to FS low time tFSCV Bus access finished to next conversion start time tSCLK % ns 280 Conversion time UNIT ns ns 19 tCONV MAX 6 External conversion clock duty cycle tCVL ADS8528, ADS8548, ADS8568 20 tCCLK or tXCLK ADS8528, CLKSEL = 0 1.33 μs ADS8548, CLKSEL = 0 1.45 μs ADS8568, CLKSEL = 0 1.7 μs 25 ns 0 ns ADS8528 0 ns ADS8548 20 ns ADS8568 40 ns 0.022 10 μs Serial clock frequency 0.1 45 MHz Serial clock duty cycle 40 60 % 12 ns Serial clock period tDMSB FS low to MSB valid delay tHDO Output data to SCLK falling edge hold time tPDDO SCLK falling edge to new data valid propagation delay tDTRI FS high to SDO_x three-state delay tSUDI Input data to SCLK falling edge setup time 3 ns tHDI Input data to SCLK falling edge hold time 5 ns (1) (2) 10 5 ns 17 ns 10 ns Over recommended operating free-air temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted. All input signals are specified with tR = tF = 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com tCVL CONVST_x tCONV tACQ tDCVB BUSY (C27 = C26 = 0) tBUCS tCSCV CS tCSRD tRDCS tRDL tRDH RD tPDDO CH A0 DB[15:0] CH A1 CH B0 CH B1 tHDO CH C0 CH C1 tDTRI CH D0 CH D1 Figure 2. Parallel Read Access Timing Diagram Table 2. Parallel Interface Timing Requirements (Read Access) (1) (2) TEST CONDITION PARAMETER tCVL CONVST_x low time tACQ Acquisition time ADS8528, ADS8548, ADS8568 MIN MAX 20 Conversion time tDCVB CONVST_x high to BUSY high delay tBUCS BUSY low to CS low time tCSCV Bus access finished to next conversion start time (3) UNIT ns 280 19 tCONV TYP ns 20 tCCLK or tXCLK ADS8528, CLKSEL = 0 1.33 µs ADS8548, CLKSEL = 0 1.45 µs ADS8568, CLKSEL = 0 1.7 µs 25 ns 0 ns ADS8528 0 ns ADS8548 20 ns ADS8568 40 ns tCSRD CS low to RD low time 0 ns tRDCS RD high to CS high time 0 ns tRDL RD pulse width 20 ns tRDH Minimum time between two read accesses 2 ns tPDDO RD or CS falling edge to data valid propagation delay tHDO Output data to RD or CS rising edge hold time tDTRI CS high to DB[15:0] three-state delay (1) (2) (3) 15 5 ns ns 10 ns Over recommended operating free-air temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted. All input signals are specified with tR = tF = 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2. Refer to CS signal or RD, whichever occurs first. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 11 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com CS tCSWR tWRL tWRH tWRCS WR tSUDI tHDI C [31:16] DB[15:0] C [15:0] Figure 3. Parallel Write Access Timing Diagram Table 3. Parallel Interface Timing Requirements (Write Access) (1) (2) ADS8528, ADS8548, ADS8568 PARAMETER tCSWR CS low to WR low time tWRL MIN TYP MAX UNIT 0 ns WR low pulse width 15 ns tWRH Minimum time between two write accesses 10 ns tWRCS WR high to CS high time 0 ns tSUDI Output data to WR rising edge setup time 5 ns tHDI Data output to WR rising edge hold time 5 ns (1) (2) Over recommended ambient temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted. All input signals are specified with tR = tF = 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2. EQUIVALENT CIRCUITS Input range: ±2VREF RSER = 200W Input range: ±4VREF RSW = 130W RSER = 200W CH_XX RSW = 130W CH_XX CS = 20pF CPAR = 5pF CS = 10pF VDC CPAR = 5pF VDC CS = 20pF AGND CS = 10pF AGND RSER = 200W RSW = 130W RSER = 200W RSW = 130W Figure 4. Equivalent Input Circuits 12 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PIN CONFIGURATIONS AGND REFBP CH_B0 50 49 52 51 REFBN AVDD 53 REFN CH_B1 54 56 55 AVDD REFIO 57 CH_C1 AGND 58 60 59 AVDD REFCN 61 REFCP AGND 62 CH_C0 64 63 RGC PACKAGE QFN-64 (TOP VIEW) HVSS 1 48 HVDD CH_D1 2 47 CH_A1 REFDN 3 46 REFAN AVDD 4 45 AVDD AGND 5 44 AGND REFDP 6 43 REFAP CH_D0 7 42 CH_A0 PAR/SER 8 41 HW/SW STBY 9 40 CONVST_D RESET 10 39 CONVST_C REFEN/WR 11 38 CONVST_B RD 12 37 CONVST_A CS/FS 13 36 ASLEEP AVDD 14 35 BUSY/INT AGND 15 34 RANGE/XCLK DB15/SDO_D 16 33 DB0/DCIN_D 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DB14/SDO_C DB13/SDO_B DB12/SDO_A DB11/REFBUFEN DB10/SCLK DB9/SDI DB8/DCEN DGND DVDD DB7 DB6/SEL_B DB5/SEL_CD DB4 DB3/DCIN_A DB2/DCIN_B DB1/DCIN_C 7.3-mm x 7.3-mm Exposed Thermal Pad Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 13 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com 14 CH_C0 REFCP AGND AVDD REFCN CH_C1 AGND AVDD REFIO REFN CH_B1 REFBN AVDD AGND REFBP CH_B0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PM PACKAGE LQFP-64 (TOP VIEW) STBY 9 40 CONVST_D RESET 10 39 CONVST_C REFEN/WR 11 38 CONVST_B RD 12 37 CONVST_A CS/FS 13 36 ASLEEP AVDD 14 35 BUSY/INT AGND 15 34 RANGE/XCLK DB15/SDO_D 16 33 DB0/DCIN_D 32 HW/SW DB1/DCIN_C 41 31 8 DB2/DCIN_B PAR/SER 30 CH_A0 DB3/DCIN_A 42 29 7 DB4 CH_D0 28 REFAP DB5/SEL_CD 43 27 6 DB6/SEL_B REFDP 26 AGND DB7 44 25 5 DVDD AGND 24 AVDD DGND 45 23 4 DB8/DCEN AVDD 22 REFAN DB9/SDI 46 21 3 DB10/SCLK REFDN 20 CH_A1 DB11/REFBUFEN 47 19 2 DB12/SDO_A CH_D1 18 HVDD DB13/SDO_B 48 17 1 DB14/SDO_C HVSS Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PIN DESCRIPTIONS DESCRIPTION PIN # NAME TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) 1 HVSS P Negative supply voltage for the analog inputs. Decouple according to the Power Supply section. 2 CH_D1 AI Analog input of channel D1. The input voltage range is controlled by the RANGE pin in hardware mode or by the Configuration Register (CONFIG) bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in software mode. 3 REFDN AI Decoupling capacitor input for reference of channel pair D. Connect to the decoupling capacitor and AGND according to the Power Supply section. 4, 14, 45, 52, 57, 61 AVDD P Analog power supply. Decouple according to the Power Supply section. 5, 15, 44, 51, 58, 62 AGND P Analog ground; connect to the analog ground plane. 6 REFDP AI Decoupling capacitor input for the channel pair D reference. Connect to the decoupling capacitor according to the Power Supply section. 7 CH_D0 AI Analog input of channel D0. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in software mode. 8 PAR/SER DI Interface mode selection input. When low, the parallel interface is selected. When high, the serial interface is enabled. 9 STBY DI Hardware mode (HW/SW = 0): standby mode input. When low, the entire device is powered down (including the internal conversion clock source and reference). When high, the device operates in normal mode. Software mode (HW/SW = 1): connect to DGND or DVDD. The standby mode can be activated using CONFIG bit C25 (STBY). 10 11 REFEN/WR DI DI/DI Reset input, active high. This pin aborts any ongoing conversions and resets the internal Configuration Register (CONFIG) to 000003FFh. A valid reset pulse should be at least 50 ns long. Hardware mode (HW/SW = 0): internal reference enable input. When high, the internal reference is enabled (the reference buffers are also enabled). When low, the internal reference is disabled and an external reference is applied at REFIO. Hardware mode (HW/SW = 0): internal reference enable input. When high, the internal reference is enabled (the reference buffers are also enabled). When low, the internal reference is disabled and an external reference is applied at REFIO. Software mode (HW/SW = 1): write input. The parallel data input is enabled when CS and WR are low. The internal reference is enabled by CONFIG bit C15 (REFEN). Software mode (HW/SW = 1): connect to DGND or DVDD. The internal reference is enabled by CONFIG bit C15 (REFEN). 12 RD DI/DI Read data input. When low, the parallel data output is enabled (if CS = 0). When high, the data output is disabled. Must be connected to DGND. 13 CS/FS DI/DI Chip select input. When low, the parallel interface is enabled. When high, the interface is disabled. Frame synchronization. The FS falling edge controls the frame transfer. 16 DB15/SDO_D DIO/DO Data bit 15 (MSB) input/output. Output is sign extension for the ADS8528/48. When SEL_CD = 1, this pin is the data output for channel pair D. When SEL_CD = 0, this pin should be tied to DGND. 17 DB14/SDO_C DIO/DO Data bit 14 input/output. Output is sign extension for the ADS8528/48. When SEL_CD = 1, this pin is the data output for channel pair C. When SEL_CD = 0, this pin should be tied to DGND. 18 DB13/SDO_B DIO/DO Data bit 13 input/output. Output is sign extension for the ADS8528 and MSB for the ADS8548. When SEL_B = 1, this pin is the data output for channel pair B. When SEL_B = 0, this pin should be tied to DGND. When SEL_CD = 0, data from channel pair D are also available on this output. DIO/DO Data bit 12 input/output. Output is sign extension for the ADS8528. Data output for channel pair A. When SEL_CD = 0, data from channel pair C are also available on this output. When SEL_CD = 0 and SEL_B = 0, SDO_A acts as single data output for all eight channels. 19 (1) RESET DB12/SDO_A AI = analog input; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; and P = power supply. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 15 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PIN DESCRIPTIONS (continued) DESCRIPTION PIN # NAME TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) DB11/REFBUFE N DIO/DI 21 DB10/SCLK DIO/DI Data bit 10 input/output 22 DB9/SDI DIO/DI Data bit 9 input/output 23 DB8/DCEN DIO/DI Data bit 8 input/output 24 DGND P Buffer I/O ground, connect to digital ground plane 25 DVDD P Buffer I/O supply, connect to digital supply. Decouple according to the Power Supply section. 26 DB7 DIO 20 27 DB6/SEL_B DIO/DI Data bit 11 input/output. Output is MSB for the ADS8528. SERIAL INTERFACE (PAR/SER = 1) Hardware mode (HW/SW = 0): reference buffer enable input. When low, all internal reference buffers are enabled (mandatory if internal reference is used). When high, all reference buffers are disabled. Software mode (HW/SW = 1): connect to DGND or DVDD. The internal reference buffers are controlled by bit C14 (REFBUFEN) in the Configuration Register (CONFIG). Serial interface clock input. Hardware mode (HW/SW = 0): connect to DGND. Software mode (HW/SW = 1): serial data input. Daisy-chain enable input. When high, DB[3:0] serve as daisy-chain inputs DCIN_[A:D]. If daisy-chain mode is not used, connect to DGND. Data bit 7 input/output Must be connected to DGND Data bit 6 input/output Select SDO_B input. When low, SDO_B is disabled and data from all eight channels are only available through SDO_A. When high and SEL_CD = 0, data from channel pairs B and D are available on SDO_B. When SEL_CD = 1, data from channel pair B are available on SDO_B. 28 DB5/SEL_CD DIO/DI Data bit 5 input/output Select SDO_C and SDO_D input. When high, data from channel pair C are available on SDO_C while data from channel pair D are available on SDO_D. When low and SEL_B = 1, data from channel pairs A and C are available on SDO_A while data from channel pairs B and D are available on SDO_B. When low and SEL_B = 0, data from all eight channels are avaiable on SDO_A. 29 DB4 DIO Data bit 4 input/output Connect to DGND 30 DB3/DCIN_A DIO/DI Data bit 3 input/output When DCEN = 1, this pin is the daisy-chain data input for SDO_A of the previous device in the chain. When DCEN = 0, connect to DGND. 31 DB2/DCIN_B DIO/DI Data bit 2 input/output When DCEN = 1 and SEL_B = 1, this pin is the daisy-chain data input for SDO_B of the previous device in the chain. When DCEN = 0, connect to DGND. 32 DB1/DCIN_C DIO/DI Data bit 1 input/output When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data input for SDO_C of the previous device in the chain. When DCEN = 0, connect to DGND. 33 DB0/DCIN_D DIO/DI Data bit 0 (LSB) input/output When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data input for SDO_D of the previous device in the chain. When DCEN = 0, connect to DGND. Hardware mode (HW/SW = 0): analog input voltage range select input. When low, the analog input voltage range is ±4VREF. When high, the analog input voltage range is ±2VREF. 34 35 16 RANGE/XCLK BUSY/INT DI/DI/DO DO Sofware mode (HW/SW = 1): this pin is an external conversion clock input if CONFIG bit C29 = 1 (CLKSEL); or an internal conversion clock output if CONFIG bit C28 = 1 (CLKOUT_EN). If this pin is not used, connect to DGND. When CONFIG bit C27 = 0 (BUSY/INT) this pin is a converter busy status output. This pin transitions high when a conversion has been started and transitions low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed and stays low when the conversion of the last channel pair has completed. When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a conversion has been completed and remains high until the next read access. This mode can only be used if all eight channels are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be changed using bit C26 (BUSY L/H) in the Configuration Register. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PIN DESCRIPTIONS (continued) DESCRIPTION PIN # NAME TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) 36 ASLEEP DI Auto-sleep enable input. When low, the device operates in normal mode. When high, the device works in auto-sleep mode where the hold mode and the actual conversion is activated 6 conversion clock (tCCLK) cycles after issuing a conversion start using a CONVST_x. This mode is recommended to save power if the device runs at a lower data rate; see the Reset and Power-Down Modes section for more details. 37 CONVST_A DI Conversion start of channel pair A. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. This signal resets the internal channel state machine that causes the data output to start with conversion results of channel A0 with the next read access. 38 CONVST_B DI Conversion start of channel pair B. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. 39 CONVST_C DI Conversion start of channel pair C. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. 40 CONVST_D DI Conversion start of channel pair D. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_D[1:0]. 41 HW/SW DI Mode selection input. When low, the hardware mode is selected and the device functions according to the settings of the external pins. When high, the software mode is selected in which the device is configured by writing to the Configuration Register (CONFIG). 42 CH_A0 AI Analog input of channel A0; channel A is the master channel pair that is always active. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in software mode. In cases where channel pairs of the device are used at different data rates, channel pair A should always run at the highest data rate. 43 REFAP AI Decoupling capacitor input for reference of channel pair A. Connect to the decoupling capacitor according to the Power Supply section. 46 REFAN AI Decoupling capacitor input for reference of channel pair A. Connect to the decoupling capacitor and AGND according to the Power Supply section. 47 CH_A1 AI Analog input of channel A1; channel A is the master channel pair that is always active. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in software mode. In cases where channel pairs of the device are used at different data rates, channel pair A should always run at the highest data rate. 48 HVDD P Positive supply voltage for the analog inputs. Decouple according to the Power Supply section. 49 CH_B0 AI Analog input of channel B0. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in software mode. 50 REFBP AI Decoupling capacitor input for reference of channel pair B. Connect to the decoupling capacitor according to the Power Supply section. 53 REFBN AI Decoupling capacitor input for reference of channel pair B. Connect to the decoupling capacitor and AGND according to the Power Supply section. 54 CH_B1 AI Analog input of channel B1. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in software mode. 55 REFN AI Negative reference input/output pin. Connect to a decoupling capacitor and AGND according to the Power Supply section. 56 REFIO AIO 59 CH_C1 AI Analog input of channel C1. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in software mode. 60 REFCN AI Decoupling capacitor input for reference of channel pair C. Connect to the decoupling capacitor and AGND according to the Power Supply section. 63 REFCP AI Decoupling capacitor input for reference of channel pair C. Connect to the decoupling capacitor according to the Power Supply section. 64 CH_C0 AI Analog input of channel C0. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in software mode. Reference voltage input/output. The internal reference is enabled by the REFEN/WR pin in hardware mode or by CONFIG bit C15 (REFEN) in software mode. The output value is controlled by the internal DAC (CONFIG bits C[9:0]). Connect to a decoupling capacitor according to the Power Supply section. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 17 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM HVDD HVSS AVDD DVDD Clock Generator CH_A0 SAR ADC AGND BUSY/INT CONVST_A RANGE/XCLK HW/SW Control Logic REFAP CH_A1 REFEN/WR SAR ADC AGND STBY RESET CH_B0 SAR ADC AGND CONVST_B REFBP CH_B1 SAR ADC AGND Config Register CH_C0 SAR ADC AGND CONVST_C REFCP CH_C1 SAR ADC AGND CS/FS CH_D0 SAR ADC AGND RD DB[15:0] I/O CONVST_D ASLEEP PAR/SER REFDP SCLK CH_D1 SAR ADC AGND String DAC REFIO AGND 18 2.5 VREF DGND Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. INL vs CODE (ADS8528) DNL vs CODE (ADS8528) 0.75 0.5 0.4 0.5 0.3 0.2 DNL (LSB) INL (LSB) 0.25 0 −0.25 0.1 0 −0.1 −0.2 −0.3 −0.5 −0.4 500 1000 1500 2000 Code 2500 3000 3500 −0.5 4000 0.4 INL (LSB) 0.6 0.4 0.2 0 −0.2 2500 3000 −0.6 −0.8 −0.8 −1 8000 10000 12000 14000 16000 Code G003 0 2000 4000 6000 8000 10000 12000 14000 16000 Code G004 Figure 7. Figure 8. DNL vs CODE (ADS8548 ±10VIN Range) DNL vs CODE (ADS8548 ±5VIN Range) 1 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0 −0.2 0.2 0 −0.2 −0.4 −0.4 −0.6 −0.6 −0.8 −0.8 4000 6000 8000 10000 12000 14000 16000 Code G005 G002 0 −0.4 6000 4000 −0.2 −0.6 4000 3500 0.2 −0.4 2000 2000 Code INL vs CODE (ADS8548 ±5VIN Range) 0.6 0 1500 INL vs CODE (ADS8548 ±10VIN Range) 1 −1 1000 Figure 6. 0.8 2000 500 Figure 5. 1 0 0 G001 0.8 −1 DNL (LSB) 0 DNL (LSB) INL (LSB) −0.75 −1 0 2000 4000 Figure 9. 6000 8000 10000 12000 14000 16000 Code G006 Figure 10. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 19 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. 3 2 2 1 1 INL (LSB) 3 0 0 −1 −1 −2 −2 −3 DNL (LSB) INL vs CODE (ADS8568 ±5VIN Range) 0 −3 8190 16380 24570 32760 40950 49140 57330 65520 Code G007 DNL vs CODE (ADS8568 ±10VIN Range) DNL vs CODE (ADS8568 ±5VIN Range) 3 2 2 1 1 0 0 −1 −1 −2 −2 0 8190 16380 24570 32760 40950 49140 57330 65520 Code G008 Figure 12. 3 −3 0 Figure 11. DNL (LSB) INL (LSB) INL vs CODE (ADS8568 ±10VIN Range) −3 8190 16380 24570 32760 40950 49140 57330 65520 Code G009 0 8190 16380 24570 32760 40950 49140 57330 65520 Code G010 Figure 13. Figure 14. OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE 1.5 1 0.8 0.6 0.5 Gain Error (%) Offset Error (mV) 1 0 −0.5 0.4 0.2 0 −0.2 −0.4 −0.6 −1 −0.8 −1.5 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 −1 −40 −25 −10 5 G011 Figure 15. 20 20 35 50 65 Temperature (°C) 80 95 110 125 G012 Figure 16. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. PSRR vs SUPPLY NOISE FREQUENCY CONVERSION TIME vs TEMPERATURE Power-Supply Rejection Ratio (dB) −40 1.8 CSUPPLY = 100nF on AVDD CSUPPLY = 1µF on HVDD CSUPPLY = 1µF on HVSS 1.7 Conversion Time (µs) −50 −60 −70 −80 AVDD HVDD HVSS −90 −100 0 20 40 1.6 1.5 1.4 1.3 1.2 ADS8568 ADS8548 ADS8528 1.1 1 −40 −25 −10 60 80 100 120 140 160 180 200 Supply Noise Frequency (kHz) G013 5 Figure 17. Signal-to-Noise Ratio (dB) 7389 110 125 G014 46 8 0 94 92 90 88 86 84 82 80 78 76 74 ADS8568 ADS8548 ADS8528 72 70 −40 −25 −10 0 5 Figure 19. 20 35 50 65 Temperature (°C) 80 95 110 125 G016 Figure 20. SINAD vs TEMPERATURE THD vs TEMPERATURE 94 −82 Total Harmonic Distortion (dB) Signal-to-Noise Ratio and Distortion (dB) 95 SNR vs TEMPERATURE 8947 92 90 88 86 84 82 80 78 76 74 72 70 −40 −25 −10 80 Figure 18. CODE HISTOGRAM (ADS8568, 16390 Hits) 0 20 35 50 65 Temperature (°C) ADS8568 ADS8548 ADS8528 5 20 35 50 65 Temperature (°C) 80 95 110 125 −84 ADS8568 ADS8548 ADS8528 −86 −88 −90 −92 −94 −96 −40 −25 −10 G017 Figure 21. 5 20 35 50 65 Temperature (°C) 80 95 110 125 G018 Figure 22. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 21 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. FREQUENCY SPECTRUM (ADS8568, 2048-Point FFT, fIN = 10kHz, ±10VIN Range) SFDR vs TEMPERATURE 0 ADS8568 ADS8548 ADS8528 98 −40 96 94 92 −60 −80 −100 −120 −140 90 −160 88 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 −180 110 125 0 25 50 75 G019 100 125 150 175 200 225 250 Frequency (kHz) G020 Figure 23. Figure 24. FREQUENCY SPECTRUM (ADS8568, 2048-Point FFT, fIN = 10kHz, ±5VIN Range) CHANNEL-TO-CHANNEL ISOLATION vs INPUT NOISE FREQUENCY 0 140 −20 135 −40 130 −60 Isolation (dB) Amplitude (dB) −20 Amplitude (dB) Spurious−Free Dynamic Range (dB) 100 −80 −100 −120 125 120 115 −140 110 −160 105 −180 0 25 50 75 100 100 125 150 175 200 225 250 Frequency (kHz) G021 0 25 50 75 100 125 150 175 200 225 250 Noise Frequency (kHz) G022 Figure 25. Figure 26. INTERNAL REFERENCE VOLTAGE vs ANALOG SUPPLY VOLTAGE (2.5V Mode) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (2.5V Mode) 2.504 2.515 2.503 2.51 2.505 2.501 VREF (V) VREF (V) 2.502 2.5 2.499 2.5 2.495 2.498 2.49 2.497 2.496 4.5 4.6 4.7 4.8 4.9 5 5.1 AVDD (V) 5.2 5.3 5.4 5.5 2.485 −40 −25 −10 5 G023 Figure 27. 22 20 35 50 65 Temperature (°C) 80 95 110 125 G024 Figure 28. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (3.0V Mode) ADS8568 ANALOG SUPPLY CURRENT vs TEMPERATURE 3.015 50 fDATA = MAX fDATA = 250kSPS (Auto-Sleep) 46 3.01 42 IAVDD (mA) VREF (V) 3.005 3 2.995 38 34 30 26 22 2.99 18 2.985 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 14 −40 −25 −10 110 125 20 35 50 65 Temperature (°C) 80 95 110 125 G026 Figure 29. Figure 30. ADS8568 ANALOG SUPPLY CURRENT vs DATA RATE BUFFER I/O SUPPLY CURRENT vs TEMPERATURE 50 2 Normal Operation Auto-Sleep Mode 45 40 1.6 35 1.4 30 25 20 1.2 1 0.8 15 0.6 10 0.4 5 0.2 0 0 51 fDATA = MAX fDATA = 250kSPS (Auto-Sleep) 1.8 IDVDD (mA) IAVDD (mA) 5 G025 0 −40 −25 −10 102 153 204 255 306 357 408 459 510 Sample Rate (kSPS) G027 5 20 35 50 65 Temperature (°C) 80 95 110 125 G028 Figure 31. Figure 32. ADS8568 INPUT SUPPLY CURRENT vs TEMPERATURE ADS8568 INPUT SUPPLY CURRENT vs INPUT SUPPLY VOLTAGE 4.5 IHVxx (mA) 3.5 IHVDD (fDATA = MAX) IHVSS (fDATA = MAX) IHVDD (fDATA = 250kSPS, Auto-Sleep) IHVSS (fDATA = 250kSPS, Auto-Sleep) 4 3.5 IHVxx (mA) 4 4.5 IHVDD (fDATA = MAX) IHVSS (fDATA = MAX) IHVDD (fDATA = 250kSPS, Auto-Sleep) IHVSS (fDATA = 250kSPS, Auto-Sleep) 3 2.5 3 2.5 2 1.5 2 1 1.5 1 −40 −25 −10 0.5 5 20 35 50 65 Temperature (°C) 80 95 110 125 0 5 6 7 G029 Figure 33. 8 9 10 11 12 HVDD, HVSS (V) 13 14 15 G030 Figure 34. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 23 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Graphs are valid for all devices of the family, at TA = +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V, VREF = 2.5V (internal), VIN = ±10V, and fDATA = maximum, unless otherwise noted. IHVxx (mA) ADS8568 INPUT SUPPLY CURRENT vs DATA RATE 4.5 4.25 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 IHVDD IHVSS IHVDD (Auto-Sleep) IHVSS (Auto-Sleep) 0 51 102 153 204 255 306 357 408 459 510 Sample Rate (kSPS) G031 Figure 35. 24 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com GENERAL DESCRIPTION The ADS8528/48/68 series includes eight 12-, 14-, and 16-bit analog-to-digital converters (ADCs), respectively, that operate based on the successive approximation register (SAR) architecture. This architecture is designed on the charge redistribution principle, which inherently includes a sample-and-hold function. The eight analog inputs are grouped into four channel pairs. These channel pairs can be sampled and converted simultaneously, preserving the relative phase information of the signals of each pair. Separate conversion start signals allow simultaneous sampling on each channel pair of four, six, or eight channels. These devices accept single-ended, bipolar analog input signals in the selectable ranges of ±4VREF or ±2VREF with an absolute value of up to ±12V; see the Analog Inputs section. The devices offer an internal 2.5V or 3V reference source followed by a 10-bit digital-to-analog converter (DAC) that allows the reference voltage VREF to be adjusted in 2.44mV or 2.93mV steps, respectively. The ADS8528/48/68 also offer a selectable parallel or serial interface that can be used in hardware or software mode; see the Device Configuration section for details. The Analog and Digital sections describe the functionality and control of the device in detail. ANALOG This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the device. Analog Inputs The inputs and the converters are of single-ended bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the Configuration (CONFIG) Register to either ±4VREF or ±2VREF. With the internal reference set to 2.5V (VREF bit C13 = 0 in the CONFIG Register), the input voltage range can be ±10V or ±5V. With the internal reference source set to 3V (CONFIG bit C13 = 1), an input voltage range of ±12V or ±6V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CONFIG bit C26 = 0). The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (tACQ). The source of the analog input voltage must be able to charge the input capacitance of 10pF in ±4VREF mode or of 20pF in ±2VREF mode to a 12-, 14-, or 16-bit accuracy level within the acquisition time; see Figure 4. During the conversion period, there is no further input current flow and the input impedance is greater than 1MΩ. To ensure a defined start condition, the sampling capacitors of the ADS8528/48/68 are pre-charged to a fixed internal voltage before switching into sampling mode. To maintain the linearity of the converter, the inputs should always remain within the specified range shown in the Electrical Characteristics table. The minimum –3dB bandwidth of the driving operational amplifier can be calculated using Equation 1: ln(2)(n + 1) f3dB = 2ptACQ (1) where: n = 12, 14, or 16; n is the resolution of the ADS8528/48/68 With a minimum acquisition time of tACQ = 280ns, the required minimum bandwidth of the driving amplifier is 5.2MHz for the ADS8528, 6.0MHz for the ADS8548, or 6.7MHz for the ADS8568. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the bandwidth requirement shown in Equation 1. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 25 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com A driving operational amplifier may not be required, if the impedance of the signal source (RSOURCE) fulfills the requirement of Equation 2: tACQ RSOURCE < - (RSER + RSW) CS ln(2)(n + 1) (2) where: n = 12, 14, or 16; n is the resolution of the ADC, CS = 10pF is the sample capacitor value in VIN = ±4VREF mode, RSER = 200Ω is the input resistor value, and RSW = 130Ω is the switch resistance value. With a minimum acquisition time of tACQ = 280ns, the maximum source impedance should be less than 2.7kΩ for the ADS8528, 2.3kΩ for the ADS8548, and 2.0kΩ for the ADS8568 in ±4VREF mode, or less than 1.2kΩ for the ADS8528, 1.0kΩ for the ADS8548, and 0.8kΩ for the ADS8568 in ±2VREF mode. The source impedance can be higher if the application allows longer acquisition time. Analog-to-Digital Converter (ADC) The device includes eight ADCs that operate with either an internal or an external conversion clock. Conversion Clock The device uses either an internally-generated (CCLK) or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. In this case, a complete conversion including the pre-charging of the sample capacitors takes 19 to 20 clock cycles, depending on the setup time of the incoming CONVST_x signal with relation to the rising edge of the CCLK. When CLKSEL bit is set high (CONFIG bit C29), an external conversion clock can be applied on pin 34. A complete conversion process requires 19 clock cycles in this case if the tSCVX timing requirement is fulfilled. The external clock can remain low between conversions. If the application requires lowest power dissipation at low data rates, it is recommended to use the auto-sleep mode, activated using pin 36 (ASLEEP). In this case, a conversion cycle takes up to 26 clock cycles (see the Reset and Power-Down Modes section for more details). 26 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com CONVST_x The analog inputs of each channel pair (CH_x0/1) are held with the rising edge of the corresponding CONVST_x signal. The conversion automatically starts with the next rising edge of the conversion clock. CONVST_A is a master conversion start that resets the internal state machine and causes the data output to start with the result of channel A0. In cases where channel pairs of the device are used at different data rates, CONVST_A should always be the one used at the highest frequency. A conversion start must not be issued during an ongoing conversion on the corresponding channel pair. It is allowed to initiate conversions on the other input pairs, however. If a parallel interface is used, the content of the output port depends on which CONVST_x signals have been issued. Figure 36 shows examples of different scenarios with all channel pairs active. BUSY (C27 = C26 = 0) CS CONVST_A, C CONVST_B, D RD CH A0 DB[15:0] CH A1 CH B0 CH B1 CH C0 CH C1 CH D0 Old Data CH D1 Old Data CONVST_B CONVST_A, C, D RD CH A0 DB[15:0] CH A1 Old Data CH B0 CH B1 CH C0 CH C1 CH D0 CH D1 Old Data Figure 36. Data Output versus CONVST_x (All Channels Active) Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 27 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com BUSY/INT The BUSY signal indicates if a conversion is in progress. It goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective output register. The readout of the data can be initiated immediately after the falling edge of BUSY. In contrary, the INT signal goes high when a new conversion result has been loaded in the output register (this is when the conversion has been completed) and remains high until the next read access, as shown in Figure 37. The polarity of the BUSY/INT signal can be changed using CONFIG bit C26. The mode of pin 35 can be controlled using CONFIG bit C27. CONVST_x tCONV BUSY (C27 = C26 = 0) PAR = RD SER = FS INT (C27 = 1, C26 = 0) Figure 37. BUSY versus INT Behavior of Pin 35 Reference The ADS8528/48/68 provides an internal, low-drift, 2.5V reference source. To increase the input voltage range, the reference voltage can be switched to 3V mode using the VREF bit (CONFIG bit C13). The reference feeds a 10-bit string-DAC controlled by bits REFDAC[9:0] in the Configuration (CONFIG) Register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44mV (2.92mV in 3V mode) steps and adjustable to the applications needs without additional external components. The actual output voltage can be calculated using Equation 3: Range ´ (Code + 1) VREF = 1024 (3) where: Range = the chosen maximum reference voltage output range (2.5V or 3V), Code = the decimal value of the DAC register content. Table 4 lists some examples of internal reference DAC settings with a reference range set to 2.5V. However, to ensure proper performance, the DAC output voltage should not be programmed below 0.5V. The buffered output of the DAC should be decoupled with a 100nF capacitor (minimum); for best performance, a 470nF capacitor is recommended. If the internal reference is placed into power-down (default), an external reference voltage can drive the REFIO pin. Table 4. DAC Settings Examples (2.5V Operation) 28 VREFOUT DECIMAL CODE BINARY CODE HEXADECIMAL CODE 0.5 V 204 00 1100 1100 CCh 1.25 V 511 01 1111 1111 1FFh 2.5 V 1023 11 1111 1111 3FFh Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com The voltage at the REFIO pin is buffered with four internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10µF capacitor between the pin pairs 3 and 6, 43 and 46, 50 and 53, and 60 and 63. The 10µF capacitors are available as ceramic 0805-SMD components and in X5R quality. The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to the REFAP, REFBP, REFCP, and REFDP pins. With 10µF decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4: ln(2) f3dB = 2ptCONV (4) With the minimum tCONV of 1.33µs, the external reference buffers require a minimum bandwidth of 83kHz. DIGITAL This section describes the digital control and the timing of the device in detail. Device Configuration Depending on the desired mode of operation, the ADS8528/48/68 can be configured using the external pins and/or the Configuration Register (CONFIG), as shown in Table 5. Table 5. ADS8528/48/68 Configuration Settings INTERFACE MODE HARDWARE MODE (HW/SW = 0) SOFTWARE MODE (HW/SW = 1) Parallel (PAR/SER = 0) Configuration using pins and (optionally) Configuration Configuration using Configuration Register bits C[31:0] Register bits C30, C29, C[27:26], C22, C20, C18, C14, only; status of pins 9, 11, 20, and 34 are disregarded C13, and C[9:0] (if C29 = C28 = 0) Serial (PAR/SER = 1) Configuration using pins and (optionally) Configuration Configuration using Configuration Register bits C[31:0] Register bits C30, C29, C[27:26], C22, C20, C18, C13, only; status of pins 9, 11, 20, and 34 are disregarded and C[9:0] (if C29 = C28 = 0) Hardware Mode With the HW/SW input (pin 41) set low, the device functions are controlled via the pins and, optionally, Configuration Register bits C30, C29, C[27:26], C22, C20, C18, C14 (in parallel interface mode only), C13, and C[9:0]. It is possible to generally use the part in hardware mode but to switch it into software mode to initialize or adjust the Configuration Register settings (for example, the internal reference DAC) and back to hardware mode thereafter. Software Mode When the HW/SW input is set high, the device operates in software mode with functionality set only by the Configuration Register bits (corresponding pin settings are ignored). If parallel interface is used, an update of all Configuration Register settings is performed by issuing two 16-bit write accesses on pins DB[15:0] (to avoid loosing data, the entire sequence must be finished before starting a new conversion). CS should be held low during these two accesses. To enable the actual update of the register settings, the first bit (C31) must be set to '1' during the access. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 29 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com If the serial interface is used, the update of the register contents can be performed continuously (combined read/write access). Optionally, to reduce the data transfer on the SDI line and the electromagnetic interference (EMI) of the system, the SDI input can be pulled low when a register update is not required. Figure 38 illustrates the different Configuration Register update options. RESET (or Power Up) BUSY (C20 = C21 = 0) PAR/SER = 1 FS Content Update C[31:0] Initialization Data SDI No Content Update C[31:0] PAR/SER = 0 CS WR Update Initialization Data DB[15:0] C [31:16] C [15:0] C [31:16] C [15:0] Figure 38. Configuration Register Update Options 30 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Configuration (CONFIG) Register The Configuration Register settings can only be changed in software mode and are not affected when switching to hardware mode thereafter. The register values are independent from input pin settings. Changes are active with the second rising edge of WR in parallel interface mode or with the 32nd SCLK falling edge of the access in which the register content has been updated in serial mode. The CONFIG content is defined in Table 6. Table 6. CONFIG: Configuration Register (Default: 000003FFh) 31 30 29 28 27 26 25 24 WRITE_EN READ_EN CLKSEL CLKOUT BUSY/INT BUSY POL STBY RANGE_A 23 22 21 20 19 18 17 16 RANGE_B PD_B RANGE_C PD_C RANGE_D PD_D Don't care Don't care 15 14 13 12 11 10 9 8 REFEN REFBUF VREF Don't care Don't care Don't care D9 D8 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit 31 WRITE_EN: Register update enable This bit is not active in hardware mode. 0 = Register content update disabled (default) 1 = Register content update enabled Bit 30 READ_EN: Register read-out access enable This bit is not active in hardware mode. 0 = Normal operation (conversion results available on SDO_A) 1 = Configuration Register contents output on SDO_A with next two accesses (READ_EN automatically resets to '0' thereafter) Bit 29 CLKSEL: Conversion clock selector This bit is active in hardware mode. 0 = Normal operation with internal conversion clock; mandatory in hardware mode (default) 1 = External conversion clock applied through pin 34 (XCLK) is used (conversion takes 19 clock cycles) Bit 28 CLKOUT: Internal conversion clock output enable This bit is not active in hardware mode. 0 = Normal operation (default) 1 = Internal conversion clock is available at pin 34 Bit 27 BUSY/INT: Busy/interrupt selector This bit is active in hardware mode. 0 = BUSY/INT pin in BUSY mode (default) 1 = BUSY/INT pin in interrupt mode (INT); can only be used if all eight channels are sampled simultaneously (all CONVST_x tied together) Bit 26 BUSY POL: BUSY/INT polarity selector This bit is active in hardware mode. 0 = BUSY/INT active high (default) 1 = BUSY/INT active low Bit 25 STBY: Power-down enable This bit is not active in hardware mode. 0 = Normal operation (default) 1 = Entire device is powered down (including the internal clock and reference) Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 31 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 Bit 24 www.ti.com RANGE_A: Input voltage range selector for channel pair A This bit is not active in hardware mode. 0 = Input voltage range: 4VREF (default) 1 = Input voltage range: 2VREF Bit 23 RANGE_B: Input voltage range selector for channel pair B This bit is not active in hardware mode. 0 = Input voltage range: 4VREF (default) 1 = Input voltage range: 2VREF Bit 22 PD_B: Power-down enable for channel pair B This bit is active in hardware mode. 0 = Normal operation (default) 1 = Channel pair B is powered down Bit 21 RANGE_C: Input voltage range selector for channel pair C This bit is not active in hardware mode. 0 = Input voltage range: 4VREF (default) 1 = Input voltage range: 2VREF Bit 20 PD_C: Power-down enable for channel pair C This bit is active in hardware mode. 0 = Normal operation (default) 1 = Channel pair C is powered down Bit 19 RANGE_D: Input voltage range selector for channel pair D This bit is not active in hardware mode. 0 = Input voltage range: 4VREF (default) 1 = Input voltage range: 2VREF Bit 18 PD_D: Power-down enable for channel pair D This bit is active in hardware mode. 0 = Normal operation (default) 1 = Channel pair D is powered down Bits[17:16] Not used (default = 0) Bit 15 REF_EN: Internal reference enable This bit is not active in hardware mode. 0 = Internal reference source disabled (default) 1 = Internal reference source enabled Bit 14 REFBUF: Internal reference buffers disable This bit is active in hardware mode if the parallel interface is used. 0 = Internal reference buffers enabled (default) 1 = Internal reference buffers disabled Bit 13 VREF: Internal reference voltage selector This bit is active in hardware mode. 0 = Internal reference voltage set to 2.5V (default) 1 = Internal reference voltage set to 3.0V Bits[12:10] Not used (default = 0) Bits[9:0] D[9:0]: REFDAC setting bits These bits are active in hardware mode. These bits correspond to the settings of the internal reference DACs (compare to the Reference section). Bit D9 is the MSB of the DAC. Default value is 3FFh (2.5V, nom). 32 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Parallel Interface To use the device with the parallel interface, the PAR/SER pin should be held low. The maximum achievable data throughput rate is 650kSPS for the ADS8528, 600kSPS for the ADS8548, and 510kSPS for the ADS8568 in this case. Access to the ADS8528/48/68 is controlled as illustrated in Figure 2 and Figure 3. Serial Interface The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A (always active), SDO_B, SDO_C, and SDO_D, depending on the selections made using the SEL_xx pins. Starting with the most significant bit (MSB), the output data are changed with the falling edge of SCLK. Output data of the ADS8528 and ADS8548 maintain the LSB-aligned 16-bit format with leading bits containing the extended sign (see also Table 7). Serial data input SDI are latched with the falling edge of SCLK. The serial interface can be used with one, two, or four output ports. Port SDO_B can be enabled using pin 27 (SEL_B) while ports SDO_C and SDO_D are enabled using pin 28 (SEL_CD). If all four serial data output ports are selected, the data can be read with either two 16-bit data transfers or with a single 32-bit data transfer. The data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 480kSPS for the ADS8528, 450kSPS for the ADS8548, and 400kSPS for the ADS8568 in this case. If the application allows a data transfer using two ports only, the SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1, CH_C0, and CH_C1 on SDO_A, while data from channel CH_B0 followed by CH_B1, CH_D0, and CH_D1 occur on SDO_B. In this case, a data transfer of four 16-bit words, two 32-bit words, or one continuous 64-bit word is supported. The maximum achievable data throughput rate is 360kSPS for the ADS8528, 345kSPS for the ADS8548, and 315kSPS for the ADS8568 in this case. The output SDO_A is always active and exclusively used if only one serial data port is used in the application. The data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, CH_C1, CH_D0, and CH_D1. Data can be read using eight 16-bit transfers, four 32-bit transfers, two 64-bit transfers, or a single 128-bit transfer. The maximum achievable data throughput rate is 235kSPS for the ADS8528, 230kSPS for the ADS8548 and 215kSPS for the ADS8568 in this case. Figure 1 and Figure 39 show all possible scenarios in more detail. BUSY (C20 = C21 = 0) SEL_B = 1, SEL_C/D = 0 64 SCLKs FS SDO_A CHA0 CHA1 CHC0 CHC1 SDO_B CHB0 CHB1 CHD0 CHD1 SEL_B = SEL_C/D = 0 128 SCLKs FS SDO_A CHA0 CHA1 CHB0 CHB1 CHC0 CHC1 CHD0 CHD1 Figure 39. Data Output with One or Two Active SDOs (All Input Channels Active and Converted) Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 33 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Daisy-Chain Mode The serial interface of the ADS8528/48/68 supports a daisy-chain feature that allows cascading of multiple devices to minimize the board space requirements and simplify routing of the data and control lines. In this case, pins DB3/DCIN_A, DB2/DCIN_B, DB1/DCIN_C, and DB0/DCIN_D are used as serial data inputs for channels A, B, C, and D, respectively. Figure 40 shows an example of a daisy-chain connection of three devices sharing a common CONVST line to allow simultaneous sampling of 24 analog channels along with the corresponding timing diagram. To activate the daisy-chain mode, the DCEN pin must be pulled high. However, the DCEN of the first device in the chain must remain low. In applications in which not all channel pairs are used, it is recommended to declare the part with disabled channel pair(s) to be the first in the daisy-chain. CONVST FS SCLK ADS85x8 #1 ADS85x8 #2 ADS85x8 #3 CONVST_A/B/C/D CONVST_A/B/C/D CONVST_A/B/C/D FS FS FS SCLK SCLK SCLK SDO_A SDO_A DCIN_A SDO_A DCIN_A SDO_B DCIN_B SDO_B DCIN_B SDO_B SDO_C DCIN_C SDO_C DCIN_C SDO_C DCIN_D SDO_D DCIN_D SDO_D SDO_D DVDD DCEN To Processing Unit DVDD DCEN DCEN DGND CONVST BUSY (C27 = C26 = 0) FS SDO_x #3 Don’t Care 16-Bit Data CHx0 ADS85x8 #3 16-Bit Data CHx1 ADS85x8 #3 16-Bit Data CHx0 ADS85x8 #2 16-Bit Data CHx1 ADS85x8 #2 16-Bit Data CHx0 ADS85x8 #1 16-Bit Data CHx1 ADS85x8 #1 Figure 40. Example of Daisy-Chaining Three Devices 34 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Output Data Format The data output format of the ADS8528/48/68 is binary twos complement, as shown in Table 7. For the ADS8528/48 (which deliver 12-bit or 14-bit conversion results, respectively), the leading bits of either the 16-bit frame (serial interface) or the output pins (DB[15:12] for the ADS8528 or DB[15:14] for the ADS8548 in parallel mode) deliver a sign extension. Table 7. Output Data Format BINARY CODE HEXADECIMAL CODE DESCRIPTION INPUT VOLTAGE VALUE ADS8528 ADSS8548 ADS8568 Positive full-scale +4VREF or +2VREF 0000 0111 1111 1111 07FFh 0001 1111 1111 1111 1FFFh 0111 1111 1111 1111 7FFFh Midscale +0.5LSB VREF/(2 × resolution) 0000 0000 0000 0000 0000h 0000 0000 0000 0000 0000h 0000 0000 0000 0000 0000h Midscale –0.5LSB –VREF/(2 × resolution) 1111 1111 1111 1111 FFFFh 1111 1111 1111 1111 FFFFh 1111 1111 1111 1111 FFFFh Negative full-scale –4VREF or –2VREF 1111 1000 0000 0000 F800h 1110 0000 0000 0000 E000h 1000 0000 0000 0000 8000h Reset and Power-Down Modes The device supports two reset mechanisms: a power-on reset (POR) and a pin-controlled reset (RESET) that can be issued using pin 10. Both, the POR and RESET act as a master reset that causes any ongoing conversion to be interrupted, the Configuration Register content to be set to the default value, and all channels to be switched into the sample mode. When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.2V. In normal operation, glitches on the AVDD supply below this threshold trigger a device reset. The entire device, except for the digital interface, can be powered down by pulling the STBY pin low (pin 9). As the digital interface section remains active, data can be retrieved while in stand-by mode. To power the part on again, the STBY pin must be brought high. The device is ready to start a new conversion after the 10ms required to activate and settle the internal circuitry. This user-controlled approach can be used in applications that require lower data throughput rates at lowest power dissipation. The content of CONFIG is not changed during stand-by mode and it is not required to perform a reset after returning to normal operation. Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 35 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com While the standby mode impacts the entire device, each device channel pair (except channel pair A, which as the master channel pair, is always active) can also be individually switched off by setting the Configuration Register bits C22, C20, and C18 (PD_x). If a certain channel pair is powered-down in this manner, the output register is disabled as shown in Figure 41. When reactivated, the relevant channel pair requires 10ms to fully settle before starting a new conversion. BUSY (C27 = C26 = 0) CONVST_A/B/D RD CH A0 DB[15:0] CH A1 CH B0 CH B1 CH D0 CH A0 CH D1 CH A1 Same Data (Reread) CONVST_B CONVST_A/D RD CH A0 DB[15:0] CH A1 Old Data CH B0 CH B1 CH D0 CH A0 CH D1 Old Data CH A1 Old Data (Reread) (1) Channel pair C disabled (PD_C = 1), CS = 0. NOTE: Boxed areas indicate the minimum required frame to acquire all new conversion results. The read access might be interrupted, thereafter. Figure 41. Example of Data Output Order with Channel Pair C Powered Down(1) 36 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com The auto-sleep mode is enabled by pulling pin 36 (ASLEEP) high. If the auto-sleep mode is enabled, the ADS8528/48/68 automatically reduce the current requirement to 7mA (IAVDD) after finishing a conversion; thus, the end of conversion actually activates this power-down mode. Triggering a new conversion by applying a positive CONVST_x edge puts the device back into normal operation, starts the acquisition of the analog input, and automatically starts a new conversion 6 to 7 conversion clock cycles later, as shown in Figure 42. Therefore, a complete conversion process takes 25 to 26 conversion clock cycles; thus, the maximum throughput rate in auto-sleep mode is reduced to a maximum of 400kSPS for the ADS8528, 375kSPS for the ADS8548, and 330kSPS for the ADS8568 in serial interface mode. In parallel mode, the maximum data rates are 510kSPS for the ADS8528, 470kSPS for the ADS8548 and 400kSPS for the ADS8568. If enabled, the internal reference remains active during auto-sleep mode. Table 8 compares the analog current requirements of the device in different modes. ASLEEP 6tCCLK CONVST_x BUSY ADC CH_x ACQ CONV Power-Down ACQ CONV Power-Down Figure 42. Auto-Sleep Power-Down Mode Table 8. Maximum Analog Current (IAVDD) Demand of the ADS85x8 OPERATIONA L MODE ANALOG CURRENT (IAVDD) Normal operation 12.5mA/ch pair at maximum data rate Auto-sleep 1.75mA/ch pair ENABLED/DIS ABLED BY ACTIVATED BY NORMAL OPERATION TO POWERDOWN DELAY RESUMED BY POWER-UP TO NORMAL OPERATION DELAY POWER-UP TO NEXT CONVERSION START TIME CONVST_x — — — — Each end of conversion At falling edge of BUSY CONVST_x Immediate 7 × tCCLK max PD_x = 1 (CONFIG bit) Immediate PD_x = 0 (CONFIG bit) Immediate after completing CONFIG update 10ms STBY = 0 Immediate STBY = 1 Immediate 10ms Power on Power off ASLEEP = 1 ASLEEP = 0 HW/SW = 1 Power-down of 16µA channel pair X (channel pair X) Power-down (entire device) 30µA HW/SW = 0 Power on Power off Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 37 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION TYPICAL APPLICATION EXAMPLE An example of a typical application of the ADS8528/48/68 is illustrated in Figure 43. In this case, the device is used to simultaneously sample and convert the voltages and currents on three phases and the neutral line. In this example, the BUSY signal is not used by the controller while the SW generates the required signals in timely manner. TI’s OPA2211 is used as an input driver, supporting bandwidth that allows running the device at the maximum data rate. However, because relatively low data rates are generally used in this type of applications, the auto-sleep mode is activated in this example (ASLEEP is high) to minimize the current demand on the AVDD and HVDD/HVSS power supplies. Further, the input drivers may not be necessary if the signal source fulfills the requirements as defined by Equation 2. For example, at 10kSPS, the external drivers are not necessary if the source impedance remains below 830kΩ in ±4VREF mode or 415kΩ in ±2VREF mode. While the actual values of the resistors and capacitors depend on the bandwidth and performance requirements of the application, for a data rate of 10kSPS, it is recommended to use a filter capacitor CF value of 1nF and a series resistor RF of 10kΩ. In applications supporting only single supply (for example, 5V), it is recommended to use the TPS65130 to generate the bipolar supplies required by the ADC. GROUNDING All ground pins should be connected to a clean ground reference. This connection should be kept as short as possible to minimize the inductance of these paths. It is recommended to use vias connecting the pads directly to the corresponding ground plane. In designs without ground planes, the ground trace should be kept as wide and as short as possible to reduce inductance. Avoid connections that are too close to the grounding point of a microcontroller or digital signal processor. Depending on the circuit density on the board, placement of the analog and digital components, and the related current loops, a single solid ground plane for the entire printed circuit board (PCB) or dedicated analog and digital ground areas may be used. In case of separated ground areas, ensure a low-impedance connection between the analog and digital ground of the ADC by placing a bridge underneath (or next to) the ADC. Otherwise, even short undershoots on the digital interface with a value of lower than –300mV lead to the conduction of ESD diodes, causing current to flow through the substrate and either degrading the analog performance or even damaging the part. It is recommended to use a common ground plane underneath the device as a local ground reference for all xGND pins; see Figure 44. During PCB layout, care should be taken to avoid any return currents crossing sensitive analog areas or signals. 38 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com R1 R2 AGND HVDD ADS85x8 RF CH_A0 L1 Current Signal CF OPA2211 L1 Voltage Signal AGND CF RF CH_A1 REFAP HVSS 10mF AGND R1 REFAN AGND R2 REFBN AGND 10mF HVDD CONVST_A CONVST_B CONVST_C REFBP CONVST_D RF RESET CH_B0 L2 Current Signal OPA2211 L2 Voltage Signal AGND RD CF RF Host Controller CS CF DB[15:0] CH_B1 REFIO HVSS 0.47mF AGND R1 AGND R2 REFN AGND HVDD DVDD RF CH_C0 L3 Current Signal STBY CF OPA2211 L3 Voltage Signal ASLEEP AGND CF RF REFEN/WR CH_C1 HW/SW PAR/SER REFCP HVSS 10mF AGND R1 RANGE AGND R2 REFCN REFDN AGND DGND 10mF HVDD REFDP RF CH_D0 N Current Signal CF OPA2211 N Voltage Signal AGND CF RF DVDD CH_D1 AVDD 6x 0.1mF HVSS AGND R1 R2 AGND 10mF AVDD AVDD AGND AGND AGND AGND AGND AGND AVDD AVDD AVDD AVDD AVDD DVDD 1mF DGND DGND HVSS HVSS 0.1mF 10mF 0.1mF 10mF AGND HVDD ADS85x8 HVDD Figure 43. Three-Phase + N Current/Voltage Measurement Application Based on the ADS85x8 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 39 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com POWER SUPPLY The ADS8528/48/68 require four separate supplies: an analog supply for the ADC (AVDD), the buffer I/O supply for the digital interface (DVDD), and the high-voltage supplies driving the analog input circuitry (HVDD and HVSS). Generally, there are no specific requirements with regard to the power sequencing of the device. However, when HVDD is supplied before AVDD, the internal electrostatic discharge (ESD) structure conducts, increasing the IHVDD beyond the specified value, until the AVDD is applied. The AVDD supply provides power to the internal circuitry of the ADC. If run at maximum data rate, the IAVDD is too high to allow use of a passive filter between the digital board supply of the application and the AVDD pins. A linear regulator is recommended to generate the analog supply voltage. Each AVDD pin should be decoupled to AGND with a 100nF ceramic capacitor. In addition, a single 10µF capacitor should be placed close to the device but without compromising the placement of the smaller capacitors. Optionally, each supply pin can be decoupled using a 1µF ceramic capacitor without the requirement for the additional 10µF capacitor. The DVDD supply is only used to drive the digital I/O buffers and allows seamless interface with most state-of-the-art processors and controllers. As a result of the low IDVDD value, a 10Ω series resistor can be used on the DVDD pin to reduce the noise energy from the external digital circuitry influencing the performance of the device. A bypass ceramic capacitor of 1µF (or alternatively, a pair of 100nF and 10µF capacitors) should be placed between pins 24 and 25. The high-voltage supplies (HVSS and HVDD) are connected to the analog inputs. These supplies are not required to be of symmetrical nature with regard to AGND. Noise and glitches on these supplies directly couple into the input signals. Place a 100nF ceramic decoupling capacitor, located as close to the device as possible, between each of pins 1, 48, and AGND. An additional 10µF capacitor is used that should be placed close to the device but without compromising the placement of the smaller capacitors. Figure 44 shows a layout recommendation for the ADS8528/48/68 along with the proper decoupling and reference capacitors placement and connections. The layout recommendation takes into account the actual size of the components used. 40 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com Top View RF RF RF CF CF RF CF CF 10mF RF CF 0.1mF To HVDD HVSS HVDD CH_D1 CH_A1 REFDN REFAN AVDD AVDD AGND AGND REFDP REFAP CH_D0 CH_A0 8 41 10mF 40 39 11 38 12 37 13 36 CF 33 17 18 19 20 21 22 23 27 28 29 31 16 CF RF 32 35 34 30 AVDD AGND 26 LEGEND Top Layer; Copper Pour and Traces 9 10 DVDD RF RF 10mF DGND CF 10mF CH_B0 REFBP AVDD AGND REFBN REFN CH_B1 REFIO AVDD AGND CH_C1 AVDD REFCN AGND CH_C0 Tto HVSS REFCP 0.1mF 10mF 10mF 0.47mF Lower Layer; AGND Area Lower Layer; DGND Area Via (1) All AVDD/DVDD decoupling capacitors are placed on the bottom layer underneath the device power-supply pins and are connected by vias. All 100nF ceramic capacitors are placed as close as possible to the device while the 10µF capacitors are also close but without compromising the placement of the smaller capacitors. Figure 44. Layout Recommendation Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 41 ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (August 2011) to Revision A Page • Deleted INL column from Family/Ordering Information table ............................................................................................... 2 • Changed DC Accuracy, INL parameter in ADS8568 Electical Chatacteristics table ............................................................ 5 42 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS8528SPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8528SPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8528SRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8528SRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8548SPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8548SPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8548SRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8548SRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8568SPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8568SPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8568SRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8568SRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2011 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8528SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 ADS8528SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS8528SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS8548SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 ADS8548SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS8548SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS8568SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 ADS8568SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS8568SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8528SPMR LQFP PM 64 1000 367.0 367.0 45.0 ADS8528SRGCR VQFN RGC 64 2000 367.0 367.0 38.0 ADS8528SRGCT VQFN RGC 64 250 210.0 185.0 35.0 ADS8548SPMR LQFP PM 64 1000 367.0 367.0 45.0 ADS8548SRGCR VQFN RGC 64 2000 367.0 367.0 38.0 ADS8548SRGCT VQFN RGC 64 250 210.0 185.0 35.0 ADS8568SPMR LQFP PM 64 1000 367.0 367.0 45.0 ADS8568SRGCR VQFN RGC 64 2000 367.0 367.0 38.0 ADS8568SRGCT VQFN RGC 64 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. 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