Order this document by MC145745/D SEMICONDUCTOR TECHNICAL DATA Product Preview The MC145745 is a selectable modem chip compatible with ITU V.21 (300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex asynchronous). The built–in differential line driver has the capability of driving 0 dBm into a 600 Ω load with a 5 V single power supply. This device also includes a DTMF generator, DTMF receiver, call–progress tone detector, answer tone generator, and a receive timing control circuit. Besides having a clock generator with a crystal oscillator connected to it, the device has a divider circuit to which input of a double frequency clock is possible from external sources, such as from a microcontroller unit (MCU). The serial control port (SCP) permits the MCU to access internal registers for exercising the built–in features. A low consumption device, the MC145745 integrates various functions in a small package. This modem IC is best suited for telemeter and other applications of this type. • • • • • • • • • Conforms to ITU V.21 and V.23 Recommendations DTMF Generator and Receiver for all 16 Standard Digits Capable of Driving 0 dBm into a 600 Ω Load (VCC = 5 V) Automatic Gain Control (AGC) Amplifier for the DTMF Receiver Call–Progress Tone Detector Four–Wire Serial Data Interface (SCP) Programmable Transmission and Carrier Detection Levels FSK/DTMF Analog Loopback Self–Test Function Crystal Oscillator (3.579545 MHz) and Half Divider Circuit (7.159090 MHz) for External Inputs • Operates in the Voltage Range of 3.3 – 5.5 V • Power Down Mode (ICC < 1 µA) FW SUFFIX SOIC CASE 751M 28 1 ORDERING INFORMATION MC145745FW SOIC PIN ASSIGNMENT GND 1 28 VCC Vref 2 27 RxA CDA 3 26 TxA1 TLA 4 25 TxA2 TEST 1 5 24 TEST 2 RxD 6 23 SCPEN TxD 7 22 SCPCLK CD 8 21 SCP Rx CLKO 9 20 SCP Tx X1 10 19 RESET X2 11 18 PB3 ECLK 12 17 PB2 PB0 13 16 PB1 GND 14 15 VCC This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 0 7/96 Motorola, Inc. 1996 MOTOROLA MC145745 1 BLOCK DIAGRAM RxA CDA ANTI–ALIAS AND LOW–PASS FILTER LOOPBACK PATH Vref TxA2 – + TxA1 CLKO 4 Rx AMP AND AGC CONTROL CLOCK GENERATOR TONE GENERATOR DTMF RECEIVER CPT DETECTOR FSK CARRIER DETECTOR SMOOTHING FILTER AND Tx GAIN CONTROL TIMING CONTROL CIRCUIT FSK V.21 MODEM PB0 – PB3 CD TxD FSK V.23 MODEM RxD 1/2 RESET X1 MC145745 2 X2 ECLK TLA VCC GND SCP Tx SCP Rx SCPEN SCPCLK MOTOROLA PIN DESCRIPTIONS Pin Location Symbol Type 1, 14 GND — Ground — These are the ground pins of the digital and the analog circuits. The 0 V potential of the device is determined by the input voltage at these pins. 2 Vref — Reference Analog Ground — This pin provides the analog ground voltage VCC/2, which is regulated internally. This pin should be decoupled to GND with 0.1 µF and 100 µF capacitors. 3 CDA — Carrier Detect Level Adjustment — The detection level for FSK/call–progress tone is determined according to the voltage at this pin. When VCC = 5 V and the carrier detection level bit (BR3:b1) of the SCP register is 0, or when VCC = 3.6 V and (BR3:b1) is 1, the CDA voltage is set to 1.25 V by the internal divider. This voltage sets the detection levels at ON to OFF: – 44 dBm (typ) and OFF to ON: – 47 dBm (typ). This high impedance pin should be decoupled to GND with a 0.1 µF capacitor. The carrier detection level is proportional to the terminal voltage at this pin. An external voltage may be applied to this pin to adjust the carrier detect threshold. The following equations may be used to find the CDA voltage requirements for a given threshold voltage. VCDA = 256 x Von VCDA = 362 x Voff 4 TLA — Transmit Level Adjustment — This pin is used to adjust the transmit carrier level which is determined by the resistor (RTLA) connected between this pin and GND. The maximum level is obtained when this pin is shorted to GND (RTLA = 0). 5, 24 TEST 1, TEST 2 I/O Test Pins 1 and 2 — These test pins are for manufacturer’s use only. These pins should be left open in normal operation. 6 RxD O Receive Data Output — This pin is the receive data output. When the device is in the FSK mode, logic high on this pin indicates that the mark carrier frequency has been received from RxA, and the logic low indicates that the space carrier frequency has been received. 7 TxD I Transmit Data Input — This pin is the transmit data input. When the device is in the FSK mode, logic high on this pin generates the mark frequency at TxA1 and TxA2 output, and logic low generates the space frequency. 8 CD O Carrier Detect Output — This pin outputs at low level if a valid FSK, DTMF, or CPTD signal is received. If the pin is at high level, the receive data output pin (RxD) is internally clamped at high level to avoid erroneous output of received data caused by line noise. 9 CLKO O Clock Output — This pin provides a buffered 3.58 MHz clock output that can drive one CMOS device such as the MC74HC04. 10 X1 O Crystal Oscillator Circuit Output — A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the other end connected to X2. 11 X2 I Crystal Oscillator Circuit Input — A 3.579545 MHz ± 0.1% crystal oscillator is tied to this pin with the other end connected to X1. X2 may be driven directly from an appropriate external clock source. 12 ECLK I External Clock Input — ECLK is the input of double frequency, 7.159090 MHz ± 0.1%, of the reference clock. This pin must be connected to GND when not in use. 13 PB0 O DTMF Receive Data Parallel Output 0 (LSB) — Pins 13, 16, 17, and 18 are the DTMF receive data parallel output occurring together with the CD (Pin 8) data valid output. The outputs of these pins are valid as long as the CD pin is low. In power down modes 1 and 2, the DTMF receiver is disabled and these pins are in high impedance. 15, 28 VCC — Positive Power Supply — These are the power supply pins for the digital and the analog circuits. These pins should be decoupled to GND with 0.1 µF and 100 µF capacitors. 16, 17, 18 PB1, PB2, PB3 O DTMF Receive Data Parallel Outputs 1, 2, and 3 (MSB) — These pins are the DTMF receiver data parallel outputs. details. outputs See pin 13 for more details 19 RESET I Reset — A high to low trigger pulse applied to this pin sets all the registers in the default state. It should remain at high during normal operations. 20 SCP Tx O SCP Output Transmit — Refer to Serial Control Port (SCP Interface) for additional information. 21 SCP Rx I SCP Receive Input — Refer to Serial Control Port (SCP Interface) for additional information. 22 SCPCLK I SCP Clock — Refer to Serial Control Port (SCP Interface) for additional information. 23 SCPEN I SCP Enable — Refer to Serial Control Port (SCP Interface) for additional information. MOTOROLA Description MC145745 3 PIN DESCRIPTIONS (continued) Pin Location Symbol Type Description 25 TxA2 O Transmit Buffer Output 2 (Inverting) — This pin is the inverting output of the line driver. When VCC = 5 V, + 7 dBm (typ), differential output voltage (VTxA1 – VTxA2), can be obtained with a load of 1.2 kΩ between pins TxA1 and TxA2. In typical applications, the output level on the telephone line will be half of the differential output (refer to Application Circuit). 26 TxA1 O Transmit Buffer Output 1 (Non–Inverting) — This pin is the non–inverting output of the line driver. Refer to TxA2. 27 RxA I Receive Signal Input — This pin is the analog signal input which has 500 kΩ input resistance (typ). ABSOLUTE MAXIMUM RATINGS Rating Symbol DC Supply Voltage Value Unit VCC – 0.5 to + 7.0 V DC Input Voltage Vin – 0.5 to VCC + 0.5 V DC Output Voltage Vout – 0.5 to VCC + 0.5 V Iin ± 20 mA DC Output Current Iout ± 25 mA Power Dissipation PD 500 mW Storage Temperature Range Tstg – 65 to + 150 °C DC Input Current This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range GND (Vin or Vout) VCC. Reliability of operation is enhanced if unused logic inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). v v RECOMMENDED OPERATIONAL CONDITIONS Parameter Symbol Min Typ Max Unit VCC 3.3 5.0 5.5 V DC Input Voltage Vin 0 — VCC V DC Output Voltage Vout 0 — VCC V Crystal Oscillation Frequency fosc — 3.579545 — MHz — 7.15909 — – 30 25 + 85 °C DC Supply Voltage External Input Frequency (ECLK) Operating Temperature Range TA DC ELECTRICAL CHARACTERISTICS (VCC = + 3.3 to + 5.5 V, TA = – 30 to + 85°C) Min Typ Max Unit Input Voltage ((TxD, ECLK, RESET, R SCPCLK SCP Rx, SCPCLK, SCPEN) High Level VIH 0.7 x VCC — — V Low Level VIL — — 1.1 Output Voltage (RxD CD (RxD, CD, CLKO, CLKO PB0–3, SCP Tx) High Level VOH Vin = VIH or VIL, Iout = 20 µA VCC – 0.1 VCC – 0.01 — Low Level VOL Vin = VIH or VIL Iout = 20 µA Iout = 2 mA — — 0.01 — 0.1 0.4 Vin = VCC or GND — ± 1.0 ± 10.0 µA FSK Mode, RTLA = 0 TxA1 and TxA2 open — 7 — mA DTMF Receive Mode, no input — 9 — FSK Mode, RTLA = 0 TxA1 and TxA2 open — 6 — DTMF Receive Mode, no input — 8 — Power–Down Mode 1 — — 500 µA Power–Down Mode 2 — — 1.0 µA Characteristic Input Leakage Current (TxD, ECLK, RESET, SCP Rx, SCPCLK, SCPEN) Quiescent Supply Current VCC = 5 V VCC = 3.6 V Power–Down Supply Current MC145745 4 Symbol Iin ICC ICC ICC Conditions MOTOROLA AC ELECTRICAL CHARACTERISTICS (VCC = + 3.6 V ± 0.3 V, TA = – 30 to + 85_C) TRANSMIT CARRIER CHARACTERISTICS Characteristic V.21 Carrier Frequency Originate Mode V.21 Carrier Frequency Answer Mode V.23 Carrier Frequency Symbol Conditions Oscillation Frequency: 3 579545 MHz (X2) 3.579545 or 7.159090 MHz (ECLK) Min Typ Max Unit 974 980 986 Hz 1174 1180 1186 Mark “1” f1M Space “0” f1S Mark “1” f2M 1644 1650 1656 Space “0” f2S 1844 1850 1856 Mark “1” f1M 1294 1300 1306 Space “0” f1S 2094 2100 2106 — 4 — dBm — – 40 — dB Transmit Carrier Level VO Secondary Harmonic Level V2h Out–of–Band Level VOE Transmit Attenuator = 0 dB RTLA = 0, 0 RL = 1.2 1 2 kΩ VTxA1 – VTxA2 Refer to Figure 1 dBm TRANSMIT ATTENUATOR CHARACTERISTICS Characteristic Symbol Conditions Min Typ Max Unit 0 — 15 dB – 0.5 –1 – 1.7 — — — 0.5 1 1 dB Min Typ Max Unit 50 500 — kΩ – 48 — – 12 dBm — – 44 — dBm — – 47 — 2 — — dB CD1 = 0, CD0 = 0, CD Pin — 450 — ms CD1 = 0, CD0 = 1, CD Pin — 15 — CD1 = 1, CD0 = 0, CD Pin — 15 — CD1 = 1, CD0 = 1, CD Pin — 75 — CD1 = 0, CD0 = 0, CD Pin — 30 — CD1 = 0, CD0 = 1, CD Pin — 30 — CD1 = 1, CD0 = 0, CD Pin — 15 — CD1 = 1, CD0 = 1, CD Pin — 10 — Min Typ Max Unit — 400 — Hz Attenuation Range Attenuator Accuracy 1 – 5 dB 6 – 9 dB 10 – 15 dB RECEIVER CHARACTERISTICS (Includes Hybrid, Demodulator, and Carrier Detector) Characteristic Symbol Input Resistance RIRX Receive Carrier Amplitude Carrier Detection Threshold VIRX OFF to ON VCDON ON to OFF VCDOFF Hysteresis (VCDON – VCDOFF) Carrier Detection Timing Conditions OFF to ON ON to OFF CDA = 1.25 V fin 1 0 kHz i = 1.0 BR3 (b1) = 1 HYS TCDON TCDOFF CPTD CHARACTERISTICS Characteristic Symbol Conditions BPF Center Frequency fc BPF Pass–Band Lower Cut–Off Frequency fi – 3 dB — 330 — Hz BPF Pass–Band Upper Cut–Off Frequency fh – 3 dB — 470 — Hz CDA = 1.25 V fin i = 400 Hz BR3 (b1) = 1 — – 44 — dBm — – 47 — CPT Detection Level CPT Detection Timing MOTOROLA VTD ON VTDON VTD OFF VTDOFF TTD ON TTDON — 10 — TTD OFF TTDOFF — 25 — ms MC145745 5 DTMF TRANSMIT CHARACTERISTICS Characteristic Tone Output Level Symbol Low Group Vfl High Group Vfh High Group Pre–Emphasis PE DTMF Distortion DIST DTMF Frequency Deviation ∆fV Out–of–Band Level VOE Setup Time tosc Conditions Transmit Attenuator = 0 dB RTLA = 0 Ω fosc = 3.579545 MHz Single Tone Mode RL = 1.2 1 2 kΩ VTxA1 – VTxA2 Min Typ Max Unit — 0 — dBm — 1 — dBm 0 — 3 dB — 5 — % –1 — 1 % Refer to Figure 1 dB — 4 — ms Min Typ Max Unit 50 500 — kΩ – 48 — 0 dBm – 10 — 10 dB 1.5% + 2 Hz – 1.5% – 2Hz — — — — — — ± 3.5% CD1 = 0 , CD0 = 0 — 30 — CD1 = 0 , CD0 = 1 — 35 — CD1 = 1 , CD0 = 0 — 45 — CD1 = 0 , CD0 = 0 — 25 — CD1 = 0 , CD0 = 1 — 35 — CD1 = 1 , CD0 = 0 — 25 — Min Typ Max Unit DTMF RECEIVER CHARACTERISTICS Characteristic Symbol Conditions Input Resistance Detection Signal Level (Each Tone) BR3 = (0, 0, 1, 0) Twist (High/Low Group) Frequency Detection Band Width (Figure 3) Frequency Non–Detection Band Width (Figure 3) DTMF Detection Timing (Figure 2) OFF to ON Delay ON to OFF Delay TDVON TDVOFF ms DEMODULATOR CHARACTERISTICS Characteristic Symbol Conditions V.21 Bit Bias Receive Level = – 24 dBm S/N = 4 dB — 5 — % V.23 Bit Bias Receive Level = – 24 dBm S/N = 14 dB — 10 — % V.21 Bit Error Rate Receive Level = – 24 dBm S/N = 4 dB 511–Bit Pattern — 0.00001 — V.23 Bit Error Rate Receive Level = – 24 dBm S/N = 14 dB 511–Bit Pattern — 0.00001 — MC145745 6 MOTOROLA TRANSMIT CARRIER LEVEL (dBr) 0 3.4 k 4 k 16 k 256 k f (Hz) 0 – 25 – 15 dB/OCT. – 55 Figure 1. Out–of–Band Level Von Voff RxA ton toff CD Figure 2. FSK, DTMF, and CPT Carrier Detection Timing DETECT MINIMUM WIDTH NO–DETECT ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ – 3.5% NO–DETECT ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ + 3.5% – 1.5% – 2 Hz fo + 1.5% + 2 Hz Figure 3. DTMF Frequency Detection Bandwidth MOTOROLA MC145745 7 SCP TIMING CHARACTERISTICS Ref. No. Characteristic Min Max Unit 1 SCPEN Active Before Rising Edge of SCPCLK 50 — ns 2 SCPCLK Rising Edge Before SCPEN Active 50 — ns 3 SCP Rx Setup Time Before SCPCLK Rising Edge 35 — ns 4 SCP Rx Hold Time After SCPCLK Rising Edge 20 — ns 5 SCPCLK Period 250 — ns 6 SCPCLK Pulse Width (Low) 50 — ns 7 SCPCLK Pulse Width (High) 50 — ns 8 SCP Tx Active Delay Time 0 50 ns 9 SCPCLK Falling Edge to SCP Tx High Impedance — 30 ns 10 SCPEN Inactive Before SCPCLK Rising Edge 50 — ns 11 SCPCLK Rising Edge Before SCPEN Inactive 50 — ns 12 SCPCLK Falling Edge to SCP Tx Valid Data 0 50 ns 10 SCPEN 2 11 1 5 SCPCLK 1 2 3 4 5 6 7 7 4 8 9 6 3 SCP Rx R/W A2 A1 A0 D3 D2 12 8 SCP Tx D0 D1 9 D3 D2 D1 D0 Figure 4. Serial Control Port Timing MC145745 8 MOTOROLA SERIAL CONTROL PORT (SCP INTERFACE) DEVICE DESCRIPTION The MC145745 is a selectable modem chip compatible with V.21 (300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex asynchronous). This device includes a DTMF generator, DTMF receiver, call–progress tone detector, answer tone generator, and a receive timing control circuit. The built–in differential line driver has the capability of driving 0 dBm into a 600 Ω load with a 5.0 V single power supply. The MC145745 also includes a serial control port (SCP) that permits an MCU to exercise the built– in features. The MC145745 provides an SCP interface to access an internal byte register which controls the device operations; such as function mode, carrier detect timing, transmit/receive gain, and transmit tones. The transmit and receive amplifiers’ gain is programmable by SCP register setting (BR4). The TLA pin is also available to adjust the transmit level that is determined by the resistor (RTLA) value connected between the pin and GND. The DTMF receiver amplifier includes a built–in AGC amplifier which automatically adjusts the input amplifier gain corresponding to the amplitude of the DTMF tone input signal. The AGC dynamic range can be selected in four options. The highest received sensitivity obtained is approximately – 50 dBm when the dynamic range of the AGC amplifier is maximized. The tone generator, which can generate 16 DTMF tones, is used at the terminal for transmission of the call and control tones. In addition, a single tone can be generated for tests and other uses. Power down is amenable to software control by setting the byte register BR2. While the device is in the power down state, SCP still operates independently. There are two power down options available: power down 1 (the system clock operates alone) and power down 2 (the system clock stops). The clock generator constitutes an oscillation circuit with a 3.58 MHz crystal connected between the X1 and X2 pins. This device also has a 7.15909 MHz external clock input (ECLK), which has a clock divider circuit for providing a 3.58 MHz clock to the internal circuits. If the ECLK pin is used, the X2 pin should be held low. If the oscillation circuit (X1 and X2) is used, the ECLK pin should be held low. This device also has a clock buffer output (CLKO), which can be used for providing a 3.58 MHz clock to the external device. Table 1 shows the clock input and output relations in the different modes. Table 1. Clock Selection Truth Table Input F Function i M Mode d P Power D Down 1 P Power D Down 2 Oh M Other Mode d MOTOROLA The MC145745 is equipped with an SCP. The SCP is a full–duplex four–wire interface with control and status information passed to and from the internal register. The SCP is compatible with the Serial Peripheral Interface (SPI) of single chip MCUs used in other standard Motorola devices. The SCP consists of SCP Tx, SCP Rx, SCPCLK, and SCPEN for transmitting control data, status data, and DTMF receive data between the MCU and the MC145745. The SCPCLK determines the transmission and reception data rates, and the SCPEN governs when the data transaction is to take place. The operation/configuration of the MC145745 is programmed by setting the state of the internal register bit. The control, status, and data information resides in 4–bit wide registers which are accessed via the 8–bit SCP bus transaction. The first four bits of the 8–bit bus transaction are the read/ write direction and the register address. The next four bits are the data written to or read from the internal registers. The SCP interface is independent of the 3.58 MHz master clock. It runs by using SCPCLK as the synchronizing signal. SCP TRANSACTION The SCP interface includes both read and write capabilities, which together comprise the SCP transaction. These SCP transaction functionalities are described below. SCP Read The SCP read action transaction is shown in Figure 5. During the SCP read action, the SCPEN pin must be in the low position. After SCPEN high goes low, then at the first four SCPCLK rising edges, Read/Write (R/W) bit and three address bits (A0 – A2) are shifted into the intermediate buffer register. If the read action is to be performed, the R/W bit must be at 1. And then, at the following four SCPCLK falling edges, the 4–bit chosen register data is shifted out on SCP Tx. SCPEN must be restored to high after this transaction, before another falling edge of SCPCLK is encountered. While SCP Tx is in output mode, SCP Rx is disregarded. Also, whenever SCP Tx is not transmitting data, a high impedance condition is maintained. SCP Write Output ECLK (Pin 12) X2 (Pin 11) CLKO (Pin 9) 0 fxtal fxtal fext 0 fext/2 0 X 0 fext 0 0 0 fxtal fxtal fext 0 fext/2 The SCP write action transaction is shown in Figure 6. During the SCP write action, the SCPEN pin must be in the low position. After SCPEN high goes low, then at the first four SCPCLK rising edges, R/W and three address bits (A0 – A2) are shifted into the intermediate buffer register. If the write action is to be performed, the R/W bit must be at 0. And then, at the following four SCPCLK rising edges, the 4–bit data is shifted in from SCP Rx and written into the chosen register. During the write operation, SCP Tx is in high impedance. If the chosen register and/or the chosen bit are “read only,” the write action to it has no effect. MC145745 9 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ SCPEN SCPCLK SCP Rx DON’T CARE R/W A2 A1 A0 DON’T CARE SCP Tx D3 HIGH IMPEDANCE D2 D1 D0 Figure 5. Serial Control Port Read Operation SCPEN SCPCLK SCP Rx SCP Tx ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ R/W ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ DON’T CARE A2 A1 A0 D3 D2 D1 D0 DON’T CARE HIGH IMPEDANCE Figure 6. Serial Control Port Write Operation DESCRIPTION OF THE SCP TERMINAL The SCP bus is made up of the following four pins. SCP Tx (Pin 20) The SCP Tx pin outputs the control, status, and data information from the 4–bit wide register. During the read action transaction, a R/W bit and the three address bits are shifted in from SCP Rx at four SCPCLK rising edges, subsequent to SCPEN going low. After this, if a read operation is selected, SCP Tx comes out of the high impedance state at the first falling edge of SCPCLK, and outputs the first bit (MSB) of the chosen register. The remaining three bits of the chosen register are shifted out from SCP Tx at the following three SCPCLK falling edges. After the last bit (LSB) is shifted out, SCPEN must return to high. Then SCP Tx returns to the high impedance condition. SCP Rx (Pin 21) The SCP Rx pin is used to input control and data information into the 4–bit wide register. Data is shifted in from SCP Rx at SCPCLK rising edge, while SCPEN is low. The first bit is the R/W bit (1 = read, 0 = write), and the next three MC145745 10 bits address one of seven byte–registers. The address bits are shifted in MSB first. If the write action is chosen, the 4–bit data is shifted in from SCP Rx at the next four SCPCLK rising edges. If the read action is chosen, 4–bit data in the selected register is shifted out on SCP Tx. SCP Rx is ignored while SCPEN is high. SCPCLK (Pin 22) The SCPCLK pin is an input of standard clock for handshaking between SCP and MCU. After SCPEN comes low and the SCP transaction occurs, data is shifted from SCP Rx into the device at the rising edge of SCPCLK, and is shifted out on SCP Tx at the falling edge of SCPCLK. When SCPEN is high, SCPCLK is ignored (i.e., it may be continuous or it can operate in the burst mode). SCPEN (Pin 23) When the SCPEN pin is held low, the SCP transaction is enabled and control, status, and data information is transferred. If SCPEN is returned to high, the SCP action in progress is aborted, and the SCP Tx pin enters a high impedance condition. MOTOROLA SCP REGISTER MAP The MC145745 register map is shown in Table 2. Seven of the 4–bit wide byte registers (BR) are provided in the register block. According to these published specifications, BR signifies each register and the address of SCP data. R/W is the read/write register, and RO is read only. If there is a high to low pulse on the RESET pin or the power supply turns off, this register returns to the default state. The default condition that occurs after a power reset is as follows. BR0 V.23 Receive, Transmit Enable BR1 DTMF CDON = 30 ms, DTMF CDOFF = 25 ms FSK CDON = 450 ms, FSK CDOFF = 30 ms FSK Mode BR2 BR3 BR4 AGC Range = Maximum, Carrier Detect Level: High Transmission Gain = Maximum BR5 DTMF Transmission: 941 Hz + 1633 Hz BR6 DTMF Reception: Unknown Table 2. SCP Register Map Register b3 (Bit 3: MSB) BR0 (R/W) b2 (Bit 2) b1 (Bit1) b0 (Bit 0: LSB) Modem Choice FSK Channel Transmission Enable 0 V.23 V.21: Answer V.23: Receive Enable 1 V.21 V.21: Originate V.23: Transmit Disable FSK CDT2 FSK CDT1 DTMF CDT2 DTMF CDT1 TCDON b3=0, b2=0 : 450 ms b3=0, b2=1 : 15 ms b3=1, b2=0 : 15 ms b3=1, b2=1 : 75 ms TCDOFF b3=0, b2=0 : 30 ms b3=0, b2=1 : 30 ms b3=1, b2=0 : 15 ms b3=1, b2=1 : 10 ms TCDON b1=0, b0=0 : 30 ms b1=0, b0=1 : 35 ms b1=1, b0=0 : 45 ms TCDOFF b1=0, b0=0 : 25 ms b1=0, b0=1 : 35 ms b1=1, b0=0 : 25 ms BR2 (R/W) (see Table 3) Function Mode 4 Function Mode 3 Function Mode 2 Function Mode 1 BR3 (R/W) AGC Range 2 AGC Range 1 Carrier Detect Level 1 Test BR1 (R/W) 0 B3=0, b2=0 : – 5 to + 20 dB B3=0, b2=1 : – 5 to + 15 dB High Level (Set when VCC = 5 V) Normal 1 b3=1, b2=0 : – 5 to + 10 dB b3=1, b2=1 : – 5 to + 5 dB Low Level (Set when VCC = 3.6 V) Test Mode BR4 (R/W) (see Table 4) Transmission Gain 4 Transmission Gain 3 Transmission Gain 2 Transmission Gain 1 BR5 (R/W) (see Table 5) Tone Transmission 4 Tone Transmission 3 Tone Transmission 2 Tone Transmission 1 BR6 (RO) (see Table 5) DTMF Reception 4 DTMF Reception 3 DTMF Reception 2 DTMF Reception 1 NOTES: 1. BR0 (b0) is a non–working bit. 2. DTMF Loopback data is entered into BR5 and output from the parallel port. MOTOROLA MC145745 11 Table 3. Function Mode Setup Register b3 b2 b1 b0 Comments FSK Mode 0 0 0 0 The device works as one of two FSK modes, V.21/V.23. FSK Loopback 0 0 0 1 The FSK modulator is internally connected to the FSK demodulator. CPT Detect Mode 0 0 1 0 The device works as the 400 Hz tone detector. Answer Tone Transmission Mode 0 0 1 1 The device works as the 2100 Hz answer tone generator. DTMF Transmission Mode 0 1 0 0 The device works as the DTMF generator. The receiver is disabled. Single Tone Transmission Mode 0 1 0 1 The device outputs one of the eight tones used for DTMF. Power Down 1 0 1 1 0 Whole circuits except for the SCP and the oscillator circuit are disabled. Power Down 2 0 1 1 1 Whole circuits except for the SCP are disabled. DTMF Reception Mode 1 0 0 0 The device works as the DTMF receiver. The received DTMF tone is demodulated to the 4–bit code, then output from the SCP interface and/or the parallel port. DTMF Loopback 1 0 0 1 The DTMF generator is internally connected to the DTMF receiver, then the DTMF code written in BR5 is loopbacked to the parallel port (PB0 – PB3). Table 4. Transmission Attenuator Range MC145745 12 Transmission Attenuator Range b3 b2 b1 b0 0 dB 0 0 0 0 – 1 dB 0 0 0 1 – 2 dB 0 0 1 0 – 3 dB 0 0 1 1 – 4 dB 0 1 0 0 – 5 dB 0 1 0 1 – 6 dB 0 1 1 0 – 7 dB 0 1 1 1 – 8 dB 1 0 0 0 – 9 dB 1 0 0 1 – 10 dB 1 0 1 0 – 11 dB 1 0 1 1 – 12 dB 1 1 0 0 – 13 dB 1 1 0 1 – 14 dB 1 1 1 0 – 15 dB 1 1 1 1 MOTOROLA Table 5. Tone Generator/Receiver Data BR5/BR6 Setting or Data Output Tone Generator Tone Receiver MOTOROLA K Key Input Low Group Frequency (Hz) High Group Frequency (Hz) Single Si l Tone T (Hz) b3 b2 b1 b0 D 941 1633 941 0 0 0 0 1 697 1209 697 0 0 0 1 2 697 1336 697 0 0 1 0 3 697 1477 697 0 0 1 1 4 770 1209 770 0 1 0 0 5 770 1336 770 0 1 0 1 6 770 1477 770 0 1 1 0 7 852 1209 852 0 1 1 1 8 852 1336 1336 1 0 0 0 9 852 1477 1477 1 0 0 1 0 941 1336 1336 1 0 1 0 * 941 1209 1209 1 0 1 1 # 941 1477 1477 1 1 0 0 A 697 1633 1633 1 1 0 1 B 770 1633 1633 1 1 1 0 C 852 1633 1633 1 1 1 1 MC145745 13 10 Ω 600 : 600 TxA1 TxD TxA2 CD I/O PORT * 600 Ω RxD MCU TIP SCPEN RxA SCPCLK CDA SCP Rx TLA RING 0.1 µF SCP Tx 4 PB0 – PB3 TEST1 +5V RESET TEST2 Vref CLKO ECLK 100 µF 0.1 µF MC145745 X1 VCC X2 GND 3.579545 MHz * +5V 100 µF LINE PROTECTION CIRCUIT SYSTEM GROUND 0.1 µF REFERENCE ANALOG GROUND Figure 7. Application Circuit MC145745 14 MOTOROLA PACKAGE DIMENSIONS FW SUFFIX SOIC CASE 751M–01 VIEW AB A –Y– 28 15 B –Z– 1 E V X 45_ " 5_ 14 28X D 0.25 (0.010) M T Z 0.18 (0.007) M T S Y 0.18 (0.007) S M T Y S Z S VIEW AB CL NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.65 (0.026). MILLIMETERS MIN MAX 17.80 18.03 7.40 7.62 ––– 2.65 2.25 2.45 0.35 0.51 10.00 10.60 0.40 0.70 1.27 BSC 0.10 0.25 0.635 BSC ––– 8_ 0.25 0.75 0.05 0.20 1.40 REF DIM A B C C1 D E F G J L θ V W X INCHES MIN MAX 0.701 0.710 0.291 0.300 ––– 0.104 0.090 0.096 0.014 0.020 0.394 0.414 0.016 0.028 0.050 BSC 0.004 0.010 0.025 BSC ––– 8_ 0.010 0.030 0.002 0.008 0.055 REF 0.10 (0.004) T C J C1 –T– SEATING PLANE W 4X L 24X G W REF F θ Z MOTOROLA MC145745 15 Motorola reserves the right to make changes without further notice to any products herein. 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