TI1 MSP430FR2032IG56R Mixed-signal microcontroller Datasheet

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MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
MSP430FR203x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16 MHz
– Wide Supply Voltage Range From 1.8 V to
3.6 V
• Optimized Low-Power Modes (at 3 V)
– Active: 126 µA/MHz
– Standby
• LPM3.5 With VLO: 0.4 µA
• Real-Time Clock (RTC) Counter (LPM3.5
With 32768-Hz Crystal): 0.77 µA
– Shutdown (LPM4.5): 15 nA
• Low-Power Ferroelectric RAM (FRAM)
– Up to 15.5KB of Nonvolatile Memory
– Built-In Error Correction Code (ECC)
– Configurable Write Protection
– Unified Memory of Program, Constants, and
Storage
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– IR Modulation Logic
– Two 16-Bit Timers With Three Capture/Compare
Registers Each (Timer_A3)
– One 16-Bit Counter-Only RTC Counter
– 16-Bit Cyclic Redundancy Check (CRC)
• Enhanced Serial Communications
– Enhanced USCI A (eUSCI_A) Supports UART,
IrDA, and SPI
– Enhanced USCI B (eUSCI_B) Supports SPI and
I2C
• High-Performance Analog
– 10-Channel 10-Bit Analog-to-Digital Converter
(ADC)
• Internal 1.5-V Reference
• Sample-and-Hold 200 ksps
1.2
•
•
•
•
• Clock System (CS)
– On-Chip 32-kHz RC Oscillator (REFO)
– On-Chip 16-MHz Digitally Controlled Oscillator
(DCO) With Frequency Locked Loop (FLL)
• ±1% Accuracy With On-Chip Reference at
Room Temperature
– On-Chip Very Low-Frequency 10-kHz Oscillator
(VLO)
– On-Chip High-Frequency Modulation Oscillator
(MODOSC)
– External 32-kHz Crystal Oscillator (XT1)
– Programmable MCLK Prescalar of 1 to 128
– SMCLK Derived From MCLK With
Programmable Prescalar of 1, 2, 4, or 8
• General Input/Output and Pin Functionality
– Total 60 I/Os on 64-Pin Package
– 16 Interrupt Pins (P1 and P2) Can Wake up
MCU From LPMs
– All I/Os are Capacitive Touch I/Os
• Development Tools and Software
– Free Professional Development Environments
• Family Members (Also See Section 3)
– MSP430FR2033: 15KB of Program FRAM +
512B of Information FRAM + 2KB of RAM
– MSP430FR2032: 8KB of Program FRAM +
512B of Information FRAM + 1KB of RAM
• Package Options
– 64 Pin: LQFP (PM)
– 56 Pin: TSSOP (G56)
– 48 Pin: TSSOP (G48)
• For Complete Module Descriptions, See the
MSP430FR4xx and MSP430FR2xx Family User's
Guide (SLAU445)
Applications
Smoke or Fire Detectors
Glass Breakage Detectors
Industrial Sensor Management
System Supervisor, Low-Power Coprocessors
•
•
•
Temperature Sensors or Controllers
Data Storage, Data Integration
Human Machine Interface (HMI) Controllers
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
1.3
www.ti.com
Description
The TI MSP430™ family of low-power microcontrollers consists of several devices that feature different
sets of peripherals targeted for various applications. The architecture, combined with extensive low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The DCO allows the device to wake up from low-power modes to active mode
in less than 10 µs.
Device Information (1)
PART NUMBER
MSP430FR2033IPM
LQFP (64)
10 mm × 10 mm
MSP430FR2033IG56
TSSOP (56)
14.0 mm × 6.1 mm
MSP430FR2033IG48
TSSOP (48)
12.5 mm × 6.1 mm
MSP430FR2032IPM
LQFP (64)
10 mm × 10 mm
MSP430FR2032IG56
TSSOP (56)
14.0 mm × 6.1 mm
MSP430FR2032IG48
TSSOP (48)
12.5 mm × 6.1 mm
(1)
(2)
2
BODY SIZE (2)
PACKAGE
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2014–2015, Texas Instruments Incorporated
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1.4
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
P1.x/P2.x
XOUT
XIN
Clock
System
Control
Power
Management
Module
DVSS
P5.x/P6.x
P7.x/P8.x
Capacitive Touch I/O
XT1
DVCC
P3.x/P4.x
ADC
FRAM
RAM
Up to 10-ch
Single-end
10-bit
200ksps
15KB+512B
8KB+512B
2KB
1KB
I/O Ports
P1/P2
2×8 IOs
Interrupt
& Wakeup
PA
1×16 IOs
CRC16
TA0
TA1
eUSCI_A0
16-bit
Cyclic
Redundancy
Check
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
(UART,
IrDA, SPI)
RST/NMI
I/O Ports
P3/P4
2×8 IOs
I/O Ports
P5/P6
2×8 IOs
PB
1×16 IOs
PC
1×16 IOs
eUSCI_B0
RTC
Counter
I/O Ports
P7/P8
1×8 IOs
1×4 IOs
PD
1×12 IOs
MAB
16-MHZ CPU
inc.
16 Registers
MDB
EEM
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
SYS
JTAG
SBW
•
•
•
•
•
Watchdog
(SPI, I2C)
16-bit
Real-Time
Clock
LPM3.5 Domain
Figure 1-1. Functional Block Diagram
The device has one main power pair of DVCC and DVSS that supplies both digital and analog
modules. Recommended bypass and decouple capacitors are 4.7 µF to 10 µF and 0.1 µF,
respectively, with ±5% accuracy.
P1 and P2 feature the pin-interrupt function and can wake the MCU from LPM3.5.
Each Timer_A3 has three CC registers, but only the CCR1 and CCR2 are externally connected. CCR0
registers can only be used for internal period timing and interrupt generation.
In LPM3.5, the RTC counter can be functional while the remaining peripherals are off.
Not all I/Os are bonded in TSSOP-56 and TSSOP-48 packages (refer to Table 4-1). All I/Os can be
configured as Capacitive Touch I/Os.
Copyright © 2014–2015, Texas Instruments Incorporated
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Device Overview
3
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
Device Overview ......................................... 1
5.11
Thermal Characteristics ............................. 17
1.1
Features .............................................. 1
5.12
Timing and Switching Characteristics ............... 18
1.2
Applications ........................................... 1
1.3
Description ............................................ 2
6.1
CPU
1.4
Functional Block Diagram ............................ 3
6.2
Operating Modes .................................... 32
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
6.3
Interrupt Vector Addresses.......................... 33
6.4
Bootstrap Loader (BSL) ............................. 34
6.5
JTAG Standard Interface............................ 34
4.1
Pin Diagrams ......................................... 6
6.6
Spy-Bi-Wire Interface (SBW)........................ 35
4.2
Signal Descriptions ................................... 9
6.7
FRAM................................................ 35
4.3
Pin Multiplexing
6.8
Memory Protection .................................. 35
4.4
Connection of Unused Pins ......................... 12
.....................................
6
12
Specifications ........................................... 13
5.1
Absolute Maximum Ratings ......................... 13
5.2
ESD Ratings
........................................
Recommended Operating Conditions ...............
5.3
5.4
13
13
7
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 14
5.5
5.6
5.7
5.8
5.9
5.10
Active Mode Supply Current Per MHz ..............
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current..........................
Low-Power Mode LPM3, LPM4 Supply Currents
(Into VCC) Excluding External Current ..............
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
Typical Characteristics - Current Consumption Per
Module ..............................................
Detailed Description ................................... 32
..........................................
...........................
6.11 Memory ..............................................
6.12 Identification .........................................
Applications, Implementation, and Layout........
7.1
Device Connection and Layout Fundamentals ......
Peripherals
36
6.10
Device Descriptors (TLV)
60
14
8
15
15
16
17
9
32
6.9
7.2
14
.................................................
61
68
69
69
Peripheral- and Interface-Specific Design
Information .......................................... 72
Device and Documentation Support ............... 74
8.1
Device Support ...................................... 74
8.2
Documentation Support ............................. 76
8.3
Trademarks.......................................... 77
8.4
Electrostatic Discharge Caution ..................... 77
8.5
Glossary ............................................. 77
Mechanical Packaging and Orderable
Information .............................................. 78
9.1
Packaging Information
..............................
78
2 Revision History
Changes from November 1, 2014 to August 14, 2015
•
•
•
•
•
•
•
•
•
•
•
•
•
4
Page
Corrected "10-BIT ADC CHANNELS" column for MSP430FR2032IPM in Table 3-1, Device Comparison .............. 5
Added Tstg MIN and MAX values .................................................................................................. 13
Added Section 5.2, ESD Ratings.................................................................................................. 13
Changed all graphs in Section 5.9, Typical Characteristics, Low-Power Mode Supply Currents, for new
measurements ...................................................................................................................... 16
Added VREF, 1.2V parameter to Table 5-1, PMM, SVS and BOR ............................................................... 18
Changed tSTE,LEAD MIN value at 2 V from 40 ns to 50 ns ...................................................................... 26
Changed tSTE,LEAD MIN value at 3 V from 24 ns to 45 ns ...................................................................... 26
Changed tVALID,SO MAX value at 2 V from 55 ns to 65 ns ...................................................................... 26
Changed tVALID,SO MAX value at 3 V from 30 ns to 40 ns ...................................................................... 26
Changed fADCOSC TYP value from 4.5 MHz to 5.0 MHz ........................................................................ 29
In Table 6-1, Operating Modes, changed the entry for "Power Consumption at 25°C, 3 V" in AM from
100 µA/MHz to 126 µA/MHz ....................................................................................................... 32
In Table 6-1, Operating Modes, added "with RTC only" to the entry for "Power Consumption at 25°C, 3 V" in
LPM3.5 ............................................................................................................................... 32
In Table 6-2, Interrupt Sources, Flags, and Vectors, removed "FRAM access time error" (ACCTEIFG) from the
"System NMI" row .................................................................................................................. 33
Revision History
Copyright © 2014–2015, Texas Instruments Incorporated
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Product Folder Links: MSP430FR2033 MSP430FR2032
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SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison (1) (2)
DEVICE
PROGRAM
FRAM +
INFORMATION
FRAM (BYTES)
SRAM
(BYTES)
TA0, TA1
eUSCI_A
eUSCI_B
10-BIT ADC
CHANNELS
I/O
PACKAGE
TYPE
MSP430FR2033IPM
15360 + 512
2048
3 × CCR (3)
1
1
10
60
PM
(LQFP64)
MSP430FR2033IG56
15360 + 512
2048
3 × CCR (3)
1
1
8
52
G56
(TSSOP56)
MSP430FR2033IG48
15360 + 512
2048
3 × CCR (3)
1
1
8
44
G48
(TSSOP48)
MSP430FR2032IPM
8192 + 512
1024
3 × CCR (3)
1
1
10
60
PM
(LQFP64)
MSP430FR2032IG56
8192 + 512
1024
3 × CCR (3)
1
1
8
52
G56
(TSSOP56)
MSP430FR2032IG48
8192 + 512
1024
3 × CCR (3)
1
1
8
44
G48
(TSSOP48)
(1)
(2)
(3)
For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website
at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
Copyright © 2014–2015, Texas Instruments Incorporated
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Device Comparison
5
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Figure 4-1 shows the 64-pin PM package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
P5.7
P5.6
P5.5
P5.4
P5.3/UCB0SOMI/UCB0SCL
P5.2/UCB0SIMO/UCB0SDA
P5.1/UCB0CLK
P5.0/UCB0STE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P8.3/TA1.2
P8.2/TA1CLK
P8.1/ACLK/A9
P8.0/SMCLK/A8
Figure 4-1. 64-Pin PM (LQFP) Designation (Top View)
6
Terminal Configuration and Functions
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SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Figure 4-2 shows the 56-pin G56 package.
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P8.3/TA1.2
P8.2/TA1CLK
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P5.0/UCB0STE
P5.1/UCB0CLK
P5.2/UCB0SIMO/UCB0SDA
P5.3/UCB0SOMI/UCB0SCL
P5.4
P5.5
Figure 4-2. 56-Pin DGG (TSSOP) Designation (Top View)
Terminal Configuration and Functions
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Figure 4-3 shows the 48-pin G48 package.
P3.1
P3.0
P7.3
P7.2
P7.1
P7.0
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P6.0
P6.1
P6.2
P6.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P5.0/UCB0STE
P5.1/UCB0CLK
P5.2/UCB0SIMO/UCB0SDA
P5.3/UCB0SOMI/UCB0SCL
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
Figure 4-3. 48-Pin DGG (TSSOP) Designation (Top View)
8
Terminal Configuration and Functions
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4.2
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NAME
PACKAGE SUFFIX
I/O
DESCRIPTION
PM
G56
G48
P4.7
1
7
7
I/O
General-purpose I/O
P4.6
2
8
8
I/O
General-purpose I/O
P4.5
3
9
9
I/O
General-purpose I/O
P4.4
4
10
10
I/O
General-purpose I/O
P4.3
5
11
11
I/O
General-purpose I/O
P4.2/XOUT
6
12
12
I/O
General-purpose I/O
Output terminal for crystal oscillator
General-purpose I/O
P4.1/XIN
7
13
13
I/O
DVSS
8
14
14
Power ground
DVCC
9
15
15
Power supply
Input terminal for crystal oscillator
Reset input active low
RST/NMI/SBWTDIO
10
16
16
I/O
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
Test Mode pin – selected digital I/O on JTAG pins
TEST/SBWTCK
11
17
17
I
Spy-Bi-Wire input clock
General-purpose I/O
P4.0/TA1.1
12
18
18
I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
General-purpose I/O
P8.3/TA1.2 (1)
13
19
I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
P8.2/TA1CLK (1)
General-purpose I/O
14
20
I/O
Timer clock input TACLK for TA1
General-purpose I/O
P8.1/ACLK/A9
(1)
15
I/O
ACLK output
Analog input A9
General-purpose I/O
P8.0/SMCLK/A8 (1)
16
I/O
SMCLK output
Analog input A8
General-purpose I/O (2)
P1.7/TA0.1/TDO/A7 (2)
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
17
21
19
I/O
Test data output
Analog input A7
General-purpose I/O (2)
P1.6/TA0.2/TDI/TCLK/A6 (2)
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
18
22
20
I/O
Test data input or test clock input
Analog input A6
(1)
(2)
Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
PACKAGE SUFFIX
NAME
PM
G56
I/O
DESCRIPTION
G48
General-purpose I/O (2)
Timer clock input TACLK for TA0
P1.5/TA0CLK/TMS/A5 (2)
19
23
21
I/O
Test mode select
Analog input A5
General-purpose I/O (2)
MCLK output
P1.4/MCLK/TCK/A4/VREF+
(2)
20
24
22
I/O
Test clock
Analog input A4
Output of positive reference voltage with ground as reference
General-purpose I/O
P1.3/UCA0STE/A3
21
25
23
I/O
eUSCI_A0 SPI slave transmit enable
Analog input A3
General-purpose I/O
P1.2/UCA0CLK/A2
22
26
24
I/O
eUSCI_A0 SPI clock input/output
Analog input A2
General-purpose I/O
P1.1/UCA0RXD/UCA0SOMI/
A1/Veref+
eUSCI_A0 UART receive data
23
27
25
I/O
eUSCI_A0 SPI slave out/master in
Analog input A1, and ADC positive reference
General-purpose I/O
P1.0/UCA0TXD/UCA0SIMO/
A0/Veref-
eUSCI_A0 UART transmit data
24
28
26
I/O
eUSCI_A0 SPI slave in/master out
Analog input A0, and ADC negative reference
(1)
25
I/O
General-purpose I/O
P5.6 (1)
26
I/O
General-purpose I/O
P5.5 (1)
27
29
I/O
General-purpose I/O
P5.4 (1)
28
30
I/O
General-purpose I/O
P5.3/UCB0SOMI/UCB0SCL
29
31
27
I/O
P5.2/UCB0SIMO/UCB0SDA
30
32
28
I/O
P5.1/UCB0CLK
31
33
29
I/O
P5.7
General-purpose I/O
eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
General-purpose I/O
eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
General-purpose I/O
eUSCI_B0 clock input/output
General-purpose I/O
P5.0/UCB0STE
32
34
30
I/O
P2.7
33
35
31
I/O
General-purpose I/O
P2.6
34
36
32
I/O
General-purpose I/O
P2.5
35
37
33
I/O
General-purpose I/O
P2.4
36
38
34
I/O
General-purpose I/O
P2.3
37
39
35
I/O
General-purpose I/O
P2.2
38
40
36
I/O
General-purpose I/O
P2.1
39
41
37
I/O
General-purpose I/O
eUSCI_B0 slave transmit enable
10
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
PACKAGE SUFFIX
PM
G56
G48
P2.0
40
42
38
P6.7 (1)
41
(1)
42
P6.5 (1)
43
43
P6.4 (1)
44
44
P6.3
45
45
P6.2
46
46
P6.1
47
P6.0
I/O
DESCRIPTION
I/O
General-purpose I/O
I/O
General-purpose I/O
I/O
General-purpose I/O
I/O
General-purpose I/O
I/O
General-purpose I/O
39
I/O
General-purpose I/O
40
I/O
General-purpose I/O
47
41
I/O
General-purpose I/O
48
48
42
I/O
General-purpose I/O
P3.7
49
49
43
I/O
General-purpose I/O
P3.6
50
50
44
I/O
General-purpose I/O
P3.5
51
51
45
I/O
General-purpose I/O
P3.4
52
52
46
I/O
General-purpose I/O
P3.3
53
53
47
I/O
General-purpose I/O
P3.2
54
54
48
I/O
General-purpose I/O
P3.1
55
55
1
I/O
General-purpose I/O
P3.0
56
56
2
I/O
General-purpose I/O
P7.7 (1)
57
I/O
General-purpose I/O
P7.6 (1)
58
I/O
General-purpose I/O
(1)
59
1
I/O
General-purpose I/O
P7.4 (1)
60
2
I/O
General-purpose I/O
P7.3
61
3
3
I/O
General-purpose I/O
P7.2
62
4
4
I/O
General-purpose I/O
P7.1
63
5
5
I/O
General-purpose I/O
P7.0
64
6
6
I/O
General-purpose I/O
P6.6
P7.5
Terminal Configuration and Functions
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Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.9.12.
4.4
Connection of Unused Pins
Table 4-2 shows the correct termination of unused pins.
Table 4-2. Connection of Unused Pins (1)
(1)
(2)
12
PIN
POTENTIAL
Px.0 to Px.7
Open
Set to port function, output direction (PxDIR.n = 1)
COMMENT
RST/NMI
DVCC
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown (2)
TEST
Open
This pin always has an internal pulldown enabled.
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage applied at DVCC pin to VSS
–0.3
4.1
UNIT
V
Voltage applied to any pin (2)
–0.3
VCC + 0.3
(4.1 Maximum)
V
Diode current at any device pin
±2
mA
Maximum junction temperature, TJ
85
°C
125
°C
Storage temperature, Tstg
(1)
(2)
(3)
(3)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage applied at DVCC pin (1) (2) (3)
VSS
Supply voltage applied at DVSS pin
TA
Operating free-air temperature
–40
TJ
Operating junction temperature
–40
CDVCC
Recommended capacitor at DVCC (4)
4.7
fSYSTEM
Processor frequency (maximum MCLK frequency)
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
NOM
1.8
MAX
V
85
°C
0
(3) (5)
UNIT
3.6
V
85
10
°C
µF
No FRAM wait states
(NWAITSx = 0)
0
8
With FRAM wait states
(NWAITSx = 1) (6)
0
16 (7)
MHz
40
kHz
16 (7)
MHz
Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the SVS levels. Refer to the SVS threshold parameters in Table 5-1.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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Active Mode Supply Current Into VCC Excluding External Current (1)
5.4
FREQUENCY (fMCLK = fSMCLK)
EXECUTION
MEMORY
PARAMETER
TEST
CONDITIONS
1 MHz
0 WAIT STATES
(NWAITSx = 0)
TYP
IAM,
FRAM(0%)
IAM,
FRAM(100%)
IAM,
RAM
(1)
(2)
(2)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
MAX
TYP
16 MHz
1 WAIT STATE
(NWAITSx = 1)
MAX
TYP
MAX
3700
FRAM
0% cache hit ratio
3 V, 25°C
504
2874
3156
3 V, 85°C
516
2919
3205
FRAM
100% cache hit ratio
3 V, 25°C
209
633
1056
3 V, 85°C
217
647
1074
RAM
3 V, 25°C
231
809
1450
UNIT
µA
1298
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32786 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5
Active Mode Supply Current Per MHz
VCC = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
dIAM,FRAM/df
(1)
Active mode current consumption per MHz,
execution from FRAM, no wait states (1)
TEST CONDITIONS
TYP
UNIT
((IAM, 75% cache hit rate at 8 MHz) –
(IAM, 75% cache hit rate at 1 MHz))
/ 7 MHz
126
µA/MHz
All peripherals are turned on in default settings.
5.6
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3 V, TA = 25°C (unless otherwise noted) (1) (2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
(1)
(2)
14
Low-power mode LPM0 supply current
8 MHz
MAX
TYP
16 MHz
MAX
TYP
2V
158
307
415
3V
169
318
427
UNIT
MAX
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32786 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
Specifications
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5.7
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM3,XT1
Low-power mode 3, includes SVS (2) (3) (4)
ILPM3,VLO
Low-power mode 3, VLO, excludes SVS (5)
ILPM3,
Low-power mode 3, RTC, excludes SVS (6)
ILPM4,
RTC
SVS
ILPM4
(1)
(2)
(3)
(4)
(5)
(6)
VCC
Low-power mode 4, includes SVS
Low-power mode 4, excludes SVS
–40°C
TYP
25°C
MAX
(1)
85°C
TYP
MAX
TYP
1.99
3.00
3V
1.13
1.31
2V
1.06
1.21
3V
0.92
1.00
2V
0.86
1.00
2.75
3V
1.08
1.25
3.04
3V
0.65
0.75
1.88
2V
0.63
0.73
1.85
3V
0.51
0.58
1.51
2V
0.50
0.57
1.49
MAX
µA
2.94
1.75
UNIT
2.89
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
Not applicable for devices with HF crystal oscillator only.
Characterized with a GOLLEDGE MS1V-TK/I_32.768KHZ crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
RTC periodically wakes up every second with external 32768-Hz as source.
5.8
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ILPM3.5,
XT1
Low-power mode 3.5, includes SVS (1) (2)
(also see Figure 5-2)
ILPM4.5,
SVS
Low-power mode 4.5, includes SVS (4)
ILPM4.5
(1)
(2)
(3)
(4)
(5)
Low-power mode 4.5, excludes SVS (5)
VCC
(3)
–40°C
TYP
MAX
25°C
85°C
TYP
MAX
TYP
MAX
1.25
1.06
2.06
3V
0.71
0.77
2V
0.66
0.70
3V
0.23
0.25
2V
0.20
0.20
3V
0.010
0.015
2V
0.008
0.013
0.95
0.375
0.32
0.43
0.24
0.070
0.073
0.140
0.060
UNIT
µA
µA
µA
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
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Typical Characteristics, Low-Power Mode Supply Currents
5
3
LPM3.5 Supply Current (µA)
LPM3 Supply Current (µA)
4.5
4
3.5
3
2.5
2
1.5
1
0.5
2.5
2
1.5
1
0.5
0
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
-40
-30
-20
-10
0
Temperature (°C)
LPM3
SVS disabled
10
20
30
40
50
60
70
80
Temperature (°C)
DVCC = 3 V
RTC counter on
LPM3.5
12.5-pF crystal on XT1
Figure 5-1. LPM3 Supply Current vs Temperature
DVCC = 3 V
SVS enabled
Figure 5-2. LPM3.5 Supply Current vs Temperature
LPM4.5 Supply Current (µA)
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (°C)
LPM4.5
DVCC = 3 V
SVS enabled
Figure 5-3. LPM4.5 Supply Current vs Temperature
16
Specifications
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5.10 Typical Characteristics - Current Consumption Per Module
MODULE
TEST CONDITIONS
REFERENCE CLOCK
Timer_A
TYP
UNIT
Module input clock
5
µA/MHz
eUSCI_A
UART mode
Module input clock
7
µA/MHz
eUSCI_A
SPI mode
Module input clock
5
µA/MHz
eUSCI_B
SPI mode
Module input clock
5
µA/MHz
Module input clock
5
µA/MHz
32 kHz
85
nA
MCLK
8.5
µA/MHz
eUSCI_B
2
I C mode, 100 kbaud
RTC
CRC
From start to end of operation
5.11 Thermal Characteristics
PARAMETERS
θJA
Junction-to-ambient thermal resistance, still air (1)
θJC, (TOP) Junction-to-case (top) thermal resistance (2)
(3)
VALUE
UNIT
61.7
°C/W
25.4
°C/W
θJB
Junction-to-board thermal resistance
32.7
°C/W
ΨJB
Junction-to-board thermal characterization parameter
32.4
°C/W
ΨJT
Junction-to-top thermal characterization parameter
2.5
°C/W
62.4
°C/W
18.7
°C/W
31.4
°C/W
θJA
Junction-to-ambient thermal resistance, still air(
LQFP-64 (PM)
(1)
θJC, (TOP) Junction-to-case (top) thermal resistance (2)
θJB
Junction-to-board thermal resistance (3)
ΨJB
Junction-to-board thermal characterization parameter
31.1
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.8
°C/W
θJA
Junction-to-ambient thermal resistance, still air( (1)
68.9
°C.W
23
°C/W
TSSOP-56 (DGG56)
θJC, (TOP) Junction-to-case (top) thermal resistance (2)
(3)
θJB
Junction-to-board thermal resistance
35.8
°C/W
ΨJB
Junction-to-board thermal characterization parameter
35.3
°C/W
ΨJT
Junction-to-top thermal characterization parameter
1.1
°C/W
(1)
(2)
(3)
TSSOP-48 (DGG48)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold place test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold place fixture to control the PCB
temperature, as described in JESD51-8.
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5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
V
Power Cycle Reset
SVS Reset
V SVS+
BOR Reset
V SVS–
V BOR
t BOR
t
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
VBOR, safe
Safe BOR power-down level
tBOR, safe
Safe BOR reset delay (2)
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
ISVSH,LPM
SVSH current consumption, low-power modes
VCC = 3.6 V
VSVSH-
SVSH power-down level
1.71
1.81
1.87
V
VSVSH+
SVSH power-up level
1.76
1.88
1.99
V
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
tPD,SVSH, LPM
SVSH propagation delay, low-power modes
VREF,
1.2-V REF voltage (3)
(1)
(2)
(3)
18
1.2V
0.1
V
10
ms
1.5
240
nA
70
1.158
1.200
µA
mV
10
µs
100
µs
1.242
V
A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.
This is a characterized result with external 1-mA load to ground from –40°C to +85°C.
Specifications
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5.12.2 Reset Timing
Table 5-2. Wake-Up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
tWAKE-UP FRAM
Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller or
from a LPM if immediate activation is selected for
wakeup (1)
3V
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode (1)
3V
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode
tWAKE-UP LPM3.5
Wake-up time from LPM3.5 to active mode
(2)
tWAKE-UP LPM4.5
Wake-up time from LPM4.5 to active mode
(2)
tWAKE-UP-RESET
tRESET
(1)
(2)
(2)
MIN
TYP
MAX
10
UNIT
µs
200 ns +
2.5/fDCO
3V
10
µs
3V
10
µs
3V
350
µs
SVSHE = 1
3V
350
µs
SVSHE = 0
3V
1
ms
Wake-up time from RST or BOR event to active
mode (2)
3V
1
ms
Pulse duration required at RST/NMI pin to accept a
reset
3V
2
µs
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
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5.12.3 Clock Specifications
Table 5-3. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
fXT1, LF
XT1 oscillator crystal, low
frequency
LFXTBYPASS = 0
DCXT1, LF
XT1 oscillator LF duty cycle
Measured at MCLK,
fLFXT = 32768 Hz
fXT1,SW
XT1 oscillator logic-level squarewave input frequency
LFXTBYPASS = 1
DCXT1, SW
LFXT oscillator logic-level squareLFXTBYPASS = 1
wave input duty cycle
OALFXT
Oscillation allowance for
LF crystals (4)
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
CL,eff
Integrated effective load
capacitance (5)
See
tSTART,LFXT Start-up time
fFault,LFXT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
20
MIN
(8)
TYP
MAX
32768
30%
(2) (3)
70%
40%
(6)
XTS = 0 (9)
0
UNIT
Hz
32768
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(7)
Oscillator fault frequency
VCC
Hz
60%
200
kΩ
1
pF
1000
ms
3500
Hz
To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-4. DCO FLL, Frequency
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
FLL lock frequency, 16 MHz, 25°C
fDCO,
FLL lock frequency, 16 MHz, –40°C to +85°C
VCC
Measured at MCLK, Internal
trimmed REFO as reference
3V
FLL
FLL lock frequency, 16 MHz, –40°C to +85°C
fDUTY
Duty cycle
Jittercc
Cycle-to-cycle jitter, 16 MHz
Jitterlong
Long-term jitter, 16 MHz
tFLL, lock
FLL lock time
Measured at MCLK, XT1
crystal as reference
MIN
TYP
1.0%
–2.0%
2.0%
–0.5%
0.5%
40%
Measured at MCLK, XT1
crystal as reference
MAX
–1.0%
50%
UNIT
60%
0.25%
3V
0.022%
120
ms
Table 5-5. REFO
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
REFO oscillator current consumption
TA = 25°C
3V
15
µA
REFO calibrated frequency
Measured at MCLK
3V
32768
Hz
REFO absolute calibrated tolerance
–40°C to +85°C
REFO frequency temperature drift
Measured at MCLK (1)
3V
dfREFO/
dVCC
REFO frequency supply voltage drift
Measured at MCLK at
25°C (2)
1.8 V to 3.6 V
fDC
REFO duty cycle
Measured at MCLK
1.8 V to 3.6 V
tSTART
REFO start-up time
40% to 60% duty cycle
fREFO
dfREFO/dT
(1)
(2)
1.8 V to 3.6 V
–3.5%
40%
3.5%
0.01
%/°C
1
%/V
50%
60%
50
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-6. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fVLO
VLO frequency
Measured at MCLK
3V
10
kHz
dfVLO/dT
VLO frequency temperature drift
Measured at MCLK (1)
3V
0.5
%/°C
dfVLO/dVCC VLO frequency supply voltage drift
Measured at MCLK (2)
1.8 V to 3.6 V
4
%/V
fVLO,DC
Measured at MCLK
(1)
(2)
Duty cycle
3V
50%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-7. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift
fMODOSC/dVCC
MODOSC frequency supply voltage drift
fMODOSC,DC
Duty cycle
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
3V
3.8
4.8
5.8
MHz
3V
0.102
1.8 V to 3.6 V
1.02
3V
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40%
50%
%/℃
%/V
60%
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5.12.4 Digital I/Os
Table 5-8. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2V
0.90
TYP
MAX
1.50
3V
1.35
2.25
2V
0.50
1.10
3V
0.75
1.65
2V
0.3
0.8
3V
0.4
1.2
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
functions
VIN = VSS or VCC
5
pF
Ilkg(Px.y)
(1)
(2)
High-impedance leakage current
(1) (2)
20
2 V, 3 V
35
–20
V
V
V
50
kΩ
20
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Table 5-9. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
I(OHmax) = –3 mA (1)
TEST CONDITIONS
2V
1.4
2.0
I(OHmax) = –5 mA (1)
3V
2.4
3.0
I(OLmax) = 3 mA (1)
2V
0.0
0.60
I(OHmax) = 5 mA (1)
3V
0.0
0.60
2V
16
3V
16
VOH
High-level output voltage
VOL
Low-level output voltage
fPort_CLK
Clock output frequency
CL = 20 pF (2)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
(1)
(2)
22
TYP
MAX
UNIT
V
V
MHz
2V
10
3V
7
2V
10
3V
5
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The port can output frequencies at least up to the specified limit and might support higher frequencies.
Specifications
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5.12.4.1 Digital I/O Typical Characteristics
10
Low-Level Output Current (mA)
Low-Level Output Current (mA)
25
T A = 85°C
20
T A = 25°C
15
10
5
0
T A = 25°C
7.5
5
2.5
0
0
0.5
1
1.5
2
Low-Level Output Voltage (V)
2.5
3
0
Figure 5-5. Typical Low-Level Output Current vs Low-Level
Output Voltage (DVCC = 3 V)
0.25
0.5
0.75
1
1.25
1.5
Low-Level Output Voltage (V)
1.75
2
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage (DVCC = 2 V)
0
High-Level Output Current (mA)
0
High-Level Output Current (mA)
T A = 85°C
T A = 85°C
-5
T A = 25°C
-10
-15
-20
T A = 85°C
T A = 25°C
-2.5
-5
-7.5
-10
-25
0
0.5
1
1.5
2
High-Level Output Voltage (V)
2.5
Figure 5-7. Typical High-Level Output Current vs High-Level
Output Voltage (DVCC = 3 V)
3
0
0.25
0.5
0.75
1
1.25
1.5
High-Level Output Voltage (V)
1.75
2
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage (DVCC = 2 V)
5.12.5 Timer_A
Table 5-10. Timer_A Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fTA
TEST CONDITIONS
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
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VCC
2 V, 3 V
MIN
MAX
UNIT
16
MHz
Specifications
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5.12.6 eUSCI
Table 5-11. eUSCI (UART Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
VCC
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
MIN
MAX
UNIT
2 V, 3 V
16
MHz
2 V, 3 V
5
MHz
TYP
UNIT
Table 5-12. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
UCGLITx = 0
tt
UART receive deglitch time
12
UCGLITx = 1
(1)
40
2 V, 3 V
UCGLITx = 2
68
UCGLITx = 3
(1)
ns
110
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-13. eUSCI (SPI Master Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
CONDITIONS
MIN
MAX
UNIT
8
MHz
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
eUSCI input clock frequency
Table 5-14. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
tSTE,LAG
STE lag time, Last clock to STE inactive
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
24
2V
45
3V
35
2V
0
3V
0
ns
ns
2V
20
3V
20
2V
0
3V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-9 and Figure 5-10.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-9 and Figure 5-10.
Specifications
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-9. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-10. SPI Master Mode, CKPH = 1
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Table 5-15. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
tHD,SO
SOMI output data hold time
(1)
(2)
(3)
26
(3)
UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF
VCC
MIN
2V
55
3V
45
2V
20
3V
20
MAX
ns
ns
2V
65
3V
40
2V
40
3V
35
2V
4
3V
4
2V
12
3V
12
65
40
3V
5
ns
ns
3V
5
ns
ns
2V
2V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-11 and Figure 5-12.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-11 and Figure 5-12.
Specifications
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tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 5-11. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tVALID,SO
tDIS
SOMI
Figure 5-12. SPI Slave Mode, CKPH = 1
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Table 5-16. eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-13)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
2 V, 3 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2 V, 3 V
0
ns
tSU,DAT
Data setup time
2 V, 3 V
250
ns
tSU,STO
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
Setup time for STOP
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2 V, 3 V
0
MAX
2 V, 3 V
2 V, 3 V
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
UCGLITx = 0
50
600
UCGLITx = 1
25
300
12.5
150
UCGLITx = 2
2 V, 3 V
UCGLITx = 3
6.3
75
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2 V, 3 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-13. I2C Mode Timing
28
Specifications
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5.12.7 ADC
Table 5-17. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DVCC
ADC supply voltage
V(Ax)
Analog input voltage range
All ADC pins
IADC
Operating supply current into
DVCC terminal, reference
current not included, repeatsingle-channel mode
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC capacitor array,
including wiring and pad
RI
Input MUX ON resistance
DVCC = 2 V, 0 V = VAx = DVCC
VCC
MIN
TYP
MAX
UNIT
2.0
3.6
V
0
DVCC
V
2V
185
3V
207
2.2 V
1.6
µA
2.0
pF
2
kΩ
Table 5-18. ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC linearity
parameters
2 V to
3.6 V
0.45
5
5.5
MHz
Internal ADC oscillator
(MODOSC)
ADCDIV = 0, fADCCLK = fADCOSC
2 V to
3.6 V
4.5
5.0
5.5
MHz
2 V to
3.6 V
2.18
Conversion time
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
External fADCCLK from ACLK, MCLK, or SMCLK,
ADCSSEL ≠ 0
2 V to
3.6 V
fADCCLK
fADCOSC
tCONVERT
TEST CONDITIONS
tADCON
Turnon settling time of
the ADC
The error in a conversion started after tADCON is less
than ±0.5 LSB,
Reference and input signal already settled
tSample
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (t) are required for an error
of less than ±0.5 LSB
(1)
2.67
µs
(1)
100
2V
1.5
3V
2.0
ns
µs
12 × ADCDIV × 1/fADCCLK
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Table 5-19. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
Integral linearity error (10-bit mode)
EI
VDVCC as reference
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
ED
VDVCC as reference
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
EO
VDVCC as reference
Offset error (8-bit mode)
VDVCC as reference
Gain error (10-bit mode)
Internal 1.5-V reference
EG
VDVCC as reference
Gain error (8-bit mode)
Internal 1.5-V reference
Total unadjusted error (10-bit mode)
ET
Total unadjusted error (8-bit mode)
VDVCC as reference
Internal 1.5-V reference
VDVCC as reference
TYP
MAX
–2
2
2 V to
3.6 V
–2
2
2.4 V to
3.6 V
–1
1
2 V to
3.6 V
–1
1
2.4 V to
3.6 V
–6.5
6.5
2 V to
3.6 V
–6.5
6.5
UNIT
LSB
LSB
mV
2.4 V to
3.6 V
–2.0
2.0
–3.0%
3.0%
2 V to
3.6 V
–2.0
2.0
–3.0%
3.0%
2.4 V to
3.6 V
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
2 V to
3.6 V
Internal 1.5-V reference
MIN
2.4 V to
3.6 V
–3.0%
LSB
LSB
LSB
LSB
3.0%
VSENSOR
See
(1)
ADCON = 1, INCH = 0Ch, TA = 0°C
3V
1.013
mV
TCSENSOR
See
(2)
ADCON = 1, INCH = 0Ch
3V
3.35
mV/°C
tSENSOR
Sample time required if channel 12 is
selected (3)
ADCON = 1, INCH = 0Ch, Error of
conversion result ≤ 1 LSB, AM and all
LPM above LPM3
3V
30
ADCON = 1, INCH = 0Ch, Error of
conversion result ≤ 1 LSB, LPM3
3V
100
(sample)
(1)
(2)
(3)
30
µs
The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can
be computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
Specifications
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5.12.8 FRAM
Table 5-20. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tRetention
MAX
1015
Read and write endurance
Data retention duration
TJ = 25°C
100
TJ = 70°C
40
TJ = 85°C
10
UNIT
cycles
years
5.12.9 Emulation and Debug
Table 5-21. JTAG and Spy-Bi-Wire Interface Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2 V, 3 V
0
10
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2 V, 3 V
0.028
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
tSBW,Rst
Spy-Bi-Wire return to normal operation time
(2)
fTCK
TCK input frequency, 4-wire JTAG
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
VCC
(1)
MIN
TYP
2 V, 3 V
110
µs
15
100
µs
2V
0
16
3V
0
16
2 V, 3 V
20
35
50
MHz
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.2
Operating Modes
The MSP430 has one active mode and several software selectable low-power modes of operation. An
interrupt event can wake up the device from low-power mode LPM0 or LPM3, service the request, and
restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and
LPM4.5 disable the core supply to minimize power consumption.
Table 6-1. Operating Modes
MODE
Maximum System Clock
Power Consumption at 25°C, 3 V
Wake-up time
Clock
Core
32
LPM3
LPM4
LPM3.5
LPM4.5
ACTIVE
MODE
CPU OFF
STANDBY
OFF
ONLY RTC
COUNTER
SHUTDOWN
16 MHz
16 MHz
40 kHz
0
40 kHz
0
126 µA/MHz
20 µA/MHz
1.2 µA
0.6 µA
without SVS
0.77 µA with
RTC only
13 nA
without SVS
N/A
instant
10 µs
10 µs
150 µs
150 µs
I/O
N/A
All
All
I/O
Regulator
Full
Regulation
Full
Regulation
Partial Power
Down
Partial Power
Down
Partial Power
Down
Power Down
SVS
On
On
Optional
Optional
Optional
Optional
Brown Out
On
On
On
On
On
On
MCLK
Active
Off
Off
Off
Off
Off
SMCLK
Optional
Optional
Off
Off
Off
Off
FLL
Optional
Optional
Off
Off
Off
Off
DCO
Optional
Optional
Off
Off
Off
Off
MODCLK
Optional
Optional
Off
Off
Off
Off
REFO
Optional
Optional
Optional
Off
Off
Off
ACLK
Optional
Optional
Optional
Off
Off
Off
XT1CLK
Optional
Optional
Optional
Off
Optional
Off
VLOCLK
Optional
Optional
Optional
Off
Optional
Off
CPU
On
Off
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
RAM
On
On
On
On
Off
Off
On
On
On
On
On
Off
Backup Memory
(1)
LPM0
RTC Counter,
I/O
Wake-up events
Power
AM
(1)
Backup memory contains one 32-byte register in the peripheral memory space. Refer to Table 6-31 and Table 6-49 for its memory
allocation.
Detailed Description
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Table 6-1. Operating Modes (continued)
AM
MODE
Peripherals
I/O
6.3
LPM0
LPM4
LPM3.5
LPM4.5
STANDBY
OFF
ONLY RTC
COUNTER
SHUTDOWN
Optional
Optional
Off
Off
Off
Optional
Optional
Off
Off
Off
ACTIVE
MODE
CPU OFF
Timer0_A3
Optional
Timer1_A3
Optional
LPM3
WDT
Optional
Optional
Optional
Off
Off
Off
eUSCI_A0
Optional
Optional
Off
Off
Off
Off
eUSCI_B0
Optional
Optional
Off
Off
Off
Off
CRC
Optional
Optional
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
Off
Off
RTC Counter
Optional
Optional
Optional
Off
State Held
Off
General Digital
Input/Output
On
Optional
State Held
State Held
Off
State Held
Capacitive Touch I/O
Optional
Optional
Optional
Off
Off
Off
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence
Table 6-2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
FFFEh
63, Highest
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
Nonmaskable
FFFCh
62
NMIIFG
OFIFG
Nonmaskable
FFFAh
61
Timer0_A3
TA0CCR0 CCIFG0
Maskable
FFF8h
60
Timer0_A3
TA0CCR1 CCIFG1, TA0CCR2
CCIFG2, TA0IFG (TA0IV)
Maskable
FFF6h
59
Timer1_A3
TA1CCR0 CCIFG0
Maskable
FFF4h
58
Timer1_A3
TA1CCR1 CCIFG1, TA1CCR2
CCIFG2, TA1IFG (TA1IV)
Maskable
FFF2h
57
RTC Counter
RTCIFG
Maskable
FFF0h
56
Watchdog Timer Interval mode
WDTIFG
Maskable
FFEEh
55
eUSCI_A0 Receive or Transmit
UCTXCPTIFG, UCSTTIFG,
UCRXIFG, UCTXIFG (UART
mode)
UCRXIFG, UCTXIFG (SPI
mode)
(UCA0IV))
Maskable
FFECh
54
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-up, Brownout, Supply Supervisor
External Reset RST
Watchdog Time-out, Key Violation
FRAM uncorrectable bit error detection
Software POR,
FLL unlock error
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLUNLOCKIFG
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM bit error detection
User NMI
External NMI
Oscillator Fault
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Table 6-2. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
eUSCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG (SPI
mode)
UCALIFG, UCNACKIFG,
UCSTTIFG, UCSTPIFG,
UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1,
UCRXIFG2, UCTXIFG2,
UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C
mode)
(UCB0IV)
Maskable
FFEAh
53
ADC
ADCIFG0, ADCINIFG,
ADCLOIFG, ADCHIIFG,
ADCTOVIFG, ADCOVIFG
(ADCIV)
Maskable
FFE8h
52
P1
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
FFE6h
51
P2
P2IFG.0 to P2IFG.7 (P2IV)
Maskable
FFE4h
50, Lowest
Reserved
Maskable
FFE2h-FF88h
Reserved
Signatures
6.4
BSL Signature 2
0FF86h
BSL Signature 1
0FF84h
JTAG Signature 2
0FF82h
JTAG Signature 1
0FF80h
Bootstrap Loader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device
memory through the BSL is protected by an user-defined password. Use of the BSL requires four pins as
shown in Table 6-3. BSL entry requires a specific entry sequence on the RST/NMISBWTDIO and
TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see
the MSP430FR4xx and MSP430FR2xx Bootstrap Loader (BSL) User's Guide (SLAU610).
Table 6-3. BSL Pin Requirements and Functions
6.5
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.0
Data transmit
P1.1
Data receive
VCC
Power Supply
VSS
Ground Supply
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 64. For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface
and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).
34
Detailed Description
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Table 6-4. JTAG Pin Requirements and Function
6.6
DEVICE SIGNAL
DIRECTION
P1.4/MCLK/TCK/A4/VREF+
IN
JTAG FUNCTION
JTAG clock input
P1.5/TA0CLK/TMS/A5
IN
JTAG state control
P1.6/TA0.2/TDI/TCLK/A6
IN
JTAG data input/TCLK input
P1.7/TA0.1/TDO/A7
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External Reset
VCC
Power Supply
VSS
Ground Supply
Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with
MSP430 development tools and device programmers. Table 6-5 shows the Spy-Bi-Wire interface pin
requirements. For further details on interfacing to development tools and device programmers, refer to the
MSP430 Hardware Tools User's Guide (SLAU278).
Table 6-5. Spy-Bi-Wire Pin Requirements and Functions
6.7
DEVICE SIGNAL
DIRECTION
SBW FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power Supply
VSS
Ground Supply
FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
6.8
Memory Protection
The device features memory protection that can restrict user access and enable write protection:
• Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
• Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control
bits in System Configuration register 0. For more detailed information, refer to the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
NOTE
The FRAM is protected by default on PUC. To write to FRAM during code execution, the
application must first clear the corresponding PFWP or DFWP bit in System Configuration
Register 0 to unprotect the FRAM.
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6.9
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
6.9.1
Power Management Module (PMM) and On-chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using ADC sampling 1.5-V reference without any external components
support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V Reference ADC result
(1)
A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when the ADC
channel 4 is selected as the function. For more detailed information, refer to the MSP430FR4xx and
MSP430FR2xx Family User's Guide (SLAU445).
6.9.2
Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very low-power low-frequency
oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled
oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz
reference clock, and on-chip asynchronous high-speed clock (MODOSC). The clock system is designed to
target cost-effective designs with minimal external components. A fail-safe mechanism is designed for
XT1. The clock system module offers the following clock signals.
• Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the
bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
• Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from
the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
• Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to
40 kHz.
All peripherals may have one or several clock sources depending on specific functionality. Table 6-6
shows the clock distribution used in this device.
36
Detailed Description
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Table 6-6. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
Frequency
Range
MCLK
SMCLK
ACLK
MODCLK
XT1CLK (1)
VLOCLK
DC to
16 MHz
DC to
16 MHz
DC to
40 kHz
5 MHz ±10%
DC to
40 kHz
10 kHz
±50%
CPU
N/A
Default
FRAM
N/A
Default
RAM
N/A
Default
CRC
N/A
Default
I/O
N/A
Default
TA0
TASSEL
10b
01b
TA1
TASSEL
10b
01b
eUSCI_A0
UCSSEL
10b or 11b
eUSCI_B0
UCSSEL
10b or 11b
WDTSSEL
00b
01b
ADC
ADCSSEL
11b
01b
RTC
RTCSS
01b
(1)
00b (TA0CLK pin)
00b (TA1CLK pin)
01b
WDT
EXTERNAL PIN
00b (UCA0CLK pin)
01b
00b (UCB0CLK pin)
10b
00b
10b
11b
To enable XT1 functionality, configure P4SEL0.1 (XIN) and P4SEL0.2 (XOUT) before configuring the Clock System registers.
6.9.3
General-Purpose Input/Output Port (I/O)
There are up to 60 I/O ports implemented, depending on the package.
• P1, P2, P3, P4, P5, P6, and P7 are full 8-bit ports; P8 has 4 bits implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive Touch I/O functionality is supported on all pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, refer to the Configuration After Reset section in the Digital I/O chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445)
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Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals.
Table 6-7. WDT Clocks
6.9.5
WDTSSELx
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
VLOCLK
System Module (SYS)
The SYS module handles many of the system functions within the device. These include Power-On Reset
(POR) and Power-Up Clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootstrap loader entry mechanisms, and configuration management (device descriptors). SYS
also includes a data exchange mechanism through SBW called a JTAG mailbox mail box that can be used
in the application.
Table 6-8. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
38
Detailed Description
ADDRESS
015Eh
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
Reserved
22h
FLL unlock (PUC)
24h
Reserved
26h to 3Eh
PRIORITY
Highest
Lowest
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Table 6-8. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
REGISTER
SYSSNIV, System NMI
SYSUNIV, User NMI
6.9.6
ADDRESS
INTERRUPT EVENT
VALUE
No interrupt pending
00h
SVS low-power reset entry
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
Reserved
0Eh
Reserved
10h
VMAIFG Vacant memory access
12h
015Ch
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
Correctable FRAM bit error detection
18h
015Ah
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIFG NMI pin or SVSH event
02h
OFIFG oscillator fault
04h
Reserved
06h to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
6.9.7
Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA.
Table 6-9. eUSCI Pin Configurations
eUSCI_A0
PIN
UART
SPI
P1.0
TXD
SIMO
P1.1
RXD
P1.2
P1.3
PIN
STE
2
I C
P5.0
eUSCI_B0
SOMI
SCLK
SPI
STE
P5.1
SCLK
P5.2
SDA
SIMO
P5.3
SCL
SOMI
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Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare
registers each. Each timer can support multiple captures or compares, PWM outputs, and interval timing.
Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow
conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA1 are
not externally connected and can only be used for hardware period timing and interrupt generation. In Up
mode, they can be used to set the overflow value of the counter.
Table 6-10. Timer0_A3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P1.5
TA0CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive
Touch I/O (internal)
INCLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TA0
DEVICE OUTPUT
SIGNAL
CCI0A
CCI0B
DVSS
VCC
TA0.1
CCI1A
From RTC (internal)
CCI1B
TA0.1
CCR1
TA1
Timer1_A3 CCI1B
input
DVSS
GND
DVCC
VCC
TA0.2
CCI2A
TA0.2
From Capacitive
Touch I/O (internal)
CCI2B
Timer1_A3 INCLK
Timer1_A3 CCI2B
input,
IR Input
DVSS
GND
DVCC
VCC
P1.6
40
GND
DVCC
P1.7
Timer1_A3 CCI0B
input
Detailed Description
CCR2
TA2
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Table 6-11. Timer1_A3 Signal Connections
PORT PIN
P8.2
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
Timer0_A3 CCR2B
output (internal)
INCLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TA0
DEVICE OUTPUT
SIGNAL
CCI0A
P4.0
P8.3
Timer0_A3 CCR0B
output (internal)
CCI0B
DVSS
GND
DVCC
VCC
TA1.1
CCI1A
Timer0_A3 CCR1B
output (internal)
CCI1B
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
Timer0_A3 CCR2B
output (internal)
CCI2B
DVSS
GND
DVCC
VCC
TA1.1
CCR1
TA1
To ADC trigger
TA1.2
CCR2
TA2
IR Input
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode. This configuration helps an application easily acquire
a modulated infrared command for directly driving an external IR diode.
The IR functions are controlled by the following bits in the System Configuration 1 (SYSCFG1) register:
IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSEL (data select), and IRDATA
(data). For more information, refer to the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family
User's Guide (SLAU445).
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6.9.9
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Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. The RTC
can periodically wake up the CPU from LPM0, LPM3, or LPM3.5 based on timing from a low-power clock
source such as the XT1 and VLO clocks. In AM, RTC can be driven by SMCLK to generate highfrequency timing events and interrupts. The RTC overflow events trigger:
• Timer0_A3 CCR1B
• ADC conversion trigger when ADCSHSx bits are set as 01b
6.9.10 10-Bit Analog Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, reference generator and a conversion result
buffer. A window comparator with a lower and upper limit allows CPU independent result monitoring with
three window comparator interrupt flags.
The ADC supports 10 external inputs and four internal inputs (see Table 6-12).
Table 6-12. ADC Channel Connections
(1)
(2)
ADCSHSx
ADC CHANNELS
EXTERNAL PIN OUT
0
A0/Veref–
P1.0
1
A1/Veref+
P1.1
2
A2
P1.2
3
A3
P1.3
4
A4 (1)
P1.4
5
A5
P1.5
6
A6
P1.6
7
A7
P1.7
8
A8
P8.0 (2)
9
A9
P8.1 (2)
10
Not used
N/A
11
Not used
N/A
12
On-chip temperature sensor
N/A
13
Reference voltage (1.5 V)
N/A
14
DVSS
N/A
15
DVCC
N/A
When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be directly measured by A4 channel.
P8.0 and P8.1 are only available in the LQFP-64 package.
The A/D conversion can be started by software or a hardware trigger. Table 6-13 shows the trigger
sources that are available.
Table 6-13. ADC Trigger Signal Connections
ADCSHSx
42
Detailed Description
TRIGGER SOURCE
BINARY
DECIMAL
00
0
ADCSC bit (software trigger)
01
1
RTC event
10
2
TA1.1B
11
3
TA1.2B
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6.9.11 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
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6.9.12 Input/Output Schematics
6.9.12.1 Port P1 Input/Output With Schmitt Trigger
A0..A7
From ADC A
P1REN.x
P1DIR.x
0
From Module
1
DVSS
0
DVCC
1
P1OUT.x
0
From Module
1
P1SEL0.x
EN
To module
D
P1IN.x
P1IE.x
P1 Interrupt
Q
D
S
P1IFG.x
P1IES.x
From JTAG
Edge
Select
Bus
Keeper
P1.0/UCA0TXD/UCA0SIMO/A0
P1.1/UCA0RXD/UCA0SOMI/A1
P1.2/UCA0CLK/A2
P1.3/UCA0STE/A3
P1.4/MCLK/TCK/A4/VREF+
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/A6
P1.7/TA0.1/TDO/A7
To JTAG
Figure 6-1. Port P1 Input/Output With Schmitt Trigger
44
Detailed Description
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Table 6-14. Port P1 Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/UCA0TXD/UCA0SIMO/A0
0
UCA0TXD/UCA0SIMO
A0
P1.1 (I/O)
P1.1/UCA0RXD/UCA0SOMI/A1
1
UCA0RXD/UCA0SOMI
A1
P1.2/UCA0CLK/A2
2
3
P1.5/TA0CLK/TMS/A5
4
5
6
(1)
(2)
7
JTAG
I: 0; O: 1
0
0
N/A
X
1
0
N/A
X
X
1 (x = 0)
N/A
I: 0; O: 1
0
0
N/A
X
1
0
N/A
X
1 (x = 1)
N/A
0
0
N/A
UCA0CLK
X
1
0
N/A
X
X
1 (x = 2)
N/A
P1.3 (I/O)
I: 0; O: 1
0
0
N/A
UCA0STE
X
1
0
N/A
A3
X
X
1 (x = 3)
N/A
I: 0; O: 1
0
0
Disabled
1
0
Disabled
Disabled
VSS
0
MCLK
1
A4, VREF+
X
X
1 (x = 4)
JTAG TCK
X
X
X
TCK
P1.5 (I/O)
I: 0; O: 1
0
0
Disabled
TA0CLK
0
VSS
1
1
0
Disabled
A5
X
X
1 (x = 5)
Disabled
JTAG TMS
X
X
X
TMS
I: 0; O: 1
0
0
Disabled
1
0
Disabled
TA0.CCI2A
0
TA0.2
1
A6
X
X
1 (x = 6)
Disabled
JTAG TDI/TCLK
X
X
X
TDI/TCLK
I: 0; O: 1
0
0
Disabled
1
0
Disabled
P1.7 (I/O)
P1.7/TA0.1/TDO/A7
ADCPCTLx (2)
X
P1.6 (I/O)
P1.6/TA0.2/TDI/TCLK/A6
P1SEL0.x
I: 0; O: 1
P1.4 (I/O)
P1.4/MCLK/TCK/A4/VREF+
P1DIR.x
P1.2 (I/O)
A2
P1.3/UCA0STE/A3
CONTROL BITS AND SIGNALS (1)
TA0.CCI1A
0
TA0.1
1
A7
X
X
1 (x = 7)
Disabled
JTAG TDO
X
X
X
TDO
X = don't care
Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and the input Schmitt trigger to prevent leakage when
analog signals are applied.
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6.9.12.2 Port P2 Input/Output With Schmitt Trigger
P2REN.x
P2DIR.x
DVSS
0
DVCC
1
P2OUT.x
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2IN.x
P2IE.x
P2 Interrupt
Q
D
Bus
Keeper
1
S
P2IFG.x
1
P2IES.x
Edge
Select
Figure 6-2. Port P2 Input/Output With Schmitt Trigger
Table 6-15. Port P2 Pin Functions
PIN NAME (P2.x)
x
CONTROL BITS AND
SIGNALS
FUNCTION
P2DIR.x
P2.0
0
P2.0 (I/O)
I: 0; O: 1
P2.1
1
P2.1 (I/O)
I: 0; O: 1
P2.2
2
P2.2 (I/O)
I: 0; O: 1
P2.3
3
P2.3 (I/O)
I: 0; O: 1
P2.4
4
P2.4 (I/O)
I: 0; O: 1
P2.5
5
P2.5 (I/O)
I: 0; O: 1
P2.6
6
P2.6 (I/O)
I: 0; O: 1
P2.7
7
P2.7 (I/O)
I: 0; O: 1
46
Detailed Description
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6.9.12.3 Port P3 Input/Output With Schmitt Trigger
P3REN.x
P3DIR.x
DVSS
0
DVCC
1
P3OUT.x
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3IN.x
Bus
Keeper
Figure 6-3. Port P3 Input/Output With Schmitt Trigger
Table 6-16. Port P3 Pin Functions
PIN NAME (P3.x)
x
FUNCTION
CONTROL BITS AND
SIGNALS
P3DIR.x
P3.0
0
P3.0 (I/O)
I: 0; O: 1
P3.1
1
P3.1 (I/O)
I: 0; O: 1
P3.2
2
P3.2 (I/O)
I: 0; O: 1
P3.3
3
P3.3 (I/O)
I: 0; O: 1
P3.4
4
P3.4 (I/O)
I: 0; O: 1
P3.5
5
P3.5 (I/O)
I: 0; O: 1
P3.6
6
P3.6 (I/O)
I: 0; O: 1
P3.7
7
P3.7 (I/O)
I: 0; O: 1
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6.9.12.4 Port P4.0 Input/Output With Schmitt Trigger
P4REN.x
P4DIR.x
0
From Module
1
DVSS
0
DVCC
1
P4OUT.x
0
From Module
1
P4SEL0.x
EN
D
To module
P4IN.x
Bus
Keeper
P4.0/TA1.1
Figure 6-4. Port P4.0 Input/Output With Schmitt Trigger
Table 6-17. Port P4.0 Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/TA1.1
48
Detailed Description
0
CONTROL BITS AND SIGNALS
P4DIR.x
P4SEL0.x
I: 0; O: 1
0
TA1.CCI1A
0
TA1.1
1
1
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6.9.12.5 Port P4.1 and P4.2 Input/Output With Schmitt Trigger
XIN, XOUT
P4REN.x
P4DIR.x
DVSS
0
DVCC
1
P4OUT.x
P4SEL0.x
P4IN.x
Bus
Keeper
P4.1/XIN
P4.2/XOUT
Figure 6-5. Port P4.1 and P4.2 Input/Output With Schmitt Trigger
Table 6-18. Port P4.1 and P4.2 Pin Functions
PIN NAME (P4.x)
P4.1/XIN
P4.2/XOUT
(1)
x
1
2
FUNCTION
P4.1 (I/O)
CONTROL BITS AND SIGNALS (1)
P4DIR.x
P4SEL0.x
I: 0; O: 1
0
XIN
P4.2 (I/O)
X
1
I: 0; O: 1
0
X
1
XOUT
X = don't care
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6.9.12.6 Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
P4REN.x
P4DIR.x
DVSS
0
DVCC
1
P4OUT.x
P4.3
P4.4
P4.5
P4.6
P4.7
P4IN.x
Bus
Keeper
Figure 6-6. Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
Table 6-19. Port P4.3, P4.4, P4.5, P4.6, and P4.7 Pin Functions
PIN NAME (P4.x)
x
CONTROL BITS AND
SIGNALS
FUNCTION
P4DIR.x
P4.3
3
P4.3 (I/O)
I: 0; O: 1
P4.4
4
P4.4 (I/O)
I: 0; O: 1
P4.5
5
P4.5 (I/O)
I: 0; O: 1
P4.6
6
P4.6 (I/O)
I: 0; O: 1
P4.7
7
P4.7 (I/O)
I: 0; O: 1
50
Detailed Description
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6.9.12.7 Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
P5REN.x
P5DIR.x
0
From Module
1
DVSS
0
DVCC
1
P5OUT.x
0
From Module
1
P5.0/UCB0STE
P5.1/UCB0CLK
P5.2/UCB0SIMO/UCB0SDA
P5.3/UCB0SOMI/UCB0SCL
P5SEL0.x
EN
D
To module
P5IN.x
Bus
Keeper
Figure 6-7. Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
Table 6-20. Port P5.0, P5.1, P5.2, and P5.3 Pin Functions
PIN NAME (P5.x)
P5.0/UCB0STE
P5.1/UCB0CLK
x
0
1
P5.2/UCB0SIMO/UCB0SDA
2
P5.3/UCB0SOMI/UCB0SCL
3
FUNCTION
CONTROL BITS AND SIGNALS
P5DIR.x
P5SEL0.x
P5.0 (I/O)
I: 0; O: 1
0
UCB0STE
0
1
P5.1 (I/O)
I: 0; O: 1
0
UCB0CLK
0
1
P5.2 (I/O)
I: 0; O: 1
0
0
1
I: 0; O: 1
0
0
1
UCB0SIMO/UCB0SDA
P5.3 (I/O)
UCB0SOMI/UCB0SCL
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6.9.12.8 Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
P5OUT.x
P5.4
P5.5
P5.6
P5.7
P5IN.x
Bus
Keeper
Figure 6-8. Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
Table 6-21. Port P5.4, P5.5, P5.6, and P5.7 Pin Functions
PIN NAME (P5.x)
x
CONTROL BITS AND
SIGNALS
FUNCTION
P5DIR.x
P5.4
4
P5.4 (I/O)
I: 0; O: 1
P5.5
5
P5.5 (I/O)
I: 0; O: 1
P5.6
6
P5.6 (I/O)
I: 0; O: 1
P5.7
7
P5.7 (I/O)
I: 0; O: 1
52
Detailed Description
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6.9.12.9 Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
P6REN.x
P6DIR.x
DVSS
0
DVCC
1
P6OUT.x
P6.0
P6.1
P6.2
P6.3
P6IN.x
Bus
Keeper
Figure 6-9. Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
Table 6-22. Port P6 Pin Functions
PIN NAME (P6.x)
x
FUNCTION
CONTROL BITS AND
SIGNALS
P6DIR.x
P6.0
0
P6.0 (I/O)
I: 0; O: 1
P6.1
1
P6.1 (I/O)
I: 0; O: 1
P6.2
2
P6.2 (I/O)
I: 0; O: 1
P6.3
3
P6.3 (I/O)
I: 0; O: 1
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6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
P6REN.x
P6DIR.x
DVSS
0
DVCC
1
P6OUT.x
P6.4
P6.5
P6.6
P6.7
P6IN.x
Bus
Keeper
Figure 6-10. Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
Table 6-23. Port P6.4, P6.5, P6.6, and P6.7 Pin Functions
PIN NAME (P6.x)
x
CONTROL BITS AND
SIGNALS
FUNCTION
P6DIR.x
P6.4
4
P6.4 (I/O)
I: 0; O: 1
P6.5
5
P6.5 (I/O)
I: 0; O: 1
P6.6
6
P6.6 (I/O)
I: 0; O: 1
P6.7
7
P6.7 (I/O)
I: 0; O: 1
54
Detailed Description
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6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
P7REN.x
P7DIR.x
DVSS
0
DVCC
1
P7OUT.x
P7.0
P7.1
P7.2
P7.3
P7IN.x
Bus
Keeper
Figure 6-11. Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
Table 6-24. Port P7.0, P7.1, P7.2, and P7.3 Pin Functions
PIN NAME (P7.x)
x
FUNCTION
CONTROL BITS AND
SIGNALS
P7DIR.x
P7.0
0
P7.0 (I/O)
I: 0; O: 1
P7.1
1
P7.1 (I/O)
I: 0; O: 1
P7.2
2
P7.2 (I/O)
I: 0; O: 1
P7.3
3
P7.3 (I/O)
I: 0; O: 1
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6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
P7REN.x
P7DIR.x
DVSS
0
DVCC
1
P7OUT.x
P7.4
P7.5
P7.6
P7.7
P7IN.x
Bus
Keeper
Figure 6-12. Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
Table 6-25. Port P7.4, P7.5, P7.6, and P7.7 Pin Functions
PIN NAME (P7.x)
x
CONTROL BITS AND
SIGNALS
FUNCTION
P7DIR.x
P7.4
4
P7.4 (I/O)
I: 0; O: 1
P7.5
5
P7.5 (I/O)
I: 0; O: 1
P7.6
6
P7.6 (I/O)
I: 0; O: 1
P7.7
7
P7.7 (I/O)
I: 0; O: 1
56
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6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
A8..9
From ADC A
P8REN.x
P8DIR.x
0
From Module
1
DVSS
0
DVCC
1
P8OUT.x
0
From MCLK, ACLK
1
P8SEL0.x
EN
To module
D
P8IN.x
Bus
Keeper
P8.0/SMCLK/A8
P8.1/ACLK/A9
Figure 6-13. Port P8.0 and P8.1 Input/Output With Schmitt Trigger
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Table 6-26. Port P8.0 and P8.1 Pin Functions
PIN NAME (P8.x)
x
FUNCTION
P8.0 (I/O)
P8.0/SMCLK/A8
0
(1)
(2)
58
P8SEL0.x
ADCPCTLx (2)
I: 0; O: 1
0
0
1
0
X
X
1 (x = 8)
I: 0; O: 1
0
0
1
0
X
1 (x = 9)
0
SMCLK
1
P8.1 (I/O)
1
P8DIR.x
VSS
A8
P8.1/ACLK/A9
CONTROL BITS AND SIGNALS (1)
VSS
0
ACLK
1
A9
X
X = don't care
Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and the input Schmitt trigger to prevent leakage when
analog signals are applied.
Detailed Description
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6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
P8REN.x
P8DIR.x
0
From Module
1
DVSS
0
DVCC
1
P8OUT.x
0
From Module
1
P8SEL0.x
EN
D
To module
P8IN.x
Bus
Keeper
P8.2/TA1CLK
P8.3/TA1.2
Figure 6-14. Port P8.2 and P8.3 Input/Output With Schmitt Trigger
Table 6-27. Port P8.2 and P8.3 Pin Functions
PIN NAME (P8.x)
P8.2/TA1CLK
x
2
FUNCTION
P8SEL0.x
P8.2 (I/O)
I: 0; O: 1
0
TA1 CLK
0
VSS
1
P8.3 (I/O)
P8.3/TA1.2
3
CONTROL BITS AND SIGNALS
P8DIR.x
I: 0; O: 1
TA1.CCI2A
0
TA1.2
1
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0
1
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6.10 Device Descriptors (TLV)
Table 6-28 lists the Device IDs of the MSP430FR203x device variants. Table 6-29 lists the contents of the
device descriptor tag-length-value (TLV) structure for MSP430FR203x devices.
Table 6-28. Device IDs
DEVICE ID
DEVICE
1A04h
1A05h
MSP430FR2033
75h
82h
MSP430FR2032
78h
82h
Table 6-29. Device Descriptors
DESCRIPTION
VALUE
Info length
1A00h
06h
CRC length
1A01h
06h
1A02h
per unit
1A03h
per unit
CRC value (1)
Information Block
Device ID
See Table 6-28
1A06h
per unit
1A07h
per unit
Die Record Tag
1A08h
08h
Die Record length
1A09h
0Ah
1A0Ah
per unit
1A0Bh
per unit
1A0Ch
per unit
1A0Dh
per unit
1A0Eh
per unit
1A0Fh
per unit
1A10h
per unit
1A11h
per unit
1A12h
per unit
1A13h
per unit
ADC Calibration Tag
1A14h
11h
ADC Calibration Length
1A15h
08h
1A16h
per unit
1A17h
per unit
1A18h
per unit
Die X position
Die Y position
Test Result
ADC Gain Factor
ADC Offset
ADC 1.5-V Reference Temperature 30°C
ADC 1.5-V Reference Temperature 85°C
60
1A05h
Firmware revision
Die Record
(1)
1A04h
Hardware revision
Lot Wafer ID
ADC Calibration
MSP430FR203x
ADDRESS
1A19h
per unit
1A1Ah
per unit
1A1Bh
per unit
1A1Ch
per unit
1A1Dh
per unit
The CRC value covers the checksum from 1A04h to 1A77h by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1.
Detailed Description
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Table 6-29. Device Descriptors (continued)
MSP430FR203x
DESCRIPTION
ADDRESS
VALUE
Calibration Tag
1A1Eh
12h
Calibration Length
1A1Fh
04h
1A20h
per unit
1A21h
per unit
1A22h
per unit
1A23h
perunit
Reference and DCO Calibration 1.5-V Reference Factor
DCO Tap Settings for 16 MHz, Temperature
30°C (2)
(2)
This value can be directly loaded into DCO bits in CSCTL0 register to get accurate 16-MHz frequency at room temperature, especially
when MCU exits from LPM3 and below. TI suggests using a predivider to decrease the frequency, if the temperature drift might result an
overshoot beyond 16 MHz.
6.11 Memory
Table 6-30 shows the memory organization of the MSP430FR203x devices.
Table 6-30. Memory Organization
Access
MSP430FR2033
MSP430FR2032
Read/Write
(Optional Write Protect) (1)
15KB
FFFFh-FF80h
FFFFh-C400h
8KB
FFFFh-FF80h
FFFFh-E000h
Read/Write
2KB
27FFh-2000h
1KB
23FFh-2000h
Read/Write
(Optional Write Protect) (2)
512B
19FFh-1800h
512B
19FFh-1800h
Bootstrap loader (BSL) Memory (ROM)
Read only
1KB
13FFh-1000h
1KB
13FFh-1000h
Peripherals
Read/Write
4KB
0FFFh-0000h
4KB
0FFFh-0000h
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
RAM
Information Memory (FRAM)
(1)
(2)
The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. Refer to the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide (SLAU445) for more details
The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. Refer to the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445) for more details
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6.11.1 Peripheral File Map
Table 6-31 shows the base address and the memory size of the register region for each peripheral, and
Table 6-32 through Table 6-50 show all of the available registers for each peripheral and their address
offsets.
Table 6-31. Peripherals Summary
BASE ADDRESS
SIZE
Special Functions (See Table 6-32)
MODULE NAME
0100h
0010h
PMM (See Table 6-33)
0120h
0020h
SYS (See Table 6-34)
0140h
0030h
CS (See Table 6-35)
0180h
0020h
FRAM (See Table 6-36)
01A0h
0010h
CRC (See Table 6-37)
01C0h
0008h
WDT (See Table 6-38)
01CCh
0002h
Port P1, P2 (See Table 6-39)
0200h
0020h
Port P3, P4 (See Table 6-40)
0220h
0020h
Port P5, P6 (See Table 6-41)
0240h
0020h
Port P7, P8 (See Table 6-42)
0260h
0020h
Capacitive Touch I/O (See Table 6-43)
02E0h
0010h
Timer0_A3 (See Table 6-44)
0300h
0030h
Timer1_A3 (See Table 6-45)
0340h
0030h
RTC (See Table 6-46)
03C0h
0010h
eUSCI_A0 (See Table 6-47)
0500h
0020h
eUSCI_B0 (See Table 6-48)
0540h
0030h
Backup Memory (See Table 6-49)
0660h
0020h
ADC (See Table 6-50)
0700h
0040h
62
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Table 6-32. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
REGISTER
OFFSET
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
Table 6-33. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM Control 1
PMMCTL1
02h
PMM Control 2
PMMCTL2
04h
PMM interrupt flags
PMMIFG
0Ah
PM5 Control 0
PM5CTL0
10h
Table 6-34. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SYSCTL
00h
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System control
Bootstrap loader configuration area
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
System configuration 0
SYSCFG0
20h
System configuration 1
SYSCFG1
22h
System configuration 2
SYSCFG2
24h
Table 6-35. CS Registers (Base Address: 0180h)
REGISTER
OFFSET
CS control register 0
REGISTER DESCRIPTION
CSCTL0
00h
CS control register 1
CSCTL1
02h
CS control register 2
CSCTL2
04h
CS control register 3
CSCTL3
06h
CS control register 4
CSCTL4
08h
CS control register 5
CSCTL5
0Ah
CS control register 6
CSCTL6
0Ch
CS control register 7
CSCTL7
0Eh
CS control register 8
CSCTL8
10h
Table 6-36. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
FRAM control 0
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
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Table 6-37. CRC Registers (Base Address: 01C0h)
REGISTER
OFFSET
CRC data input
REGISTER DESCRIPTION
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 6-38. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
OFFSET
WDTCTL
00h
Table 6-39. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P1IN
00h
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pulling register enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
P1IE
1Ah
P1IFG
1Ch
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P1 input
Port P1 output
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 pulling register enable
P2REN
07h
Port P2 selection 0 (1)
P2SEL0
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
P2IE
1Bh
P2IFG
1Dh
Port P2 interrupt enable
Port P2 interrupt flag
(1)
Port P2 selection register does not feature any valid bits. P2SEL0 presents for 16-bit Port A operation with P1SEL0.
Table 6-40. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P3IN
00h
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pulling register enable
P3REN
06h
Port P3 selection 0 (1)
P3SEL0
0Ah
Port P3 input
Port P3 output
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pulling register enable
P4REN
07h
Port P4 selection 0
P4SEL0
0Bh
(1)
64
Port P3 selection register does not feature any valid bits. P3SEL0 presents for 16-bit Port B operation with P4SEL0.
Detailed Description
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Table 6-41. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 input
Port P5 pulling register enable
P5REN
06h
Port P5 selection 0
P5SEL0
0Ah
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pulling register enable
P6REN
07h
P6SEL0
0Bh
Port P6 input
Port P6 selection 0
(1)
(1)
Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.
Table 6-42. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pulling register enable
P7REN
06h
P7SEL0
0Ah
P8IN
01h
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 pulling register enable
P8REN
07h
Port P8 selection 0
P8SEL0
0Bh
Port P7 input
Port P7 selection 0
(1)
Port P8 input
Port P8 output
(1)
Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.
Table 6-43. Capacitive Touch I/O Registers (Base Address: 02E0h)
REGISTER DESCRIPTION
Capacitive Touch I/O 0 control
REGISTER
OFFSET
CAPTIO0CTL
0Eh
Table 6-44. Timer0_A3 Registers (Base Address: 0300h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 control
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
TA0 expansion register 0
TA0 interrupt vector
TA0EX0
20h
TA0IV
2Eh
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Table 6-45. Timer1_A3 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1EX0
20h
TA1IV
2Eh
TA1 control
TA1 counter register
TA1 expansion register 0
TA1 interrupt vector
Table 6-46. RTC Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTCCTL
00h
RTCIV
04h
RTC modulo
RTCMOD
08h
RTC counter
RTCCNT
0Ch
RTC control
RTC interrupt vector
Table 6-47. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER
OFFSET
eUSCI_A control word 0
REGISTER DESCRIPTION
UCA0CTLW0
00h
eUSCI_A control word 1
UCA0CTLW1
02h
eUSCI_A control rate 0
UCA0BR0
06h
UCA0BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA0MCTLW
08h
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
lUCA0IRTCTL
12h
eUSCI_A IrDA receive control
IUCA0IRRCTL
13h
UCA0IE
1Ah
UCA0IFG
1Ch
UCA0IV
1Eh
eUSCI_A status
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Table 6-48. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER
OFFSET
eUSCI_B control word 0
REGISTER DESCRIPTION
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
66
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Table 6-48. eUSCI_B0 Registers (Base Address: 0540h) (continued)
REGISTER
OFFSET
eUSCI_B I2C own address 1
REGISTER DESCRIPTION
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B receive address
UCB0ADDRX
1Ch
UCB0ADDMASK
1Eh
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
UCB0I2CSA
20h
UCB0IE
2Ah
UCB0IFG
2Ch
UCB0IV
2Eh
Table 6-49. Backup Memory Registers (Base Address: 0660h)
REGISTER
OFFSET
Backup Memory 0
REGISTER DESCRIPTION
BAKMEM0
00h
Backup Memory 1
BAKMEM1
02h
Backup Memory 2
BAKMEM2
04h
Backup Memory 3
BAKMEM3
06h
Backup Memory 4
BAKMEM4
08h
Backup Memory 5
BAKMEM5
0Ah
Backup Memory 6
BAKMEM6
0Ch
Backup Memory 7
BAKMEM7
0Eh
Backup Memory 8
BAKMEM8
10h
Backup Memory 9
BAKMEM9
12h
Backup Memory 10
BAKMEM10
14h
Backup Memory 11
BAKMEM11
16h
Backup Memory 12
BAKMEM12
18h
Backup Memory 13
BAKMEM13
1Ah
Backup Memory 14
BAKMEM14
1Ch
Backup Memory 15
BAKMEM15
1Eh
Table 6-50. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC control register 0
ADCCTL0
00h
ADC control register 1
ADCCTL1
02h
ADC control register 2
ADCCTL2
04h
ADC window comparator low threshold
ADCLO
06h
ADC window comparator high threshold
ADCHI
08h
ADC memory control register 0
ADCMCTL0
0Ah
ADC conversion memory register
ADCMEM0
12h
ADCIE
1Ah
ADCIFG
1Ch
ADCIV
1Eh
ADC interrupt enable
ADC interrupt flags
ADC interrupt vector word
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6.12 Identification
6.12.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this
data sheet, see Section 8.2.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.10.
6.12.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
Section 8.2.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.10.
6.12.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320).
68
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430FR413x devices.
These guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail
ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters).
DVCC
Power Supply
Decoupling
+
10 µF
100 nF
DVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass
capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the
respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT
pin can be used for other purposes. If they are left unused, they must be terminated according to
Section 4.4.
Figure 7-2 shows a typical connection diagram.
XIN
CL1
XOUT
CL2
Figure 7-2. Typical Crystal Connection
See the application report MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on
selecting, testing, and designing a crystal oscillator with the MSP430 devices.
Applications, Implementation, and Layout
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7.1.3
www.ti.com
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the
target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate
the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide (SLAU278).
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
TEST
RST/NMI/SBWTDIO
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TCK
TMS
TCK
GND
RST
TEST/SBWTCK
C1
1 nF
(see Note B)
A.
B.
DVSS
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
70
Applications, Implementation, and Layout
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
1 nF
(see Note B)
A.
B.
DVSS
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown
capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the device family user’s guide (SLAU367) for more information on the referenced control registers
and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see Section 4.4.
Applications, Implementation, and Layout
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7.1.6
www.ti.com
General Layout Recommendations
•
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the
application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.
Proper bypass capacitors on DVCC and reference pins, if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
Refer to the Circuit Board Layout Techniques design guide (SLOA089) for a detailed discussion of
PCB layout considerations. This document is written primarily about op amps, but the guidelines are
generally applicable for all mixed-signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See the application report MSP430 System-Level ESD Considerations
(SLAA530) for guidelines.
Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in
Section 5.1, Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
7.2.1.1
Partial Schematic
DVSS
Using an
External
Positive
Reference
Using an
External
Negative
Reference
VREF+/VEREF+
+
10 µF
100 nF
VEREF+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
72
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Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-μF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A bypass capacitor of 100 nF is used to filter out any high-frequency noise.
7.2.1.3
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
Applications, Implementation, and Layout
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www.ti.com
8 Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Getting Started and Next Steps
For an introduction to the MSP430 family of devices and the tools and libraries that are available to help
with your development, visit the Getting Started page.
8.1.1.2
Development Tools Support
8.1.1.2.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMX.5
DEBUGGING
SUPPORT
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
8.1.1.2.2 Recommended Hardware Options
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
8.1.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
PACKAGE
TARGET BOARD AND PROGRAMMER BUNDLE
TARGET BOARD ONLY
64-pin LQFP (PM)
MSP-FET430U64D
MSP-TS430PM64D
8.1.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
8.1.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
8.1.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
PART NUMBER
MSP-GANG
74
PC PORT
FEATURES
PROVIDER
Serial and USB
Program up to eight devices at a time. Works with PC or as a
stand-alone device.
Texas Instruments
Device and Documentation Support
Copyright © 2014–2015, Texas Instruments Incorporated
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MSP430FR2033, MSP430FR2032
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SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
8.1.1.2.3 Recommended Software Options
8.1.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
8.1.1.2.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a stand-alone package.
8.1.1.2.3.3 Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the
need for an IDE.
8.1.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430FR2033). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications of the final
device
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI internal qualification testing.
MSP – Fully qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. TI recommends that these devices not be used in any production system because their expected
end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PM) and temperature range (for example, T). Figure 8-1 provides a legend for
reading the complete device name for any family member.
Device and Documentation Support
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MSP 430 FR 4 133 I PM T
Processor Family
430 MCU Platform
Device Type
Series
Feature Set
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
430 MCU Platform
TI’s 16-Bit Low-Power Microcontroller Platform
Device Type
Memory Type
FR = FRAM
Series
FRAM 4 Series = Up to 16 MHz with LCD
FRAM 2 Series = Up to 16 MHz without LCD
Feature Set
1 and 2 Digit – ADC Channels / 16-bit Timers / I/Os
13 = Up to 10 / 3 / Up to 60
Optional: Temperature Range
S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Distribution Format
T = Small reel
R = Large reel
No Marking = Tube or Tray
st
nd
rd
3 Digit – FRAM (KB) / SRAM (KB)
3 = 16 / 2
2=8/1
1 = 4 / 0.5
Figure 8-1. Device Nomenclature
8.2
Documentation Support
The following documents describe the MSP430FR203x microcontrollers. Copies of these documents are
available on the Internet at www.ti.com.
8.2.1
SLAU445
MSP430FR4xx and MSP430FR2xx Family User's Guide. Detailed description of all
modules and peripherals available in this device family.
SLAZ625
MSP430FR2033 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
SLAZ626
MSP430FR2032 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
76
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FR2033
Click here
Click here
Click here
Click here
Click here
MSP430FR2032
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Copyright © 2014–2015, Texas Instruments Incorporated
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MSP430FR2033, MSP430FR2032
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8.2.2
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.3
Trademarks
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.5
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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www.ti.com
9 Mechanical Packaging and Orderable Information
9.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
78
Mechanical Packaging and Orderable Information
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR2033 MSP430FR2032
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR2032IG48
ACTIVE
TSSOP
DGG
48
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2032
MSP430FR2032IG48R
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2032
MSP430FR2032IG56
ACTIVE
TSSOP
DGG
56
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2032
MSP430FR2032IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2032
MSP430FR2032IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2032
MSP430FR2032IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2032
MSP430FR2033IG48
ACTIVE
TSSOP
DGG
48
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2033
MSP430FR2033IG48R
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2033
MSP430FR2033IG56
ACTIVE
TSSOP
DGG
56
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2033
MSP430FR2033IG56R
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2033
MSP430FR2033IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2033
MSP430FR2033IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
FR2033
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2015
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.6
15.8
1.8
12.0
24.0
Q1
MSP430FR2032IG48R
TSSOP
DGG
48
2000
330.0
24.4
MSP430FR2032IG56R
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR2032IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430FR2033IG48R
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
MSP430FR2033IG56R
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
MSP430FR2033IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR2032IG48R
TSSOP
DGG
48
2000
367.0
367.0
45.0
MSP430FR2032IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
MSP430FR2032IPMR
LQFP
PM
64
1000
367.0
367.0
45.0
MSP430FR2033IG48R
TSSOP
DGG
48
2000
367.0
367.0
45.0
MSP430FR2033IG56R
TSSOP
DGG
56
2000
367.0
367.0
45.0
MSP430FR2033IPMR
LQFP
PM
64
1000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
SCALE 1.200
SMALL OUTLINE PACKAGE
C
8.3
TYP
7.9
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
6.2
6.0
29
56X
0.27
0.17
0.08
1.2 MAX
C A
B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
29
28
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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