Ordering number : EN6183A
Monolithic Digital IC
PWM Current Control Type
Stepping Motor Driver
LB11847
Overview
The LB11847 is a driver IC for stepping motors with PWM current control bipolar drive (fixed OFF time). A special
feature of this IC is that VREF voltage is constant while the current can be set in 15 steps, allowing drive of motors ranging
from 1-2 phase exciter types to 4W 1-2 phase exciter types. The current decay pattern can also be selected (SLOW
DECAY, FAST DECAY, MIX DECAY) to increase the decay of regenerative current at chopping OFF, thereby
improving response characteristics. This is especially useful for carriage and paper feed stepping motors in printers and
similar applications where highprecision control and low vibrations are required.
Features
• PWM current control (fixed OFF time)
• Load current digital selector (1-2, W1-2, 2W1-2, 4W1-2 phase exciter drive possible)
• Selectable current decay pattern (SLOW DECAY, FAST DECAY, MIX DECAY)
• Simultaneous ON prevention function (feedthrough current prevention)
• Noise canceler
• Built-in thermal shutdown circuit
• Built-in logic low-voltage OFF circuit
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Motor supply voltage
VBB
Output peak current
IOPEAK
Output continuous current
IO max
Logic supply voltage
VCC
Logic input voltage range
VIN
Emitter output voltage
VE
Conditions
tW ≤ 20μs
Ratings
Unit
50
V
1.75
A
1.5
A
7.0
V
-0.3 to VCC
V
1.0
V
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
90308 MS PC/61199RM(KI) No.6183-1/15
LB11847
Continued from preceding page.
Parameter
Allowable power dissipation
Symbol
Pd max
Conditions
Ratings
Unit
Ta = 25°C
3.0
W
With heat sink
20
W
Operating temperature
Topr
-20 to +85
°C
Storage temperature
Tstg
-55 to +150
°C
Allowable Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Motor supply voltage range
VBB
10 to 45
V
Logic supply voltage range
VCC
4.75 to 5.25
V
Reference voltage range
VREF
0.0 to 3.0
V
Electrical Characteristics at Ta = 25°C, VBB = 45V, VCC = 5V, VREF = 1.52V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Output block
Output stage supply voltage
Output saturation voltage
Output leak current
Output sustain voltage
IBB ON
2.3
3.5
5.0
mA
IBB OFF
0.5
0.8
1.1
mA
1.2
1.6
V
VO(sat) 1
IO = +1.0A, sink
VO(sat) 2
IO = +1.5A, sink
1.5
1.9
V
VO(sat) 3
IO = -1.0A, source
1.9
2.2
V
VO(sat) 4
IO = -1.5A, source
2.2
2.4
V
IO(leak) 1
VO = VBB, sink
50
μA
IO(leak) 2
VO = 0V, source
VSUS
L = 15 mH, IO = 1.5A, Guaranteed design value
-50
μA
45
V
Logic block
Logic supply current
Input voltage
ICC ON
I4 = 2.0V, I3 = 2.0V, I2 = 2.0V, I1 = 2.0V
19.5
26
36.5
mA
ICC OFF
ENABLE = 2.0V
10.5
15
19.5
mA
VIH
2.0
V
VIL
Input current
Sensing voltage
0.8
V
100
μA
IIH
VIH = 2.0V
IIL
VIL = 0.8V
VE
I4 = 2.0V, I3 = 2.0V, I2 = 2.0V, I1 = 2.0V
0.470
0.50
0.525
V
I4 = 2.0V, I3 = 2.0V, I2 = 2.0V, I1 = 0.8V
0.445
0.48
0.505
V
I4 = 2.0V, I3 = 2.0V, I2 = 0.8V, I1 = 2.0V
0.425
0.46
0.485
V
I4 = 2.0V, I3 = 2.0V, I2 = 0.8V, I1 = 0.8V
0.410
0.43
0.465
V
I4 = 2.0V, I3 = 0.8V, I2 = 2.0V, I1 = 2.0V
0.385
0.41
0.435
V
I4 = 2.0V, I3 = 0.8V, I2 = 2.0V, I1 = 0.8V
0.365
0.39
0.415
V
I4 = 2.0V, I3 = 0.8V, I2 = 0.8V, I1 = 2.0V
0.345
0.37
0.385
V
I4 = 2.0V, I3 = 0.8V, I2 = 0.8V, I1 = 0.8V
0.325
0.35
0.365
V
I4 = 0.8V, I3 = 2.0V, I2 = 2.0V, I1 = 2.0V
0.280
0.30
0.325
V
I4 = 0.8V, I3 = 2.0V, I2 = 2.0V, I1 = 0.8V
0.240
0.26
0.285
V
I4 = 0.8V, I3 = 2.0V, I2 = 0.8V, I1 = 2.0V
0.195
0.22
0.235
V
I4 = 0.8V, I3 = 2.0V, I2 = 0.8V, I1 = 0.8V
0.155
0.17
0.190
V
I4 = 0.8V, I3 = 0.8V, I2 = 2.0V, I1 = 2.0V
0.115
0.13
0.145
V
I4 = 0.8V, I3 = 0.8V, I2 = 2.0V, I1 = 0.8V
0.075
0.09
0.100
μA
-10
Reference current
IREF
VREF = 1.5V
-0.5
CR pin current
ICR
CR = 1.0V
-4.6
V
μA
-1.0
mA
MD pin current
IMD
MD = 1.0V, CR = 4.0V
-5.0
μA
DECAY pin current Low
IDECL
VDEC = 0.8V
-10
μA
DECAY pin current High
IDECH
VDEC = 2.0V
Thermal shutdown temperature
TSD
Logic ON voltage
LVSD1
3.35
3.65
3.95
V
Logic OFF voltage
LVSD2
3.20
3.50
3.80
V
LVSD hysteresis width
ΔLVSD
0.065
0.15
0.23
V
5
μA
°C
170
No.6183-2/15
LB11847
Package Dimensions
unit : mm (typ)
3147C
Pd max – Ta
15
12.7
11.2
R1.7
0.4
8.4
28
Allowable power dissipation, Pd max – W
25
1
14
20.0
4.0
4.0
26.75
(1.81)
0.6
1.78
20
With an arbitrary large heat sink
20.0
15
10.4
10
5
Independent IC
1.56
0
– 20
1.0
3.0
0
20
40
60
80
100
Ambient temperature, Ta – °C
SANYO : DIP28H(500mil)
VCC
PHASE1
ENABLE1
IA1
IA2
IA3
IA4
IB4
IB3
IB2
IB1
ENABLE2
PHASE2
GND
Pin Assignment
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LB11847
14
VBB
13
VREF2
12
CR2
11
E2
10
DECAY2
9
OUT B
8
OUT B
7
OUT A
6
OUT A
5
DECAY1
4
E1
3
CR1
2
VREF1
MD
1
Top view
No.6183-3/15
LB11847
Pin Function
Pin number
Pin name
Function descripyion
1
MD
Sets the OFF time for FAST mode and SLOW mode in MIX DECAY.
Setting input range: 4V to 1.5V
2
VREF1
13
VREF2
Output set current reference supply pins.
Setting voltage range: 0V to 3V
Output OFF time setting pins for switching operation.
3
CR1
12
CR2
4
E1
11
E2
Pins for controlling the set current with sensing resistor RE.
5
DECAY1
10
DECYA2
SLOW mode/FAST mode selector pins.
SLOW DECAY : H
FAST DECAY : L
6
OUT A
Output pins.
7
OUT A
8
OUT B
9
OUT B
14
VBB
Output stage supply voltage pin.
15
GND
Ground pin.
27
PHASE1
Output phase selector input pins.
16
PHASE2
26
ENABLE1
17
ENABLE2
22, 23
IA4, IA3
24, 25
IA2, IA1
21, 20
IB4, IB3
19, 18
IB2, IB1
28
Output ON/OFF setting input pins.
Output set current digital input pins.
15-stage voltage setting.
Logic block supply voltage pin.
VCC
Truth Table
PHASE
ENABLE
OUT A
OUT A
H
L
H
L
L
L
L
H
-
H
OFF
OFF
Set Current Truth Table
IA4
I A3
IA2
IA1
1
1
1
1
11.5/11.5 × VREF/3.04RE = IOUT
Set current IOUT
Current ratio (%)
100
1
1
1
0
11.0/11.5 × VREF/3.04RE = IOUT
95.65
1
1
0
1
10.5/11.5 × VREF/3.04RE = IOUT
91.30
1
1
0
0
10.0/11.5 × VREF/3.04RE = IOUT
86.95
1
0
1
1
9.5/11.5 × VREF/3.04RE = IOUT
82.61
1
0
1
0
9.0/11.5 × VREF/3.04RE = IOUT
78.26
1
0
0
1
8.5/11.5 × VREF/3.04RE = IOUT
73.91
1
0
0
0
8.0/11.5 × VREF/3.04RE = IOUT
69.56
0
1
1
1
7.0/11.5 × VREF/3.04RE = IOUT
60.87
0
1
1
0
6.0/11.5 × VREF/3.04RE = IOUT
52.17
0
1
0
1
5.0/11.5 × VREF/3.04RE = IOUT
43.48
0
1
0
0
4.0/11.5 × VREF/3.04RE = IOUT
34.78
0
0
1
1
3.0/11.5 × VREF/3.04RE = IOUT
26.08
0
0
1
0
2.0/11.5 × VREF/3.04RE = IOUT
17.39
* Current ratio (%) is the calculated set current value.
Current Decay Switching Truth Table
Current decay mode
DECAY pin
MD pin
Output chopping
SLOW DECAY
H
L
Upper-side chopping
FAST DECAY
L
L
Dual-side chopping
MIX DECAY
L
4V to 1.5V input
CR voltage > MD : dual-side chopping
voltage setting
CR voltage < MD : upper-side chopping
No.6183-4/15
GND
VREF1
circuit
selector
E1
E2
blanking
circuit
blanking
circuit
CR2
multi-
multi-
CR1
One-shot
One-shot
circuit
circuit
selector
VREF2
IB4
IA4
ENABLE2
DECAY2
IB3
Cuttent
circuit
Control logic
PHASE2
VCC
IA3
OUT B
IB2
OUT B
IA2
Thermal shutdown
VBB
IB1
Cuttent
circuit
Control logic
OUT A
IA1
ENABLE1
DECAY1
PHASE1
MD
OUT A
LB11847
Block Diagram
No.6183-5/15
LB11847
Sequence Table
Phase A
Phase B
No.
IA4
IA3
IA2
IA1 ENA1 PHA1
0
1
1
1
1
0
0
1
1
1
1
1
0
0
2
1
1
1
1
0
3
1
1
1
0
0
4
1
1
0
1
5
1
1
0
0
6
1
0
1
7
1
0
1
8
1
0
9
1
0
10
0
11
0
12
13
IOUT
Phase
Phase
Phase
Phase
IOUT
1-2
W1-2
2W1-2
4W1-2
*
0%
○
○
○
0
17.39
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
IB4
IB3
I B2
IB1
100%
0
0
1
0
1
100
0
0
1
0
0
0
100
0
0
1
1
0
0
26.08
0
95.65
0
1
0
0
0
0
34.78
0
0
91.30
0
1
0
1
0
0
43.48
0
0
86.95
0
1
1
0
0
0
52.17
1
0
0
82.61
0
1
1
1
0
0
60.87
0
0
0
78.26
1
0
0
0
0
0
69.56
0
1
0
0
73.91
1
0
0
1
0
0
73.91
0
0
0
0
69.56
1
0
1
0
0
0
78.26
1
1
1
0
0
60.87
1
0
1
1
0
0
82.61
1
1
0
0
0
52.17
1
1
0
0
0
0
86.95
0
1
0
1
0
0
43.48
1
1
0
1
0
0
91.30
0
1
0
0
0
0
34.78
1
1
1
0
0
0
95.65
14
0
0
1
1
0
0
26.08
1
1
1
1
0
0
100
15
0
0
1
0
0
0
17.39
1
1
1
1
0
0
100
16
0
0
0
1
1
*
1
1
1
1
0
0
100
17
0
0
1
0
0
1
17.39
1
1
1
1
0
0
100
18
0
0
1
1
0
1
26.08
1
1
1
1
0
0
100
19
0
1
0
0
0
1
34.78
1
1
1
0
0
0
95.65
20
0
1
0
1
0
1
43.48
1
1
0
1
0
0
91.30
21
0
1
1
0
0
1
52.17
1
1
0
0
0
0
86.95
22
0
1
1
1
0
1
60.87
1
0
1
1
0
0
82.61
23
1
0
0
0
0
1
69.56
1
0
1
0
0
0
78.26
24
1
0
0
1
0
1
73.91
1
0
0
1
0
0
73.91
25
1
0
1
0
0
1
78.26
1
0
0
0
0
0
69.56
26
1
0
1
1
0
1
82.61
0
1
1
1
0
0
60.87
27
1
1
0
0
0
1
86.95
0
1
1
0
0
0
52.17
28
1
1
0
1
0
1
91.30
0
1
0
1
0
0
43.48
29
1
1
1
0
0
1
95.65
0
1
0
0
0
0
34.78
30
1
1
1
1
0
1
100
0
0
1
1
0
0
26.08
31
1
1
1
1
0
1
100
0
0
1
0
0
0
17.39
0
ENA2 PHA2
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
* : Iout percentage (%) is the calculated setting value.
No.6183-6/15
LB11847
Switch Timing Chart during PWM Drive
SLOW DECAY (upper-side chopping)
DECAY pin : High
MD pin : Low
E pin
Output pin
tn
RC pin
Output pin
Switching waveform
FAST DECAY
DECAY pin : High
MD pin : Low
Noise spike
E pin
Output pin
RC pin
Output pin
Switching waveform
No.6183-7/15
LB11847
MIX DECAY
Noise spike
tm
E pin
Output pin
tn
RC pin
t on
Output pin
t off
Switching wavwform
ton
toff
tm
tn
: Output ON time
: Output OFF time
: FAST DECAY time in MIX DECAY mode
: Noise cancelling time
MIX DECAY logic setting
DECAY pin : L
MD pin : 1.5V to 4.0V voltage setting
CR voltage and MD pin voltage are compared to select dual-side chopping
or upper-side chopping.
CR voltage > MD pin voltage: dual-side chopping
CR voltage < MD pin voltage: top-side choppinng
No.6183-8/15
LB11847
SLOW DECAY current path
Regenerative current during upper-side transistor switching operation
ON
VBB
Current path at output ON
OFF
Regenerative circuit
when upper-side transistor is OFF
OUT A
OUT A
SBD
SBD
ON
Constant
Sensing voltage comparator
Re
Current path in FAST DECAY mode
VBB
ON
Current path at output ON
OFF
Current path in FAST DECAY mode
OUT A
SBD
SBD
OUT A
ON
Sensing voltage comparator
OFF
Re
No.6183-9/15
LB11847
Composite Vectors of Set Current (1 step normalized to 90°)
Phase B
IOUT
15
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Sequence No.
0
IOUT
Phase A
No.
θ
0
θ0
0°
100.0
1
θ1
9.87°
101.5
2
θ2
14.6°
103.35
3
θ3
20.0°
101.78
4
θ4
25.5°
101.12
5
θ5
30.96°
101.4
6
θ6
36.38°
102.61
7
θ7
41.63°
104.7
8
θ8
45.0°
104.5
9
θ9
48.37°
104.7
10
θ10
53.62°
102.61
11
θ11
59.04°
101.4
12
θ12
64.5°
101.12
13
θ13
70.0°
101.78
14
θ14
75.4°
103.35
15
θ15
80.13°
101.5
16
θ16
90.0°
100.0
Rotation angles
Composite vectors
* Rotation angle and composite spectrum are calculated values.
No.6183-10/15
LB11847
Set Current Waveform Model
Phase A
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
IOUT
Phase B
IOUT
PHASE1
PHASE2
No.6183-11/15
LB11847
Sample Application Circuit
5V
10μF
IA1
IA2
IA3
20
19
18
17
16
15
GND
ENABLE1
21
PHASE2
PHASE1
22
ENABLE2
23
IB1
24
IB2
25
IB3
26
IB4
27
IA4
28
VCC
Logic input
OUT A
OUT A
OUT B
OUT B
5
6
7
8
9
L
1.5V to 4.0V
voltage setting
10
11
12
13
VBB
DECAY1
4
VREF2
E1
3
CR2
CR1
2
E2
VREF1
1
DECAY2
MD
LB11847
14
L
SBD
SBD
SBD
42V
SBD
47μF
0.51Ω
1.5V
0.51Ω
15kΩ
15kΩ
470pF
470pF
Notes on Usage
1. External diodes
Because this IC uses upper-side transistor switching in SLOW DECAY mode and dual-side transistor switching in
FAST DECAY mode, it requires external diodes between the OUT pins and ground for the regenerative current during
switching OFF. Use Schottky barrier diodes with low VF.
2. VREF pin
Because the VREF pin serves for input of the set current reference voltage, precautions against noise must be taken.
The input voltage range is 0 to 3.0V.
3. GND pin
The ground circuit for this IC must be designed so as to allow for high-current switching. Blocks where high current
flows must use low-impedance patterns and must be removed from small-signal lines. Especially the ground
connection for the sensing resistor RE at pin E, and the ground connection for the Schottky barrier diodes should be in
close proximity to the IC ground.
The capacitors between VCC and ground, and VBB and ground should be placed close to the VCC and VBB pins,
respectively.
No.6183-12/15
LB11847
4. Simultaneous ON prevention function
This IC incorporates a circuit to prevent feedthrough current when phase switching. For reference, the output ON and
OFF delay times at PHASE and ENABLE switching are given below.
Reference data * typical value
Sink side
Source side
PHASE switching
ON delay time
1.9μs
2.2μs
(Low → High)
OFF delay time
0.8μs
1.8μs
PHASE switching
ON delay time
1.4μs
1.7μs
(High → Low)
OFF delay time
0.9μs
1.35μs
ENABLE switching
ON delay time
2.15μs
2.75μs
OFF delay time
1.2μs
5.8μs
5. Noise canceler
This IC has a noise canceling function to prevent malfunction due to noise spikes generated when switching ON. The
noise cancel time tn is determined by internal resistance of the CR pin and the constant of the externally connected CR
components. The constant also determines the switching OFF time.
Figure 1 shows the internal configuration at the CR pin, and Figure 2 shows the CR pin constant setting range.
Equation when logic voltage VCC = 5V
CR pin voltage E1 = VCC • R/(R1+R2+R) [V]
Noise cancel time tn ≈ (R1+R2) • C • 1n {(E1-1.5)/(E1-4.0)} [s]
Switching OFF time toff ≈ –R • C • 1n (1.5/E1) [s]
Internal resistance at CR pin : R1 = 1kΩ, R2 = 300Ω (typ.)
*The CR constant setting range in Figure 2 on page 16 is given for reference. It applies to a switching OFF time in the
range from 8 to 100μs. The switching time can also be made higher than 100μs. However, a capacitor value of more
than several thousand pF will result in longer noise canceling time, which can cause the output current to become
higher than the set current. The longer switching OFF time results in higher output current ripple, causing a drop in
average current and rotation efficiency. When keeping the switching OFF time within 100μs, it is recommended to stay
within the CR constant range shown in Figure 2.
Internal configuration at CR pin
VCC line
One-shot multi-blanking
time circuit
R1
CR pin
E1
C:470pF
1kΩ
R2
300Ω
R:15kΩ
Figure 1
No.6183-13/15
LB11847
Switching OFF Time and CR Setting Range
(toff time : approx. 8 to 100μs)
C [pF]
3000
t off time : 30μs
2000
t off time : 50μs
t off time : 100μs
1000
0
0
50k
100k
R [Ω]
Figure 2
No.6183-14/15
LB11847
ICC -- VCC
IBB -- VBB
5
Logic supply voltage : IA1, 2, 3, 4
PHA, ENA = VCC
typical value
Output stage supply current, IBB – mA
Logic supply current, ICC – mA
50
40
t ON
u
Outp
30
FF
ut O
Outp
20
10
0
Logic supply voltage : IA1, 2, 3, 4
PHA, ENA = VCC
typical value
4
N
Output O
3
2
Output OFF
1
0
0
1
2
3
4
5
6
7
0
Logic supply voltage, VCC – mV
Sink side
[typical value]
30
40
50
60
2.4
2.0
1.6
1.2
0.8
0.4
0
VO(sat) -- IO
2.8
Output saturation voltage, VO(sat) – V
Output saturation voltage, VO(sat) – V
20
Output stage supply voltage, VBB – V
VO(sat) -- IO
2.8
10
Source side
[typical value]
2.4
2.0
1.6
1.2
0.8
0.4
0
0
0.4
0.8
1.2
1.6
Output current, IO – A
2.0
2.4
0
0.4
0.8
1.2
1.6
2.0
2.4
Output current, IO – A
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PS No.6183-15/15