Cypress CY7C60323-LTXCT Encoreâ ¢ iii low voltage wireless presenter tool Datasheet

CY7C603xx
enCoRe™ III Low Voltage
enCoRe™ III Low Voltage
Features
Applications
■
Powerful Harvard-architecture processor
❐ M8C processor speeds to 12 MHz
❐ Low power at high speed
❐ 2.4 V to 3.6 V operating voltage
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Commercial temperature range: 0 °C to +70 °C
■
Wireless mice
■
Wireless gamepads
■
Wireless presenter tools
■
Wireless keypads
■
PlayStation® 2 wired gamepads
Configurable peripherals
❐ 8-bit timers, counters, and PWM
❐ Full duplex master or slave SPI
❐ 10-bit ADC
❐ 8-bit successive approximation ADC
❐ Comparator
■
PlayStation 2 bridges for wireless gamepads
❐ Applications requiring a cost effective low voltage 8-bit
microcontroller.
■
■
■
■
■
■
■
Logic Block Diagram
Flexible on-chip memory
❐ 8K flash program storage 50,000 erase/write cycles
❐ 512 bytes SRAM data storage
❐ In-System serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Port 3
Global Digital
Interconnect
Port 0
Global Analog Interconnect
SRAM
512 Bytes
SROM
Flash 8K
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources (Includes IMO and ILO)
Precision, programmable clocking
❐ Internal ±2.5% 24 and 48 MHz oscillator
❐ Internal oscillator for watchdog and sleep
enCoRe III LV Core
DIGITAL
SYSTEM
Programmable pin configurations
❐ 10 mA drive on all general purpose I/O (GPIO)
❐ Pull-up, pull-down, high-Z, strong, or open drain drive modes
on all GPIO
❐ Up to 8 analog inputs on GPIO
❐ Configurable interrupt on all GPIO
Digital
PSoC
Block
Array
Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of IO combinations
Digital
Clocks
Additional system resources
2
❐ I C master, slave, and Multimaster to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
•
Port 1
System Bus
Complete development tools
®
❐ Free development software (PSoC Designer™)
❐ Full-featured, In-circuit emulator and programmer
❐ Complex breakpoint structure
❐ 128K trace memory
Cypress Semiconductor Corporation
Document Number: 38-16018 Rev. *N
Port 2
198 Champion Court
POR and LVD
I2C
System Resets
ANALOG SYSTEM
Analog
PSoC
Block
Array
Switch
Mode
Pump
Analog
Ref.
Internal
Voltage
Ref.
Analog
Mux
SYSTEM RESOURCES
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 7, 2011
CY7C603xx
Contents
enCoRe III Low Voltage Functional Overview ................ 3
enCoRe III LV Core ..................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 3
Additional System Resources ..................................... 4
enCoRe III LV Device Characteristics ............................. 4
Getting Started .................................................................. 4
Development Kits ........................................................ 4
Development Tools .......................................................... 5
PSoC Designer Software Subsystems ........................ 5
In-Circuit Emulator ....................................................... 5
Designing with PSoC Designer ....................................... 6
Select Components ..................................................... 6
Configure Components ............................................... 6
Organize and Connect ................................................ 6
Generate, Verify, and Debug ....................................... 6
Pin Information ................................................................. 7
28-pin Part Pinout ........................................................ 7
32-pin Part Pinout ........................................................ 8
Register Reference ......................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Document Number: 38-16018 Rev. *N
Electrical Specifications ................................................ 15
Absolute Maximum Ratings ....................................... 16
Operating Temperature ............................................. 16
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 22
Packaging Information ................................................... 28
Packaging Dimensions .............................................. 28
Thermal Impedances ................................................ 30
Solder Reflow Peak Temperature ............................. 30
Ordering Information ...................................................... 31
Ordering Code Definitions ......................................... 31
Acronyms ........................................................................ 32
Acronyms Used ......................................................... 32
Reference Documents .................................................... 32
Document Conventions ................................................. 33
Units of Measure ....................................................... 33
Numeric Conventions ................................................ 33
Glossary .......................................................................... 33
Document History Page ................................................. 38
Sales, Solutions, and Legal Information ...................... 39
Worldwide Sales and Design Support ....................... 39
Products .................................................................... 39
PSoC® Solutions ...................................................... 39
Page 2 of 39
CY7C603xx
enCoRe III Low Voltage Functional Overview
Figure 1. Digital System Block Diagram
Port 3
The enCoRe III low voltage (enCoRe III LV) CY7C603xx device
is based on the flexible PSoC® architecture. This supports a
simple set of peripherals that can be configured to match the
needs of each application. Additionally, a fast CPU, flash
program memory, SRAM data memory, and configurable IO are
included in a range of convenient pinouts.
Port 1
Port 2
Digital Clocks
From Core
This architecture enables the user to create customized
peripheral configurations that match the requirements of each
individual application. A fast CPU, flash program memory, SRAM
data memory, and configurable IO are included in both 28-pin
SSOP and 32-pin QFN packages.
Port 0
To Analog
System
To System Bus
DIGITAL SYSTEM
The enCoRe III LV architecture, as shown in Figure 1, consists
of four main areas: the enCoRe III LV Core, the system
resources, digital system, and analog system. Configurable
global bus resources allow combining all the device resources
into a complete custom system. Each enCoRe III LV device
supports a limited set of digital and analog peripherals.
Depending on the package, up to 28 general purpose I/Os
(GPIOs) are also included. The GPIOs provide access to the
global digital and analog interconnects.
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
Row Input
Configuration
Digital enCoRe III LV Block Array
8
8
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
enCoRe III LV Core
The enCoRe III LV core is a powerful engine that supports a rich
feature set. It encompasses SRAM for data storage, an interrupt
controller, sleep and watchdog timers, and IMO (internal main
oscillator) and ILO (internal low-speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a four MIPS 8-bit
Harvard -architecture microprocessor. The core includes a CPU,
memory, clocks, and configurable GPIO.
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
The Analog System
System resources provide additional capability, such as digital
clocks to increase flexibility, I2C functionality for implementing an
I2C master, slave, multi-master, an internal voltage reference
that provides an absolute value of 1.3 V to a number of
subsystems, a switch mode pump (SMP) that generates normal
operating voltages off a single battery cell, and various system
resets supported by the M8C.
The analog system consists of two configurable blocks. Analog
peripherals are very flexible and may be customized to support
specific application requirements. Some of the common analog
functions for this device (available as user modules) are:
The Digital System
The digital system consists of 4 digital enCoRe III LV blocks.
Each block is an 8-bit resource. Digital peripheral configurations
include the following:
■
PWM usable as timer or counter
■
SPI master and slave
■
I2C slave and multi-master
■
CMP
■
ADC10
■
SARADC
Document Number: 38-16018 Rev. *N
■
Analog-to-digital converters (single with 8-bit resolution)
■
Pin-to-pin comparators
■
Single-ended comparators with absolute (1.3-V) reference
■
1.3-V reference (as a system resource)
Analog blocks are provided in columns of two, which includes
one continuous time (CT) (CT - ACE00 or ACE01) and one
switched capacitor (SC) (SC - ASE10 or ASE11) blocks.
Page 3 of 39
CY7C603xx
Figure 2. Analog System Block Diagram
enCoRe III LV Device Characteristics
The enCoRe III LV devices have four digital blocks and four
analog blocks. Table 1 lists the resources available for specific
enCoRe III LV devices.
Array Input
Configuration
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY7C60323PVXC
Analog
Outputs
AllIO
Analog
Inputs
ACI1[1:0]
Digital
Blocks
ACI0[1:0]
Digital
Rows
Part
Number
Digital
IO
Table 1. enCoRe III LV Device Characteristics
24
1
4
24
0
2
4
512
Bytes
8K
X
Getting Started
X
X
ACOL1MUX
X
Analog Mux Bus
X
Array
ACE00
ACE01
ASE10
ASE11
The Analog Multiplexer System
The analog mux bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with
comparators and analog-to-digital converters (ADC). An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Additional System Resources
System resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
The quickest path to understanding the enCoRe III LV silicon is
by reading this data sheet and using the PSoC Designer
integrated development environment (IDE). This data sheet is an
overview of the enCoRe III LV and presents specific pin, register,
and electrical specifications. enCoRe III LV is based on the
architecture of the CY8C21x34. For in-depth information, along
with detailed programming information, refer to the PSoC
Programmable System-on-Chip Technical Reference Manual,
which is available at http://www.cypress.com.
For up-to-date ordering, packaging, and electrical specification
information, refer to the latest device data sheets on the web at
http://www.cypress.com.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks may
be generated using digital blocks as clock dividers.
■
The I2C module provides 100 kHz and 400 kHz communication
over two wires. slave, master, and multi-master modes are all
supported.
■
Low voltage detection interrupts can signal the application of
falling voltage levels, while the advanced power-on reset (POR)
circuit eliminates the need for a system supervisor.
■
An internal 1.3-V voltage reference provides an absolute
reference for the analog system.
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
■
An integrated switch mode pump generates normal operating
voltages from a single 1.2 V battery cell, providing a low-cost
boost converter.
Technical Support
■
Versatile analog multiplexer system.
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Document Number: 38-16018 Rev. *N
Page 4 of 39
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
CY7C603xx
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
■
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC's resources for an application.
Document Number: 38-16018 Rev. *N
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Page 5 of 39
CY7C603xx
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All of the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information that you may need to
successfully implement your design.
Document Number: 38-16018 Rev. *N
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It lets you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
Page 6 of 39
CY7C603xx
Pin Information
The enCoRe III LV device is available in 28-pin SSOP and 32-pin QFN packages. Every port pin (labeled with a “P”) is capable of
Digital IO and connection to the common analog bus. However, Vss, VDD, SMP, and XRES are not capable of Digital IO.
28-pin Part Pinout
Figure 3. CY7C60323-PVXC 28-pin Device
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
Vss
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
Table 2. Pin Definitions - CY7C60323-PVXC 28-pin Device
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Type
Digital
Analog
IO
I, M
IO
I, M
IO
I, M
IO
I, M
IO
M
IO
M
IO
I, M
IO
I, M
Power
IO
M
IO
M
IO
M
IO
M
Power
IO
M
IO
M
IO
M
IO
M
Input
IO
I, M
IO
I, M
IO
M
IO
M
IO
I, M
IO
I, M
IO
I, M
IO
I, M
Power
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output, integrating input.
Analog column mux input, integrating input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Ground connection.
I2C serial clock (SCL).
I2C serial data (SDA).
I2C SCL, ISSP-SCLK.
Ground connection.
I2C SDA, ISSP-SDATA.
Optional external clock input (EXTCLK).
Active HIGH external reset with internal pull down.
Direct switched capacitor block input.
Direct switched capacitor block input.
Analog column mux input
Analog column mux input
Analog column mux input
Analog column mux input
Supply voltage.
LEGEND A = analog, I = input, O = output, and M = analog mux input.
Document Number: 38-16018 Rev. *N
Page 7 of 39
CY7C603xx
32-pin Part Pinout
P0[4], A, I, M
P0[2], A, I, M
26
25
A, I, M
Vss
P0[3],
P0[5],
P0[7],
Vdd
P0[6],
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QFN
(Top View)
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
M, I2C SDA, P1[5]
M, P1[3]
9
10
11
12
13
14
15
16
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
M, P3[1]
M, I2C SCL, P1[7]
32
31
30
29
28
27
A, I, M
A, I, M
A, I, M
Figure 4. CY7C60323-LFXC 32-pin Device
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
30
29
28
27
26
25
QFN
9
10
11
12
13
14
15
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK,
M, P1[4]
P1[6]
(Top View)
Document Number: 38-16018 Rev. *N
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
M, I2C SDA, P1[5]
M, P1[3]
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
Vss
M, I2C SCL, P1[7]
32
31
Figure 5. CY7C60333-LFXC 32-pin Device
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
Page 8 of 39
CY7C603xx
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QFN
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
9
10
11
12
13
14
15
16
M, P3[1]
M, 12C SCL, P1[7]
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Figure 6. CY7C60323-LTXC 32-pin Device Sawn
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
1
2
3
4
5
6
7
8
QFN
24
23
22
21
20
19
18
17
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M, 12C SDA, P1[5]
M, P1[3]
M, 12C SCL, P1[1]
Vss
M, 12C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
9
10
11
12
13
14
15
16
Vss
M, 12C SCL, P1[7]
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Figure 7. CY7C60333-LTXC 32-pin Device Sawn
Document Number: 38-16018 Rev. *N
Page 9 of 39
CY7C603xx
Table 3. 32-pin Part Pinout (QFN[1])
Pin
No.
Type
Name
Description
Digital
Analog
1
IO
I, M
P0[1]
2
IO
M
P2[7]
3
IO
M
P2[5]
4
IO
M
P2[3]
5
IO
M
P2[1]
6
IO
M
P3[3]
In CY7C60323 part.
SMP
Switch mode pump (SMP) connection to required external components in CY7C60333
part.
P3[1]
In CY7C60323 Part.
6
7
Power
IO
7
M
Power
Vss
Analog column mux input, integrating input.
Ground connection in CY7C60333 part.
8
IO
M
P1[7]
I2C serial clock (SCL).
9
IO
M
P1[5]
I2C serial data (SDA).
10
IO
M
P1[3]
11
IO
M
P1[1]
12
Power
Vss
13
IO
M
P1[0]
14
IO
M
P1[2]
15
IO
M
P1[4]
16
IO
17
M
Input
I2C SCL, ISSP-SCLK.
Ground connection.
I2C SDA, ISSP-SDATA.
Optional external clock input (EXTCLK).
P1[6]
XRES
Active HIGH external reset with internal pull-down.
18
IO
M
P3[0]
19
IO
M
P3[2]
20
IO
M
P2[0]
21
IO
M
P2[2]
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Analog column mux input.
25
IO
I, M
P0[2]
Analog column mux input.
26
IO
I, M
P0[4]
Analog column mux input.
27
IO
I, M
P0[6]
Analog column mux input.
28
Power
VDD
Supply voltage.
29
IO
I, M
P0[7]
Analog column mux input.
30
IO
I, M
P0[5]
Analog column mux input
31
IO
I, M
P0[3]
Analog column mux input, integrating input.
32
Power
Vss
Ground connection.
LEGEND A = analog, I = input, O = output, and M = analog mux input.
Note
1. The QFN package has a center pad that must be connected to ground (Vss).
Document Number: 38-16018 Rev. *N
Page 10 of 39
CY7C603xx
Register Reference
Register Mapping Tables
This section lists the registers of the enCoRe III LV device. For
detailed register information, refer the PSoC System-on-Chip
Technical Reference Manual.
The enCoRe III LV device has a total register address space of
512 bytes. The register space is referred to as IO space and is
divided into two banks, Bank 0 and Bank 1. The XOI bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XOI bit is set to 1 the user is in Bank 1.
Register Conventions
The register conventions specific to this section are listed in
Table 4.
Table 4. Register Conventions
Convention
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Table 5. Register Map 0 Table: User Space
Name
Addr
(0,Hex) Access
Name
Addr
(0,Hex)
Access
Name
Access
80
RW
Name
Addr
(0,Hex)
Access
PRT0DR
00
RW
40
PRT0IE
01
RW
41
81
C1
PRT0GS
02
RW
42
82
C2
PRT0DM2
03
RW
43
83
C3
PRT1DR
04
RW
44
PRT1IE
05
RW
45
85
C5
PRT1GS
06
RW
46
86
C6
PRT1DM2
07
RW
47
87
C7
PRT2DR
08
RW
48
88
C8
PRT2IE
09
RW
49
89
C9
PRT2GS
0A
RW
4A
8A
CA
PRT2DM2
0B
RW
4B
8B
CB
PRT3DR
0C
RW
4C
8C
CC
PRT3IE
0D
RW
4D
8D
CD
PRT3GS
0E
RW
4E
8E
CE
PRT3DM2
0F
RW
4F
8F
CF
10
50
90
CUR_PP
D0
RW
11
51
91
STK_PP
D1
RW
12
52
92
13
53
93
IDX_PP
D3
RW
14
54
94
MVR_PP
D4
RW
15
55
95
MVW_PP
D5
RW
16
56
96
I2C_CFG
D6
RW
17
57
97
I2C_SCR
D7
#
18
58
98
I2C_DR
D8
RW
19
59
99
I2C_MSCR
D9
#
1A
5A
9A
INT_CLR0
DA
RW
1B
5B
9B
INT_CLR1
DB
RW
1C
5C
Blank fields are Reserved and must not be accessed.
Document Number: 38-16018 Rev. *N
ASE10CR0
Addr
(0,Hex)
ASE11CR0
84
9C
C0
RW
C4
D2
DC
# Access is bit specific.
Page 11 of 39
CY7C603xx
Table 5. Register Map 0 Table: User Space (continued)
Name
Addr
(0,Hex) Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
1D
5D
9D
INT_CLR3
DD
RW
1E
5E
9E
INT_MSK3
DE
RW
1F
5F
9F
DF
DBB00DR0
20
#
AMX_IN
60
RW
A0
INT_MSK0
E0
RW
DBB00DR1
21
W
AMUXCFG
61
RW
A1
INT_MSK1
E1
RW
DBB00DR2
22
RW
PWM_CR
62
RW
A2
INT_VC
E2
RC
DBB00CR0
23
#
A3
RES_WDT
E3
W
DBB01DR0
24
#
DBB01DR1
25
W
DBB01DR2
26
RW
DBB01CR0
27
#
DCB02DR0
28
#
ADC0_CR
68
#
A8
E8
DCB02DR1
29
W
ADC1_CR
69
#
A9
E9
DCB02DR2
2A
RW
6A
AA
EA
DCB02CR0
2B
#
6B
AB
EB
DCB03DR0
2C
#
TMP_DR0
6C
RW
AC
EC
DCB03DR1
2D
W
TMP_DR1
6D
RW
AD
ED
DCB03DR2
2E
RW
TMP_DR2
6E
RW
AE
EE
DCB03CR0
2F
#
TMP_DR3
6F
RW
AF
63
CMP_CR0
64
#
65
CMP_CR1
66
RW
67
A4
E4
A5
E5
A6
DEC_CR0
E6
RW
A7
DEC_CR1
E7
RW
EF
30
70
RDI0RI
B0
RW
F0
31
71
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
34
74
RDI0LT1
B4
RW
F4
35
75
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
B7
F6
CPU_F
F7
RL
38
78
B8
F8
39
79
B9
F9
3A
7A
BA
FA
3B
7B
BB
FB
3C
7C
BC
3D
7D
BD
DAC_D
FD
RW
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
Document Number: 38-16018 Rev. *N
FC
# Access is bit specific.
Page 12 of 39
CY7C603xx
Table 6. Register Map 1 Table: Configuration Space
Name
Addr
(1,Hex) Access
Name
Addr
(1,Hex)
Access
Name
ASE10CR0
Addr
(1,Hex)
Access
80
RW
Name
Addr
(1,Hex)
PRT0DM0
00
RW
40
PRT0DM1
01
RW
41
81
C1
PRT0IC0
02
RW
42
82
C2
PRT0IC1
03
RW
43
PRT1DM0
04
RW
44
83
PRT1DM1
05
RW
45
85
C5
PRT1IC0
06
RW
46
86
C6
ASE11CR0
84
Access
C0
C3
RW
C4
PRT1IC1
07
RW
47
87
C7
PRT2DM0
08
RW
48
88
C8
PRT2DM1
09
RW
49
89
C9
PRT2IC0
0A
RW
4A
8A
CA
PRT2IC1
0B
RW
4B
8B
CB
PRT3DM0
0C
RW
4C
8C
CC
PRT3DM1
0D
RW
4D
8D
CD
PRT3IC0
0E
RW
4E
8E
CE
PRT3IC1
0F
RW
4F
8F
10
50
90
GDI_O_IN
CF
D0
RW
11
51
91
GDI_E_IN
D1
RW
12
52
92
GDI_O_OU
D2
RW
13
53
93
GDI_E_OU
D3
RW
14
54
94
D4
15
55
95
D5
16
56
96
D6
17
57
97
18
58
98
MUX_CR0
D8
RW
19
59
99
MUX_CR1
D9
RW
1A
5A
9A
MUX_CR2
DA
RW
MUX_CR3
DB
RW
D7
1B
5B
9B
1C
5C
9C
1D
5D
9D
OSC_GO_EN
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
DC
9F
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
DBB01FN
24
RW
CMP_GO_EN
64
RW
A4
VLT_CMP
E4
R
DBB01IN
25
RW
A5
ADC0_TR
E5
RW
DBB01OU
26
RW
ADC1_TR
E6
RW
DCB02FN
28
RW
68
A8
IMO_TR
E8
DCB02IN
29
RW
69
A9
ILO_TR
E9
W
DCB02OU
2A
RW
6A
AA
BDG_TR
EA
RW
AB
ECO_TR
EB
W
23
27
2B
65
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
CLK_CR3
6B
Blank fields are Reserved and must not be accessed.
Document Number: 38-16018 Rev. *N
RW
E7
W
# Access is bit specific.
Page 13 of 39
CY7C603xx
Table 6. Register Map 1 Table: Configuration Space (continued)
Name
DCB03FN
Addr
(1,Hex) Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
2C
RW
TMP_DR0
6C
RW
AC
EC
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
TMP_DR3
6F
RW
AF
2F
30
70
31
71
EF
RDI0RI
B0
RW
F0
RDI0SYN
B1
RW
F1
32
ACE00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACE00CR2
73
RW
RDI0LT0
B3
RW
F3
RDI0LT1
B4
RW
F4
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
34
74
35
75
36
ACE01CR1
76
RW
37
ACE01CR2
77
RW
38
78
B7
Access
F6
CPU_F
B8
F7
RL
F8
39
79
B9
3A
7A
BA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
DAC_CR
FD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Blank fields are Reserved and must not be accessed.
Document Number: 38-16018 Rev. *N
F9
FLS_PR1
FA
RW
RW
# Access is bit specific.
Page 14 of 39
CY7C603xx
Electrical Specifications
This section presents the DC and AC electrical specifications of the enCoRe III LV device. For up-to-date electrical specifications,
check the latest data sheet by visiting the web at http://www.cypress.com.
Specifications are valid for 0 °C  TA  70 °C and TJ  85 °C as specified, except where noted.
Refer to Table 19 on page 22 for the electrical specifications for the internal main oscillator (IMO) using SLIMO mode.
Figure 10. Voltage versus CPU Frequency
Figure 11. IMO Frequency Trim Options
3.60 V
Valid
Operating
Region
3.00
V
Vdd Voltage
Vdd Voltage
3.60
V
2.70
V
2.40
V
SLIMO
Mode=1
3.00 V
SLIMO
Mode=0
SLIMO SLIMO
Mode=1 Mode=1
2.40 V
93 kHz
3 MHz
CPU Frequency
12 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
The allowable CPU operating region for 12 MHz has been extended down to 2.7 V from the original 3.0 V design target. The customer’s
application is responsible for monitoring voltage and throttling back CPU speed in accordance with Figure 10 when voltage
approaches 2.7 V. Refer to Table 16 for LVD specifications. Note that the device does not support a preset trip at 2.7 V. To detect VDD
drop at 2.7 V, an external circuit or device such as the WirelessUSB LP - CYRF6936 must be employed; or if the design permits, the
nearest LVD trip value at 2.9 V can be used.
Document Number: 38-16018 Rev. *N
Page 15 of 39
CY7C603xx
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Parameter
TSTG
Description
Storage temperature
Min
Typ
Max
Unit
–40
–
+90
°C
125
See
package
label
°C
72
Hours
+70
°C
TBAKETEMP Bake temperature
TBAKETIME Bake time
See
package
label
TA
Ambient temperature with power applied
VDD
Supply voltage on VDD relative to Vss
VIO
DC input voltage
VIOZ
DC voltage applied to tri-state
IMIO
Maximum current into any port pin
ESD
Electro static discharge voltage
LU
Latch up current
0
–
–0.5
–
5
V
Vss – 0.5
–
VDD + 0.5
V
Vss – 0.5
–
VDD + 0.5
V
–25
–
+25
mA
2000
–
–
V
–
–
200
mA
Notes
Higher storage temperatures
reduce data retention time.
Human body model ESD.
Operating Temperature
Table 8. Operating Temperature
Parameter
Min
Typ
Max
Unit
TA
Ambient temperature
Description
0
–
+70
°C
TJ
Junction temperature
0
–
+85
°C
Document Number: 38-16018 Rev. *N
Notes
The temperature rise from ambient
to junction is package specific. See
Table 31 on page 30. The user must
limit the power consumption to
comply with this requirement.
Page 16 of 39
CY7C603xx
DC Electrical Characteristics
DC Chip-Level Specifications
Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 9. DC Chip-Level Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VDD
Supply voltage
2.40
–
3.6
V
IDD3
Supply current, IMO = 6 MHz using SLIMO
mode.
–
1.2
2
mA
See Table 16 on page 20.
Conditions are VDD = 3.3 V,
TA = 25 °C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
IDD27
Supply current, IMO = 6 MHz using SLIMO
mode.
–
1.1
1.5
mA
Conditions are VDD = 2.55 V,
TA = 25 °C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
ISB27
Sleep (Mode) current with POR, LVD, sleep
timer, WDT, and internal slow oscillator
active. Mid temperature range.
–
2.6
4.
A
VDD = 2.55 V, 0 °C <TA < 40 °C.
ISB
Sleep (Mode) current with POR, LVD, sleep
timer, WDT, and internal slow oscillator
active.
–
2.8
5
A
VDD = 3.3 V, 0 °C <TA < 70 °C.
VREF
Reference voltage (Bandgap)
1.28
1.30
1.32
V
Trimmed for appropriate VDD.
VDD = 3.0 V to 3.6 V.
VREF27
Reference voltage (Bandgap)
1.16
1.30
1.33
V
Trimmed for appropriate VDD.
VDD = 2.4 V to 3.0 V.
AGND
Analog ground
VREF –
0.003
VREF
VREF +
0.003
V
DC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, and 2.7 V at 25 °C and
are for design guidance only.
Table 10. 3.3 V DC GPIO Specifications
Parameter
Description
Min
Typ
Max
Unit
4
5.6
8
k
Pull-down resistor
4
5.6
8
k
High output level
VDD –
1.0
–
–
V
IOH = 3 mA, VDD > 3.0 V
VOL
Low output level
–
–
0.75
V
IOL = 10 mA, VDD > 3.0 V
IOH
High level source current
3
–
–
mA
IOL
Low level sink current
10
–
–
mA
VIL
Input low level
–
–
0.8
VIH
Input high level
2.1
–
VH
Input hysteresis
–
60
–
mV
IIL
Input leakage (absolute value)
–
1
–
nA
Gross tested to 1 A.
CIN
Capacitive load on pins as input
–
3.5
10
pF
Package and pin dependent.
Temp = 25 °C.
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 °C.
RPU
Pull-up resistor
RPD
VOH
Document Number: 38-16018 Rev. *N
Notes
V
VDD = 3.0 to 3.6.
V
VDD = 3.0 to 3.6.
Page 17 of 39
CY7C603xx
Table 11. 2.7V DC GPIO Specifications
Parameter
Description
Min
Typ
Max
Unit
4
5.6
8
k
Pull-down resistor
4
5.6
8
k
High output level
VDD –
0.4
–
–
V
IOH = 2.5 mA (6.25 Typ), VDD = 2.4
to 3.0 V (16 mA maximum, 50 mA
Typ combined IOH budget).
VOL
Low output level
–
–
0.75
V
IOL = 10 mA, VDD = 2.4 to 3.0 V
(90 mA maximum combined IOL
budget).
IOH
High level source current
2.5
–
–
mA
IOL
Low level sink current
10
–
–
mA
VIL
Input low level
–
–
0.75
V
VDD = 2.4 to 3.0.
VDD = 2.4 to 3.0.
RPU
Pull-up resistor
RPD
VOH
Notes
VIH
Input high level
2.0
–
–
V
VH
Input hysteresis
–
90
–
mV
IIL
Input leakage (absolute value)
–
1
–
nA
Gross tested to 1 A.
CIN
Capacitive load on pins as input
–
3.5
10
pF
Package and pin dependent.
Temp = 25 °C.
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 °C.
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 12. 3.3-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Min
Typ
Max
Units
Notes
–
2.5
15
mV
TCVOSOA Average input offset voltage drift
–
10
–
µV/C
IEBOA
Input leakage current (Port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
IEBOA00
Input leakage current (Port 0, Pin 0 analog pin)
–
50
–
nA
Gross tested to 1 µA
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 C
VCMOA
Common mode voltage range
0
–
VDD – 1
V
GOLOA
Open loop gain
–
80
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Min
Typ
Max
Units
–
2.5
15
mV
Table 13. 2.7-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Notes
TCVOSOA Average input offset voltage drift
–
10
–
µV/C
IEBOA
Input leakage current (Port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
IEBOA00
Input leakage current (Port 0, Pin 0 analog pin)
–
50
–
nA
Gross tested to 1 µA
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 C
VCMOA
Common mode voltage range
0
–
VDD – 1
V
GOLOA
Open loop gain
–
80
–
dB
ISOA
Amplifier supply current
–
10
30
µA
Document Number: 38-16018 Rev. *N
Page 18 of 39
CY7C603xx
DC Switch Mode Pump Specifications
Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 14. DC Switch Mode Pump (SMP) Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VPUMP3V
3.3 V output voltage from pump
3.00
3.25
3.60
V
Configurated as in Note 2.
Average, neglecting ripple.
SMP trip voltage is set to 3.25 V.
VPUMP2V
2.6 V output voltage from pump
2.45
2.55
2.80
V
Configurated as in Note 2.
Average, neglecting ripple.
SMP trip voltage is set to 2.55 V.
IPUMP
Available output current
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.3 V, VPUMP = 2.55 V
8
8
–
–
–
–
mA
mA
VBAT3V
Input voltage range from battery
1.0
–
3.3
V
Configurated as in Note 2.
SMP trip voltage is set to 3.25 V.
VBAT2V
Input voltage range from battery
1.0
–
2.8
V
Configurated as in Note 2.
SMP trip voltage is set to 2.55 V.
VBATSTART
Minimum input voltage from battery to start
pump
1.2
–
–
V
Configurated as in Note 2.
0 °C < TA < 100 °C.
1.25 V at TA = –40 °C.
VPUMP_Line
Line regulation (over Vi range)
–
5
–
%VO
Configurated as in Note 2. VO is the
VDD value for PUMP trip specified by
the VM[2:0] setting in the DC POR
and LVD specification, Table 16 on
page 20.
VPUMP_Load
Load regulation
–
5
–
%VO
Configurated as in Note 2. VO is the
“VDD Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD specification, Table 16 on
page 20.
–
100
–
mVpp Configurated as in Note 2. Load is
5 mA.
VPUMP_Ripple Output vovltage ripple (depends on
cap/load)
Configurated as in Note 2.
SMP trip voltage is set to 3.25 V.
SMP trip voltage is set to 2.55 V.
E3
Efficiency
35
50
–
%
Configurated as in Note 2. Load is
5 mA.
SMP trip voltage is set to 3.25 V.
E2
Efficiency
35
80
–
%
For I load = 1 mA, VPUMP = 2.55 V,
VBAT = 1.3 V, 10 H inductor, 1 F
capacitor, and Schottky diode.
FPUMP
Switching frequency
–
1.3
–
MHz
DCPUMP
Switching duty cycle
–
50
–
%
Note
2. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 12 on page 20.
Document Number: 38-16018 Rev. *N
Page 19 of 39
CY7C603xx
Figure 12. Basic Switch Mode Pump Circuit
D
1
Vdd
enCoRe III LV
L1
VBAT
+
VPUMP
SMP
C
1
Battery
Vss
DC Analog Mux Bus Specifications
Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70° C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 15. DC Analog Mux Bus Specifications
Min
Typ
Max
Unit
RSW
Parameter
Switch resistance to common analog bus
Description
–
–
400
800


RVDD
Resistance of initialization switch to VDD
–
–
800

Notes
VDD > 2.7 V
2.4 V <VDD <2.7 V
DC POR and LVD Specifications
Table 16 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 16. DC POR and LVD Specifications
Parameter
Description
VPPOR0
VPPOR1
VDD value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
VLVD0
VM[2:0] = 000b
Min
Typ
Max
Unit
Notes
VDD must be greater than or equal to
2.5 V during startup, reset from the
XRES pin, or reset from Watchdog.
–
2.36
2.82
2.40
2.95
V
V
2.40
2.45
2.51[3]
V
V
VDD value for LVD Trip
VLVD1
VM[2:0] = 001b
2.85
2.92
2.99[4]
VLVD2
VM[2:0] = 010b
2.95
3.02
3.09
V
VLVD37
VM[2:0] = 011b
3.06
3.13
3.20
V
VDD value for PUMP Trip
VPUMP0
VM[2:0] = 000b
2.45
2.55
2.62[5]
V
VPUMP1
VM[2:0] = 001b
2.96
3.02
3.09
V
VPUMP2
VM[2:0] = 010b
3.03
3.10
3.16
V
VPUMP3
VM[2:0] = 011b
3.18
3.25
3.32[6]
V
Notes
3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
5. Always greater than 50 mV above VLVD0.
6. Always greater than 50 mV above VLVD3.
Document Number: 38-16018 Rev. *N
Page 20 of 39
CY7C603xx
DC Programming Specifications
Table 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 17. DC Programming Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VDDP
VDD for programming and erase
4.5
5.0
5.5
V
This specification applies to the
functional requirements of external
programmer tools.
VDDLV
Low VDD for verify
2.4
2.5
2.6
V
This specification applies to the
functional requirements of external
programmer tools.
VDDHV
High VDD for verify
3.5
3.6
3.7
V
This specification applies to the
functional requirements of external
programmer tools.
VDDIWRITE
Supply voltage for flash write operation
2.7
–
3.6
V
This specification applies to this
device when it is executing internal
flash writes.
IDDP
Supply current during programming or verify
–
5
25
mA
VILP
Input low voltage during programming or verify
–
–
0.8
V
VIHP
Input high voltage during programming or verify
2.1
–
–
V
IILP
Input current when applying Vilp to P1[0] or
P1[1] during programming or verify
–
–
0.2
mA
Driving internal pull down resistor.
IIHP
Input current when applying Vihp to P1[0] or
P1[1] during programming or verify
–
–
1.5
mA
Driving internal pull down resistor.
VOLV
Output low voltage during programming or
verify
–
–
Vss + 0.75
V
VOHV
Output high voltage during programming or
verify
VDD – 1.0
–
VDD
V
FlashENPB
Flash endurance (per block)
50,000[7]
–
–
–
Erase/write cycles per block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
(total)[8]
FlashENT
Flash dndurance
FlashDR
Flash data retention
DC I2C Specifications
Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 18. DC I2C Specifications[9]
Symbol
VILI2C
VIHI2C
Description
Input low level
Input high level
Min
–
0.7 × VDD
Typ
–
–
Max
0.3 × VDD
–
Units
V
V
Notes
2.4 V VDD 3.6 V
2.4 V VDD 3.6 V
Notes
7. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V and
3.0 V to 3.6 V.
8. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
9. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 38-16018 Rev. *N
Page 21 of 39
CY7C603xx
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 19. 3.3 V AC Chip-Level Specifications
Description
Min
Typ
Max
Unit
FIMO24
Parameter
Internal main oscillator frequency for 24 MHz
23.4
24
24.6[10, 11]
MHz
Trimmed for 3.3 V operation
using factory trim values. See
Figure 11 on page 15. SLIMO
mode = 0.
FIMO6
Internal main oscillator frequency for 6 MHz
5.5
6
6.5[10, 11]
MHz
Trimmed for 3.3 V operation
using factory trim values. See
Figure 11 on page 15. SLIMO
mode = 1.
FCPU2
CPU frequency (3.3 V nominal)
0.093
12
12.3[10, 11]
MHz
SLIMO mode = 0.
MHz
FBLK33
Digital block frequency (3.3 V nominal)
0
24
24.6[10, 12]
F32K1
Internal low speed oscillator frequency
15
32
64
kHz
F32K_U
Internal low speed oscillator untrimmed
frequency
5
–
100
kHz
DCILO
Internal low speed oscillator duty cycle
20
50
80
%
TXRST
External reset pulse width
10
–
–
s
DC24M
24 MHz duty cycle
40
50
60
%
Step24M
24 MHz Trim step size
–
50
–
kHz
Fout48M
48 MHz output frequency
46.8
48.0
49.2[11]
MHz
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
SRPOWER_UP Power supply slew rate
–
–
250
V / ms
TPOWERUP
Time from end of POR to CPU executing
code
–
16
100
ms
tjit_IMO
24-MHz IMO cycle-to-cycle jitter (RMS)[13]
–
200
700
ps
24-MHz IMO long term N cycle-to-cycle jitter
(RMS)[13]
–
300
900
ps
24-MHz IMO period jitter (RMS)[13]
–
100
400
ps
Notes
Trimmed. Using factory trim
values.
N = 32
Notes
10. Accuracy derived from Internal Main Oscillator with appropriate trim for VDD range.
11. 3.0 V < VDD < 3.6 V.
12. See the individual user module data sheets for information on maximum frequencies for user modules.
13. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” for more information.
Document Number: 38-16018 Rev. *N
Page 22 of 39
CY7C603xx
Table 20. 2.7 V AC Chip-Level Specifications
Description
Min
Typ
Max
Unit
FIMO12
Parameter
Internal main oscillator (IMO) frequency for
12 MHz
11.5
120
12.7[14, 15]
MHz
Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 15. SLIMO
mode = 1.
FIMO6
IMO frequency for 6 MHz
5.5
6
6.5[14, 15]
MHz
Trimmed for 2.7 V operation
using factory trim values. See
Figure 11 on page 15. SLIMO
mode = 1.
FCPU1
CPU frequency (2.7 V nominal)
0.093
3
3.15[14, 15]
MHz
12 MHz only for SLIMO mode = 0.
12.5[14, 15]
MHz
Refer to the AC digital block
specifications.
FBLK27
Digital block frequency (2.7 V nominal)
0
12
F32K1
Internal low speed oscillator frequency
8
32
96
kHz
F32K_U
Internal low speed oscillator untrimmed
frequency
5
–
100
kHz
DCILO
Internal low speed oscillator duty cycle
20
50
80
%
TXRST
External reset pulse width
10
–
–
s
FMAX
Maximum frequency of signal on row input or
row output.
–
–
12.3
MHz
SRPOWER_UP Power supply slew rate
–
–
250
V / ms
TPOWERUP
Time from End of POR to CPU executing
code
–
16
100
ms
tjit_IMO
12 MHz IMO cycle-to-cycle jitter (RMS)[16]
–
400
1000
ps
12 MHz IMO long term N cycle-to-cycle jitter
(RMS)[16]
–
600
1300
ps
12 MHz IMO period jitter (RMS)[16]
–
100
500
ps
Notes
N = 32
Notes
14. Accuracy derived from Internal Main Oscillator with appropriate trim for VDD range.
15. 2.4 V < VDD < 3.0 V.
16. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at
www.cypress.com under Application Notes for more information.
Document Number: 38-16018 Rev. *N
Page 23 of 39
CY7C603xx
AC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 21. 3.3 V AC GPIO Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
Normal Strong Mode
FGPIO
GPIO operating frequency
0
–
12
MHz
TRiseS
Rise time, slow strong mode, cload = 50 pF
7
27
–
ns
VDD = 3 to 3.6 V, 10%–90%
TFallS
Fall time, slow strong mode, cload = 50 pF
7
22
–
ns
VDD = 3 to 3.6 V, 10%–90%
Min
Typ
Max
Unit
Notes
Normal Strong Mode
Table 22. 2.7 V AC GPIO Specifications
Parameter
Description
FGPIO
GPIO operating frequency
0
–
3
MHz
TRiseF
Rise time, normal strong mode, cload = 50 pF
6
–
50
ns
VDD = 2.4 to 3.0 V, 10%–90%
TFallF
Fall time, normal strong mode, cload = 50 pF
6
–
50
ns
VDD = 2.4 to 3.0 V, 10%–90%
TRiseS
Rise time, slow strong mode, cload = 50 pF
18
40
120
ns
VDD = 2.4 to 3.0 V, 10%–90%
TFallS
Fall time, slow strong mode, cload = 50 pF
18
40
120
ns
VDD = 2.4 to 3.0 V, 10%–90%
Figure 13. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
Table 23 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7V at 25 °C and are
for design guidance only.
Table 23. AC Operational Amplifier Specifications
Parameter
TCOMP
Description
Comparator mode response time, 50 mV
overdrive
Document Number: 38-16018 Rev. *N
Min
Typ
Max
Unit
100
200
ns
ns
Notes
VDD > 3.0 V.
2.4 V < Vcc <3.0 V.
Page 24 of 39
CY7C603xx
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 24. 3.3 V AC Digital Block Specifications
Function
Description
Min
Typ
Max
Unit
–
–
24.6
MHz
50[17]
–
–
ns
–
–
24.6
MHz
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
50
–
–
ns
Disable mode
All Functions
Block input clock frequency
Timer/
Counter/
PWM
Enable input pulse width
Dead Band
Kill pulse width:
Input clock frequency
Notes
3.0 V < VDD < 3.6 V.
50
–
–
ns
Input clock frequency
–
–
24.6
MHz
3.0 V  VDD  3.6 V.
SPIM
Input clock frequency
–
–
8.2
MHz
The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
SPIS
Input clock frequency
–
–
4.1
MHz
Note for SPIS Input Clock
Frequency: The input clock is the
SPI SCLK in SPIS mode.
Width of SS_ Negated between transmissions
50
–
–
ns
Transmitter
Input clock frequency
–
–
24.6
MHz
The baud rate is equal to the input
clock frequency divided by 8.
Receiver
Input clock frequency
–
–
24.6
MHz
The baud rate is equal to the input
clock frequency divided by 8.
Table 25. 2.7 V AC Digital Block Specifications
Function
Description
Min
Typ
Max
Unit
–
–
12.7
MHz
100
–
–
ns
–
–
12.7
MHz
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
100
–
–
ns
Disable mode
All
Functions
Block input clock frequency
Timer/
Counter/
PWM
Enable input clock width
Input clock frequency
Notes
2.4 V  VDD  3.0 V.
Dead Band Kill pulse width:
100
–
–
ns
Input clock frequency
–
–
12.7
MHz
2.4 V  VDD 3.0 V.
SPIM
Input clock frequency
–
–
6.35
MHz
The SPI serial clock (SCLK) frequency
is equal to the input clock frequency
divided by 2.
SPIS
Input clock frequency
–
–
4.1
MHz
Note for input clock frequency:
The input clock is the SPI SCLK in
SPIS mode.
100
–
–
ns
Transmitter Input clock frequency
Width of SS_ Negated between transmissions
–
–
12.7
MHz
The baud rate is equal to the input
clock frequency divided by 8.
Receiver
–
–
12.7
MHz
The baud rate is equal to the input
clock frequency divided by 8.
Input clock frequency
Note
17. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-16018 Rev. *N
Page 25 of 39
CY7C603xx
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 26. 3.3 V AC External Clock Specifications
Min
Typ
Max
Unit
Notes
FOSCEXT
Parameter
Frequency with CPU clock divide by 1
Description
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz at
3.3 V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
FOSCEXT
Frequency with CPU clock divide by 2 or greater
0.186
–
24.6
MHz
If the frequency of the external clock is
greater than 12 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
ns
–
High period with CPU clock divide by 1
41.7
–
5300
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power-up IMO to switch
150
–
–
s
Table 27. 2.7 V AC External Clock Specifications
Min
Typ
Max
Unit
Notes
FOSCEXT
Parameter
Frequency with CPU clock divide by 1
Description
0.093
–
3.080
MHz
Maximum CPU frequency is 3 MHz at
2.7 V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
FOSCEXT
Frequency with CPU clock divide by 2 or
greater
0.186
–
6.35
MHz
If the frequency of the external clock is
greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
ns
–
High period with CPU clock divide by 1
160
–
5300
–
Low period with CPU clock divide by 1
160
–
–
ns
–
Power-up IMO to switch
150
–
–
s
AC Programming Specifications
Table 28 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 28. AC Programming Specifications
Parameter
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK3
TDSCLK2
TERASEALL
Description
Rise time of SCLK
Fall time of SCLK
Data set up time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (Block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Flash erase time (Bulk)
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
10
40
–
–
20
Max
20
20
–
–
8
–
–
50
70
–
Unit
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
TPROGRAM_
HOT
Flash block erase + flash block write time
–
–
100
ms
3.0  VDD  3.6
2.4  VDD  3.0
Erase all blocks and protection fields
at once.
0 °C  TJ  100 °C
TPROGRAM_
COLD
Flash block erase + flash block write time
–
–
200
ms
-40 °C  TJ  0 °C
Document Number: 38-16018 Rev. *N
Notes
Page 26 of 39
CY7C603xx
AC I2C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 3.6 V and
0 °C < TA < 70 °C, or 2.4 V to 3.0 V and 0 °C < TA < 70 °C, respectively. Typical parameters apply to 3.3 V, or 2.7 V at 25 °C and are
for design guidance only.
Table 29. AC Characteristics of the I2C SDA and SCL Pins for VDD >3.0 V
Parameter
Description
FSCLI2C
SCL clock frequency
THDSTAI2C
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
TLOWI2C
THIGHI2C
Standard-Mode
Min
Max
Fast-Mode
Min
Max
Unit
0
100
0
400
kHz
4.0
–
0.6
–
s
LOW period of the SCL clock
4.7
–
1.3
–
s
HIGH period of the SCL clock
4.0
–
0.6
–
s
TSUSTAI2C
Set up time for a repeated START condition
4.7
–
0.6
–
s
THDDATI2C
Data hold time
0
–
0
–
s
TSUDATI2C
Data setup time
250
–
100[18]
–
ns
TSUSTOI2C
Set up time for STOP condition
4.0
–
0.6
–
s
TBUFI2C
Bus free time between a STOP and START condition
4.7
–
1.3
–
s
TSPI2C
Pulse width of spikes are suppressed by the input filter.
–
–
0
50
ns
Table 30. 2.7 V AC Characteristics of the I2C SDA and SCL Pins (Fast-Mode not Supported)
Parameter
Description
Standard-Mode
Fast-Mode
Unit
Min
Max
Min
Max
0
100
–
–
kHz
4.0
–
–
–
s
FSCLI2C
SCL clock frequency
THDSTAI2C
Hold time (repeated) START condition. After this period, the first clock
pulse is generated.
TLOWI2C
LOW period of the SCL clock
4.7
–
–
–
s
THIGHI2C
HIGH period of the SCL clock
4.0
–
–
–
s
TSUSTAI2C
Setup time for a repeated START condition
4.7
–
–
–
s
THDDATI2C
Data hold time
0
–
–
–
s
TSUDATI2C
Data setup time
250
–
–
–
ns
TSUSTOI2C
Setup Time for STOP Condition
4.0
–
–
–
s
TBUFI2C
Bus free time between a STOP and START condition
4.7
–
–
–
s
TSPI2C
Pulse width of spikes are suppressed by the input filter.
–
–
–
–
ns
Note
18. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-16018 Rev. *N
Page 27 of 39
CY7C603xx
Figure 14. Definition of Timing for Fast-/Standard-Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Packaging Information
This section illustrates the packaging specifications for the CY7C603xx device, along with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com.
Packaging Dimensions
Figure 15. 28-pin (210-Mil) SSOP
51-85079 *E
Document Number: 38-16018 Rev. *N
Page 28 of 39
CY7C603xx
Figure 16. 32-pin QFN (5 × 5 mm) (SAWN)
001-30999 *C
Document Number: 38-16018 Rev. *N
Page 29 of 39
CY7C603xx
Thermal Impedances
Solder Reflow Peak Temperature
Table 31. Thermal Impedances per Package
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Package
Typical JA [19]
Typical JC
28-pin SSOP
62 °C / W
28 °C / W
32-pin QFN [21]
19 °C / W
32 °C / W
Table 32. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Time at Maximum
Peak Temperature
28-pin SSOP
260 °C
30 s
32-pin QFN
260 °C
30 s
Notes
19. TJ = TA + Power x JA
20. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
21. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages available at http://www.amkor.com.
Document Number: 38-16018 Rev. *N
Page 30 of 39
CY7C603xx
Ordering Information
The following table lists the CY7C603xx device’s key package features and ordering codes
Table 33. CY7C603xx Device Key Features and Ordering Information
Flash Size
RAM Size
SMP
I/O
28-SSOP
Package Type
CY7C60323-PVXC
Ordering Part Number
8K
512
No
24
28-SSOP Tape and Reel
CY7C60323-PVXCT
8K
512
No
24
32-QFN SAWN
CY7C60323-LTXC
8K
512
No
28
32-QFN SAWN Tape and Reel
CY7C60323-LTXCT
8K
512
No
28
Ordering Code Definitions
CY
7
C
60 xxx
Part Number: 1xx, 2xx = enCoRe II LV; 3xx = enCoRe III LV; 4xx = enCoRe IV LV
Family name: Low Voltage RF Companion MCU
Technology: CMOS
Cypress Products
Company ID : CY = Cypress
Document Number: 38-16018 Rev. *N
Page 31 of 39
CY7C603xx
Acronyms
Acronyms Used
Table 34 lists the acronyms that are used in this document.
Table 34. Acronyms Used in this Datasheet
Acronym
AC
Description
alternating current
Acronym
MIPS
Description
million instructions per second
ADC
analog-to-digital converter
PCB
printed circuit board
API
application programming interface
PGA
programmable gain amplifier
CPU
central processing unit
PLL
phase-locked loop
continuous time
POR
power-on reset
CT
DAC
DC
digital-to-analog converter
PPOR
precision power on reset
direct current
PSoC®
Programmable System-on-Chip
DTMF
dual-tone multi-frequency
PWM
pulse-width modulator
ECO
external crystal oscillator
QFN
quad flat no leads
electrically erasable programmable read-only
memory
RTC
real time clock
general purpose I/O
SAR
successive approximation
EEPROM
GPIO
ICE
in-circuit emulator
SC
SLIMO
switched capacitor
IDE
integrated development environment
ILO
internal low speed oscillator
IMO
internal main oscillator
SPITM
serial peripheral interface
I/O
input/output
SRAM
static random access memory
ISSP
in-system serial programming
SROM
supervisory read only memory
LCD
liquid crystal display
SSOP
shrink small-outline package
LPC
low power comparator
USB
universal serial bus
LVD
low voltage detect
WDT
watchdog timer
MAC
multiply-accumulate
XRES
external reset
SMP
slow IMO
switch mode pump
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 38-16018 Rev. *N
Page 32 of 39
CY7C603xx
Document Conventions
Units of Measure
Table 35 lists the units of measures.
Table 35. Units of Measure
Symbol
Unit of Measure
Symbol
µH
Unit of Measure
kB
1024 bytes
dB
decibels
µs
microseconds
°C
degree Celsius
ms
milliseconds
µF
microfarads
ns
nanoseconds
fF
femtofarads
ps
picoseconds
pF
picofarads
µV
microvolts
kHz
kilohertz
mV
millivolts
MHz
megahertz
mVpp
rt-Hz
root hertz
nV
k
kilohms

ohm
V
microhenry
millivolts peak-to-peak
nanovolts
volts
µW
microwatts
W
watts
µA
microamperes
mA
milliamperes
mm
nA
nanoamperes
ppm
pA
pikoamperes
%
millimeter
parts per million
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are switched capacitor (SC) and continuous time (CT) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
Programming
Interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 38-16018 Rev. *N
Page 33 of 39
CY7C603xx
Glossary
(continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows the user to analyze the operation of the system under development.
A debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse operation.
Document Number: 38-16018 Rev. *N
Page 34 of 39
CY7C603xx
Glossary
(continued)
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides users with the programmability
and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power
is off.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with
resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
Document Number: 38-16018 Rev. *N
Page 35 of 39
CY7C603xx
Glossary
(continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
power-on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse-width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Document Number: 38-16018 Rev. *N
Page 36 of 39
CY7C603xx
Glossary
(continued)
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device
A device that allows another device to control the timing for data exchanges between two devices. Or when devices
are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
An acronym for static random access memory. A memory device allowing users to store and retrieve data at a
high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains
unchanged until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 38-16018 Rev. *N
Page 37 of 39
CY7C603xx
Document History Page
Description Title: CY7C603xx, enCoRe™ III Low Voltage
Document Number: 38-16018
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
339394
BON
See ECN
New Advance Data Sheet.
*A
399556
BHA
See ECN
Changed from Advance Information to Preliminary.
Changed data sheet format.
Removed CY7C604xx.
Description of Change
*B
461240
TYJ
See ECN
Modified Figure 10 to include 2.7 V Vdd at 12 MHz operation.
*C
470485
TYJ
See ECN
Corrected part numbers in section 4 to match with part numbers in Ordering Information. From CY7C60323-28PVXC, CY7C60323-56LFXC and
CY7C60333-56LFXC to CY7C60323-PVXC, CY7C60323-LFXC and
CY7C60333-LFXC respectively.
Changed from Preliminary to Final data sheet.
*D
513713
KKVTMP
See ECN
Change title from Wireless enCoRe II to enCoRe III Low Voltage.
Applied new template formatting.
*E
2197567
UVS/AESA
See ECN
Added 32-Pin Sawn QFN Pin Diagram, package diagram, and ordering
information.
*F
2620679
CMCC/PYR
S
12/12/2008
Added Packaging Handling information.
Deleted note regarding link to amkor.com for MLF package dimensions.
*G
2852393
XUT
01/15/2010
Added Table of Contents.
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT,
and TPROGRAM_COLD specifications.
Updated copyright and Sales, Solutions, and Legal Information URLs.
Updated 28-Pin SSOP and 32-Pin QFN (PUNCH and SAWN) package diagrams.
*H
2892683
NJF
03/15/2010
Updated Cypress website links.
Updated Development Kits.
Updated 3.3 V AC Chip-Level Specifications and 2.7 V AC Chip-Level Specifications.
Removed AC Analog Mux Bus Specs section.
Updated 32-pin Sawn QFN package diagram.
Removed inactive parts from Ordering Information.
*I
2911952
GNKK
04/13/2010
Updated revision in the footer.
*J
3014656
BHA
09/15/2010
Updated Logic Block Diagram to enCore III LV.
Added Ordering Code Definitions
Added Acronyms and Units of Measure table.
Datasheet updated as per latest Template.
*K
3114976
NJF
12/19/10
*L
3180466
CSAI
02/23/2011
Updated Packaging Information.
Updated in new template.
*M
3210223
CSAI
03/30/2011
Removed prune parts CY7C60333-LTXC and CY7C60333-LTXCT from the
datasheet.
*N
3285017
DIVA
07/07/2011
Updated Getting Started, Development Tools, and Designing with PSoC Designer.
Updated Thermal Impedances and Solder Reflow Peak Temperature table.
Document Number: 38-16018 Rev. *N
Updated 3.3-V and 2.7-V AC Digital Block Specifications.
Updated DC Operational Amplifier Specifications.
Updated I2C Timing Diagram.
Added DC I2C Specifications.
Added UILO max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
Page 38 of 39
CY7C603xx
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC® Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-16018 Rev. *N
Revised July 7, 2011
All products and company names mentioned in this document may be the trademarks of their respective holders.
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