Cypress CY24272 Rambus xdrâ ¢ clock generator with zero sda hold time Datasheet

CY24272
Rambus XDR™ Clock Generator with
Zero SDA Hold Time
Rambus‚ XDR™ Clock Generator with Zero SDA Hold Time
Features
■
Table 1. Device Comparison
Meets Rambus Extended Data Rate (XDR™) clocking
requirements
■
25 ps typical cycle-to-cycle jitter
❐ –135 dBc/Hz typical phase noise at 20 MHz offset
■
100 or 133 MHz differential clock input
■
300–667 MHz high speed clock support
■
Quad (open drain) differential output drivers
■
Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
■
Spread Aware™
■
2.5 V operation
■
28-pin TSSOP package
CY24271
CY24272
SDA hold time = 300 ns
(SMBus compliant)
SDA hold time = 0 ns
(I2C compliant)
RRC = 200  typical
(Rambus standard drive)
RRC = 295  minimum
(Reduced output drive)
Logic Block Diagram
/BYPASS
EN
EN
RegA
CLK0
CLK0B
EN
RegB
CLK1
Bypass
MUX
CLK1B
EN
RegC
PLL
REFCLK,REFCLKB
CLK2
CLK2B
EN
RegD
CLK3
CLK3B
SCL
Cypress Semiconductor Corporation
Document Number: 001-42414 Rev. *A
•
SDA
ID0
ID1
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 17, 2011
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CY24272
Contents
Pinouts .............................................................................. 3
PLL Multiplier .................................................................... 4
Input Clock Signal ............................................................ 4
Modes of Operation .......................................................... 4
Device ID and SMBus Device Address ........................... 5
SMBus Protocol ................................................................ 5
SMBus Data Byte Definitions .......................................... 5
Absolute Maximum Conditions ....................................... 7
DC Operating Conditions ................................................. 8
DC Electrical Specifications ............................................ 9
AC Operating Conditions ................................................. 9
AC Electrical Specification ............................................ 10
Test and Measurement Setup ........................................ 11
Example External Resistor Values
and Termination Voltages for a 50 W Channel ............ 11
Document Number: 001-42414 Rev. *A
Signal Waveforms .......................................................... 11
Jitter ................................................................................. 11
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Drawing and Dimension ................................. 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
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CY24272
Pinouts
Figure 1. Pin Diagram - 28-pin TSSOP
VDDP
VSSP
ISET
VSS
REFCLK
VDDC
VSSC
SCL
SDA
EN
ID0
ID1
/BYPASS
CY24272
REFCLKB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
CLK0
CLK0B
VSS
CLK1
CLK1B
VDD
VSS
CLK2
CLK2B
VSS
CLK3
CLK3B
VDD
Table 2. Pin Definition - 28-pin TSSOP
Pin No.
Name
IO
Description
1
VDDP
PWR
2.5 V power supply for phased lock loop (PLL)
2
VSSP
GND
Ground
3
ISET
I
4
VSS
GND
5
REFCLK
I
Reference clock input (connect to clock source)
6
REFCLKB
I
Complement of reference clock (connect to clock source)
7
VDDC
PWR
2.5 V power supply for core
8
VSSC
GND
Ground
9
SCL
I
SMBus clock (connect to SMBus)
10
SDA
I
SMBus data (connect to SMBus)
11
EN
I
Output Enable (CMOS signal)
12
ID0
I
Device ID (CMOS signal)
Set clock driver current (external resistor)
Ground
13
ID1
I
Device ID (CMOS signal)
14
/BYPASS
I
REFCLK bypassing PLL (CMOS signal)
15
VDD
PWR
Power supply for outputs
16
CLK3B
O
Complement clock output
17
CLK3
O
18
VSS
GND
19
CLK2B
O
Complement clock output
20
CLK2
O
Clock output
Clock output
Ground
21
VSS
GND
Ground
22
VDD
PWR
Power supply for outputs
23
CLK1B
O
Complement clock output
24
CLK1
O
Clock output
25
VSS
GND
26
CLK0B
O
27
CLK0
O
28
VDD
PWR
Document Number: 001-42414 Rev. *A
Ground
Complement clock output
Clock output
Power supply for outputs
Page 3 of 16
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CY24272
PLL Multiplier
Table 3 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.
Default multiplier at power up is 4.
Table 3. PLL Multiplier Selection
Register
MULT2
Frequency Multiplier
Output Frequency (MHz)
REFCLK = 100 MHz[1], REFSEL = 0 REFCLK = 133 MHz[1], REFSEL = 1
MULT1
MULT0
0
0
0
3
300
400
0
0
1
4
400[2]
–
0
1
0
5
500
667
0
1
1
6
600
–
1
0
0
Reserved
–
–
1
0
1
9/2
450
600
1
1
0
Reserved
–
–
1
1
1
15/4
375
500
Input Clock Signal
Modes of Operation
The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).
The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.
Table 5 on page 5 shows selection from one to all four of the
outputs, the Outputs Disabled Mode (EN = low), and Bypass
Mode (EN = high, /BYPASS = low). There is an option reserved
for vendor test. Disabled outputs are set to High Z.
When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in
DC Operating Conditions on page 8 and AC Operating
Conditions on page 9.
For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in Figure 2 on page 7, provide a
reference voltage VTH at the REFCLKB pin. This determines the
proper trip point of REFCLK. For the range of VTH specified in
DC Operating Conditions on page 8, the outputs also meet the
DC and AC Operating Conditions tables.
At power up, the SMBus registers default to the last entry in
Table 6 on page 6. The value at RegTest is 0. The values at
RegA, RegB, RegC, and RegD are all ‘1’. Thus, all outputs are
controlled by the logic applied to EN and /BYPASS.
Table 4. SMBus Device Addresses for CY24272
XCG
Device
0
1
2
3
Operation
Hex
Address
Write
D8
Read
D9
Write
DA
Read
DB
Write
DC
Read
DD
Write
DE
Read
DF
8-bit SMBus Device Address Including Operation
Five Most Significant Bits
1
1
0
1
ID1
ID0
0
0
0
1
1
0
1
1
1
WR# / RD
0
1
0
1
0
1
0
1
Notes
1. Output frequencies shown in Table 3 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.
2. Default PLL multiplier at power up.
Document Number: 001-42414 Rev. *A
Page 4 of 16
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CY24272
Table 5. Modes of Operation for CY24272
EN
/BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B
X
X
X
X
High Z
High Z
CLK2/CLK2B CLK3/CLK3B
X
H
X
1
X
X
X
X
H
L
0
X
X
X
X
REFCLK/
REFCLKB[3]
REFCLK/
REFCLKB
REFCLK/
REFCLKB
REFCLK/
REFCLKB
H
H
0
0
0
0
0
High Z
High Z
High Z
High Z
H
H
0
0
0
0
1
High Z
High Z
High Z
CLK/CLKB
H
H
0
0
0
1
0
High Z
High Z
CLK/CLKB
High Z
H
H
0
0
0
1
1
High Z
High Z
CLK/CLKB
CLK/CLKB
H
H
0
0
1
0
0
High Z
CLK/CLKB
High Z
High Z
H
H
0
0
1
0
1
High Z
CLK/CLKB
High Z
CLK/CLKB
H
H
0
0
1
1
0
High Z
CLK/CLKB
CLK/CLKB
High Z
H
H
0
0
1
1
1
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
H
H
0
1
0
0
0
CLK/CLKB
High Z
High Z
High Z
H
H
0
1
0
0
1
CLK/CLKB
High Z
High Z
CLK/CLKB
H
H
0
1
0
1
0
CLK/CLKB
High Z
CLK/CLKB
High Z
H
H
0
1
0
1
1
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
H
H
0
1
1
0
0
CLK/CLKB
CLK/CLKB
High Z
High Z
H
H
0
1
1
0
1
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
H
H
0
1
1
1
0
CLK/CLKB
CLK/CLKB
CLK/CLKB
High Z
H
0[4]
1[4]
1[4]
1[4]
1[4]
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
H
X
CLK1/CLK1B
L
High Z
High Z
Reserved for Vendor Test
Device ID and SMBus Device Address
SMBus Data Byte Definitions
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address designates a
write or read operation. Table 4 on page 4 shows the addresses
for four CY24272 devices on the same SMBus.
Three data bytes are defined for the CY24272. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
SMBus Protocol
The CY24272 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
The definition of Byte 2 is shown in Table 6 on page 6,
Table 7 on page 6, and Table 8 on page 6. The upper five bits are
the revision numbers of the device and the lower three bits are
the ID numbers assigned to the vendor by Rambus.
DC specifications are modified to Rambus standard to support
1.8, 2.5, and 3.3 volt devices. Time out detection and packet
error protocol SMBus features are not supported.
Hold time for SDA is reduced relative to the CY24271, so that it
is compatible with I2C.
Notes
3. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
4. Default mode of operation is at power up.
Document Number: 001-42414 Rev. *A
Page 5 of 16
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CY24272
Table 6. Command Code 80h[5]
Bit
Register
POD
Type
Description
7
Reserved
0
RW
Reserved (no internal function)
6
MULT2
0
RW
PLL Multiplier Select (reference Table 3 on page 4)
5
MULT1
0
RW
4
MULT0
1
RW
3
RegA
1
RW
Clock 0 Output Select
2
RegB
1
RW
Clock 1 Output Select
1
RegC
1
RW
Clock 2 Output Select
0
RegD
1
RW
Clock 3 Output Select
Table 7. Command Code 81h[5]
Bit
Register
POD
Type
7
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
1
RW
Description
Reserved (no internal function)
Reserved (must be set to ‘1’ for proper operation)
2
REFSEL
0
RW
Reference Frequency Select (reference Table 3 on page 4)
1
Reserved
0
RW
Reserved (must be set to ‘0’ for proper operation)
0
RegTest
0
RW
Reserved (must be set to ‘0’ for proper operation)
Table 8. Command Code 82h[5]
Bit
Register
POD
Type
7
Device
Revision
Number
?
RO
?
RO
?
RO
4
?
RO
3
?
RO
6
5
2
0
RO
1
Vendor ID
1
RO
0
0
RO
Description
Contact factory for Device Revision Number information.
Rambus assigned Vendor ID Code
Note
5. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 3 on page 4 for PLL multipliers and Table 5 on page 5 for clock output selections.
Document Number: 001-42414 Rev. *A
Page 6 of 16
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CY24272
Figure 2. Differential and Single-Ended Clock Inputs
Supply Voltage
V TH
REFCLKB
Input
Input
REFCLK
REFCLK
XDR Clock Generator
XDR Clock Generator
Differential Input
Single-ended Input
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–0.5
4.6
V
VDD
Clock Buffer Supply Voltage
VDDC
Core Supply Voltage
–0.5
4.6
V
VDDP
PLL Supply Voltage
–0.5
4.6
V
VIN
Input Voltage (SCL and SDA)
Relative to VSS
–0.5
4.6
V
Input Voltage (REFCLK/REFCLKB)
Relative to VSS
–0.5
VDD + 1.0
V
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
V
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient
Functional
0
70
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJA
Junction to Ambient thermal
resistance
Zero air flow
–
100
°C/W
ESDHBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
V
Document Number: 001-42414 Rev. *A
Page 7 of 16
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CY24272
DC Operating Conditions
Parameter
Description
Condition
Min
Max
Unit
2.5 V ± 5%
2.375
2.625
V
VDDP
Supply Voltage for PLL
VDDC
Supply Voltage for Core
2.5 V ± 5%
2.375
2.625
V
VDD
Supply Voltage for Clock Buffers
2.5 V ± 5%
2.375
2.625
V
VIHCLK
Input High Voltage, REFCLK/REFCLKB
0.6
0.95
V
VILCLK
Input Low Voltage, REFCLK/REFCLKB
–0.15
+0.15
V
VIXCLK[6]
VIXCLK[6]
Crossing Point Voltage, REFCLK/REFCLKB
200
550
mV
–
150
mV
VIH
Input Signal High Voltage at ID0, ID1, EN, and /BYPASS
1.4
2.625
V
VIL
Input Signal Low Voltage at ID0, ID1, EN, and /BYPASS
–0.15
0.8
V
VIH,SM
Input Signal High Voltage at SCL and SDA[7]
VIL,SM
Input Signal Low Voltage at SCL and SDA
VTH[8]
Input Threshold Voltage for single-ended REFCLK
VIH,SE
Input Signal High Voltage for single-ended REFCLK
VIL,SE
Input Signal Low Voltage for single-ended REFCLK
–0.15
VTH – 0.3
V
TA
Ambient Operating Temperature
0
70
°C
Difference in Crossing Point Voltage, REFCLK/REFCLKB
1.4
3.465
V
–0.15
0.8
V
0.35
0.5 × VDD
V
VTH + 0.3
2.625
V
Notes
6. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
7. This range of SCL and SDA input high voltage enables the CY24272 for use with 3.3 V, 2.5 V, or 1.8 V SMBus voltages.
8. Single-ended operation guaranteed only when 0.8 < (VIH,SE – VTH)/(VTH – VIL,SE) < 1.2.
Document Number: 001-42414 Rev. *A
Page 8 of 16
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CY24272
AC Operating Conditions
The AC operating conditions follow.[9]
Parameter
tCYCLE,IN
Description
Condition
REFCLK, REFCLKB input cycle time
Min
Max
Unit
REFSEL = 0, /BYPASS = High
9
11
ns
REFSEL = 1, /BYPASS = High
7
8
ns
/BYPASS = Low
4
–
ns
–
185
ps
Over 10,000 cycles
40%
60%
tCYCLE
Measured at 20%–80% of input
voltage for REFCLK and
REFCLKB inputs
175
700
ps
Rise and Fall Times Difference
–
150
ps
Modulation Index for triangular modulation
–
0.6
%
%
tJIT,IN(cc)
Input Cycle to Cycle Jitter[10]
tDCIN[11]
Input Duty Cycle
tRIN / tFIN
Rise and Fall Times
tRIN / tFIN
pMIN[12]
Modulation Index for non-triangular modulation
–
0.5[13]
fMIN[12]
Input Frequency Modulation
30
33
kHz
tSR,IN
Input Slew Rate (measured at 20%–80% of
input voltage) for REFCLK
1
4
V/ns
CIN,REF
Capacitance at REFCLK inputs
–
7
pF
CIN,CMOS
Capacitance at CMOS inputs
–
10
pF
fSCL
SMBus clock frequency input in SCL pin
DC
100
kHz
Min
Typ
Max
Unit
DC Electrical Specifications
Parameter
Description
voltage[14]
VOX[9]
VCOS[9]
Differential output crossing point
–
1.08
–
V
Output voltage swing (peak-to-peak single-ended)[15]
–
400
–
mV
VOL,ABS
Absolute output low voltage at CLK[3:0], CLK[3:0]B[16]
0.85
–
–
V
VISET
Reference voltage for swing controlled current, IREF
0.98
1.0
1.02
V
IDD[17]
Power Supply Current at 2.625V, fref = 100 MHz, and fout = 300 MHz
–
–
85
mA
IDD[17]
Power Supply Current at 2.625V, fref = 133 MHz, and fout = 667 MHz
–
–
125
mA
IOL/IREF
Ratio of output low current to reference current[18]
6.8
7.0
7.2
IOL,ABS
Minimum current at VOL,ABS[19]
25
–
–
VOL,SDA
SDA output low voltage at test condition of SDA output low current = 4 mA
–
–
0.4
V
IOL,SDA
SDA output low voltage at test condition of SDA voltage = 0.8 V
6
–
–
mA
IOZ
Current during High Z per pin at CLK[3:0], CLK[3:0]B
–
–
10
A
ZOUT
Output dynamic impedance when clock output signal is at VOL = 0.9 V[20]
1000
–
–

mA
Notes
9. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
10. Jitter measured at crossing points and is the absolute value of the worst case deviation.
11. Measured at crossing points.
12. If input modulation is used; input modulation is allowed but not required.
13. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated
by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
14. VOX is measured on external divider network.
15. VCOS = (clock output high voltage – clock output low voltage), measured on the external divider network.
16. VOL_ABS is measured at the clock output pins of the package.
17. This range of SCL and SDA input high voltage enables the CY24272 for use with 3.3 V, 2.5 V, or 1.8 V SMBus voltages.
18. IREF is equal to VISET/RRC.
19. Minimum IOL,ABS is measured at the clock output pin with RRC = 266 ohms or less.
20. ZOUT is defined at the output pins as (0.94 V – 0.90 V)/(I0.94 – I0.90) under conditions specified for IOL, ABS.
Document Number: 001-42414 Rev. *A
Page 9 of 16
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CY24272
AC Electrical Specification
The AC Electrical specifications follow. [21]
Parameter
Min
Typ
Max
Unit
1.25
–
3.34
ns
Jitter over 1-6 clock cycles at 400–635 MHz
–
25
40
ps
Jitter over 1-6 clock cycles at 638–667 MHz
–
25
30
ps
L20
Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz
(In addition, device must not exceed L(f) = 10log[1+(50×106/f)2.4] –138 for
f = 1 MHz to 100 MHz except for the region near f = REFCLK/Q where Q is
the value of the internal reference divider.)
–
–135
–128
dBC/Hz
tJIT(hper,cc)
Cycle-to-cycle duty cycle error at 400–635 MHz
–
25
40
ps
Cycle-to-cycle duty cycle error at 636–667 MHz
–
25
30
ps
Drift in tSKEW when ambient temperature varies between 0 °C and 70 °C and
supply voltage varies between 2.375 V and 2.625 V.[24]
–
–
15
ps
tCYCLE
tJIT(cc)
tSKEW
Description
Clock Cycle time[22]
[23]
DC
Long term average output duty cycle
45%
50
55%
tCYCLE
tEER,SCC
PLL output phase error when tracking SSC
–100
–
100
ps
tCR,tCF
Output rise and fall times at 400–667 MHz (measured at 20%–80% of output
voltage)
–
150
–
ps
tCR,CF
Difference between output rise and fall times on the same pin of the single
device (20%–80%) of 400–667 MHz[25]
–
–
100
ps
Min
Max
Units
10
100
kHz
Table 9. SMBus Timing Specification
Parameter
FSMB
Description
SMBus Operating Frequency
TBUF
Bus free time between Stop and Start Condition
4.7
–
s
THD:STA
Hold time after (Repeated) Start Condition.
After this period, the first clock is generated.
4.0
–
s
TSU:STA
Repeated Start Condition setup time
4.7
–
s
TSU:STO
Stop Condition setup time
4.0
–
s
THD:DAT
Data Hold time
0
–
ns
TSU:DAT
Data Setup time
250
–
ns
TTIMEOUT
Detect clock low timeout
–
–
Not supported
TLOW
Clock low period
4.7
–
s
THIGH
Clock high period
4.0
50
s
TLOW:SEXT
Cumulative clock low extend time (slave device)
–
25
ms
CY24272 doesn’t
extend
TLOW:MEXT
Cumulative clock low extend time (master device)
–
10
ms
TF
Clock/Data Fall Time
–
300
ns
TR
Clock/Data Rise Time
–
1000
ns
TPOR
Time in which a device must be operational after power on reset
–
500
ms
Notes
21. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
22. Max and min output clock cycle times are based on nominal outputs frequency of 300 and 667 MHz, respectively. For spread spectrum modulated differential or
single-ended REFCLK, the output clock tracks the modulation of the input.
23. Output short term jitter spec is the absolute value of the worst case deviation.
24. tSKEW is the timing difference between any two of the four differential clocks and is measured at common mode voltage. tSKEW is the change in tSKEW when the
operating temperature and supply voltage change.
25. tCR,CF applies only when appropriate RRC and output resistor network resistor values are selected to match pull up and pull down currents.
Document Number: 001-42414 Rev. *A
Page 10 of 16
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CY24272
Test and Measurement Setup
Figure 3. Clock Outputs
Measurement
Point
VTS
CLK
Swing Current
Control
R1
R2
R T1
Z CH
R3 C
VT
R T2
S
Differential Driver
ISET
Measurement
Point
VTS
R RC
R1
CLKB
R2
Example External Resistor Values
and Termination Voltages for a 50  Channel
Parameter
Value
Unit
R1
33.0

R2
18.0

R3
17.0

RT1
60.4

RT2
301

CS
2700
pF
RRC
432

VTS
2.5
V
VT
1.2
V
Signal Waveforms
A physical signal that appears at the pins of a device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. Input and output voltage waveforms are defined as
shown in Figure 4 on page 12. Both rise and fall times are defined
between the 20% and 80% points of the voltage swing, with the
swing defined as VH–VL.
Document Number: 001-42414 Rev. *A
Z CH
R3 C
S
VT
R T1
R T2
Figure 5 on page 12 shows the definition of the output crossing
point. The nominal crossing point between the complementary
outputs is defined as the 50% point of the DC voltage levels.
There are two crossing points defined: Vx+ at the rising edge of
CLK and Vx– at the falling edge of CLK. For some waveforms,
both Vx+ and Vx– are below Vx,nom (for example, if tCR is larger
than tCF).
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms. Figure 6
on page 12 shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle jitter
is the difference between cycle times of adjacent cycles. Equal
requirements apply rising edges of the CLK signal. Figure 7 on
page 12 shows the definition of cycle-to-cycle duty cycle error
(tDC,ERR). Cycle-to-cycle duty cycle is defined as the difference
between tPW+ (high times) of adjacent differential clock cycles.
Equal requirements apply to tPW-, low times of the differential
click cycles.
Page 11 of 16
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CY24272
Figure 4. Input and Output Waveforms
VH
80%
V (t)
20%
VL
tR
tF
Figure 5. Crossing Point Voltage
CLK
Vx+
Vx.nom
Vx-
CLKB
Figure 6. Cycle-to-cycle Jitter
CLK
CLKB
tCYCLE,i
tCYCLE,i+1
tJ = tCYCLE,i - tCYCLE,i+1 over 10,000 consecutive cycles
Figure 7. Cycle-to-cycle Duty-cycle Error
CLK
CLKB
tPW-(i)
tCYCLE,(i)
tPW+(i)
tPW-(i+1)
tPW+(i+1)
tCYCLE,(i+1)
tDC,ERR = tPW-(i) - tPW-(i+1) and tPW-(i+1) - tPW+(i+1)
Document Number: 001-42414 Rev. *A
Page 12 of 16
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CY24272
Ordering Information
Part Number
Package Type
Product Flow
Pb-free
CY24272ZXC
28-pin TSSOP
Commercial, 0 °C to 70 °C
CY24272ZXCT
28-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
Ordering Code Definitions
CY 24272 ZX
C
T
T = Tape and Reel
Temperature Range:
C = Commercial
Package Type:
ZX = 28-pin TSSOP (Pb-free)
Base Device Part Number
Company ID: CY = Cypress
Package Drawing and Dimension
Figure 8. 28-pin Thin Shrunk Small Outline Package (4.40-mm Body) ZZ28
51-85120 *B
Document Number: 001-42414 Rev. *A
Page 13 of 16
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CY24272
Acronyms
Acronym
Description
CMOS
complementary metal oxide semiconductor
ESD
electrostatic discharge
PLL
phase locked loop
TSSOP
thin shrunk small outline package
XDR
extended data rate
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
Hz
Hertz
kHz
kilo Hertz
MHz
Mega Hertz
µs
micro seconds
µA
micro Amperes
mA
milli Amperes
ms
milli seconds
ns
nano seconds

ohms
%
percent
pF
pico Farads
ps
pico seconds
mV
milli Volts
V
Volts
W
Watts
Document Number: 001-42414 Rev. *A
Page 14 of 16
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CY24272
Document History Page
Document Title: CY24272 Rambus XDR™ Clock Generator with Zero SDA Hold Time
Document Number: 001-42414
REV.
Orig. of
Change
ECN NO. Issue Date
**
1749003
See ECN
*A
3175899 02/17/2011
Description of Change
KVM/AESA New data sheet
No 8 or 15/2 multipliers or 133MHz * 4 option
Max frequency is 667MHz
Document Number: 001-42414 Rev. *A
BASH
Added Ordering Code Definitions.
Updated Package Drawing and Dimension.
Added Acronyms and Units of Measure.
Updated in new template.
Page 15 of 16
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CY24272
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-42414 Rev. *A
Revised February 17, 2011
Page 16 of 16
Rambus is a registered trademark, and XDR is a trademark, of Rambus Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
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