Cypress CY7C1011CV33-10ZXI 2-mbit (128k x 16) static ram Datasheet

CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
The CY7C1011CV33 is a high performance CMOS static RAM
organized as 131,072 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
■
Pin and function compatible with CY7C1011BV33
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ 360 mW (max)
■
Data Retention at 2.0
■
Automatic power down when deselected
■
Independent control of upper and lower bits
■
Easy memory expansion with CE and OE features
■
Available in Pb-free and non Pb-free 44-pin TSOP II, 44-pin
TQFP and 48-Ball VFBGA packages
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A16). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A16).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. For more information, see the “Truth
Table” on page 9 for a complete description of Read and Write
modes.
The input and output pins (IO0 through IO15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
128K x 16
RAM Array
IO0–IO7
IO8–IO15
•
BHE
WE
CE
OE
BLE
A16
A15
A14
A12
A13
A9
Cypress Semiconductor Corporation
Document Number: 38-05232 Rev. *F
A10
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 04, 2008
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CY7C1011CV33
Pin Configuration
Figure 1. 44-Pin TSOP II [1]
A4
A3
A2
A1
A0
CE
IO1
IO2
IO3
IO4
VCC
VSS
IO5
IO6
IO7
IO8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Figure 2. 48-Ball FBGA Pinout [1]
A5
A6
A7
OE
BHE
BLE
IO16
IO15
IO14
IO13
VSS
VCC
IO12
IO11
IO10
IO9
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
IO8
BHE
A3
A4
CE
IO0
B
IO9
IO10
A5
A6
IO2
IO1
C
VSS
IO11
NC
A7
IO3
VCC
D
VCC
IO12
NC
NC
IO4
VSS
E
IO14
IO13
A14
A15
IO5
IO6
F
IO15
NC
A12
A13
WE
IO7
G
NC
A8
A9
A10
A11
NC
H
A12
A11
A10
A9
OE
BHE
BLE
40
39
38
37
36
35
34
A13
A14
A15
A16
Figure 3. 44-Pin TQFP II
42
41
43
44
1
26
IO 10
IO 5
9
25
IO 9
IO 6
10
24
IO 8
11
23
NC
IO 7
21
8
22
IO 4
A8
IO11
A7
7
20
VSS
A5
VCC
27
A6
6
VCC
18
VSS
28
19
29
NC
5
17
4
IO3
16
IO 2
A4
IO 13
IO 12
A3
31
30
14
3
15
IO 1
A1
2
A2
IO 0
IO 14
13
IO 15
32
12
33
WE
A0
1
CE
Note
1. NC pins are not connected on the die.
Document Number: 38-05232 Rev. *F
Page 2 of 14
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CY7C1011CV33
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Document Number: 38-05232 Rev. *F
-10
-12
-15
Unit
10
12
15
ns
Comm’l
90
85
80
mA
Ind’l
100
95
Auto-A
100
Comm’l/Ind’l
10
Auto-A
10
mA
mA
10
10
mA
mA
Page 3 of 14
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CY7C1011CV33
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Latch Up Current ..................................................... >200 mA
Operating Range
Range
Supply Voltage on VCC Relative to GND[2] .....–0.5V to +4.6V
Ambient
Temperature (TA)
VCC
0°C to +70°C
3.3V ± 10%
DC Voltage Applied to Outputs
in High Z State[2] ...................................... –0.5V to VCC+0.5V
Commercial
Industrial
–40°C to +85°C
DC Input Voltage[2] .................................. –0.5V to VCC+0.5V
Automotive-A
–40°C to +85°C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
-10
Min
-12
Max
-15
Max
VOH
Output HIGH Voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min, IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
VIL
Input LOW Voltage[2]
–0.3
0.8
–0.3
IIX
Input Leakage
Current
GND < VI < VCC
IOZ
Output Leakage Current
ICC
VCC Operating Supply
Current
ISB1
ISB2
2.4
Min
2.4
0.4
V
VCC
+ 0.3
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
μA
–1
+1
–1
+1
μA
80
mA
40
40
mA
10
10
mA
–1
+1
+1
GND < VI < VCC,
Output disabled
Com’l/Ind’l
–1
+1
Auto-A
–1
+1
VCC = Max, IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l
90
85
Ind’l
100
95
Auto-A
100
Automatic CE Power
Down Current — CMOS
Inputs
Max VCC, CE > VCC – 0.3V, Com’l/Ind’l
VIN > VCC – 0.3V, or
Auto-A
VIN < 0.3V, f = 0
10
V
2.0
–1
40
Unit
0.4
Auto-A
Max VCC, CE > VIH
Com’l/Ind’l
VIN > VIH or VIN < VIL, f = fMAX Auto-A
Max
2.4
0.4
Com’l/Ind’l
Automatic CE Power
Down Current —TTL
Inputs
Min
40
10
Note
2. VIL (min) = –2.0V for pulse durations of less than 20 ns.
Document Number: 38-05232 Rev. *F
Page 4 of 14
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CY7C1011CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max
Unit
8
pF
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Thermal Resistance
(Junction to Case)
TSOP II
TQFP
FBGA
Unit
44.56
42.66
46.98
°C/W
10.75
14.64
9.63
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms [3]
10-ns devices:
12-, 15-ns devices:
Z = 50Ω
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317Ω
3.3V
OUTPUT
30 pF*
OUTPUT
R2
351Ω
30 pF*
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.0V
ALL INPUT PULSES
90%
GND
90%
10%
Rise Time: 1 V/ns
3.3V
10%
(c)
Fall Time: 1 V/ns
OUTPUT
R2
351Ω
5 pF
(d)
Note
3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure 4 (a). All other speeds are tested using the Thevenin load shown
in Figure 4 (b). High-Z characteristics are tested for all speeds using the test load shown in Figure 4 (d).
Document Number: 38-05232 Rev. *F
Page 5 of 14
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CY7C1011CV33
Switching Characteristics
Over the Operating Range [4]
Parameter
Description
-10
Min
-12
Max
Min
-15
Max
Min
Max
Unit
Read Cycle
tpower[5]
VCC(Typical) to the First Access
1
1
1
μs
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
10
tDOE
OE LOW to Data Valid
5
[6]
OE LOW to Low Z
tLZOE
10
3
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low Z[6]
ns
12
15
ns
6
7
ns
3
0
5
3
Z[6, 7]
15
3
0
Z[6, 7]
12
0
6
3
5
ns
ns
7
ns
3
tHZCE
CE HIGH to High
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low Z
0
0
0
Byte Disable to High Z
tHZBE
6
ns
ns
0
0
5
7
ns
0
6
ns
7
ns
[8, 9]
Write Cycle
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
7
8
10
ns
tAW
Address Setup to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Setup to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Setup to Write End
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[6]
3
3
3
ns
tHZWE
WE LOW to High Z[6, 7]
tBW
Byte Enable to End of Write
5
7
6
8
7
10
ns
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 5. Transition is measured ±500
mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05232 Rev. *F
Page 6 of 14
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CY7C1011CV33
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05232 Rev. *F
Page 7 of 14
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CY7C1011CV33
Switching Waveforms
(continued)
Figure 7. Write Cycle No. 1 (CE Controlled)[13, 14]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA IO
Figure 8. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
tBW
BHE, BLE
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA IO
Notes
13. Data IO is high impedance if OE, BHE, and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05232 Rev. *F
Page 8 of 14
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CY7C1011CV33
Switching Waveforms
(continued)
Figure 9. Write Cycle No. 3 (WE Controlled, LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA IO
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High Z
IO0– IO7 IO8 – IO15
High Z
Power Down
Mode
Standby (ISB)
Power
L
L
H
L
L
Data Out
Data Out
Read – All Bits
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read – Lower Bits Only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read – Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write – All Bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write – Lower Bits Only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write – Upper Bits Only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document Number: 38-05232 Rev. *F
Page 9 of 14
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CY7C1011CV33
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1011CV33-10ZC
CY7C1011CV33-10ZXC
CY7C1011CV33-10ZXI
12
Package Type
51-85087 44-pin TSOP II
51-85150 48-ball (6 x 8 x 1 mm) VFBGA
CY7C1011CV33-10ZSXA
51-85087 44-pin TSOP II (Pb-Free)
CY7C1011CV33-12ZC
51-85087 44-pin TSOP II
CY7C1011CV33-12ZI
CY7C1011CV33-12ZXI
Operating
Range
Commercial
44-pin TSOP II (Pb-Free)
51-85087 44-pin TSOP II (Pb-Free)
CY7C1011CV33-10BVI
CY7C1011CV33-12ZXC
15
Package
Diagram
Industrial
Automotive-A
Commercial
44-pin TSOP II (Pb-Free)
51-85087 44-pin TSOP II
Industrial
44-pin TSOP II (Pb-Free)
CY7C1011CV33-12AXI
51-85064 44-pin TQFP (Pb-Free)
CY7C1011CV33-12BVI
51-85150 48-ball (6 x 8 x 1 mm) VFBGA
CY7C1011CV33-15ZXC
51-85087 44-pin TSOP II (Pb-Free)
Commercial
The 44 pin TSOP II package containing the Automotive grade device is designated as “ZS”, while the same package containing the Commercial/Industrial grade device
is “Z”.
Document Number: 38-05232 Rev. *F
Page 10 of 14
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CY7C1011CV33
Package Diagrams
Figure 10. 44-Pin Thin Small Outline Package Type II
51-85087-*A
Document Number: 38-05232 Rev. *F
Page 11 of 14
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CY7C1011CV33
Package Diagrams
(continued)
Figure 11. 44-pin Thin Plastic Quad Flat Pack
12.00±0.25 SQ
10.00±0.10 SQ
44
34
0° MIN.
1
33
0.37±0.05
R. 0.08 MIN.
0.20 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
GAUGE PLANE
R. 0.08 MIN.
0.20 MIN.
0-7°
0.20 MIN.
0.60±0.15
1.00 REF.
11
0.80
B.S.C.
23
DETAIL
12
A
22
NOTE:
1. JEDEC STD REF MS-026
SEATING PLANE
1.60 MAX.
12°±1°
(8X)
1.40±0.05
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.10
0.20 MAX.
SEE DETAIL
Document Number: 38-05232 Rev. *F
A
51-85064-*C
Page 12 of 14
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CY7C1011CV33
Package Diagrams
(continued)
Figure 12. 48-Ball FBGA (6 x 8 x 1 mm)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.10 C
0.21±0.05
0.25 C
B
0.15(4X)
51-85150-*D
Document Number: 38-05232 Rev. *F
1.00 MAX
0.26 MAX.
SEATING PLANE
C
Page 13 of 14
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CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM
Document Number: 38-05232
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
117132
07/31/02
HGK
New Data Sheet
*A
118057
08/19/02
HGK
Pin configuration for 48-ball FBGA correction
*B
119702
10/11/02
DFP
Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated
address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page 1
from 8 to 10 mA
*C
386106
See ECN
PCI
Added lead-free parts in Ordering Information Table
*D
498501
See ECN
NXR
Corrected typo in the Logic Block Diagram on page# 1
Included the Maximum Ratings for Static Discharge Voltage and Latch up Current on
page# 3
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Updated the Ordering Information Table
*E
522620
See ECN
VKN
Added Thermal Resistance Table
*F
1891366 See ECN VKN/AESA Added -10ZSXA part
Updated Ordering Information table
© Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05232 Rev. *F
Revised January 04, 2008
Page 14 of 14
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