Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 ISO122 Precision Lowest-Cost Isolation Amplifier 1 Features 3 Description • • • • • • • • The ISO122 is a precision isolation amplifier incorporating a novel duty cycle modulationdemodulation technique. The signal is transmitted digitally across a 2-pF differential capacitive barrier. With digital modulation the barrier characteristics do not affect signal integrity, thus resulting in excellent reliability and good high-frequency transient immunity across the barrier. Both barrier capacitors are imbedded in the plastic body of the package. 1 100% Tested for High-Voltage Breakdown Rated 1500 Vrms High IMR: 140 dB at 60 Hz Bipolar Operation: VO = ±10 V 16-Pin Plastic DIP and 28-Lead SOIC Ease of Use: Fixed Unity Gain Configuration 0.020% Maximum Nonlinearity ±4.5-V to ±18-V Supply Range 2 Applications • • • • • • Industrial Process Control: – Transducer Isolator, Isolator for Thermocouples, RTDs, Pressure Bridges, and Flow Meters, 4-mA to 20-mA Loop Isolation Ground Loop Elimination Motor and SCR Control Power Monitoring PC-Based Data Acquisition Test Equipment The ISO122 is easy to use. No external components are required for operation. The key specifications are 0.020% maximum nonlinearity, 50-kHz signal bandwidth, and 200-V/°C VOS drift. A power supply range of 4.5 V to 18 V and quiescent currents of 5 mA on VS1 and ±5.5 mA on VS2 make the ISO122 ideal for a wide range of applications. The ISO122 is available in 16-pin plastic DIP and 28-lead plastic surface-mount packages. Device Information(1) PART NUMBER ISO122 PACKAGE BODY SIZE (NOM) PDIP (16) 17.90 mm × 7.50 mm SOIC (28) 20.01 mm × 6.61 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic VIN VOUT –VS2 Gnd +VS2 –VS1 Gnd +VS1 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 8 8.3 Feature Description................................................... 8 8.4 Device Functional Modes.......................................... 9 9 Application and Implementation .......................... 9 9.1 Application Information.............................................. 9 9.2 Typical Application ................................................. 10 10 Power Supply Recommendations ..................... 17 10.1 Signal and Supply Connections ............................ 17 11 Layout................................................................... 18 11.1 Layout Guidelines ................................................. 18 11.2 Layout Example .................................................... 18 12 Device and Documentation Support ................. 19 12.1 Trademarks ........................................................... 19 12.2 Electrostatic Discharge Caution ............................ 19 12.3 Glossary ................................................................ 19 13 Mechanical, Packaging, and Orderable Information ........................................................... 19 5 Revision History Changes from Original (November1993) to Revision A • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 6 Pin Configuration and Functions 16 Pins PDIP NVF Package Top View 28 Pins SOIC DVA Package Top View +VS1 1 16 Gnd 1 +VS1 1 28 Gnd 1 –VS1 2 15 VIN –VS1 2 27 VIN VOUT 7 10 –VS2 VOUT 13 16 –VS2 Gnd 2 8 9 +VS2 Gnd 2 14 15 +VS2 Pin Functions PIN NAME I/O DESCRIPTION PDIP SOIC GND 8 14 - Low-side ground reference GND 16 28 - High-side ground reference VIN 15 27 I High-side analog input VOUT 7 13 O Low-side analog output +VS1 1 1 - High-side positive analog supply -VS1 2 2 - High-side negative analog supply +VS2 9 15 - Low-side positive analog supply -VS2 10 16 - Low-side negative analog supply Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 3 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Supply voltage MAX UNIT ±18 V VIN 100 V Continuous isolation voltage 1500 Vrms Junction temperature 150 °C Output short to common Continuous Storage temperature, Tstg (1) –40 125 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TA NOM MAX –25 85 +VS1 15 -VS1 –15 +VS2 15 -VS2 –15 VIN ±10 UNIT °C 7.4 Thermal Information ISO122 THERMAL METRIC (1) NVF (PDIP) DVA (SOIC) 16 PINS 28 PINS RθJA Junction-to-ambient thermal resistance 51.0 79.8 RθJC(top) Junction-to-case (top) thermal resistance 32.4 32.9 RθJB Junction-to-board thermal resistance 29.5 42.2 ψJT Junction-to-top characterization parameter 10.4 6.6 ψJB Junction-to-board characterization parameter 29.0 40.9 (1) 4 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 7.5 Electrical Characteristics At TA = +25°C , VS1 = VS2 = ±15 V, and RL = 2 kΩ, unless otherwise noted. PARAMETER TEST CONDITIONS ISO122P/U MIN TYP ISO122JP/JU MAX MIN TYP MAX UNIT ISOLATION Voltage rated continuous ac 60Hz 100% Test (1) 1s, 5pc PD Isolation Mode Rejection 60Hz 1500 1500 Vac 2400 2400 Vac Barrier Impedance Leakage Current at 60Hz VISO = 240Vrms 140 140 1014 || 2 1014 || 2 0.18 dB Ω || pF 0.5 0.18 0.5 µArms ±0.50 ±0.05 ±0.50 %FSR ±0.016 ±0.020 ±0.025 ±0.050 ±20 ±50 GAIN Nominal Gain 1 VO = ±10V Gain Error ±0.05 Gain vs Temperature 1 ±10 Nonlinearity (2) V/V ±10 ppm/°C %FSR INPUT OFFSET VOLTAGE Initial Offset ±20 vs Temperature vs Supply ±50 ±200 ±200 ±2 ±2 Noise mV µV/°C mV/V 4 µV/√Hz INPUT Voltage Range ±10 Resistance ±12.5 ±10 200 ±12.5 V 200 kΩ OUTPUT Voltage Range Current Drive ±10 ±12.5 ±10 ±12.5 ±5 ±15 ±5 ±15 mA 0.1 0.1 µF 20 20 mVp-p 50 50 kHz Capacitive Load Drive Ripple Voltage (3) V FREQUENCY RESPONSE Small-Signal Bandwidth Slew Rate Settling Time 0.10% Settling Time 0.01% VO = ±10V Overload Recovery Time 2 2 V/µs 50 50 µs 350 350 µs 150 150 µs POWER SUPPLIES Rated Voltage Voltage Range VS1 VS2 ±15 ±4.5 Quiescent Current ±15 ±18 ±4.5 V ±18 ±5 ±7 ±5 ±7 ±5.5 ±7 ±5.5 ±7 V mA TEMPERATURE RANGE θJA θJC (1) (2) (3) Specification –25 85 –25 85 °C Operating –25 85 –25 85 °C Storage –40 125 –40 125 °C Thermal Resistance 100 100 °C/W 65 65 °C/W Tested at 1.6 X rated, fail on 5pC partial discharge. Nonlinearity is the peak deviation of the output voltage from the best-fit straight line. It is expressed as the ratio of deviation to FSR. Ripple frequency is at carrier frequency (500kHz). Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 5 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com 7.6 Typical Characteristics At TA = +25°C, and VS = ±15 V, unless otherwise noted. +10 Output Voltage (V) Output Voltage (V) +10 0 –10 0 500 0 –10 0 1000 50 Time (µs) f = 2kHz f = 20kHz Figure 1. Sine Response Figure 2. Sine Response +10 Output Voltage (V) +10 Output Voltage (V) 100 Time (µs) 0 –10 0 500 0 –10 50 0 1000 100 Time (µs) Time (µs) Figure 3. Step Response Figure 4. Step Response 160 Max DC Rating 140 1k 120 IMR (dB) Peak Isolation Voltage 2.1k Degraded Performance 100 100 80 Typical Performance 60 0 40 100 1k 10k 100k 1M 10M 100M 1 Frequency (Hz) 100 1k 10k 100k 1M Frequency (Hz) Figure 5. Isolation Voltage vs Frequency 6 10 Submit Documentation Feedback Figure 6. IMR vs Frequency Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 Typical Characteristics (continued) At TA = +25°C, and VS = ±15 V, unless otherwise noted. 60 54 100mA Leakage Current (rms) PSRR (dB) 10mA 40 +VS1 , +VS2 –VS1 , –VS2 20 1mA 1500Vrms 100mA 10mA 240Vrms 1mA 0.1mA 0 1 10 100 1k 10k 100k 1 1M 10 100 10k 100k 1M Figure 8. Isolation Leakage Current vs Frequency VOUT/VIN 100kHz Freq Out 0 250 –10 200 –20 150 –30 100 –40 50 0 500kHz 1MHz Frequency Out Figure 7. PSRR vs Frequency V OUT / VIN dBm 1k Frequency (Hz) Frequency (Hz) 1.5MHz Input Frequency NOTE: Shaded area shows aliasing frequencies that cannot be removed by a low-pass filter at the output. Figure 9. Signal Response to Inputs Greater than 250 kHz Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 7 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The ISO122 isolation amplifier uses an input and an output section galvanically isolated by matched 1-pF isolating capacitors built into the plastic package. The input is duty-cycle modulated and transmitted digitally across the barrier. The output section receives the modulated signal, converts it back to an analog voltage and removes the ripple component inherent in the demodulation. Input and output sections are fabricated, then laser trimmed for exceptional circuitry matching common to the input and output sections. The sections are then mounted on opposite ends of the package with the isolating capacitors mounted between the two sections. The ISO122 contains 250 transistors. 8.1.1 Modulator An input amplifier (A1, Functional Block Diagram) integrates the difference between the input current (VIN/200 kΩ) and a switched ±100-mA current source. This current source is implemented by a switchable 200-mA source and a fixed 100-µA current sink. To understand the basic operation of the modulator, assume that VIN = 0 V. The integrator will ramp in one direction until the comparator threshold is exceeded. The comparator and sense amp will force the current source to switch; the resultant signal is a triangular waveform with a 50% duty cycle. The internal oscillator forces the current source to switch at 500 kHz. The resultant capacitor drive is a complementary duty-cycle modulation square wave. 8.1.2 Demodulator The sense amplifier detects the signal transitions across the capacitive barrier and drives a switched current source into integrator A2. The output stage balances the duty-cycle modulated current against the feedback current through the 200 kW feedback resistor, resulting in an average value at the VOUT pin equal to VIN. The sample and hold amplifiers in the output feedback loop serve to remove undesired ripple voltages inherent in the demodulation process. 8.2 Functional Block Diagram Isolation Barrier 200µA 200µA Sense 150pF 200kW VIN 1pF 1pF 1pF 1pF Sense 150pF 100µA 200kW 100µA VOUT – – || + A1 A2 S/H G=1 Osc +VS1 Gnd 1 –VS1 +VS2 + S/H G=6 Gnd 2 –VS2 8.3 Feature Description 8.3.1 Isolation Amplifier The ISO122 is a precision analog isolation amplifier. The input signal is transmitted digitally across a high-voltage differential capacitive barrier. With digital modulation the barrier characteristics do affect signal integrity, resulting in excellent reliability and high-frequency transient immunity. 8 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 8.4 Device Functional Modes The ISO122 does not have any additional functional modes. 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Carrier Frequency Considerations The ISO122 amplifier transmits the signal across the isolation barrier by a 500kHz duty cycle modulation technique. For input signals having frequencies below 250 kHz, this system works like any linear amplifier. But for frequencies above 250 kHz, the behavior is similar to that of a sampling amplifier. The signal response to inputs greater than 250 kHz performance curve shows this behavior graphically; at input frequencies above 250 kHz the device generates an output signal component of reduced magnitude at a frequency below 250 kHz. This is the aliasing effect of sampling at frequencies less than two times the signal frequency (the Nyquist frequency). At the carrier frequency and its harmonics, both the frequency and amplitude of the aliasing go to zero. 9.1.2 Isolation Mode Voltage Induced Errors IMV can induce errors at the output as indicated by the plots of IMV vs Frequency. It should be noted that if the IMV frequency exceeds 250 kHz, the output also will display spurious outputs (aliasing), in a manner similar to that for VIN > 250 kHz and the amplifier response will be identical to that shown in the Signal Response to Inputs Greater Than 250-kHz performance curve. This occurs because IMV-induced errors behave like input-referred error signals. To predict the total error, divide the isolation voltage by the IMR shown in the IMR vs Frequency curve and compute the amplifier response to this input-referred error signal from the data given in the Signal Response to Inputs Greater than 250-kHz performance curve. For example, if a 800-kHz 1000-Vrms IMR is present, then a total of [(–60 dB) + (–30 dB)] x (1000 V) = 32-mV error signal at 200 kHz plus a 1 V, 800-kHz error signal will be present at the output. 9.1.3 High IMV dV/dt Errors As the IMV frequency increases and the dV/dt exceeds 1000 Vµs, the sense amp may start to false trigger, and the output will display spurious errors. The common-mode current being sent across the barrier by the high slew rate is the cause of the false triggering of the sense amplifier. Lowering the power-supply voltages below ±15 V may decrease the dV/dt to 500 V/µs for typical performance. 9.1.4 High Voltage Testing Texas Instruments has adopted a partial discharge test criterion that conforms to the German VDE0884 Optocoupler Standards. This method requires the measurement of minute current pulses (< 5 pC) while applying 2400-Vrms, 60-Hz high-voltage stress across every ISO122 isolation barrier. No partial discharge may be initiated to pass this test. This criterion confirms transient overvoltage (1.6 × 1500 Vrms) protection without damage to the ISO122. Lifetest results verify the absence of failure under continuous rated voltage and maximum temperature. This new test method represents the “state of the art” for nondestructive high–voltage reliability testing. It is based on the effects of nonuniform fields that exist in heterogeneous dielectric material during barrier degradation. In the case of void nonuniformities, electric field stress begins to ionize the void region before bridging the entire high-voltage barrier. The transient conduction of charge during and after the ionization can be detected externally as a burst of 0.01–0.1 ms current pulses that repeat on each AC voltage cycle. The minimum AC barrier voltage that initiates partial discharge is defined as the “inception voltage.” Decreasing the barrier voltage to a lower level is required before partial discharge ceases and is defined as the “extinction voltage.” The Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 9 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com Application Information (continued) package insulation processes have been characterized and developed to yield an inception voltage in excess of 2400 Vrms so that transient overvoltages below this level will not damage the ISO122. The extinction voltage is above 1500 Vrms so that even overvoltage induced partial discharge will cease once the barrier voltage is reduced to the 1500 Vrms (rated) level. Older high-voltage test methods relied on applying a large enough overvoltage (above rating) to break down marginal parts, but not so high as to damage good ones. Our new partial discharge testing gives us more confidence in barrier reliability than breakdown/no breakdown criteria. 9.2 Typical Application 9.2.1 Output Filter C2 1000pF +VS1 +VS2 1 VIN 15 In 9 7 ISO 122 8 16 Gnd R1 R2 4.75kW 9.76kW A1 OPA602 10 C1 220pF –VS2 Gnd2 2 VOUT = VIN Gnd1 –VS1 Figure 10. ISO122 With Output Filter for Improved Ripple 9.2.1.1 Design Requirements The ISO122 isolation amplifiers (ISO amps) have a small (10 to 20 mVp-p typical) residual demodulator ripple at the output. A simple filter can be added to eliminate the output ripple without decreasing the 50-kHz signal bandwidth of the ISO amp. 9.2.1.2 Detailed Design Procedure The ISO122 is designed to have a 50-kHz single-pole (Butterworth) signal response. By cascading the ISO amp with a simple 50-kHz, Q = 1, two-pole, low-pass filter, the overall signal response becomes three-pole Butterworth. The result is a maximally flat 50-kHz magnitude response and the output ripple reduced below the noise level. Figure 10 shows the complete circuit. The two-pole filter is a unity-gain Sallen-Key type consisting of A1, R1, R2, C1, and C2. The values shown give Q = 1 and f–3-dB bandwidth = 50 kHz. Because the op amp is connected as a unity-gain follower, gain and gain accuracy of the ISO amp are unaffected. Using a precision op amp such as the OPA602 also preserves the DC accuracy of the ISO amp. 10 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 Typical Application (continued) 9.2.1.3 Application Curves +3 0 Gain (dB) –3 1 –9 2 –15 –21 –27 2k 5k 10k 20k 50k Frequency (Hz) 100k 200k 1) Standard ISO122 has 50kHz single-pole (Butterworth) response. 2) ISO122 with cascaded 50kHz, Q = 1, two-pole, low-pass filter has three-pole Butterworth response. Figure 11. Gain vs. Frequency Figure 12. Standard ISO122 (Approximately 20-mVp-p Output Ripple) Figure 13. Filtered ISO122 (No Visible Output Ripple) Figure 14. Step Response of Standard ISO122 Figure 15. Step Response of ISO122 With Added Twopole Output Filter Figure 16. Large-signal, 10 kHz Sine-wave Response of ISO122 With and Without Output Filter Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 11 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com Typical Application (continued) 9.2.2 Battery Monitor Figure 17 provides a means to monitor the cell voltage on a 600-V battery stack by using the battery as a power source for the isolated voltage. This Section Repeated 49 Times. ISO122P 10kW 1 e1 = 12V +V 9 10kW 15 V = e1 2 7 8 10 e2 = 12V 2 –V Multiplexer 16 Control Section Charge/Discharge Control ISO122P e49=12V 1 15 +V 9 7 e50=12V 2 25kW +V –V 7 4 25kW 5 8 10kW 10 2 10kW 25kW –V + 3 25kW 16 – INA105 6 V = e50 2 1 (Derives Input Power from the Battery.) Figure 17. Battery Monitor for a 600-V Battery Power System 12 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 Typical Application (continued) 9.2.3 Programmable Gain Amplifier In applications where variable gain configurations are required, a programmable gain amplifier like the PGA102 can be used with the ISO122. Figure 18 uses an ISO150 to provide gain pin selection options to the PGA102. A0 A1 ISO150 +15V –15V +15V –15V 1 2 1 VIN 6 2 7 PGA 8 102 45 3 9 10 15 15 7 VOUT 8 ISO122P 16 Figure 18. Programmable-Gain Isolation Channel With Gains of 1, 10, and 100 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 13 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com Typical Application (continued) 9.2.4 Thermocouple Amplifier For isolated temperature measurements, Figure 19 provides an application solution using the INA101 feeding the input stage of the ISO122. The table provides suggested resistor values based on the type of thermistor used in the application. +15V 2 10.0V 6 REF 102 Thermocouple 4 R4 +15V –15V R1 27kW Isothermal Block with 1N4148 (1) 1MW +15V –15V +15V 1 12 RG R2 2 2 4 +In 5 INA101 10 11 –In 1 R5 50W R6 10 15 14 7 VOUT 8 13 16 3 R3 100W ISO122P 9 –15V 100 Zero Adj ISA TYPE E Ground Loop Through Conduit J NOTE: (1) –2.1mV/°C at 2.00µA. K T MATERIAL SEEBACK COEFFICIENT (µV/°C) R2 (R3 = 100W) R4 (R5 + R6 = 100W) 58.5 3.48kW 56.2kW 50.2 4.12kW 64.9kW 39.4 5.23kW 80.6kW 38.0 5.49kW 84.5kW Chromel Constantan Iron Constantan Chromel Alumel Copper Constantan Figure 19. Thermocouple Amplifier With Ground Loop Elimination, Cold Junction Compensation, and Up-scale Burn-out. 14 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 Typical Application (continued) 9.2.5 Isolated 4- to 20-mA Instrument Loop For isolated temperature measurements in a 4- to 20-mA loop, Figure 20 provides a solution using the XTR101 and RCV420. A high-performance PT100 resistance temperature detector (RTD) provides the user with an isolated 0- to 5-V representation of the isolated temperature measurement. 1mA 1mA 10 8 5 RS XTR101 4-20mA 0.01µF 11 3 +VS =15V on PWS740 6 4 R1 = 100W 7 3 16 1 14 2 RCV420 5, 13 10 4 RTD (PT100) ISO122P 15 +V 15 9 7 8 11 R2 = 2.5kW 10 12 VOUT 0V-5V 2 16 –V 2mA Gnd –VS = –15V on PWS740 Figure 20. Isolated 4- to 200-mA Instrument Loop. (RTD shown.) 9.2.6 Single-Supply Operation of the ISO122P Isolation Amplifier The circuit shown in Figure 21 uses a 5.1-V Zener diode to generate the negative supply for an ISO122 from a single supply on the high-voltage side of the isolation amplifier. The input measuring range will be dependent on the applied voltage as noted in the accompanying table. VS1 (+15V) VS (V) INPUT RANGE (V)(1) 20+ 15 12 –2 to +10 –2 to +5 –2 to +2 7 INA105 Difference Amp 2 5 R1 10kW 6 Signal Source VIN + RS R4 R3 3 +VS2 (+15V) R2 15 In RC GND 16 4 9 ISO ISO 122P 122 122P (1) 1 1 Reference IN4689 5.1V NOTE: (1) Select to match RS . 7 8 VOUT = VIN 10 2 –VS1 Com 2 –VS2 (–15V) NOTE: Since the amplifier is unity gain, the input range is also the output range. The output can go to –2V since the output section of the ISO amp operates from dual supplies. For additional information see SBOA004. Figure 21. Single-Supply Operation of the ISO122P Isolation Amplifier Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 15 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com Typical Application (continued) 9.2.7 Input-Side Powered ISO Amp The user side of the ISO122 can be powered from the high-voltage side using an isolated DC-DC converter as shown in Figure 22. 1 2 4 5 6 HPR117 –15V, 20mA VIN Input GND +15V, 20mA 15 10 9 GND VIN 16 V– V+ INPUT SECTION V+ V– 1 2 Auxiliary Isolated Power Output OUTPUT SECTION ISO122P V O 7 GND 8 +15V Output GND –15V VO Figure 22. Input-Side Powered ISO Amp 9.2.8 Powered ISO Amp With Three-Port Isolation Figure 23 shows an application solution that provides isolated power to both the user and high-voltage sides of the ISO122 amplifier. +15V GND 1 2 5 4 5 6 HPR117 HPR117 6 4 2 1 VIN –15V, 20mA Input GND +15V, 20mA 15 10 9 GND VIN 16 V– V+ INPUT SECTION Auxiliary Isolated Power Output V+ V– 1 2 ISO122P Auxiliary Isolated Power Output OUTPUT SECTION V O 7 GND 8 +15V, 20mA Output GND –15V, 20mA VO Figure 23. Powered ISO Amp With Three-Port Isolation 16 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 10 Power Supply Recommendations 10.1 Signal and Supply Connections Each power-supply pin should be bypassed with 1-µF tantalum capacitors located as close to the amplifier as possible. The internal frequency of the modulator/demodulator is set at 500 kHz by an internal oscillator. Therefore, if it is desired to minimize any feedthrough noise (beat frequencies) from a DC-DC converter, use a π filter on the supplies (see Figure 24). The ISO122 output has a 500-kHz ripple of 20 mV, which can be removed with a simple 2-pole low-pass filter with a 100-kHz cutoff using a low-cost op amp (see Figure 10). The input to the modulator is a current (set by the 200-kΩ integrator input resistor) that makes it possible to have an input voltage greater than the input supplies, as long as the output supply is at least ±15 V. It is therefore possible, when using an unregulated DC-DC converter, to minimize PSR related output errors with ±5-V voltage regulators on the isolated side and still get the full ±10V input and output swing. Isolation Barrier VIN VOUT –VS2 Gnd Gnd +VS2 +VS1 – VS1 –VS1 1µF 1µF –VS2 1µF 1µF Figure 24. Basic Signal and Power Connections Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 17 ISO122 SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 www.ti.com 11 Layout 11.1 Layout Guidelines To maintain the isolation barrier of the device, the distance between the high-side ground (pin 16 or 28) and the low-side ground (pin 8 or 14) should be kept at maximum; that is, the entire area underneath the device should be kept free of any conducting materials. 11.2 Layout Example Top View 1 µF SMD 0603 1 µF 1 +VS1 GND VIN -VS1 SMD 0603 ISOLATION BOUNDARY ISOLATION BOUNDARY ISO122 1 µF VOUT -VS2 GND +VS2 SMD 0603 LEGEND TOP layer: copper pour & traces 1 µF GND SMD 0603 via to ground plane Figure 25. Typical Layout 18 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 ISO122 www.ti.com SBOS160A – NOVEMBER 1993 – REVISED JANUARY 2015 12 Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. 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Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: ISO122 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO122JP ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 ISO122JP ISO122JPE4 ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 ISO122JP ISO122JU ACTIVE SOIC DVA 8 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 ISO 122JU ISO122JU/1K ACTIVE SOIC DVA 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 ISO 122JU ISO122JUE4 ACTIVE SOIC DVA 8 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 ISO 122JU ISO122P ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 ISO122P ISO122PE4 ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -25 to 85 ISO122P ISO122U ACTIVE SOIC DVA 8 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 ISO 122U ISO122U/1K ACTIVE SOIC DVA 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 ISO 122U ISO122U/1KE4 ACTIVE SOIC DVA 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 ISO 122U ISO122UE4 ACTIVE SOIC DVA 8 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 ISO 122U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2014 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO122JU/1K SOIC DVA 8 1000 330.0 24.4 10.9 18.3 3.2 12.0 24.0 Q1 ISO122U/1K SOIC DVA 8 1000 330.0 24.4 10.9 18.3 3.2 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Sep-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO122JU/1K SOIC DVA 8 1000 367.0 367.0 45.0 ISO122U/1K SOIC DVA 8 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MPDI072 – AUGUST 2001 NVF (R-PDIP-T8/16) PLASTIC DUAL-IN-LINE 0.775 (21,34) 0.735 (18,67) D 16 9 0.280 (7,11) 0.240 (6,10) Index Area 1 D 8 0.195 (4,95) 0.115 (2,92) 0.045 (1,14) 0.030 (0,76) 0.210 (5,33) MAX 0.070 (1,78) 0.045 (1,14) 0.325 (8,26) 0.300 (7,62) C Seating Plane Base Plane E 0.005 (0,13) MIN 4 PL D 1/2 Lead 0.150 (3,81) 0.115 (2,92) 0.100 (2,54) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25) M 0.015 (0,38) MIN C 0.300 (7,63) 0.014 (0,36) 0.008 (0,20) 0.060 (1,52) 0.000 (0,00) F 0.430 (10,92) MAX F 4202501/A 08/01 A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001-BB with the exception of lead count. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. A visual index feature must be located within the cross-hatched area. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MPDS105 – AUGUST 2001 DVA (R-PDSO-G8/28) PLASTIC SMALL-OUTLINE C A 18,10 17,70 0,25 M B M 28 15 B 7,60 7,40 10,65 10,01 D Index Area 1 14 2,65 2,35 C 0,75 0,25 x 45° Seating Plane 1,27 G 0,51 0,33 0,30 0,10 0,10 0,32 0,23 0,25 M C A M B S 0°–8° F 1,27 0,40 4202103/B 08/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body length dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0,15 mm per side. D. Body width dimension does not include inter-lead flash or portrusions. Inter-lead flash and protrusions shall not exceed 0,25 mm per side. E. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the cross-hatched area. G. Lead width, as measured 0,36 mm or greater above the seating plane, shall not exceed a maximum value of 0,61 mm. H. Lead-to-lead coplanarity shall be less than 0,10 mm from seating plane. I. Falls within JEDEC MS-013-AE with the exception of the number of leads. F. Lead dimension is the length of terminal for soldering to a substrate. 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