STMicroelectronics M29DW324DB70ZE1T 32 mbit 4mb x8 or 2mb x16, dual bank 16:16, boot block 3v supply flash memory Datasheet

M29DW324DT
M29DW324DB
32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– VCC = 2.7V to 3.6V for Program, Erase and
Read
■
– VPP =12V for Fast Program (optional)
ACCESS TIME: 70, 90ns
■
PROGRAMMING TIME
– 10µs per Byte/Word typical
– Double Word/ Quadruple Byte Program
■
TSOP48 (N)
12 x 20mm
MEMORY BLOCKS
– Dual Bank Memory Array: 16Mbit+16Mbit
– Parameter Blocks (Top or Bottom Location)
■
DUAL OPERATIONS
– Read in one bank while Program or Erase in
other
■
ERASE SUSPEND and RESUME MODES
FBGA
TFBGA63 (ZA)
7 x 11mm
– Read and Program another Block during
Erase Suspend
■
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■
VPP/WP PIN for FAST PROGRAM and WRITE
PROTECT
■
TEMPORARY BLOCK UNPROTECTION
MODE
■
COMMON FLASH INTERFACE
FBGA
TFBGA48 (ZE)
6 x 8mm
– 64 bit Security Code
■
EXTENDED MEMORY BLOCK
– Extra block used as security block or to store
additional information
■
LOW POWER CONSUMPTION
– Standby and Automatic Standby
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29DW324DT: 225Ch
– Bottom Device Code M29DW324DB: 225Dh
June 2003
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M29DW324DT, M29DW324DB
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA63 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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M29DW324DT, M29DW324DB
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Exit Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. 48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . . . . . . 29
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M29DW324DT, M29DW324DB
Table 17. 48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . . . . . . 29
Figure 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline . . . . 30
Table 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . 30
Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline . . . . . 31
Table 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 21. Top Boot Block Addresses, M29DW324DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Bottom Boot Block Addresses, M29DW324DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 27. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 28. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 29. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 30. Programmer Technique Bus Operations, BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . 43
Figure 20. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 21. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 23. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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M29DW324DT, M29DW324DB
SUMMARY DESCRIPTION
The M29DW324D is a 32 Mbit (4Mb x8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The device features an asymmetrical block architecture. The M29DW324D has an array of 8 parameter and 63 main blocks and is divided into two
Banks, A and B, providing Dual Bank operations.
While programming or erasing in Bank A, read operations are possible in Bank B and vice versa.
Only one bank at a time is allowed to be in program or erase mode. The bank architecture is
summarized in Table 2. M29DW324DT locates the
Parameter Blocks at the top of the memory address space while the M29DW324DB locates the
Parameter Blocks starting from the bottom.
M29DW324D has an extra 32 KWord (x16 mode)
or 64 KByte (x8 mode) block, the Extended Block,
that can be accessed using a dedicated command. The Extended Block can be protected and
so is useful for storing security information. How-
ever the protection is irreversible, once protected
the protection cannot be undone.
Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase commands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identified. The command set required to control the
memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12x20mm),
TFBGA63 (7x11mm, 0.8mm pitch) and TFBGA48
(6x8mm, 0.8mm pitch) packages. The memory is
supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
VCC VPP/WP
21
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organization Select
VCC
Supply Voltage
VPP/WP
VPP/Write Protect
VSS
Ground
NC
Not Connected Internally
15
A0-A20
DQ0-DQ14
DQ15A–1
W
E
A0-A20
M29DW324DT
M29DW324DB
G
RB
RP
BYTE
VSS
AI06867B
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M29DW324DT, M29DW324DB
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
W
RP
NC
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
M29DW324DT
M29DW324DB
12
13
37
36
24
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI06805
6/49
M29DW324DT, M29DW324DB
Figure 4. TFBGA63 Connections (Top view through package)
1
2
A
NC(1)
NC(1)
B
NC(1)
3
4
5
6
7
8
NC(1)
NC(1)
NC(1)
NC(1)
C
A3
A7
RB
W
A9
A13
D
A4
A17
VPP/WP
RP
A8
A12
E
A2
A6
A18
NC
A10
A14
F
A1
A5
A20
A19
A11
A15
G
A0
DQ0
DQ2
DQ5
DQ7
A16
H
E
DQ8
DQ10
DQ12
DQ14
BYTE
J
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
K
VSS
DQ1
DQ3
DQ4
DQ6
VSS
L
NC(1)
NC(1)
NC(1)
NC(1)
M
NC(1)
NC(1)
NC(1)
NC(1)
AI05525B
Note: 1. Balls are shorted together via the substrate but not connected to the die.
7/49
M29DW324DT, M29DW324DB
Figure 5. TFBGA48 Connections (Top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP/WP
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI08084
Table 2. Bank Architecture
Parameter Blocks
Bank
8/49
Bank Size
Main Blocks
No. of
Blocks
Block Size
No. of Blocks
Block Size
A
16 Mbit
8
8KByte/ 4 KWord
31
64KByte/ 32 KWord
B
16 Mbit
—
—
32
64KByte/ 32 KWord
M29DW324DT, M29DW324DB
Figure 6. Block Addresses (x8)
Top Boot Block (x8)
Address lines A20-A0, DQ15A-1
000000h
00FFFFh
Bottom Boot Block (x8)
Address lines A20-A0, DQ15A-1
000000h
64 KByte or
32 KWord
001FFFh
8 KByte or
4 KWord
Total of 32
Main Blocks
Bank B
1F0000h
1FFFFFh
200000h
20FFFFh
Total of 8
Parameter
Blocks (1)
00E000h
64 KByte or
32 KWord
Bank A
64 KByte or
32 KWord
00FFFFh
010000h
01FFFFh
8 KByte or
4 KWord
64 KByte or
32 KWord
Total of 31
Main Blocks
3E0000h
Bank A
3EFFFFh
3F0000h
3F1FFFh
1F0000h
64 KByte or
32 KWord
1FFFFFh
200000h
8 KByte or
4 KWord
20FFFFh
Total of 8
Parameter
Blocks (1)
3FE000h
3FFFFFh
Total of 31
Main Blocks
8 KByte or
4 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 32
Main Blocks
Bank B
3F0000h
3FFFFFh
64 KByte or
32 KWord
AI06803
Note: 1. Used as Extended Block Addresses in Extended Block mode.
2. Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.
9/49
M29DW324DT, M29DW324DB
Figure 7. Block Addresses (x16)
Top Boot Block (x16)
Address lines A20-A0
000000h
007FFFh
Bottom Boot Block (x16)
Address lines A20-A0
000000h
64 KByte or
32 KWord
000FFFh
8 KByte or
4 KWord
Total of 32
Main Blocks
Bank B
0F8000h
0FFFFFh
100000h
107FFFh
Total of 8
Parameter
Blocks (1)
007000h
64 KByte or
32 KWord
Bank A
64 KByte or
32 KWord
007FFFh
008000h
00FFFFh
8 KByte or
4 KWord
64 KByte or
32 KWord
Total of 31
Main Blocks
1F0000h
Bank A
1F7FFFh
1F8000h
1F8FFFh
0F8000h
64 KByte or
32 KWord
0FFFFFh
100000h
8 KByte or
4 KWord
107FFFh
Total of 8
Parameter
Blocks (1)
1FF000h
1FFFFFh
Total of 31
Main Blocks
8 KByte or
4 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 32
Main Blocks
Bank B
1F8000h
1FFFFFh
64 KByte or
32 KWord
AI05555
Note: 1. Used as Extended Block Addresses in Extended Block mode.
2. Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.
10/49
M29DW324DT, M29DW324DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V IH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
VPP/Write
VPP/Write Protect (VPP/WP). The
Protect pin provides two functions. The VPP function allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.
When V PP/Write Protect is Low, VIL, the memory
protects the two outermost boot blocks; Program
and Erase operations in these blocks are ignored
while V PP/Write Protect is Low, even when RP is
at VID.
When VPP/Write Protect is High, VIH, the memory
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block
Protection.
When V PP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode.
When V PP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
VIH to V PP and from V PP to VIH must be slower
than tVHVPP, see Figure 16.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating
or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the V PP/Write Protect pin and the V SS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I PP.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V PP/WP is at VIL, then the two outermost boot blocks will remain protected even if RP
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V IL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 16 and Figure 15, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V ID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
11/49
M29DW324DT, M29DW324DB
Ready/Busy is Low, V OL. Ready/Busy is high-impedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 16 and Figure
15, Reset/Temporary Unprotect AC Characteristics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, V IH, the memory is in x16 mode.
12/49
VCC Supply Voltage (2.7V to 3.6V). VCC
provides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the V CC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, ICC3.
VSS Ground. VSS is the reference for all voltage
measurements. The device features two V SS pins
which must be both connected to the system
ground.
M29DW324DT, M29DW324DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby.
The Dual Bank architecture of the M29DW324D
allows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time.
See Tables 3 and 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V IL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 12, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 14 and 15, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V IH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 12, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.
Block Protect and Chip Unprotect. Groups
of
blocks can be protected against accidental Program or Erase. The Protection Groups are shown
in Appendix A, Tables 21 and 22, Block Addresses. The whole chip can be unprotected to allow the
data inside the blocks to be changed.
The VPP/Write Protect pin can be used to protect
the two outermost boot blocks. When VPP/Write
Protect is at VIL the two outermost boot blocks are
protected and remain protected regardless of the
Block Protection Status or the Reset/Block Temporary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in Appendix D.
13/49
M29DW324DT, M29DW324DB
Table 3. Bus Operations, BYTE = V IL
Operation
E
G
Address Inputs
DQ15A–1, A0-A20
W
Data Inputs/Outputs
DQ14-DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Hi-Z
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Hi-Z
Data Input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
20h
Read Device Code
VIL
VIL
VIH
A0 = VIH, A1 = VIL,
A9 = VID, Others VIL or VIH
Hi-Z
5Ch (M29DW324DT)
5Dh (M29DW324DB)
Extended Memory
Block Verify Code
VIL
VIL
VIH
A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH
Hi-Z
81h (factory locked)
01h (not factory locked)
Output Disable
Note: X = VIL or VIH.
Table 4. Bus Operations, BYTE = V IH
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
E
G
W
Bus Read
VIL
VIL
VIH
Cell Address
Bus Write
VIL
VIH
VIL
Command Address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
0020h
Read Device Code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
225Ch (M29DW324DT)
225Dh (M29DW324DB)
Extended Memory
Block Verify Code
VIL
VIL
VIH
A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH
81h (factory locked)
01h (not factory locked)
Operation
Output Disable
Note: X = VIL or VIH.
14/49
Data Output
Data Input
M29DW324DT, M29DW324DB
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 5, or 6, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the timeout of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.
Auto Select Command
The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. It can be addressed to either Bank.
Three consecutive Bus Write operations are required to issue the Auto Select command. The final Write cycle must be addressed to one of the
Banks. Once the Auto Select command is issued
Bus Read operations to the Bank where the command was issued output the Auto Select data. Bus
Read operations to the other Bank will output the
contents of the memory array. The memory remains in Auto Select mode until a Read/Reset or
CFI Query command is issued.
In Auto Select mode the Manufacturer Code can
be read using a Bus Read operation with A0 = V IL
and A1 = VIL and A20 = Bank Address. The other
address bits may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL and A20 =
Bank Address. The other address bits may be set
to either VIL or VIH.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = V IH, A20 = Bank Address and A12-A17 specifying the address of the block inside the Bank.
The other address bits may be set to either V IL or
VIH. If the addressed block is protected then 01h is
output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
Read CFI Query Command
The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the device is in the Read Array mode, or when the device
is in Autoselected mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is issued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselected mode.
See Appendix B, Tables 23, 24, 25, 26, 27 and 28
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Program Command
The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase
Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. After
programming has started, Bus Read operations in
the Bank being programmed output the Status
Register content, while Bus Read operations to
the other Bank output the contents of the memory
array. See the section on the Status Register for
more details. Typical program times are given in
Table 7.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Register. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
15/49
M29DW324DT, M29DW324DB
Fast Program Commands
There are two Fast Program commands available
to improve the programming throughput, by writing
several adjacent words or bytes in parallel. The
Quadruple Byte Program command is available for
x8 operations, while the Double Word Program
command is available for x16 operations.
Quadruple Byte Program Command. The Quadruple Byte Program command is used to write a
page of four adjacent Bytes in parallel. The four
bytes must differ only for addresses A0, DQ15A-1.
Five bus write cycles are necessary to issue the
Quadruple Byte Program command.
■ The first bus cycle sets up the Quadruple Byte
Program Command.
■ The second bus cycle latches the Address and
the Data of the first byte to be written.
■ The third bus cycle latches the Address and the
Data of the second byte to be written.
■ The fourth bus cycle latches the Address and
the Data of the third byte to be written.
■ The fifth bus cycle latches the Address and the
Data of the fourth byte to be written and starts
the Program/Erase Controller.
Double Word Program Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must differ only for the address A0.
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Programming should not be attempted when VPP
is not at V PPH.
After programming has started, Bus Read operations in the Bank being programmed output the
Status Register content, while Bus Read operations to the other Bank output the contents of the
memory array.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Register. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
16/49
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table 7, Program, Erase Times and Program/Erase Endurance Cycles.
Unlock Bypass Command.
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long (as with some EPROM programmers) considerable time saving can be made by
using these commands. Three Bus Write operations are required to issue the Unlock Bypass
command.
Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode. The
Unlock Bypass Program command can then be issued to program addresses within the bank, or the
Unlock Bypass Reset command can be issued to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin
the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately.
Unlock Bypass Program Command.
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the address and data, and starts the Program/Erase
Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. The
operation cannot be aborted, a Bus Read operation to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Command.
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
Chip Erase Command.
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start
the Program/Erase Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
M29DW324DT, M29DW324DB
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend command. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 7. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command.
The Block Erase command can be used to erase
a list of one or more blocks in a Bank. It sets all of
the bits in the unprotected selected blocks to ’1’.
All previous data in the selected blocks is lost.
Six Bus Write operations are required to select the
first block in the list. Each additional block in the
list can be selected by repeating the sixth Bus
Write operation using the address of the additional
block. All blocks must belong to the same Bank; if
a block belonging to the other Bank is given it will
not be erased. The Block Erase operation starts
the Program/Erase Controller after a time-out period of 50µs after the last Bus Write operation.
Once the Program/Erase Controller starts it is not
possible to select any more blocks. Each additional block must therefore be selected within 50µs of
the last block. The 50µs timer restarts when an additional block is selected. After the sixth Bus Write
operation a Bus Read operation within the same
Bank will output the Status Register. See the Status Register section for details on how to identify if
the Program/Erase Controller has started the
Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command and the Read/Reset command which is
only accepted during the 50µs time-out period.
Typical block erase times are given in Table 7.
After the Erase operation has started all Bus Read
operations to the Bank being erased will output the
Status Register on the Data Inputs/Outputs. See
the section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Register. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Erase Suspend Command.
The Erase Suspend Command may be used to
temporarily suspend a Block Erase operation and
return the memory to Read mode. The command
requires one Bus Write operation.
The Program/Erase Controller will suspend within
the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/
Erase Controller has stopped the memory will be
set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an
additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase
Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase
Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Reading from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be accepted.
During Erase Suspend a Bus Read operation to
the Extended Block will output the Extended Block
data.
Erase Resume Command.
The Erase Resume command must be used to restart the Program/Erase Controller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be suspended and resumed more than
once.
17/49
M29DW324DT, M29DW324DB
Enter Extended Block Command
The M29DW324D has an extra 64KByte block
(Extended Block) that can only be accessed using
the Enter Extended Block command. Three Bus
write cycles are required to issue the Extended
Block command. Once the command has been issued the device enters Extended Block mode
where all Bus Read or Program operations to the
Boot Block addresses access the Extended Block.
The Extended Block (with the same address as
the boot block) cannot be erased, and can be
treated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are
not accessible. In Extended Block mode dual operations are possible, with the Extended Block
mapped in Bank A. When in Extended Block
mode, Erase Commands in Bank A are not allowed.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Block can be protected, however
once protected the protection cannot be undone.
Exit Extended Block Command.
The Exit Extended Block command is used to exit
from the Extended Block mode and return the device to Read mode. Four Bus Write operations are
required to issue the command.
Block Protect and Chip Unprotect Commands.
Groups of blocks can be protected against accidental Program or Erase. The Protection Groups
are shown in Appendix A, Tables 21 and 22, Block
Addresses. The whole chip can be unprotected to
allow the data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix D.
Command
Length
Table 5. Commands, 16-bit mode, BYTE = VIH
Bus Write Operations
1st
2nd
Addr
Data
1
X
F0
3
555
Auto Select
3
Program
3rd
4th
Addr
Data
Addr
Data
AA
2AA
55
X
F0
555
AA
2AA
55
(BKA)
555
90
4
555
AA
2AA
55
555
A0
Double Word Program
3
555
50
PA0
PD0
PA1
PD1
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
Erase Suspend
1
BKA
B0
Erase Resume
1
BKA
30
Read CFI Query
1
55
98
Enter Extended Block
3
555
AA
2AA
Exit Extended Block
4
555
AA
2AA
5th
Addr
Data
PA
PD
80
555
555
80
55
555
88
55
555
90
6th
Addr
Data
Addr
Data
AA
2AA
55
555
10
555
AA
2AA
55
BA
30
X
00
Read/Reset
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in
hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is V IL or DQ15 when BYTE is VIH.
18/49
M29DW324DT, M29DW324DB
Length
Table 6. Commands, 8-bit mode, BYTE = VIL
Command
Bus Write Operations
1st
2nd
Add
Data
1
X
F0
3
AAA
Auto Select
3
Program
3rd
4th
Add
Data
Add
Data
AA
555
55
X
F0
AAA
AA
555
55
(BKA)
AAA
90
4
AAA
AA
555
55
AAA
Quadruple Byte Program
5
AAA
55
PA0
PD0
Unlock Bypass
3
AAA
AA
555
55
Unlock Bypass Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
AAA
AA
555
Block Erase
6+
AAA
AA
Erase Suspend
1
BKA
B0
Erase Resume
1
BKA
30
Read CFI Query
1
AA
98
Enter Extended Block
3
AAA
Exit Extended Block
4
AAA
5th
Add
Data
A0
PA
PD
PA1
PD1
PA2
AAA
20
55
AAA
80
555
55
AAA
80
AA
555
55
AAA
88
AA
555
55
AAA
90
6th
Add
Data
Add
Data
PD2
PA3
PD3
AAA
AA
555
55
AAA
10
AAA
AA
555
55
BA
30
X
00
Read/Reset
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is V IL or DQ15 when BYTE is VIH.
Table 7. Program, Erase Times and Program, Erase Endurance Cycles
Typ (1, 2)
Max(2)
Unit
Chip Erase
40
200(3)
s
Block Erase (64 KBytes)
0.8
6(3)
s
50(4)
µs
Parameter
Min
Erase Suspend Latency time
Program (Byte or Word)
10
200(4)
µs
Double Word Program (Byte or Word)
10
200(3)
µs
Chip Program (Byte by Byte)
40
200(3)
s
Chip Program (Word by Word)
20
100(3)
s
Chip Program (Quadruple Byte or Double Word)
10
100
s
Program/Erase Cycles (per Block)
Data Retention
Note: 1.
2.
3.
4.
100,000
cycles
20
years
Typical values measured at room temperature and nominal voltages.
Sampled, but not 100% tested.
Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
Maximum value measured at worst case conditions for both temperature and VCC.
19/49
M29DW324DT, M29DW324DB
STATUS REGISTER
The M29DW324D has two Status Registers, one
for each bank. The Status Registers provide information on the current or previous Program or
Erase operations executed in each bank. The various bits convey information and errors on the operation. Bus Read operations from any address
within the Bank, always read the Status Register
during Program and Erase operations. It is also
read during Erase Suspend when an address within a block being erased is accessed.
The bits in the Status Register are summarized in
Table 8, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 8, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
20/49
Figure 9, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased correctly.
M29DW324DT, M29DW324DB
Table 8. Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Bank Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Bank Address
DQ7
Toggle
0
–
–
0
Program Error
Bank Address
DQ7
Toggle
1
–
–
0
Chip Erase
Any Address
0
Toggle
0
1
Toggle
0
Block Erase before
timeout
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
No Toggle
0
Erasing Block
0
Toggle
0
1
Toggle
0
Non-Erasing Block
0
Toggle
0
1
No Toggle
0
Erasing Block
1
No Toggle
0
–
Toggle
1
Block Erase
Erase Suspend
Non-Erasing Block
Data read as normal
1
Good Block Address
0
Toggle
1
1
No Toggle
0
Faulty Block Address
0
Toggle
1
1
Toggle
0
Erase Error
Note: Unspecified data bits should be ignored.
Figure 8. Data Polling Flowchart
Figure 9. Data Toggle Flowchart
START
START
READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
NO
YES
NO
DQ5
=1
NO
YES
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
FAIL
PASS
NO
YES
FAIL
PASS
AI90194
AI90195B
21/49
M29DW324DT, M29DW324DB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 9. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature Under Bias
–50
125
°C
TSTG
Storage Temperature
–65
150
°C
VIO
Input or Output Voltage (1,2)
–0.6
VCC +0.6
V
VCC
Supply Voltage
–0.6
4
V
VID
Identification Voltage
–0.6
13.5
V
Program Voltage
–0.6
13.5
V
VPP(3)
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to V CC +2V during transition and for less than 20ns during transitions.
3. VPP must not remain at 12V for more than a total of 80hrs.
22/49
M29DW324DT, M29DW324DB
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 10, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when relying on the quoted parameters.
Table 10. Operating and AC Measurement Conditions
M29DW324D
Parameter
70
90
Unit
Min
Max
Min
Max
VCC Supply Voltage
3.0
3.6
2.7
3.6
V
Ambient Operating Temperature
–40
85
–40
85
°C
Load Capacitance (CL)
30
30
Input Rise and Fall Times
pF
10
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 10. AC Measurement I/O Waveform
10
ns
0 to VCC
0 to VCC
V
VCC/2
VCC/2
V
Figure 11. AC Measurement Load Circuit
VPP
VCC
VCC
VCC
VCC/2
25kΩ
0V
DEVICE
UNDER
TEST
AI05557
25kΩ
CL
0.1µF
0.1µF
CL includes JIG capacitance
AI05558
Table 11. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: Sampled only, not 100% tested.
23/49
M29DW324DT, M29DW324DB
Table 12. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
10
mA
Supply Current (Standby)
E = VCC ±0.2V,
RP = VCC ±0.2V
100
µA
VPP/WP =
VIL or VIH
20
mA
VPP/WP = VPP
20
mA
ICC1(2)
ICC2
ICC3
(1,2)
Supply Current (Program/
Erase)
Program/Erase
Controller active
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7VCC
VCC +0.3
V
VPP
Voltage for VPP/WP Program
Acceleration
VCC = 3.0V ±10%
11.5
12.5
V
IPP
Current for VPP/WP Program
Acceleration
VCC = 3.0V ±10%
15
mA
VOL
Output Low Voltage
IOL = 1.8mA
0.45
V
VOH
Output High Voltage
IOH = –100µA
VID
Identification Voltage
11.5
12.5
V
Program/Erase Lockout Supply
Voltage
1.8
2.3
V
VLKO
VCC –0.4
Note: 1. Sampled only, not 100% tested.
2. In Dual operations the Supply Current will be the sum of I CC1(read) and I CC3 (program/erase).
24/49
V
M29DW324DT, M29DW324DB
Figure 12. Read Mode AC Waveforms
tAVAV
A0-A20/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGLQV
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI05559
Table 13. Read AC Characteristics
M29DW324D
Symbol
Alt
Parameter
Test Condition
Unit
70
90
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
70
90
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
70
90
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
70
90
ns
tGLQX (1)
tOLZ
Output Enable Low to Output Transition
E = VIL
Min
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
30
35
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
30
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
25
30
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or Address
Transition to Output Transition
Min
0
0
ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
5
5
ns
tBLQZ
tFLQZ
BYTE Low to Output Hi-Z
Max
25
30
ns
tBHQV
tFHQV
BYTE High to Output Valid
Max
30
40
ns
Note: 1. Sampled only, not 100% tested.
25/49
M29DW324DT, M29DW324DB
Figure 13. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI05560
Table 14. Write AC Characteristics, Write Enable Controlled
M29DW324D
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
50
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
50
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
50
ns
Output Enable High to Write Enable Low
Min
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
ns
tWHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
26/49
M29DW324DT, M29DW324DB
Figure 14. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI05561
Table 15. Write AC Characteristics, Chip Enable Controlled
M29DW324D
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
50
ns
Output Enable High Chip Enable Low
Min
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
ns
tEHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
27/49
M29DW324DT, M29DW324DB
Figure 15. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Table 16. Reset/Block Temporary Unprotect AC Characteristics
M29DW324D
Symbol
tPHWL (1)
tPHEL
Alt
Parameter
Unit
70
90
tRH
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
50
50
ns
tRB
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
ns
tPLYH
tREADY
RP Low to Read Mode
Max
50
50
µs
tPHPHH (1)
tVIDR
RP Rise Time to VID
Min
500
500
ns
VPP Rise and Fall Time
Min
250
250
ns
tPHGL
(1)
tRHWL (1)
tRHEL (1)
tRHGL
(1)
tVHVPP (1)
Note: 1. Sampled only, not 100% tested.
Figure 16. Accelerated Program Timing Waveforms
VPP
VPP/WP
VIL or VIH
tVHVPP
tVHVPP
AI05563
28/49
M29DW324DT, M29DW324DB
PACKAGE MECHANICAL
Figure 17. 48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
α
A1
DIE
L
C
CP
TSOP-G
Note: Drawing not to scale.
Table 17. 48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
0.080
0.0031
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3
0
5
0.0315
0
5
3
29/49
M29DW324DT, M29DW324DB
Figure 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline
D
D1
SD
FD
e
E
ddd
SE
E1
BALL "A1"
FE
A
e
b
A2
A1
BGA-Z33
Note: Drawing not to scale.
Table 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.0472
0.250
A2
0.0098
0.900
b
Max
0.350
0.450
0.0354
0.0138
0.0177
D
7.000
6.900
7.100
0.2756
0.2717
0.2795
D1
5.600
–
–
0.2205
–
–
ddd
–
–
0.100
–
–
0.0039
E
11.000
10.900
11.100
0.4331
0.4291
0.4370
E1
8.800
–
–
0.3465
–
–
e
0.800
–
–
0.0315
–
–
FD
0.700
–
–
0.0276
–
–
FE
1.100
–
–
0.0433
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
30/49
M29DW324DT, M29DW324DB
Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z32
Note: Drawing not to scale.
Table 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.0472
0.260
A2
0.0102
0.900
b
Max
0.350
0.450
0.0354
0.0138
0.0177
D
6.000
5.900
6.100
0.2362
0.2323
0.2402
D1
4.000
–
–
0.1575
–
–
ddd
0.100
0.0039
E
8.000
7.900
8.100
0.3150
0.3110
0.3189
E1
5.600
–
–
0.2205
–
–
e
0.800
–
–
0.0315
–
–
FD
1.000
–
–
0.0394
–
–
FE
1.200
–
–
0.0472
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
31/49
M29DW324DT, M29DW324DB
PART NUMBERING
Table 20. Ordering Information Scheme
Example:
M29DW324DB
70
N
1
T
Device Type
M29
Architecture
D = Dual Bank
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
324D = 32 Mbit (x8/x16), Boot Block, half-half partitioning
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20mm
ZA = TFBGA63: 7 x 11mm, 0.80mm pitch
ZE = TFGBA48: 6 x 8mm, 0.80mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest ST sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.
32/49
M29DW324DT, M29DW324DB
APPENDIX A. BLOCK ADDRESSES
Bank
Table 21. Top Boot Block Addresses, M29DW324DT
Block
(Kbytes/
Kwords)
Protection Block
Group
(x8)
(x16)
0
64/32
Protection Group
000000h–00FFFFh
000000h–07FFFh
1
64/32
010000h–01FFFFh
008000h–0FFFFh
2
64/32
020000h–02FFFFh
010000h–17FFFh
3
64/32
030000h–03FFFFh
018000h–01FFFFh
4
64/32
040000h–04FFFFh
020000h–027FFFh
5
64/32
050000h–05FFFFh
028000h–02FFFFh
Protection Group
Protection Group
6
64/32
060000h–06FFFFh
030000h–037FFFh
7
64/32
070000h–07FFFFh
038000h–03FFFFh
8
64/32
080000h–08FFFFh
040000h–047FFFh
9
64/32
090000h–09FFFFh
048000h–04FFFFh
Protection Group
10
64/32
0A0000h–0AFFFFh
050000h–057FFFh
11
64/32
0B0000h–0BFFFFh
058000h–05FFFFh
12
64/32
0C0000h–0CFFFFh
060000h–067FFFh
13
64/32
0D0000h–0DFFFFh
068000h–06FFFFh
Bank B
Protection Group
14
64/32
0E0000h–0EFFFFh
070000h–077FFFh
15
64/32
0F0000h–0FFFFFh
078000h–07FFFFh
16
64/32
100000h–10FFFFh
080000h–087FFFh
17
64/32
110000h–11FFFFh
088000h–08FFFFh
Protection Group
18
64/32
120000h–12FFFFh
090000h–097FFFh
19
64/32
130000h–13FFFFh
098000h–09FFFFh
20
64/32
140000h–14FFFFh
0A0000h–0A7FFFh
21
64/32
150000h–15FFFFh
0A8000h–0AFFFFh
Protection Group
22
64/32
160000h–16FFFFh
0B0000h–0B7FFFh
23
64/32
170000h–17FFFFh
0B8000h–0BFFFFh
24
64/32
180000h–18FFFFh
0C0000h–0C7FFFh
25
64/32
190000h–19FFFFh
0C8000h–0CFFFFh
Protection Group
26
64/32
1A0000h–1AFFFFh
0D0000h–0D7FFFh
27
64/32
1B0000h–1BFFFFh
0D8000h–0DFFFFh
28
64/32
1C0000h–1CFFFFh
0E0000h–0E7FFFh
29
64/32
1D0000h–1DFFFFh
0E8000h–0EFFFFh
Protection Group
30
64/32
1E0000h–1EFFFFh
0F0000h–0F7FFFh
31
64/32
1F0000h–1FFFFFh
0F8000h–0FFFFFh
33/49
Bank
M29DW324DT, M29DW324DB
Block
(Kbytes/
Kwords)
32
64/32
33
64/32
Protection Block
Group
(x8)
(x16)
200000h–20FFFFh
100000h–107FFFh
210000h–21FFFFh
108000h–10FFFFh
Protection Group
34
64/32
220000h–22FFFFh
110000h–117FFFh
35
64/32
230000h–23FFFFh
118000h–11FFFFh
36
64/32
240000h–24FFFFh
120000h–127FFFh
37
64/32
250000h–25FFFFh
128000h–12FFFFh
Protection Group
38
64/32
260000h–26FFFFh
130000h–137FFFh
39
64/32
270000h–27FFFFh
138000h–13FFFFh
40
64/32
280000h–28FFFFh
140000h–147FFFh
41
64/32
290000h–29FFFFh
148000h–14FFFFh
Protection Group
42
64/32
2A0000h–2AFFFFh
150000h–157FFFh
43
64/32
2B0000h–2BFFFFh
158000h–15FFFFh
44
64/32
2C0000h–2CFFFFh
160000h–167FFFh
45
64/32
2D0000h–2DFFFFh
168000h–16FFFFh
Bank A
Protection Group
46
64/32
2E0000h–2EFFFFh
170000h–177FFFh
47
64/32
2F0000h–2FFFFFh
178000h–17FFFFh
48
64/32
300000h–30FFFFh
180000h–187FFFh
49
64/32
310000h–31FFFFh
188000h–18FFFFh
Protection Group
50
64/32
320000h–32FFFFh
190000h–197FFFh
51
64/32
330000h–33FFFFh
198000h–19FFFFh
52
64/32
340000h–34FFFFh
1A0000h–1A7FFFh
53
64/32
350000h–35FFFFh
1A8000h–1AFFFFh
Protection Group
54
64/32
360000h–36FFFFh
1B0000h–1B7FFFh
55
64/32
370000h–37FFFFh
1B8000h–1BFFFFh
56
64/32
380000h–38FFFFh
1C0000h–1C7FFFh
57
64/32
390000h–39FFFFh
1C8000h–1CFFFFh
Protection Group
34/49
58
64/32
3A0000h–3AFFFFh
1D0000h–1D7FFFh
59
64/32
3B0000h–3BFFFFh
1D8000h–1DFFFFh
60
64/32
3C0000h–3CFFFFh
1E0000h–1E7FFFh
61
64/32
3D0000h–3DFFFFh
1E8000h–1EFFFFh
62
64/32
3E0000h–3EFFFFh
1F0000h–1F7FFFh
Protection Group
Bank A
Bank
M29DW324DT, M29DW324DB
Block
(Kbytes/
Kwords)
Protection Block
Group
(x8)
(x16)
63
8/4
Protection Group
3F0000h–3F1FFFh(1)
1F8000h–1F8FFFh(1)
64
8/4
Protection Group
3F2000h–3F3FFFh(1)
1F9000h–1F9FFFh(1)
65
8/4
Protection Group
3F4000h–3F5FFFh(1)
1FA000h–1FAFFFh(1)
66
8/4
Protection Group
3F6000h–3F7FFFh(1)
1FB000h–1FBFFFh(1)
67
8/4
Protection Group
3F8000h–3F9FFFh(1)
1FC000h–1FCFFFh(1)
68
8/4
Protection Group
3FA000h–3FBFFFh(1)
1FD000h–1FDFFFh(1)
69
8/4
Protection Group
3FC000h–3FDFFFh(1)
1FE000h–1FEFFFh(1)
70
8/4
Protection Group
3FE000h–3FFFFFh(1)
1FF000h–1FFFFFh(1)
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
35/49
M29DW324DT, M29DW324DB
Bank
Table 22. Bottom Boot Block Addresses, M29DW324DB
Block
(Kbytes/
Kwords)
Protection Block
Group
(x8)
(x16)
0
8/4
Protection Group
000000h-001FFFh(1)
000000h–000FFFh(1)
1
8/4
Protection Group
002000h-003FFFh(1)
001000h–001FFFh(1)
2
8/4
Protection Group
004000h-005FFFh(1)
002000h–002FFFh(1)
3
8/4
Protection Group
006000h-007FFFh(1)
003000h–003FFFh(1)
4
8/4
Protection Group
008000h-009FFFh(1)
004000h–004FFFh(1)
5
8/4
Protection Group
00A000h-00BFFFh(1)
005000h–005FFFh(1)
6
8/4
Protection Group
00C000h-00DFFFh(1)
006000h–006FFFh(1)
7
8/4
Protection Group
00E000h-00FFFFh(1)
007000h–007FFFh(1)
8
64/32
010000h-01FFFFh
008000h–00FFFFh
9
64/32
020000h-02FFFFh
010000h–017FFFh
10
64/32
030000h-03FFFFh
018000h–01FFFFh
11
64/32
040000h-04FFFFh
020000h–027FFFh
12
64/32
050000h-05FFFFh
028000h–02FFFFh
Protection Group
Bank A
Protection Group
13
64/32
060000h-06FFFFh
030000h–037FFFh
14
64/32
070000h-07FFFFh
038000h–03FFFFh
15
64/32
080000h-08FFFFh
040000h–047FFFh
16
64/32
090000h-09FFFFh
048000h–04FFFFh
Protection Group
17
64/32
0A0000h-0AFFFFh
050000h–057FFFh
18
64/32
0B0000h-0BFFFFh
058000h–05FFFFh
19
64/32
0C0000h-0CFFFFh
060000h–067FFFh
20
64/32
0D0000h-0DFFFFh
068000h–06FFFFh
Protection Group
21
64/32
0E0000h-0EFFFFh
070000h–077FFFh
22
64/32
0F0000h-0FFFFFh
078000h–07FFFFh
23
64/32
100000h-10FFFFh
080000h–087FFFh
24
64/32
110000h-11FFFFh
088000h–08FFFFh
Protection Group
25
64/32
120000h-12FFFFh
090000h–097FFFh
26
64/32
130000h-13FFFFh
098000h–09FFFFh
27
64/32
140000h-14FFFFh
0A0000h–0A7FFFh
28
64/32
150000h-15FFFFh
0A8000h–0AFFFFh
Protection Group
36/49
29
64/32
160000h-16FFFFh
0B0000h–0B7FFFh
30
64/32
170000h-17FFFFh
0B8000h–0BFFFFh
Bank
M29DW324DT, M29DW324DB
Block
(Kbytes/
Kwords)
31
64/32
32
64/32
Protection Block
Group
(x8)
(x16)
180000h-18FFFFh
0C0000h–0C7FFFh
190000h-19FFFFh
0C8000h–0CFFFFh
Bank A
Protection Group
33
64/32
1A0000h-1AFFFFh
0D0000h–0D7FFFh
34
64/32
1B0000h-1BFFFFh
0D8000h–0DFFFFh
35
64/32
1C0000h-1CFFFFh
0E0000h–0E7FFFh
36
64/32
1D0000h-1DFFFFh
0E8000h–0EFFFFh
Protection Group
37
64/32
1E0000h-1EFFFFh
0F0000h–0F7FFFh
38
64/32
1F0000h-1FFFFFh
0F8000h–0FFFFFh
39
64/32
200000h-20FFFFh
100000h–107FFFh
40
64/32
210000h-21FFFFh
108000h–10FFFFh
Protection Group
41
64/32
220000h-22FFFFh
110000h–117FFFh
42
64/32
230000h-23FFFFh
118000h–11FFFFh
43
64/32
240000h-24FFFFh
120000h–127FFFh
44
64/32
250000h-25FFFFh
128000h–12FFFFh
Protection Group
45
64/32
260000h-26FFFFh
130000h–137FFFh
46
64/32
270000h-27FFFFh
138000h–13FFFFh
47
64/32
280000h-28FFFFh
140000h–147FFFh
48
64/32
290000h-29FFFFh
148000h–14FFFFh
Bank B
Protection Group
49
64/32
2A0000h-2AFFFFh
150000h–157FFFh
50
64/32
2B0000h-2BFFFFh
158000h–15FFFFh
51
64/32
2C0000h-2CFFFFh
160000h–167FFFh
52
64/32
2D0000h-2DFFFFh
168000h–16FFFFh
Protection Group
53
64/32
2E0000h-2EFFFFh
170000h–177FFFh
54
64/32
2F0000h-2FFFFFh
178000h–17FFFFh
55
64/32
300000h-30FFFFh
180000h–187FFFh
56
64/32
310000h-31FFFFh
188000h–18FFFFh
Protection Group
57
64/32
320000h-32FFFFh
190000h–197FFFh
58
64/32
330000h-33FFFFh
198000h–19FFFFh
59
64/32
340000h-34FFFFh
1A0000h–1A7FFFh
60
64/32
350000h-35FFFFh
1A8000h–1AFFFFh
Protection Group
61
64/32
360000h-36FFFFh
1B0000h–1B7FFFh
62
64/32
370000h-37FFFFh
1B8000h–1BFFFFh
37/49
Bank
M29DW324DT, M29DW324DB
Block
(Kbytes/
Kwords)
63
64/32
64
64/32
Protection Block
Group
(x8)
(x16)
380000h-38FFFFh
1C0000h–1C7FFFh
390000h-39FFFFh
1C8000h–1CFFFFh
Bank B
Protection Group
65
64/32
3A0000h-3AFFFFh
1D0000h–1D7FFFh
66
64/32
3B0000h-3BFFFFh
1D8000h–1DFFFFh
67
64/32
3C0000h-3CFFFFh
1E0000h–1E7FFFh
68
64/32
3D0000h-3DFFFFh
1E8000h–1EFFFFh
69
64/32
3E0000h-3EFFFFh
1F0000h–1F7FFFh
70
64/32
3F0000h-3FFFFFh
1F8000h–1FFFFFh
Protection Group
Protection Group
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
38/49
M29DW324DT, M29DW324DB
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data structure
is read from the memory. Tables 23, 24, 25, 26, 27
and 28 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is written (see Table 28, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security number after it has been written by ST.
Table 23. Query Structure Overview
Address
Sub-section Name
Description
x16
x8
10h
20h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
36h
System Interface Information
Device timing & voltage information
27h
4Eh
Device Geometry Definition
Flash device layout
40h
80h
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
61h
C2h
Security Code Area
64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 24. CFI Query Identification String
Address
Data
Description
x16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported
19h
32h
0000h
Address for Alternate Algorithm extended Query table
1Ah
34h
0000h
Value
“Q”
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 27)
AMD
Compatible
P = 40h
NA
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
39/49
M29DW324DT, M29DW324DB
Table 25. CFI Query System Interface Information
Address
Data
Description
Value
x16
x8
1Bh
36h
0027h
VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
2.7V
1Ch
38h
0036h
VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
3.6V
1Dh
3Ah
00B5h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 mV
11.5V
1Eh
3Ch
00C5h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 mV
12.5V
1Fh
3Eh
0004h
Typical timeout per single byte/word program = 2n µs
16µs
20h
40h
0000h
Typical timeout for minimum size write buffer program = 2n µs
NA
21h
42h
000Ah
Typical timeout per individual block erase = 2n ms
1s
22h
44h
0000h
Typical timeout for full chip erase = 2n ms
NA
23h
46h
0004h
Maximum timeout for byte/word program = 2n times typical
24h
48h
0000h
Maximum timeout for write buffer program = 2n times typical
NA
25h
4Ah
0003h
Maximum timeout per individual block erase = 2n times typical
8s
26h
4Ch
0000h
Maximum timeout for chip erase = 2n times typical
NA
256 µs
Table 26. Device Geometry Definition
Address
Data
Description
Value
x16
x8
27h
4Eh
0016h
Device Size = 2n in number of bytes
4 MByte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface Code description
x8, x16
Async.
2Ah
2Bh
54h
56h
0000h
0000h
Maximum number of bytes in multi-byte program or page = 2n
NA
2Ch
58h
0002h
Number of Erase Block Regions. It specifies the number of
regions containing contiguous Erase Blocks of the same size.
2
2Dh
2Eh
5Ah
5Ch
0007h
0000h
Region 1 Information
Number of identical size erase block = 0007h+1
8
2Fh
30h
5Eh
60h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
31h
32h
62h
64h
003Eh
0000h
Region 2 Information
Number of identical size erase block = 003Eh+1
33h
34h
66h
68h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
8Kbyte
63
64Kbyte
Note: The region information contained in addresses 2Dh to 34h (or 5Ah to 68h) is correct for the M29DW324DB. For the M29DW324DT the
regions must be reversed.
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M29DW324DT, M29DW324DB
Table 27. Primary Algorithm-Specific Extended Query Table
Address
Data
Description
Value
x16
x8
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
"1"
44h
88h
0030h
Minor version number, ASCII
"0"
45h
8Ah
0000h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h
8Ch
0002h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
47h
8Eh
0001h
Block Protection
00 = not supported, x = number of blocks in per group
1
48h
90h
0001h
Temporary Block Unprotect
00 = not supported, 01 = supported
49h
92h
0004h
Block Protect /Unprotect
04 = M29W400B
4
4Ah
94h
0020h
Simultaneous Operations,
x = number of blocks in Bank B
32
4Bh
96h
0000h
Burst Mode, 00 = not supported, 01 = supported
No
4Ch
98h
0000h
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
No
4Dh
9Ah
00B5h
VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5V
4Eh
9Ch
00C5h
VPP Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5V
4Fh
9Eh
000xh
Top/Bottom Boot Block Flag
02h = Bottom Boot device, 03h = Top Boot device
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
Yes
–
Table 28. Security Code Area
Address
Data
x16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Description
64 bit: unique device number
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M29DW324DT, M29DW324DB
APPENDIX C. EXTENDED MEMORY BLOCK
The M29DW324D has an extra block, the Extended Block, that can be accessed using a dedicated
command.
This Extended Block is 32 KWords in x16 mode
and 64 KBytes in x8 mode. It is used as a security
block (to provide a permanent security identification number) or to store additional information.
The Extended Block is either Factory Locked or
Customer Lockable, its status is indicated by bit
DQ7. This bit is permanently set to either ‘1’ or ‘0’
at the factory and cannot be changed. When set to
‘1’, it indicates that the device is factory locked and
the Extended Block is protected. When set to ‘0’, it
indicates that the device is customer lockable and
the Extended Block is unprotected. Bit DQ7 being
permanently locked to either ‘1’ or ‘0’ is another
security feature which ensures that a customer
lockable device cannot be used instead of a factory locked one.
Bit DQ7 is the most significant bit in the Extended
Block Verify Code and a specific procedure must
be followed to read it. See “Extended Memory
Block Verify Code ” in Tables 3 and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE =
VIH, respectively, for details of how to read bit
DQ7.
The Extended Block can only be accessed when
the device is in Extended Block mode. For details
of how the Extended Block mode is entered and
exited, refer to the Enter Extended Block Command and Exit Extended Block Command. paragraphs, and to Tables 5 and 6, “Commands, 16-bit
mode, BYTE = VIH” and “Commands, 8-bit mode,
BYTE = VIL”, respectively.
Factory Locked Extended Block
In devices where the Extended Block is factory
locked, the Security Identification Number is written to the Extended Block address space (see Table 29, Extended Block Address and Data) in the
factory. The DQ7 bit is set to ‘1’ and the Extended
Block cannot be unprotected.
Customer Lockable Extended Block
A device where the Extended Block is customer
lockable is delivered with the DQ7 bit set to ‘0’ and
the Extended Block unprotected. It is up to the
customer to program and protect the Extended
Block but care must be taken because the protection of the Extended Block is not reversible.
There are two ways of protecting the Extended
Block:
■ Issue the Enter Extended Block command to
place the device in Extended Block mode, then
use the In-System Technique (refer to Appendix
D, In-System Technique and to the
corresponding flowcharts, Figures 22 and 23,
for a detailed explanation of the technique).
■ Issue the Enter Extended Block command to
place the device in Extended Block mode, then
use the Programmer Technique (refer to
Appendix D, Programmer Technique and to the
corresponding flowcharts, Figures 20 and 21,
for a detailed explanation of the technique).
Once the Extended Block is programmed and protected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return
the device to Read mode.
Table 29. Extended Block Address and Data
Address(1)
Device
Data
x8
x16
Factory Locked
3F0000h-3F000Fh
1F8000h-1F8007h
Security Identification
Number
3F0010h-3FFFFFh
1F8008h-1FFFFFh
Unavailable
000000h-00000Fh
000000h-000007h
Security Identification
Number
000010h-00FFFFh
000008h-007FFFh
Unavailable
M29DW324DT
M29DW324DB
Note: 1. See Tables 21 and 22, Top and Bottom Boot Block Addresses.
42/49
Customer Lockable
Determined by
Customer
Determined by
Customer
M29DW324DT, M29DW324DB
APPENDIX D. BLOCK PROTECTION
Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to
Appendix A, Tables 21 and 22 for details of the
Protection Groups. Once protected, Program and
Erase operations within the protected group fail to
change the data.
There are three techniques that can be used to
control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section.
To protect the Extended Block issue the Enter Extended Block command and then use either the
Programmer or In-System technique. Once protected issue the Exit Extended Block command to
return to read mode. The Extended Block protection is irreversible, once protected the protection
cannot be undone.
Programmer Technique
The Programmer technique uses high (V ID) voltage levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a group of blocks follow the flowchart in
Figure 20, Programmer Equipment Block Protect
Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all
groups can be unprotected at the same time. To
unprotect the chip follow Figure 21, Programmer
Equipment Chip Unprotect Flowchart. Table 30,
Programmer Technique Bus Operations, gives a
summary of each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the microprocessor bus, therefore this technique is suitable
for use after the memory has been fitted to the system.
To protect a group of blocks follow the flowchart in
Figure 22, In-System Block Protect Flowchart. To
unprotect the whole chip it is necessary to protect
all of the groups first, then all the groups can be
unprotected at the same time. To unprotect the
chip follow Figure 23, In-System Chip Unprotect
Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Table 30. Programmer Technique Bus Operations, BYTE = V IH or VIL
E
G
W
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block (Group)
Protect(1)
VIL
VID
VIL Pulse
A9 = VID, A12-A20 Block Address
Others = X
X
Chip Unprotect
VID
VID
VIL Pulse
A9 = VID, A12 = VIH, A15 = VIH
Others = X
X
Block (Group)
Protection Verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
A12-A20 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block (Group)
Unprotection Verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,
A12-A20 Block Address
Others = X
Retry = XX01h
Pass = XX00h
Operation
Note: 1. Block Protection Groups are shown in Appendix D, Tables 21 and 22.
43/49
M29DW324DT, M29DW324DB
Figure 20. Programmer Equipment Group Protect Flowchart
START
Set-up
ADDRESS = GROUP ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Protect
Wait 4µs
W = VIL
Wait 100µs
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA
NO
=
01h
YES
A9 = VIH
E, G = VIH
++n
= 25
NO
End
YES
PASS
A9 = VIH
E, G = VIH
FAIL
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
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AI05574
M29DW324DT, M29DW324DB
Figure 21. Programmer Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Unprotect
Wait 4µs
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1, A6 = VIH
E = VIL
Wait 4µs
G = VIL
INCREMENT
CURRENT GROUP
Verify
Wait 60ns
Read DATA
NO
End
NO
DATA
=
00h
YES
++n
= 1000
LAST
GROUP
YES
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
FAIL
PASS
NO
AI05575
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
45/49
M29DW324DT, M29DW324DB
Figure 22. In-System Equipment Group Protect Flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 100µs
Verify
WRITE 40h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
DATA
NO
=
01h
YES
End
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI05576
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
46/49
M29DW324DT, M29DW324DB
Figure 23. In-System Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
NO
End
NO
DATA
=
00h
++n
= 1000
YES
INCREMENT
CURRENT GROUP
YES
LAST
GROUP
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI05577
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
47/49
M29DW324DT, M29DW324DB
REVISION HISTORY
Table 31. Document Revision History
Date
Version
19-Apr-2002
-01
Document written
08-Apr-2003
2.0
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 01 equals 1.0).
Revision History moved to end of document.
When in Extended Block mode, the block at the boot block address can be used as OTP.
Data Toggle Flow chart corrected. Logic diagram corrected.
TFBGA48, 6x8mm, 0.8mm pitch package added. Identification Current IID removed from
Table 12, DC Characteristics. Erase Suspend Latency time and Data Retention
parameters and notes added to Table 7, Program, Erase Times and Program, Erase
Endurance Cycles.
Appendix C, EXTENDED MEMORY BLOCK, added. Auto Select Command sued to read
the Extended Memory Block. Extended Memory Block Verify Code row added to Tables 3
and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH. Bank Address
modified in Auto Select Command. Chip Erase Address modified in Table 8, Status
Register Bits. VSS pin connection to ground clarified. Note added to Table 20, Ordering
Information Scheme.
07-May-2003
2.1
Table 17, 48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data and
Figure 17, 48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline”
corrected.
25-Jun-2003
3.0
Document promoted from Preliminary Data to full Datasheet status. Packing option added
to Table 20, Ordering Information Scheme.
48/49
Revision Details
M29DW324DT, M29DW324DB
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