Cypress CY7C1465AV25 36-mbit (1m x 36/2m x 18/512k x 72) flow-through sram with noblâ ¢ architecture Datasheet

CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM with NoBL™ Architecture
Functional Description[1]
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin-compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• CY7C1461AV25, CY7C1463AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1465AV25 available in lead-free and non-lead-free
209-ball FBGA package.
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are
2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait
states.
The
CY7C1461AV25/CY7C1463AV25/
CY7C1465AV25 is equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby power
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
270
250
mA
Maximum CMOS Standby Current
120
120
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05355 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 22, 2006
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Logic Block Diagram – CY7C1461AV25 (1M × 36)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
BWC
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BWD
WE
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
INPUT
E
REGISTER
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
1
Logic Block Diagram – CY7C1463AV25 (2M × 18)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
BWB
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document #: 38-05355 Rev. *E
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Page 2 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
2
Logic Block Diagram – CY7C1465AV25 (512K × 72)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
WE
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
Document #: 38-05355 Rev. *E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Page 3 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations
Document #: 38-05355 Rev. *E
A
43
44
45
46
47
48
49
50
NC/72M
A
A
A
A
A
A
A
A
41
VDD
42
40
37
A0
VSS
36
A1
39
35
A
NC/144M
34
A
38
33
A
NC/288M
32
A
81
A
82
A
83
A
84
ADV/LD
85
OE
86
CEN
VSS
90
WE
VDD
91
88
CE3
92
CLK
BWA
93
89
BWC
BWB
BWD
96
94
CE2
97
95
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1461AV25
31
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
100-pin TQFP Pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 4 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations (continued)
Document #: 38-05355 Rev. *E
A
43
44
45
46
47
48
49
50
NC/72M
A
A
A
A
A
A
A
A
41
VDD
42
40
37
A0
VSS
36
A1
39
35
A
NC/144M
34
A
38
33
A
NC/288M
32
A
81
A
82
A
83
A
84
ADV/LD
85
OE
86
90
CEN
VSS
91
WE
VDD
92
88
CE3
93
CLK
BWA
94
89
NC
BWB
95
NC
CE2
97
96
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1463AV25
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
100-pin TQFP Pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 5 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1461AV25 (1M × 36)
1
2
3
4
5
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
NC/1G
A
CE1
CE2
DQPc
DQc
NC
DQc
VDDQ
DQc
DQc
DQc
NC
DQd
R
MODE
6
7
8
9
10
11
A
A
NC
BWc
BWb
CE3
CEN
ADV/LD
BWa
VSS
CLK
WE
OE
A
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
BWd
VSS
VDD
VDDQ
NC
DQb
DQPb
DQb
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQb
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQc
NC
DQd
VDDQ
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
A
A
TMS
A0
TCK
A
A
A
8
9
10
11
A
A
NC
NC/144M NC/72M
A
NC/288M
A
CY7C1463AV25 (2M × 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
NC/576M
A
NC/1G
A
NC
NC
3
4
5
6
CE1
CE2
BWb
NC
NC
CE3
CEN
ADV/LD
A
CLK
VSS
VDD
OE
VSS
A
VDDQ
VDDQ
WE
VSS
A
NC
DQb
BWa
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
VSS
VSS
7
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
NC
DQb
DQb
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
A
A
TDI
A1
TDO
A
A
A
A
A
TMS
A0
TCK
A
A
A
NC/144M NC/72M
MODE
A
Document #: 38-05355 Rev. *E
NC/288M
A
Page 6 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1465AV25 (512K × 72)
1
2
A
DQg
DQg
B
DQg
DQg
C
DQg
D
3
5
6
7
8
9
10
11
ADV/LD
A
CE3
A
DQb
DQb
WE
A
BWSb
BWSf
DQb
DQb
CE1
NC
BWSe
BWSa
DQb
DQb
NC
NC
VSS
DQb
DQb
DQPf
DQPb
CE2
A
BWSc
BWSg
NC
DQg
BWSh
BWSd NC/576M
DQg
DQg
VSS
NC
NC/1G
OE
E
DQPg
DQPc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
F
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
G
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
K
NC
NC
CLK
NC
VSS
CEN
VSS
NC
NC
NC
NC
L
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQa
DQa
R
DQPd
DQPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
T
DQd
DQd
NC
NC
U
DQd
DQd
V
DQd
DQd
A
A
W
DQd
DQd
TMS
TDI
DQc
A
4
VSS
NC/144M
A
NC
NC
A
A
A
A
A1
A
A
A
A0
A
NC/72M
MODE
TDO
VSS
DQPa
DQf
DQPe
DQe
DQe
NC/288M
DQe
DQe
A
DQe
DQe
TCK
DQe
DQe
Pin Definitions
I/O Type
Pin Description
A0
A1
A
Pin Name
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CLK
Document #: 38-05355 Rev. *E
Page 7 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
I/OSynchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,
DQPg is controlled by BWg, DQPh is controlled by BWh.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG-Clock
VDD
Power Supply
VDDQ
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
VSS
NC
NC/72M
Ground
N/A
N/A
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/576M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/1G
N/A
Not connected to the die. Can be tied to any voltage level.
ZZ
InputAsynchronous
Document #: 38-05355 Rev. *E
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
Not connected to the die. Can be tied to any voltage level.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Page 8 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Functional Overview
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 is a
synchronous flow-through burst SRAM designed specifically
to eliminate wait states during Write-Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Read Accesses
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip enable
inputs or WE. WE is latched at the beginning of a burst cycle.
Document #: 38-05355 Rev. *E
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by BWX
signals. The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25
provides byte write capability that is described in the truth table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1461AV25/CY7C1463AV25/CY7C1465AV25
is a common I/O device, data should not be driven into the
device while the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQs
and DQPX inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs and DQPX are automatically
tri-stated during the data portion of a write cycle, regardless of
the state of OE.
Burst Write Accesses
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BWX inputs must be
driven in each cycle of the burst write, in order to write the
correct bytes of data.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Page 9 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Sleep Mode
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
100
2tCYC
2tCYC
2tCYC
0
Unit
mA
ns
ns
ns
ns
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-State
Read Cycle (Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
External
L
H
L
L
L
L
L
X
L
L->H
Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H
Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Write Cycle (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 38-05355 Rev. *E
Page 10 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1461AV25)
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write No bytes written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
L
L
H
H
H
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
L
H
L
H
H
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Truth Table for Read/Write[2, 3, 9]
Function (CY7C1463AV25)
Read
WE
BWB
BWA
H
X
X
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Truth Table for
Read/Write[2, 3, 9]
Function (CY7C1465AV25)
WE
BWX
Read
H
X
Write – No Bytes Written
L
H
Write Byte X − (DQx and DQPx)
L
L
Write All Bytes
L
All BW = L
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document #: 38-05355 Rev. *E
Page 11 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Data-In (TDI)
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 2.5V/1.8V I/O logic level.
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
1
2 1 0
TEST-LOGIC
RESET
TDI
Selection
Circuitry
0
0
RUN-TEST/
IDLE
Instruction Register
31 30 29 . . . 2 1 0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
Boundary Scan Register
0
0
SHIFT-IR
1
0
TCK
1
EXIT1-DR
1
EXIT1-IR
0
1
TMS
TAP CONTROLLER
0
PAUSE-DR
0
PAUSE-IR
1
0
Performing a TAP Reset
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
x . . . . . 2 1 0
CAPTURE-IR
0
TDO
Identification Register
0
SHIFT-DR
0
1
Selection
Circuitry
0
UPDATE-IR
1
0
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05355 Rev. *E
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Page 12 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in
the Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Document #: 38-05355 Rev. *E
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209 FBGA package).
Page 13 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
20
ns
tTL
TCK Clock LOW time
20
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes:
10. .tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05355 Rev. *E
Page 14 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
1.8V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels .................................... 0.2V to VDDQ – 0.2
Input pulse levels................................................. VSS to 2.5V
Input rise and fall time..................................................... 1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................0.9V
Input timing reference levels......................................... 1.25V
Output reference levels...................................................0.9V
Output reference levels ................................................ 1.25V
Test load termination supply voltage...............................0.9V
Test load termination supply voltage ............................ 1.25V
1.8V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.25V
0.9V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.375 to 2.625 unless otherwise noted)[12]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –1.0 mA, VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 2.5V
2.1
V
VDDQ = 1.8V
1.6
V
VOL1
Output LOW Voltage
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 2.5V
0.2
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
VIL
Input LOW Voltage
VDDQ = 1.8V
IX
Input Load Current
VDDQ = 1.8V
0.2
V
1.7
VDD + 0.3
V
VDDQ = 1.8V
1.26
VDD + 0.3
V
VDDQ = 2.5V
–0.3
0.7
V
–0.3
0.36
V
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
Architecture/Memory Type (23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
CY7C1461AV25 CY7C1463AV25 CY7C1465AV25
(1M × 36)
(2M × 18)
(512K × 72)
Description
000
000
000
01011
01011
01011
001001
001001
001001
Defines memory type and architecture
Defines width and density
100111
010111
110111
00000110100
00000110100
00000110100
1
1
1
Describes the version number
Reserved for internal use
Allows unique identification of
SRAM vendor
Indicates the presence of an ID
register
Note:
12. All voltages referenced to VSS (GND).
Document #: 38-05355 Rev. *E
Page 15 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Bit Size (×72)
Instruction
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order (165-ball FBGA package)
89
89
–
Boundary Scan Order (209-ball FBGA package)
–
–
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05355 Rev. *E
Page 16 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
165-ball FBGA Boundary Scan Order [13]
CY7C1461AV25 (1M × 36), CY7C1463AV25 (2M × 18)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
N6
26
E11
51
A3
76
N1
2
N7
27
D11
52
A2
77
N2
3
N10
28
G10
53
B2
78
P1
4
P11
29
F10
54
C2
79
R1
5
P8
30
E10
55
B1
80
R2
6
R8
31
D10
56
A1
81
P3
7
R9
32
C11
57
C1
82
R3
8
P9
33
A11
58
D1
83
P2
9
P10
34
B11
59
E1
84
R4
10
R10
35
A10
60
F1
85
P4
11
R11
36
B10
61
G1
86
N5
12
H11
37
A9
62
D2
87
P6
13
N11
38
B9
63
E2
88
R6
14
M11
39
C10
64
F2
89
Internal
15
L11
40
A8
65
G2
16
K11
41
B8
66
H1
17
J11
42
A7
67
H3
18
M10
43
B7
68
J1
19
L10
44
B6
69
K1
20
K10
45
A6
70
L1
21
J10
46
B5
71
M1
22
H9
47
A5
72
J2
23
H10
48
A4
73
K2
24
G11
49
B4
74
L2
25
F11
50
B3
75
M2
Note:
13. Bit# 89 is preset HIGH.
Document #: 38-05355 Rev. *E
Page 17 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
209-ball BGA Boundary Scan Order [13, 14]
CY7C1465V25 (512K x 72)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
W6
36
F6
71
H6
106
K3
2
V6
37
K8
72
C6
107
K4
3
U6
38
K9
73
B6
108
K6
4
W7
39
K10
74
A6
109
K2
5
V7
40
J11
75
A5
110
L2
6
U7
41
J10
76
B5
111
L1
7
T7
42
H11
77
C5
112
M2
8
V8
43
H10
78
D5
113
M1
9
U8
44
G11
79
D4
114
N2
10
T8
45
G10
80
C4
115
N1
11
V9
46
F11
81
A4
116
P2
12
U9
47
F10
82
B4
117
P1
13
P6
48
E10
83
C3
118
R2
14
W11
49
E11
84
B3
119
R1
15
W10
50
D11
85
A3
120
T2
16
V11
51
D10
86
A2
121
T1
17
V10
52
C11
87
A1
122
U2
18
U11
53
C10
88
B2
123
U1
19
U10
54
B11
89
B1
124
V2
20
T11
55
B10
90
C2
125
V1
21
T10
56
A11
91
C1
126
W2
22
R11
57
A10
92
D2
127
W1
23
R10
58
C9
93
D1
128
T6
24
P11
59
B9
94
E1
129
U3
25
P10
60
A9
95
E2
130
V3
26
N11
61
D8
96
F2
131
T4
27
N10
62
C8
97
F1
132
T5
28
M11
63
B8
98
G1
133
U4
29
M10
64
A8
99
G2
134
V4
30
L11
65
D7
100
H2
135
W5
31
L10
66
C7
101
H1
136
V5
32
K11
67
B7
102
J2
137
U5
33
M6
68
A7
103
J1
138
Internal
34
L6
69
D6
104
K1
35
J6
70
G6
105
N6
Note:
14. Bit# 138 is preset HIGH.
Document #: 38-05355 Rev. *E
Page 18 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient
Range
Temperature
Commercial 0°C to +70°C
Industrial
–40°C to +85°C
VDD
VDDQ
2.5V –5%/+5% 1.7V to VDD
Electrical Characteristics Over the Operating Range[15, 16]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH
Input LOW
Voltage[15]
Voltage[15]
Test Conditions
Min.
Max.
Unit
2.375
2.625
V
for 2.5V I/O
2.375
VDD
V
for 1.8V I/O
1.7
1.9
V
for 2.5V I/O, IOH = −1.0 mA
2.0
V
for 1.8V I/O, IOH = –100 µA
1.6
V
for 2.5V I/O, IOL = 1.0 mA
0.4
V
for 1.8V I/O, IOL = 100 µA
0.2
V
for 2.5V I/O
1.7
VDD + 0.3V
V
for 1.8V I/O
1.26
VDD + 0.3V
V
for 2.5V I/O
–0.3
0.7
V
for 1.8V I/O
–0.3
0.36
V
5
µA
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
–5
Input Current of MODE
Input = VSS
–30
Input = VDD
Input Current of ZZ
µA
5
Input = VSS
µA
–5
Input = VDD
µA
30
µA
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
270
mA
10-ns cycle, 100 MHz
250
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
All speeds
150
mA
ISB2
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDD – 0.3V,
Current—CMOS Inputs f = 0, inputs static
All speeds
120
mA
ISB3
Automatic CE
VDD = Max, Device Deselected, or All speeds
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX, inputs switching
Automatic CE
VDD = Max, Device Deselected, All Speeds
Power-down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—TTL Inputs
f = 0, inputs static
150
mA
135
mA
ISB4
–5
Notes:
15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse wid th less than tCYC/2)
16. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05355 Rev. *E
Page 19 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Capacitance[17]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
100 TQFP
Max.
TA = 25°C, f = 1 MHz,
VDD = 2.5V
VDDQ = 2.5V
165 FBGA
Max.
209 FBGA
Max.
Unit
6.5
7
5
pF
3
7
5
pF
5.5
6
7
pF
Thermal Resistance[17]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Unit
25.21
20.8
25.31
°C/W
2.28
3.2
4.48
°C/W
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
(a)
INCLUDING
JIG AND
SCOPE
1.8V I/O Test Load
R = 1538Ω
(b)
(c)
10%
(a)
INCLUDING
JIG AND
SCOPE
90%
10%
90%
0.2
5 pF
VT = 0.9V
ALL INPUT PULSES
VDDQ - 0.2
OUTPUT
RL = 50Ω
Z0 = 50Ω
≤ 1ns
≤ 1ns
R = 14 KΩ
1.8V
OUTPUT
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
R = 14 KΩ
(b)
≤ 1ns
≤ 1ns
(c)
Note:
17. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05355 Rev. *E
Page 20 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Characteristics Over the Operating Range [22, 23]
–133
Parameter
tPOWER
Description
[18]
Min.
–100
Max.
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.5
3.0
ns
tCL
Clock LOW
2.5
3.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
[19, 20, 21]
6.5
2.5
2.5
tCLZ
Clock to Low-Z
tCHZ
Clock to High-Z[19, 20, 21]
3.8
tOEV
OE LOW to Output Valid
3.0
tOELZ
tOEHZ
OE LOW to Output
Low-Z[19, 20, 21]
OE HIGH to Output
High-Z[19, 20, 21]
8.5
2.5
ns
2.5
0
0
ns
4.5
ns
3.8
ns
0
3.0
ns
ns
4.0
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.5
1.5
ns
tALS
ADV/LD Set-up Before CLK Rise
1.5
1.5
ns
tWES
WE, BWX Set-up Before CLK Rise
1.5
1.5
ns
tCENS
CEN Set-up Before CLK Rise
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Set-up Before CLK Rise
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tALH
ADV/LD Hold After CLK Rise
0.5
0.5
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Hold Times
Notes:
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference level is 1.25V when VDDQ = 2.5V and is 0.9V when VDDQ = 1.8V.
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05355 Rev. *E
Page 21 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Waveforms
Read/Write Waveforms[24, 25, 26]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes:
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05355 Rev. *E
Page 22 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[24, 25, 27]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Note:
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05355 Rev. *E
Page 23 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Switching Waveforms (continued)
ZZ Mode Timing[28, 29]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
28. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
29. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05355 Rev. *E
Page 24 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
CY7C1461AV25-133AXC
Package
Diagram
Operating
Range
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1463AV25-133AXC
CY7C1461AV25-133BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1463AV25-133BZC
CY7C1461AV25-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-133BZXC
CY7C1465AV25-133BGC
CY7C1465AV25-133BGXC
CY7C1461AV25-133AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1463AV25-133AXI
CY7C1461AV25-133BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1463AV25-133BZI
CY7C1461AV25-133BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-133BZXI
CY7C1465AV25-133BGI
CY7C1465AV25-133BGXI
100
CY7C1461AV25-100AXC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1463AV25-100AXC
CY7C1461AV25-100BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1463AV25-100BZC
CY7C1461AV25-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-100BZXC
CY7C1465AV25-100BGC
CY7C1465AV25-100BGXC
CY7C1461AV25-100AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1463AV25-100AXI
CY7C1461AV25-100BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1463AV25-100BZI
CY7C1461AV25-100BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1463AV25-100BZXI
CY7C1465AV25-100BGI
CY7C1465AV25-100BGXI
Document #: 38-05355 Rev. *E
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Page 25 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05355 Rev. *E
A
Page 26 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Package Diagrams (continued)
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45±0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
0.25 C
10.00
B
15.00±0.10
0.15(4X)
SEATING PLANE
1.40 MAX.
0.36
C
51-85165-*A
Document #: 38-05355 Rev. *E
Page 27 of 29
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
51-85167-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05355 Rev. *E
Page 28 of 29
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1461AV25
CY7C1463AV25
CY7C1465AV25
Document History Page
Document Title: CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through
SRAM with NoBL™ Architecture
Document Number: 38-05355
REV.
ECN NO.
Issue Date
Orig. of
Change
**
254911
See ECN
SYT
New data sheet
Changed part number from previous revision. New and old part number differ
by the letter “A”
*A
300131
See ECN
SYT
Removed 150- and 177-MHz speed bins
Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W, respectively, for
TQFP Package
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA
packages
Added “Lead-free BG and BZ packages availability” below the Ordering Information
*B
320813
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209
FBGA
Changed the test condition from VDD = Min. to VDD = Max for VOL in the
Electrical Characteristics table
Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values
Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 FBGA
and 209 FBGA packages on the Thermal Resistance table
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package
Removed “Lead-free BG and BZ packages availability” comment below the
Ordering Information
*C
331551
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Changed typo from (-0.5V+4.6V) to (-0.5V+3.6V) for Supply Voltage on VDD
Relative to GND under the Maximum Ratings Section
Modified VOL, VOH test conditions
Replaced TBD to 100 mA for IDDZZ
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
Package
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by shading and unshading MPNs as per
availability
*D
417547
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respectively and also Changed IX current value in ZZ from –30 & 5 µA to –5 & 30
µA respectively on page# 20
Modified test condition from VIH < VDD to VIH < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information Table
*E
473650
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05355 Rev. *E
Description of Change
Page 29 of 29
Similar pages