Renesas H8FAMILY Renesas 16-bit single-chip microcomputer Datasheet

REJ09B0152-0300
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8/38602RGroup
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family / H8/300H Super Low Power Series
H8/38602R
H8/38600R
Rev.3.00
Revision Date: May 15, 2007
HD64F38602R
HD64338602R
HD64338600R
Rev. 3.00 May 15, 2007 Page ii of xxxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 3.00 May 15, 2007 Page iii of xxxii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 3.00 May 15, 2007 Page iv of xxxii
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00 May 15, 2007 Page v of xxxii
Preface
The H8/38602R Group consists of single-chip microcomputers made up of the high-speed
H8/300H CPU employing Renesas Technology original architecture as their cores, and the
peripheral functions required to configure a system. The H8/300H CPU has an instruction set that
is compatible with the H8/300 CPU.
Target Users: This manual was written for users who will be using the H8/38602R Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8/38602R Group to the target users.
Refer to the H8/300H Series Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions, and electrical characteristics.
In order to understand the details of the CPU's functions
Read the H8/300H Series Software Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registers.
Example:
Register name:
Bit order:
The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
The MSB is on the left and the LSB is on the right.
Rev. 3.00 May 15, 2007 Page vi of xxxii
Notes:
When using an on-chip emulator (E7) for H8/38602R program development and debugging, the
following restrictions must be noted.
The NMI pin is reserved for the E7, and cannot be used.
Area H'4000 to H'4FFF should not be accessed.
Area H'F780 to H'FB7F should not be accessed.
When the E7 is used, NMI is an input/output pin (open-drain in output mode).
When on-board programming/erasing is performed in boot mode, the SCI3 (P31/RXD3 and
P32/TXD3) is used.
6. When the on-chip emulator is used, even though the on-chip oscillator is selected, connect a
resonator to OSC1 and OSC2 or input an external clock to OSC1.
7. When using the E7, set the FROMCKSTP bit in clock halt register 1 to 1.
1.
2.
3.
4.
5.
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
H8/38602R Group manuals:
Document Title
Document No.
H8/38602R Group Hardware Manual
This manual
H8/300H Series Software Manual
REJ09B0213
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial
REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual REJ10B0026
Rev. 3.00 May 15, 2007 Page vii of xxxii
Application notes:
Document Title
Document No.
F-ZTAT Microcomputer On-Board Programming
REJ05B0523
All trademarks and registered trademarks are the property of their respective owners.
Rev. 3.00 May 15, 2007 Page viii of xxxii
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Features.................................................................................................................................. 1
Internal Block Diagram.......................................................................................................... 2
Pin Assignment ...................................................................................................................... 3
Pin Functions ......................................................................................................................... 4
Section 2 CPU........................................................................................................7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Address Space and Memory Map .......................................................................................... 8
Register Configuration........................................................................................................... 9
2.2.1 General Registers.................................................................................................... 10
2.2.2 Program Counter (PC) ............................................................................................ 11
2.2.3 Condition-Code Register (CCR)............................................................................. 11
Data Formats........................................................................................................................ 13
2.3.1 General Register Data Formats ............................................................................... 13
2.3.2 Memory Data Formats ............................................................................................ 15
Instruction Set ...................................................................................................................... 16
2.4.1 Table of Instructions Classified by Function .......................................................... 16
2.4.2 Basic Instruction Formats ....................................................................................... 26
Addressing Modes and Effective Address Calculation........................................................ 27
2.5.1 Addressing Modes .................................................................................................. 27
2.5.2 Effective Address Calculation ................................................................................ 30
Basic Bus Cycle ................................................................................................................... 32
2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 32
2.6.2 On-Chip Peripheral Modules .................................................................................. 33
CPU States ........................................................................................................................... 34
Usage Notes ......................................................................................................................... 35
2.8.1 Notes on Data Access to Empty Areas ................................................................... 35
2.8.2 EEPMOV Instruction.............................................................................................. 35
2.8.3 Bit-Manipulation Instruction .................................................................................. 36
Section 3 Exception Handling .............................................................................41
3.1
3.2
3.3
Exception Sources and Vector Address ............................................................................... 42
Reset .................................................................................................................................... 44
3.2.1 Reset Exception Handling....................................................................................... 44
3.2.2 Interrupt Immediately after Reset ........................................................................... 45
Input/Output Pins ................................................................................................................. 46
Rev. 3.00 May 15, 2007 Page ix of xxxii
3.4
3.5
3.6
3.7
3.8
Register Descriptions........................................................................................................... 46
3.4.1 Interrupt Edge Select Register (IEGR) ................................................................... 47
3.4.2 Interrupt Enable Register 1 (IENR1) ...................................................................... 48
3.4.3 Interrupt Enable Register 2 (IENR2) ...................................................................... 49
3.4.4 Interrupt Flag Register 1 (IRR1)............................................................................. 50
3.4.5 Interrupt Flag Register 2 (IRR2)............................................................................. 51
Interrupt Sources.................................................................................................................. 52
3.5.1 External Interrupts .................................................................................................. 52
3.5.2 Internal Interrupts ................................................................................................... 53
Operation ............................................................................................................................. 53
3.6.1 Interrupt Exception Handling Sequence ................................................................. 56
Stack Status after Exception Handling................................................................................. 57
3.7.1 Interrupt Response Time......................................................................................... 57
Usage Notes ......................................................................................................................... 58
3.8.1 Notes on Stack Area Use ........................................................................................ 58
3.8.2 Notes on Switching Functions of External Interrupt Pins....................................... 59
3.8.3 Method for Clearing Interrupt Request Flags ......................................................... 60
3.8.4 Conflict between Interrupt Generation and Disabling ............................................ 60
3.8.5 Instructions that Disable Interrupts......................................................................... 61
3.8.6 Interrupts during Execution of EEPMOV Instruction ............................................ 61
3.8.7 IENR Clearing ........................................................................................................ 61
Section 4 Clock Pulse Generators ....................................................................... 63
4.1
4.2
4.3
4.4
4.5
Register Description ............................................................................................................ 64
4.1.1 Oscillator Control Register (OSCCR) .................................................................... 64
System Clock Oscillator ...................................................................................................... 66
4.2.1 Connecting Crystal Resonator ................................................................................ 66
4.2.2 Connecting Ceramic Resonator .............................................................................. 66
4.2.3 External Clock Input Method ................................................................................. 67
4.2.4 On-Chip Oscillator Selection Method .................................................................... 67
Subclock Oscillator.............................................................................................................. 68
4.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator ............................................ 68
4.3.2 Pin Connection when not Using Subclock.............................................................. 69
4.3.3 External Clock Input Method ................................................................................. 70
4.3.4 On-Chip Oscillator Selection Method .................................................................... 70
Prescalers ............................................................................................................................. 71
4.4.1 Prescaler S .............................................................................................................. 71
4.4.2 Prescaler W............................................................................................................. 71
Usage Notes ......................................................................................................................... 72
4.5.1 Note on Resonators and Resonator Circuits ........................................................... 72
Rev. 3.00 May 15, 2007 Page x of xxxii
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
Notes on Board Design ........................................................................................... 74
Definition of Oscillation Stabilization Wait Time .................................................. 74
Note on Subclock Stop State................................................................................... 76
Note on the Oscillation Stabilization of Resonators ............................................... 76
Note on Using Power-On Reset .............................................................................. 76
Note on Using On-Chip Emulator .......................................................................... 76
Section 5 Power-Down Modes ............................................................................77
5.1
5.2
5.3
5.4
5.5
5.6
Register Descriptions ........................................................................................................... 78
5.1.1 System Control Register 1 (SYSCR1) .................................................................... 78
5.1.2 System Control Register 2 (SYSCR2) .................................................................... 80
5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) ..................................... 81
Mode Transitions and States of LSI..................................................................................... 83
5.2.1 Sleep Mode ............................................................................................................. 87
5.2.2 Standby Mode ......................................................................................................... 88
5.2.3 Watch Mode............................................................................................................ 88
5.2.4 Subsleep Mode........................................................................................................ 89
5.2.5 Subactive Mode ...................................................................................................... 89
5.2.6 Active (Medium-Speed) Mode ............................................................................... 90
Direct Transition .................................................................................................................. 91
5.3.1 Direct Transition from Active (High-Speed)
Mode to Active (Medium-Speed) Mode ................................................................. 91
5.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode................. 92
5.3.3 Direct Transition from Active (Medium-Speed)
Mode to Active (High-Speed) Mode ...................................................................... 92
5.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode ........... 93
5.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode................. 93
5.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ........... 94
5.3.7 Notes on External Input Signal Changes before/after Direct Transition................. 95
Module Standby Function.................................................................................................... 96
On-Chip Oscillator and Operation Mode ............................................................................. 96
Usage Notes ......................................................................................................................... 97
5.6.1 Standby Mode Transition and Pin States ................................................................ 97
5.6.2 Notes on External Input Signal Changes before/after Standby Mode..................... 97
Section 6 ROM ....................................................................................................99
6.1
6.2
Block Configuration........................................................................................................... 100
Register Descriptions ......................................................................................................... 101
6.2.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 101
6.2.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 102
Rev. 3.00 May 15, 2007 Page xi of xxxii
6.3
6.4
6.5
6.6
6.7
6.2.3 Erase Block Register 1 (EBR1) ............................................................................ 103
6.2.4 Flash Memory Power Control Register (FLPWCR)............................................. 103
6.2.5 Flash Memory Enable Register (FENR)............................................................... 104
On-Board Programming Modes......................................................................................... 104
6.3.1 Boot Mode ............................................................................................................ 105
6.3.2 Programming/Erasure in User Program Mode...................................................... 108
Flash Memory Programming/Erasure................................................................................ 109
6.4.1 Programming/Programming-Verifying................................................................. 109
6.4.2 Erasing/Erasing-Verifying .................................................................................... 112
6.4.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 112
Programming/Erasing Protection....................................................................................... 114
6.5.1 Hardware Protection ............................................................................................. 114
6.5.2 Software Protection .............................................................................................. 114
6.5.3 Error Protection .................................................................................................... 114
Power-Down States for Flash Memory.............................................................................. 115
Notes on Setting Module Standby Mode ........................................................................... 116
Section 7 RAM .................................................................................................. 117
Section 8 I/O Ports............................................................................................. 119
8.1
8.2
8.3
Port 1.................................................................................................................................. 119
8.1.1 Port Data Register 1 (PDR1) ................................................................................ 120
8.1.2 Port Control Register 1 (PCR1) ............................................................................ 120
8.1.3 Port Pull-Up Control Register 1 (PUCR1)............................................................ 121
8.1.4 Port Mode Register 1 (PMR1) .............................................................................. 121
8.1.5 Pin Functions ........................................................................................................ 122
8.1.6 Input Pull-Up MOS............................................................................................... 124
Port 3.................................................................................................................................. 124
8.2.1 Port Data Register 3 (PDR3) ................................................................................ 125
8.2.2 Port Control Register 3 (PCR3) ............................................................................ 125
8.2.3 Port Pull-Up Control Register 3 (PUCR3)............................................................ 126
8.2.4 Port Mode Register 3 (PMR3) .............................................................................. 126
8.2.5 Pin Functions ........................................................................................................ 127
8.2.6 Input Pull-Up MOS............................................................................................... 128
Port 8.................................................................................................................................. 128
8.3.1 Port Data Register 8 (PDR8) ................................................................................ 129
8.3.2 Port Control Register 8 (PCR8) ............................................................................ 129
8.3.3 Port Pull-Up Control Register 8 (PUCR8)............................................................ 130
8.3.4 Pin Functions ........................................................................................................ 130
8.3.5 Input Pull-Up MOS............................................................................................... 132
Rev. 3.00 May 15, 2007 Page xii of xxxii
8.4
8.5
8.6
8.7
Port 9.................................................................................................................................. 132
8.4.1 Port Data Register 9 (PDR9)................................................................................. 133
8.4.2 Port Control Register 9 (PCR9) ............................................................................ 133
8.4.3 Port Open-Drain Control Register 9 (PODR9) ..................................................... 134
8.4.4 Port Pull-Up Control Register 9 (PUCR9)............................................................ 134
8.4.5 Pin Functions ........................................................................................................ 135
8.4.6 Input Pull-Up MOS............................................................................................... 137
Port B ................................................................................................................................. 138
8.5.1 Port Data Register B (PDRB) ............................................................................... 138
8.5.2 Port Mode Register B (PMRB)............................................................................. 139
8.5.3 Pin Functions ........................................................................................................ 140
Input/Output Data Inversion .............................................................................................. 142
8.6.1 Serial Port Control Register (SPCR)..................................................................... 142
8.6.2 Port Function Control Register (PFCR)................................................................ 143
Usage Notes ....................................................................................................................... 144
8.7.1 How to Handle Unused Pin................................................................................... 144
8.7.2 Input Characteristics Difference due to Pin Function ........................................... 144
Section 9 Timer B1 ............................................................................................145
9.1
9.2
9.3
9.4
9.5
Features.............................................................................................................................. 145
Register Descriptions ......................................................................................................... 146
9.2.1 Timer Mode Register B1 (TMB1) ........................................................................ 146
9.2.2 Timer Counter B1 (TCB1).................................................................................... 147
9.2.3 Timer Load Register B1 (TLB1) .......................................................................... 147
Usage Method .................................................................................................................... 148
Operation ........................................................................................................................... 150
9.4.1 Interval Timer Operation ...................................................................................... 150
9.4.2 Auto-Reload Timer Operation .............................................................................. 150
Timer B1 Operating Modes ............................................................................................... 151
Section 10 Timer W ...........................................................................................153
10.1 Features.............................................................................................................................. 153
10.2 Input/Output Pins ............................................................................................................... 156
10.3 Register Descriptions ......................................................................................................... 156
10.3.1 Timer Mode Register W (TMRW) ....................................................................... 157
10.3.2 Timer Control Register W (TCRW) ..................................................................... 158
10.3.3 Timer Interrupt Enable Register W (TIERW) ...................................................... 159
10.3.4 Timer Status Register W (TSRW) ........................................................................ 160
10.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................. 161
10.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................. 163
Rev. 3.00 May 15, 2007 Page xiii of xxxii
10.4
10.5
10.6
10.7
10.3.7 Timer Counter (TCNT)......................................................................................... 164
10.3.8 General Registers A to D (GRA to GRD)............................................................. 165
Operation ........................................................................................................................... 166
10.4.1 Normal Operation ................................................................................................. 166
10.4.2 PWM Operation.................................................................................................... 170
Operation Timing............................................................................................................... 175
10.5.1 TCNT Count Timing ............................................................................................ 175
10.5.2 Output Compare Output Timing........................................................................... 176
10.5.3 Input Capture Timing ........................................................................................... 177
10.5.4 Timing of Counter Clearing by Compare Match .................................................. 177
10.5.5 Buffer Operation Timing ...................................................................................... 178
10.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ................................. 179
10.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 180
10.5.8 Timing of Status Flag Clearing............................................................................. 180
Timer W Operating Modes ................................................................................................ 181
Usage Notes ....................................................................................................................... 181
Section 11 Realtime Clock (RTC)..................................................................... 185
11.1 Features.............................................................................................................................. 185
11.2 Input/Output Pin ................................................................................................................ 186
11.3 Register Descriptions......................................................................................................... 187
11.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ............. 187
11.3.2 Minute Data Register (RMINDR) ........................................................................ 188
11.3.3 Hour Data Register (RHRDR) .............................................................................. 189
11.3.4 Day-of-Week Data Register (RWKDR) ............................................................... 190
11.3.5 RTC Control Register 1 (RTCCR1) ..................................................................... 191
11.3.6 RTC Control Register 2 (RTCCR2) ..................................................................... 192
11.3.7 Clock Source Select Register (RTCCSR)............................................................. 193
11.3.8 RTC Interrupt Flag Register (RTCFLG) .............................................................. 194
11.4 Operation ........................................................................................................................... 196
11.4.1 Initial Settings of Registers after Power-On ......................................................... 196
11.4.2 Initial Setting Procedure ....................................................................................... 196
11.4.3 Data Reading Procedure ....................................................................................... 197
11.5 Interrupt Sources................................................................................................................ 198
11.6 Usage Notes ....................................................................................................................... 199
11.6.1 Note on Clock Count ............................................................................................ 199
11.6.2 Note when Using RTC Interrupts ......................................................................... 199
Section 12 Watchdog Timer.............................................................................. 201
12.1 Features.............................................................................................................................. 201
Rev. 3.00 May 15, 2007 Page xiv of xxxii
12.2 Register Descriptions ......................................................................................................... 202
12.2.1 Timer Control/Status Register WD1 (TCSRWD1)............................................... 203
12.2.2 Timer Control/Status Register WD2 (TCSRWD2)............................................... 205
12.2.3 Timer Counter WD (TCWD)................................................................................ 206
12.2.4 Timer Mode Register WD (TMWD) .................................................................... 207
12.3 Operation ........................................................................................................................... 208
12.3.1 Watchdog Timer Mode ......................................................................................... 208
12.3.2 Interval Timer Mode............................................................................................. 209
12.3.3 Timing of Overflow Flag (OVF) Setting .............................................................. 209
12.4 Interrupt ............................................................................................................................. 210
12.5 Usage Notes ....................................................................................................................... 210
12.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode................. 210
12.5.2 Module Standby Mode Control............................................................................. 210
12.5.3 Clearing the WT/IT or IEOVF Bit in TCSRWD2 to 0 ......................................... 210
Section 13 Asynchronous Event Counter (AEC) ..............................................213
13.1 Features.............................................................................................................................. 213
13.2 Input/Output Pins ............................................................................................................... 215
13.3 Register Descriptions ......................................................................................................... 215
13.3.1 Event Counter PWM Compare Register (ECPWCR) ........................................... 216
13.3.2 Event Counter PWM Data Register (ECPWDR).................................................. 217
13.3.3 Input Pin Edge Select Register (AEGSR)............................................................. 218
13.3.4 Event Counter Control Register (ECCR).............................................................. 219
13.3.5 Event Counter Control/Status Register (ECCSR)................................................. 220
13.3.6 Event Counter H (ECH)........................................................................................ 222
13.3.7 Event Counter L (ECL)......................................................................................... 222
13.4 Operation ........................................................................................................................... 223
13.4.1 16-Bit Counter Operation ..................................................................................... 223
13.4.2 8-Bit Counter Operation ....................................................................................... 224
13.4.3 IRQAEC Operation............................................................................................... 225
13.4.4 Event Counter PWM Operation............................................................................ 225
13.4.5 Operation of Clock Input Enable/Disable Function.............................................. 227
13.5 Operating States of Asynchronous Event Counter............................................................. 228
13.6 Usage Notes ....................................................................................................................... 229
Section 14 Serial Communication Interface 3 (SCI3, IrDA).............................231
14.1 Features.............................................................................................................................. 231
14.2 Input/Output Pins ............................................................................................................... 233
14.3 Register Descriptions ......................................................................................................... 233
14.3.1 Receive Shift Register (RSR) ............................................................................... 234
Rev. 3.00 May 15, 2007 Page xv of xxxii
14.4
14.5
14.6
14.7
14.8
14.3.2 Receive Data Register (RDR)............................................................................... 234
14.3.3 Transmit Shift Register (TSR) .............................................................................. 234
14.3.4 Transmit Data Register (TDR).............................................................................. 234
14.3.5 Serial Mode Register (SMR) ................................................................................ 235
14.3.6 Serial Control Register (SCR) .............................................................................. 237
14.3.7 Serial Status Register (SSR) ................................................................................. 240
14.3.8 Bit Rate Register (BRR) ....................................................................................... 243
14.3.9 Serial Port Control Register (SPCR)..................................................................... 251
14.3.10 IrDA Control Register (IrCR)............................................................................... 252
14.3.11 Serial Extended Mode Register (SEMR) .............................................................. 253
Operation in Asynchronous Mode ..................................................................................... 253
14.4.1 Clock..................................................................................................................... 254
14.4.2 SCI3 Initialization................................................................................................. 258
14.4.3 Data Transmission ................................................................................................ 259
14.4.4 Serial Data Reception ........................................................................................... 261
Operation in Clock Synchronous Mode............................................................................. 265
14.5.1 Clock..................................................................................................................... 265
14.5.2 SCI3 Initialization................................................................................................. 265
14.5.3 Serial Data Transmission ...................................................................................... 266
14.5.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 268
14.5.5 Simultaneous Serial Data Transmission and Reception........................................ 270
IrDA Operation .................................................................................................................. 271
14.6.1 Transmission......................................................................................................... 272
14.6.2 Reception .............................................................................................................. 273
14.6.3 High-Level Pulse Width Selection........................................................................ 273
Interrupt Requests .............................................................................................................. 274
Usage Notes ....................................................................................................................... 277
14.8.1 Break Detection and Processing ........................................................................... 277
14.8.2 Mark State and Break Sending ............................................................................. 277
14.8.3 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ......................................................................... 277
14.8.4 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ............................................................................................. 278
14.8.5 Note on Switching SCK3 Pin Function ................................................................ 279
14.8.6 Relation between Writing to TDR and Bit TDRE ................................................ 279
14.8.7 Relation between RDR Reading and bit RDRF.................................................... 280
14.8.8 Transmit and Receive Operations when Making State Transition........................ 281
14.8.9 Setting in Subactive or Subsleep Mode ................................................................ 281
14.8.10 Oscillator when Serial Communication Interface 3 is Used ................................. 281
Rev. 3.00 May 15, 2007 Page xvi of xxxii
Section 15 Synchronous Serial Communication Unit (SSU) ............................283
15.1 Features.............................................................................................................................. 283
15.2 Input/Output Pins ............................................................................................................... 284
15.3 Register Descriptions ......................................................................................................... 285
15.3.1 SS Control Register H (SSCRH) .......................................................................... 285
15.3.2 SS Control Register L (SSCRL) ........................................................................... 287
15.3.3 SS Mode Register (SSMR) ................................................................................... 289
15.3.4 SS Enable Register (SSER) .................................................................................. 290
15.3.5 SS Status Register (SSSR) .................................................................................... 291
15.3.6 SS Receive Data Register (SSRDR) ..................................................................... 293
15.3.7 SS Transmit Data Register (SSTDR).................................................................... 293
15.3.8 SS Shift Register (SSTRSR)................................................................................. 293
15.4 Operation ........................................................................................................................... 293
15.4.1 Transfer Clock ...................................................................................................... 293
15.4.2 Relationship between Clock Polarity and Phase, and Data................................... 294
15.4.3 Relationship between Data Input/Output and Shift Register ................................ 295
15.4.4 Communication Modes and Pin Functions ........................................................... 296
15.4.5 Operation in Clocked Synchronous Communication Mode.................................. 297
15.4.6 Operation in Four-Line Bus Communication Mode ............................................. 303
15.4.7 Initialization in Four-Line Bus Communication Mode......................................... 304
15.4.8 Serial Data Transmission ...................................................................................... 305
15.4.9 Serial Data Reception ........................................................................................... 307
15.4.10 SCS Pin Control and Arbitration .......................................................................... 309
15.4.11 Interrupt Requests ................................................................................................. 310
15.5 Usage Note......................................................................................................................... 310
Section 16 I2C Bus Interface 2 (IIC2) ................................................................311
16.1 Features.............................................................................................................................. 311
16.2 Input/Output Pins ............................................................................................................... 313
16.3 Register Descriptions ......................................................................................................... 314
16.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 314
16.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 317
16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 319
16.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 321
16.3.5 I2C Bus Status Register (ICSR)............................................................................. 323
16.3.6 Slave Address Register (SAR).............................................................................. 326
16.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 326
16.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 327
16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 327
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16.4 Operation ........................................................................................................................... 328
16.4.1 I2C Bus Format...................................................................................................... 328
16.4.2 Master Transmit Operation................................................................................... 329
16.4.3 Master Receive Operation .................................................................................... 331
16.4.4 Slave Transmit Operation ..................................................................................... 333
16.4.5 Slave Receive Operation....................................................................................... 336
16.4.6 Clock Synchronous Serial Format ........................................................................ 337
16.4.7 Noise Canceler...................................................................................................... 340
16.4.8 Example of Use..................................................................................................... 340
16.5 Interrupt Request................................................................................................................ 345
16.6 Bit Synchronous Circuit..................................................................................................... 346
16.7 Usage Notes ....................................................................................................................... 347
16.7.1 Note on Issuing Stop Condition and Start (Re-Transmit) Condition .................... 347
16.7.2 Note on Setting WAIT Bit in I2C Bus Mode Register (ICMR)............................ 347
16.7.3 Restriction on Transfer Rate Setting in Multimaster Operation ........................... 347
16.7.4 Restriction on the Use of Bit Manipulation Instructions for MST and
TRS Setting in Multimaster Operation................................................................. 348
16.7.5 Usage Note on Master Receive Mode................................................................... 348
Section 17 A/D Converter ................................................................................. 349
17.1 Features.............................................................................................................................. 349
17.2 Input/Output Pins............................................................................................................... 350
17.3 Register Descriptions......................................................................................................... 350
17.3.1 A/D Result Register (ADRR) ............................................................................... 350
17.3.2 A/D Mode Register (AMR) .................................................................................. 351
17.3.3 A/D Start Register (ADSR) .................................................................................. 352
17.4 Operation ........................................................................................................................... 353
17.4.1 A/D Conversion .................................................................................................... 353
17.4.2 External Trigger Input Timing.............................................................................. 353
17.4.3 Operating States of A/D Converter....................................................................... 354
17.5 Example of Use.................................................................................................................. 354
17.6 A/D Conversion Accuracy Definitions .............................................................................. 357
17.7 Usage Notes ....................................................................................................................... 359
17.7.1 Permissible Signal Source Impedance .................................................................. 359
17.7.2 Influences on Absolute Accuracy ......................................................................... 359
17.7.3 Usage Notes .......................................................................................................... 360
Section 18 Comparators .................................................................................... 361
18.1 Features.............................................................................................................................. 361
18.2 Input/Output Pins............................................................................................................... 362
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18.3 Register Descriptions ......................................................................................................... 362
18.3.1 Compare Control Registers 0, 1 (CMCR0, CMCR1) ........................................... 362
18.3.2 Compare Data Register (CMDR).......................................................................... 364
18.4 Operation ........................................................................................................................... 365
18.4.1 Operation Sequence .............................................................................................. 365
18.4.2 Hysteresis Characteristics of Comparator............................................................. 366
18.4.3 Interrupt Setting .................................................................................................... 366
18.5 Usage Notes ....................................................................................................................... 368
Section 19 Power-On Reset Circuit ...................................................................369
19.1 Feature ............................................................................................................................... 369
19.2 Operation ........................................................................................................................... 370
19.2.1 Power-On Reset Circuit ........................................................................................ 370
Section 20 List of Registers ...............................................................................371
20.1 Register Addresses (Address Order).................................................................................. 372
20.2 Register Bits....................................................................................................................... 376
20.3 Register States in Each Operating Mode ........................................................................... 380
Section 21 Electrical Characteristics .................................................................385
21.1 Absolute Maximum Ratings for F-ZTAT Version............................................................. 385
21.2 Electrical Characteristics for F-ZTAT Version.................................................................. 386
21.2.1 Power Supply Voltage and Operating Range........................................................ 386
21.2.2 DC Characteristics ................................................................................................ 393
21.2.3 AC Characteristics ................................................................................................ 399
21.2.4 A/D Converter Characteristics .............................................................................. 405
21.2.5 Comparator Characteristics................................................................................... 407
21.2.6 Watchdog Timer Characteristics........................................................................... 407
21.2.7 Power-On Reset Circuit Characteristics ............................................................... 408
21.2.8 Flash Memory Characteristics .............................................................................. 409
21.3 Absolute Maximum Ratings for Masked ROM Version.................................................... 411
21.4 Electrical Characteristics for Masked ROM Version......................................................... 412
21.4.1 Power Supply Voltage and Operating Range........................................................ 412
21.4.2 DC Characteristics ................................................................................................ 419
21.4.3 AC Characteristics ................................................................................................ 425
21.4.4 A/D Converter Characteristics .............................................................................. 431
21.4.5 Comparator Characteristics................................................................................... 433
21.4.6 Watchdog Timer Characteristics........................................................................... 433
21.4.7 Power-On Reset Circuit Characteristics ............................................................... 434
21.5 Operation Timing............................................................................................................... 435
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21.6 Output Load Circuit ........................................................................................................... 440
21.7 Recommended Resonators................................................................................................. 440
21.8 Usage Note......................................................................................................................... 441
Appendix
A.
B.
C.
D.
......................................................................................................... 443
Instruction Set .................................................................................................................... 443
A.1
Instruction List...................................................................................................... 443
A.2
Operation Code Map............................................................................................. 458
A.3
Number of Execution States ................................................................................. 461
A.4
Combinations of Instructions and Addressing Modes .......................................... 472
I/O Ports............................................................................................................................. 473
B.1
I/O Port Block Diagrams ...................................................................................... 473
B.2
Port States in Each Operating State ...................................................................... 486
B.3
Port 9 Related Register Settings and Pin Functions.............................................. 487
Product Part No. Lineup .................................................................................................... 491
Package Dimensions .......................................................................................................... 492
Main Revisions and Additions in this Edition..................................................... 495
Index
......................................................................................................... 513
Rev. 3.00 May 15, 2007 Page xx of xxxii
Figures
Section 1
Figure 1.1
Figure 1.2
Figure 1.3
Overview
Internal Block Diagram of H8/38602R Group .............................................................. 2
Pin Assignment of H8/38602R Group (TNP-32) .......................................................... 3
Pin Assignment of H8/38602R Group (32P6U-A)........................................................ 3
Section 2 CPU
Figure 2.1 Memory Map................................................................................................................. 8
Figure 2.2 CPU Registers ............................................................................................................... 9
Figure 2.3 Usage of General Registers ......................................................................................... 10
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 11
Figure 2.5 General Register Data Formats (1).............................................................................. 13
Figure 2.5 General Register Data Formats (2).............................................................................. 14
Figure 2.6 Memory Data Formats................................................................................................. 15
Figure 2.7 Instruction Formats...................................................................................................... 26
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 30
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 32
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 33
Figure 2.11 CPU Operating States................................................................................................ 34
Figure 2.12 State Transitions ........................................................................................................ 35
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Same Address ............................................................................................................ 36
Section 3
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Exception Handling
Reset Exception Handling Sequence........................................................................... 45
Block Diagram of Interrupt Controller........................................................................ 54
Flow up to Interrupt Acceptance ................................................................................. 55
Interrupt Exception Handling Sequence...................................................................... 56
Stack Status after Exception Handling ........................................................................ 57
Operation when Odd Address is Set in SP .................................................................. 58
PFCR and PMRB (or AEGSR) Setting and Interrupt Request
Flag Clearing Procedure .............................................................................................. 59
Section 4
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Clock Pulse Generators
Block Diagram of Clock Pulse Generators.................................................................. 63
Typical Connection to Crystal Resonator.................................................................... 66
Typical Connection to Ceramic Resonator.................................................................. 66
Example of External Clock Input ................................................................................ 67
Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator................................ 68
Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator.................................. 69
Rev. 3.00 May 15, 2007 Page xxi of xxxii
Figure 4.7 Pin Connection when not Using Subclock .................................................................. 69
Figure 4.8 Pin Connection when Inputting External Clock .......................................................... 70
Figure 4.9 Example of Crystal and Ceramic Resonator Assignment............................................ 72
Figure 4.10 Negative Resistance Measurement and Circuit Modification Suggestions ............... 73
Figure 4.11 Example of Incorrect Board Design .......................................................................... 74
Figure 4.12 Oscillation Stabilization Wait Time .......................................................................... 75
Section 5
Figure 5.1
Figure 5.2
Figure 5.3
Power-Down Modes
Mode Transition Diagram ........................................................................................... 84
Standby Mode Transition and Pin States..................................................................... 97
External Input Signal Capture when Signal Changes
before/after Standby Mode or Watch Mode ............................................................... 98
Section 6
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
ROM
Flash Memory Block Configuration.......................................................................... 100
Programming/Erasing Flowchart Example in User Program Mode.......................... 108
Program/Program-Verify Flowchart ......................................................................... 110
Erase/Erase-Verify Flowchart ................................................................................... 113
Module Standby Mode Setting.................................................................................. 116
Section 8
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
I/O Ports
Port 1 Pin Configuration............................................................................................ 119
Port 3 Pin Configuration............................................................................................ 124
Port 8 Pin Configuration............................................................................................ 128
Port 9 Pin Configuration............................................................................................ 132
Port B Pin Configuration........................................................................................... 138
Input/Output Data Inversion Function....................................................................... 142
Section 9
Figure 9.1
Figure 9.2
Figure 9.3
Timer B1
Block Diagram of Timer B1...................................................................................... 145
Timer B1 Initial Setting Flow ................................................................................... 148
Processing Flow When Changing Setting during Counter Operation ....................... 149
Section 10
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Timer W
Timer W Block Diagram......................................................................................... 155
Free-Running Counter Operation ............................................................................ 166
Periodic Counter Operation..................................................................................... 167
0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 167
Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 168
Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 168
Input Capture Operating Example........................................................................... 169
Buffer Operation Example (Input Capture)............................................................. 170
PWM Mode Example (1) ........................................................................................ 171
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Figure 10.10 PWM Mode Example (2) ...................................................................................... 171
Figure 10.11 Buffer Operation Example (Output Compare) ...................................................... 172
Figure 10.12 PWM Mode Example
(TOB, TOC, and TOD = 0: initial output values are set to 0)............................... 173
Figure 10.13 PWM Mode Example
(TOB, TOC, and TOD = 1: initial output values are set to 1)............................... 174
Figure 10.14 Count Timing for Internal Clock Source ............................................................... 175
Figure 10.15 Count Timing for External Clock Source.............................................................. 175
Figure 10.16 Output Compare Output Timing ........................................................................... 176
Figure 10.17 Input Capture Input Signal Timing........................................................................ 177
Figure 10.18 Timing of Counter Clearing by Compare Match................................................... 177
Figure 10.19 Buffer Operation Timing (Compare Match).......................................................... 178
Figure 10.20 Buffer Operation Timing (Input Capture) ............................................................. 178
Figure 10.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 179
Figure 10.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 180
Figure 10.23 Timing of Status Flag Clearing by CPU................................................................ 180
Figure 10.24 Contention between TCNT Write and Clear ......................................................... 183
Figure 10.25 Internal Clock Switching and TCNT Operation.................................................... 183
Section 11
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Realtime Clock (RTC)
Block Diagram of RTC ........................................................................................... 186
Definition of Time Expression ................................................................................ 191
Initial Setting Procedure .......................................................................................... 196
Example: Reading of Inaccurate Time Data............................................................ 197
Section 12
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Watchdog Timer
Block Diagram of Watchdog Timer ........................................................................ 202
Example of Watchdog Timer Operation.................................................................. 208
Interval Timer Mode Operation............................................................................... 209
Timing of OVF Flag Setting.................................................................................... 209
Section 13
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Asynchronous Event Counter (AEC)
Block Diagram of Asynchronous Event Counter .................................................... 214
Software Procedure when Using ECH and ECL as 16-Bit Event Counter.............. 223
Software Procedure when Using ECH and ECL as 8-Bit Event Counters .............. 224
Event Counter Operation Waveform....................................................................... 226
Example of Clock Control Operation...................................................................... 227
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Figure 14.1 Block Diagram of SCI3 ........................................................................................... 232
Figure 14.2 Data Format in Asynchronous Communication ...................................................... 254
Rev. 3.00 May 15, 2007 Page xxiii of xxxii
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............ 254
Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 258
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 259
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 260
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 262
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) ..................... 263
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) ..................... 264
Figure 14.9 Data Format in Clock Synchronous Communication.............................................. 265
Figure 14.10 Example of SCI3 Operation in Transmission in
Clock Synchronous Mode ..................................................................................... 266
Figure 14.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode) .................... 267
Figure 14.12 Example of SCI3 Reception Operation in Clock Synchronous Mode................... 268
Figure 14.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 269
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and
Receive Operations (Clock Synchronous Mode) .................................................. 270
Figure 14.15 IrDA Block Diagram............................................................................................. 271
Figure 14.16 IrDA Transmission and Reception ........................................................................ 272
Figure 14.17 (a) RDRF Setting and RXI Interrupt ..................................................................... 276
Figure 14.17 (b) TDRE Setting and TXI Interrupt ..................................................................... 276
Figure 14.17 (c) TEND Setting and TEI Interrupt...................................................................... 276
Figure 14.18 Receive Data Sampling Timing in Asynchronous Mode ...................................... 278
Figure 14.19 Relation between RDR Read Timing and Data..................................................... 280
Section 15 Synchronous Serial Communication Unit (SSU)
Figure 15.1 Block Diagram of SSU............................................................................................ 284
Figure 15.2 Relationship between Clock Polarity and Phase, and Data ..................................... 294
Figure 15.3 Relationship between Data Input/Output Pin and Shift Register ............................ 295
Figure 15.4 Initialization in Clocked Synchronous Communication Mode................................ 297
Figure 15.5 Example of Operation in Data Transmission .......................................................... 298
Figure 15.6 Sample Serial Transmission Flowchart ................................................................... 299
Figure 15.7 Example of Operation in Data Reception (MSS = 1) .............................................. 300
Figure 15.8 Sample Serial Reception Flowchart (MSS = 1)....................................................... 301
Figure 15.9 Sample Flowchart for Serial Transmit and Receive Operations.............................. 302
Figure 15.10 Initialization in Four-Line Bus Communication Mode ......................................... 304
Figure 15.11 Example of Operation in Data Transmission (MSS = 1)....................................... 306
Figure 15.12 Example of Operation in Data Reception (MSS = 1) ............................................ 308
Figure 15.13 Arbitration Check Timing ..................................................................................... 309
Rev. 3.00 May 15, 2007 Page xxiv of xxxii
Section 16 I2C Bus Interface 2 (IIC2)
Figure 16.1 Block Diagram of I2C Bus Interface 2..................................................................... 312
Figure 16.2 External Circuit Connections of I/O Pins ................................................................ 313
Figure 16.3 I2C Bus Formats ...................................................................................................... 328
Figure 16.4 I2C Bus Timing........................................................................................................ 328
Figure 16.5 Master Transmit Mode Operation Timing (1) ......................................................... 330
Figure 16.6 Master Transmit Mode Operation Timing (2) ......................................................... 330
Figure 16.7 Master Receive Mode Operation Timing (1)........................................................... 332
Figure 16.8 Master Receive Mode Operation Timing (2)........................................................... 333
Figure 16.9 Slave Transmit Mode Operation Timing (1) ........................................................... 334
Figure 16.10 Slave Transmit Mode Operation Timing (2) ......................................................... 335
Figure 16.11 Slave Receive Mode Operation Timing (1)........................................................... 336
Figure 16.12 Slave Receive Mode Operation Timing (2)........................................................... 337
Figure 16.13 Clock Synchronous Serial Transfer Format .......................................................... 337
Figure 16.14 Transmit Mode Operation Timing......................................................................... 338
Figure 16.15 Receive Mode Operation Timing .......................................................................... 339
Figure 16.16 Block Diagram of Noise Conceler......................................................................... 340
Figure 16.17 Sample Flowchart for Master Transmit Mode....................................................... 341
Figure 16.18 Sample Flowchart for Master Receive Mode ........................................................ 342
Figure 16.19 Sample Flowchart for Slave Transmit Mode......................................................... 343
Figure 16.20 Sample Flowchart for Slave Receive Mode .......................................................... 344
Figure 16.21 Timing of Bit Synchronous Circuit ....................................................................... 346
Section 17
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Figure 17.8
A/D Converter
Block Diagram of A/D Converter ........................................................................... 349
External Trigger Input Timing ................................................................................ 353
Example of A/D Conversion Operation .................................................................. 355
Flowchart of Procedure for Using A/D Converter (Polling by Software) ............... 356
Flowchart of Procedure for Using A/D Converter (Interrupts Used) ...................... 356
A/D Conversion Accuracy Definitions (1) .............................................................. 358
A/D Conversion Accuracy Definitions (2) .............................................................. 358
Example of Analog Input Circuit ............................................................................ 359
Section 18
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Comparators
Block Diagram of Comparators............................................................................... 361
Hysteresis/Non-Hysteresis Selection by CDR......................................................... 366
Procedure for Setting Interrupt (1) .......................................................................... 367
Procedure for Setting Interrupt (2) .......................................................................... 368
Section 19 Power-On Reset Circuit
Figure 19.1 Power-On Reset Circuit........................................................................................... 369
Figure 19.2 Power-On Reset Circuit Operation Timing ............................................................. 370
Rev. 3.00 May 15, 2007 Page xxv of xxxii
Section 21
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
Electrical Characteristics
Power Supply Voltage and Oscillation Frequency Range (1) ................................. 386
Power Supply Voltage and Oscillation Frequency Range (2) ................................. 387
Power Supply Voltage and Operating Frequency Range (1)................................... 388
Power Supply Voltage and Operating Frequency Range (2)................................... 389
Power Supply Voltage and Operating Frequency Range (3)................................... 390
Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (1) ................................................................................................... 391
Figure 21.7 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (2) ................................................................................................... 392
Figure 21.8 Power Supply Voltage and Oscillation Frequency Range (1) ................................. 412
Figure 21.9 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 413
Figure 21.10 Power Supply Voltage and Operating Frequency Range (1)................................. 414
Figure 21.11 Power Supply Voltage and Operating Frequency Range (2)................................. 415
Figure 21.12 Power Supply Voltage and Operating Frequency Range (3)................................. 416
Figure 21.13 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (1).................................................................................................. 417
Figure 21.14 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (2).................................................................................................. 418
Figure 21.15 Clock Input Timing ............................................................................................... 435
Figure 21.16 RES Low Width Timing........................................................................................ 435
Figure 21.17 Input Timing.......................................................................................................... 435
Figure 21.18 SCK3 Input Clock Timing .................................................................................... 435
Figure 21.19 SCI3 Input/Output Timing in Clock Synchronous Mode...................................... 436
Figure 21.20 SSU Input/Output Timing in Clock Synchronous Mode....................................... 436
Figure 21.21 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 1) ................................. 437
Figure 21.22 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 0) ................................. 437
Figure 21.23 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 1) ................................... 438
Figure 21.24 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 0) ................................... 438
Figure 21.25 I2C Bus Interface Input/Output Timing ................................................................. 439
Figure 21.26 Power-On Reset Circuit Reset Timing .................................................................. 439
Figure 21.27 Output Load Condition.......................................................................................... 440
Figure 21.28 Recommended Resonators .................................................................................... 440
Appendix
Figure B.1 (a) Port 1 Block Diagram (P12)................................................................................ 473
Figure B.1 (b) Port 1 Block Diagram (P11)................................................................................ 474
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Figure B.1 (c) Port 1 Block Diagram (P10)................................................................................ 475
Figure B.2 (a) Port 3 Block Diagram (P32)................................................................................ 476
Figure B.2 (b) Port 3 Block Diagram (P31)................................................................................ 477
Figure B.2 (c) Port 3 Block Diagram (P30)................................................................................ 478
Figure B.3 (a) Port 8 Block Diagram (P84 to P82)..................................................................... 479
Figure B.4 (a) Port 9 Block Diagram (P93)................................................................................ 480
Figure B.4 (b) Port 9 Block Diagram (P92)................................................................................ 481
Figure B.4 (c) Port 9 Block Diagram (P91)................................................................................ 482
Figure B.4 (d) Port 9 Block Diagram (P90)................................................................................ 483
Figure B.5 (a) Port B Block Diagram (PB5 or PB4) .................................................................. 484
Figure B.5 (b) Port B Block Diagram (PB3 or PB2) .................................................................. 484
Figure B.5 (c) Port B Block Diagram (PB1 or PB0) .................................................................. 485
Figure D.1 Package Dimensions (TNP-32) ................................................................................ 492
Figure D.2 Package Dimensions (32P6U-A).............................................................................. 493
Rev. 3.00 May 15, 2007 Page xxvii of xxxii
Rev. 3.00 May 15, 2007 Page xxviii of xxxii
Tables
Section 1 Overview
Table 1.1
Pin Functions ............................................................................................................ 4
Section 2 CPU
Table 2.1
Operation Notation ................................................................................................. 16
Table 2.2
Data Transfer Instructions....................................................................................... 17
Table 2.3
Arithmetic Operations Instructions (1) ................................................................... 18
Table 2.3
Arithmetic Operations Instructions (2) ................................................................... 19
Table 2.4
Logic Operations Instructions................................................................................. 20
Table 2.5
Shift Instructions..................................................................................................... 20
Table 2.6
Bit Manipulation Instructions (1)............................................................................ 21
Table 2.6
Bit Manipulation Instructions (2)............................................................................ 22
Table 2.7
Branch Instructions ................................................................................................. 23
Table 2.8
System Control Instructions.................................................................................... 24
Table 2.9
Block Data Transfer Instructions ............................................................................ 25
Table 2.10
Addressing Modes .................................................................................................. 27
Table 2.11
Absolute Address Access Ranges ........................................................................... 29
Table 2.12
Effective Address Calculation (1)........................................................................... 30
Table 2.12
Effective Address Calculation (2)........................................................................... 31
Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address .................................................................. 42
Table 3.2
Reset Sources.......................................................................................................... 44
Table 3.3
Pin Configuration.................................................................................................... 46
Table 3.4
Interrupt Wait States ............................................................................................... 57
Section 4 Clock Pulse Generators
Table 4.1
Methods for Selecting System Clock Oscillator and On-Chip Oscillator............... 67
Section 5 Power-Down Modes
Table 5.1
Operating Frequency and Waiting Time................................................................. 79
Table 5.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 85
Table 5.3
Internal State in Each Operating Mode................................................................... 86
Section 6 ROM
Table 6.1
Setting Programming Modes ................................................................................ 104
Table 6.2
Boot Mode Operation ........................................................................................... 107
Table 6.3
System Clock Frequencies for which Automatic Adjustment of
LSI Bit Rate is Possible......................................................................................... 108
Table 6.4
Reprogramming Data Computation Table ............................................................ 111
Rev. 3.00 May 15, 2007 Page xxix of xxxii
Table 6.5
Table 6.6
Table 6.7
Additional-Program Data Computation Table ...................................................... 111
Programming Time ............................................................................................... 111
Flash Memory Operating States............................................................................ 115
Section 9 Timer B1
Table 9.1
Timer B1 Operating Modes .................................................................................. 151
Section 10 Timer W
Table 10.1
Timer W Functions ............................................................................................... 154
Table 10.2
Pin Configuration.................................................................................................. 156
Table 10.3
Timer W Operating Modes ................................................................................... 181
Section 11 Realtime Clock (RTC)
Table 11.1
Pin Configuration.................................................................................................. 186
Table 11.2
Interrupt Sources................................................................................................... 198
Section 12 Watchdog Timer
Table 12.1
Assembly Program for Clearing WT/IT or IEOVF Bit to 0 ................................. 211
Table 12.2
The Value of "xx" ................................................................................................. 211
Section 13 Asynchronous Event Counter (AEC)
Table 13.1
Pin Configuration.................................................................................................. 215
Table 13.2
Examples of Event Counter PWM Operation....................................................... 226
Table 13.3
Operating States of Asynchronous Event Counter................................................ 228
Table 13.4
Maximum Clock Frequency ................................................................................. 229
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.1
Pin Configuration.................................................................................................. 233
Table 14.2
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 0) (1) ..................................................... 244
Table 14.2
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 0) (2) ..................................................... 244
Table 14.2
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 0) (3) ..................................................... 245
Table 14.2
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 0) (4) ..................................................... 245
Table 14.3
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 1) (1) ..................................................... 246
Table 14.3
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 1) (2) ..................................................... 246
Table 14.3
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 1) (3) ..................................................... 247
Rev. 3.00 May 15, 2007 Page xxx of xxxii
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.6
Table 14.7
Table 14.8
Table 14.9
Table 14.10
Table 14.11
Table 14.12
Table 14.13
Table 14.14
Examples of BRR Settings for Various Bit Rates
(Asynchronous Mode and ABCS Bit is 1) (4)...................................................... 247
Relation between n and Clock .............................................................................. 248
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 248
BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1) ................... 249
BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2) ................... 250
Relation between n and Clock .............................................................................. 250
Data Transfer Formats (Asynchronous Mode)...................................................... 255
SMR Settings and Corresponding Data Transfer Formats.................................... 256
SMR and SCR Settings and Clock Source Selection............................................ 257
SSR Status Flags and Receive Data Handling...................................................... 262
IrCKS2 to IrCKS0 Bit Settings............................................................................. 273
SCI3 Interrupt Requests........................................................................................ 274
Transmit/Receive Interrupts ................................................................................. 275
Section 15 Synchronous Serial Communication Unit (SSU)
Table 15.1
Pin Configuration.................................................................................................. 284
Table 15.2
Relationship between Communication Modes and Input/Output Pins.................. 296
Table 15.3
Interrupt Requests ................................................................................................. 310
Section 16 I2C Bus Interface 2 (IIC2)
Table 16.1
Pin Configuration.................................................................................................. 313
Table 16.2
Transfer Rate ........................................................................................................ 316
Table 16.3
Interrupt Requests ................................................................................................. 345
Table 16.4
Time for Monitoring SCL..................................................................................... 346
Section 17 A/D Converter
Table 17.1
Pin Configuration.................................................................................................. 350
Table 17.2
Operating States of A/D Converter....................................................................... 354
Section 18 Comparators
Table 18.1
Pin Configuration.................................................................................................. 362
Table 18.2
Combination of CMR and CMLS Bits ................................................................. 364
Section 21 Electrical Characteristics
Table 21.1
Absolute Maximum Ratings ................................................................................. 385
Table 21.2
DC Characteristics ................................................................................................ 393
Table 21.3
Control Signal Timing .......................................................................................... 399
Table 21.4
Serial Interface Timing ......................................................................................... 402
Table 21.5
Synchronous Serial Communication Unit (SSU) Timing ..................................... 403
Table 21.6
I2C Bus Interface Timing ...................................................................................... 404
Table 21.7
A/D Converter Characteristics .............................................................................. 405
Table 21.8
Comparator Characteristics................................................................................... 407
Rev. 3.00 May 15, 2007 Page xxxi of xxxii
Table 21.9
Table 21.10
Table 21.11
Table 21.12
Table 21.13
Table 21.14
Table 21.15
Table 21.16
Table 21.17
Table 21.18
Table 21.19
Table 21.20
Table 21.21
Watchdog Timer Characteristics........................................................................... 407
Power-On Reset Circuit Characteristics ............................................................... 408
Flash Memory Characteristics .............................................................................. 409
Absolute Maximum Ratings ................................................................................. 411
DC Characteristics ................................................................................................ 419
Control Signal Timing .......................................................................................... 425
Serial Interface Timing ......................................................................................... 428
Synchronous Serial Communication Unit (SSU) Timing ..................................... 429
I2C Bus Interface Timing...................................................................................... 430
A/D Converter Characteristics.............................................................................. 431
Comparator Characteristics................................................................................... 433
Watchdog Timer Characteristics........................................................................... 433
Power-On Reset Circuit Characteristics ............................................................... 434
Appendix
Table A.1
Table A.2
Table A.2
Table A.2
Table A.3
Table A.4
Table A.5
Table B.1
Instruction Set....................................................................................................... 445
Operation Code Map (1) ....................................................................................... 458
Operation Code Map (2) ....................................................................................... 459
Operation Code Map (3) ....................................................................................... 460
Number of Cycles in Each Instruction.................................................................. 462
Number of Cycles in Each Instruction.................................................................. 463
Combinations of Instructions and Addressing Modes .......................................... 472
Port 9 Related Register Settings and Pin Functions.............................................. 487
Rev. 3.00 May 15, 2007 Page xxxii of xxxii
Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8/300H central processing unit with an internal 16-bit architecture
 Upward-compatible with H8/300 CPU on an object level
 Sixteen 16-bit general registers
 62 basic instructions
• Various peripheral functions
 RTC (can be used as a free-running counter)
 Asynchronous event counter (AEC)
 Timer B1
 Timer W
 Watchdog timer
 SCI (asynchronous or clock synchronous serial communication interface)
 SSU (synchronous serial communication unit)*
 I2C bus interface (conforms to the I2C bus interface format that is advocated by Philips
Electronics)*
 10-bit A/D converter
 Comparators
Note: * SSU and IIC2 are shared.
• On-chip memory
Product Classification
Model
ROM
RAM
Flash memory version
TM
(F-ZTAT version)
H8/38602RF
HD64F38602R
16 Kbytes
1 Kbyte
Masked ROM version
H8/38602R
HD64338602R
16 Kbytes
1 Kbyte
H8/38600R
HD64338600R
8 Kbytes
512 bytes
TM
Note: F-ZTAT is a trademark of Renesas Technology Corp.
• General I/O ports
 I/O pins: 13 I/O pins, including three large current ports (IOL = 15 mA, @VOL = 1.0 V)
 Input-only pins: 6 input pins (also used as analog input pins)
• Supports various power-down states
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Section 1 Overview
• Compact package
Package
Code
Body Size
Pin Pitch
P-VQFN-32
TNP-32
5 × 6 mm
0.5 mm
P-LQFP-32
32P6U-A
7 × 7 mm
0.8 mm
1.2
Remarks
Internal Block Diagram
E7_0
E7_1
E7_2
X1
Subclock oscillator
Vcc
AVcc
Vss
RES
TEST/ADTRG
NMI*1
H8/300H CPU
X2
OSC1
System clock oscillator
RAM
OSC2
Realtime clock
Timer B1
Timer W
10-bit A/D converter
Comparators
Asynchronous
event counter
SSU*2
SCI3/IrDA
I2C bus
interface 2 *2
Port 8
Watchdog timer
P82/FTIOB
P83/FTIOC
P84/FTIOD
Port 9
Port 1
Power-on reset circuit
P90/SCS/SCL
P91/SSCK/SDA
P92/SSO (/IRQ0)
P93/SSI (/IRQ1)
Port B
P30/SCK3/VCref (/IRQ0)
P31/RXD3/IrRXD
P32/TXD3/IrTXD
ROM
Port 3
P10/AEVH/FTIOA/TMOW/CLKOUT
P11/AEVL/FTCI (/IRQ1)
P12/IRQAEC/AECPWM
PB0/AN0/IRQ0
PB1/AN1/IRQ1
PB2/AN2
PB3/AN3
PB4/AN4/COMP0
PB5/AN5/COMP1
Notes: 1. The NMI pin is not available when the E7 or on-chip emulator debugger is used.
2. SSU and IIC2 are shared.
Figure 1.1 Internal Block Diagram of H8/38602R Group
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Section 1 Overview
P31/RXD3/IrRXD
P32/TXD3/IrTXD
P93/SSI (/IRQ1)
P92/SSO (/IRQ0)
P91/SSCK/SDA
P90/SCS/SCL
E7_0
E7_1
E7_2
25
24
23
22
21
20
19
18
17
Pin Assignment
P30/SCK3/VCref (/IRQ0)
26
16
NMI
PB5/AN5/COMP1
27
15
P12/IRQAEC/AECPWM
PB4/AN4/COMP0
28
14
P11/AEVL/FTCI (/IRQ1)
PB3/AN3
29
13
P10/AEVH/FTIOA/TMOW/CLKOUT
PB2/AN2
30
12
P82/FTIOB
PB1/AN1/IRQ1
31
11
P83/FTIOC
PB0/AN0/IRQ0
32
10
P84/FTIOD
8
9
TEST/ADTRG
OSC1
Vcc
7
6
VSS
5
OSC2
4
RES
3
X2
2
X1
AVcc
1
TNP-32
(Top view)
P32/TXD3/IrTXD
P93/SSI (/IRQ1)
P92/SSO (/IRQ0)
P91/SSCK/SDA
P90/SCS/SCL
E7_0
E7_1
E7_2
24
23
22
21
20
19
18
17
Figure 1.2 Pin Assignment of H8/38602R Group (TNP-32)
P31/RXD3/IrRXD
25
16
NMI
P30/SCK3/VCref (/IRQ0)
26
15
P12/IRQAEC/AECPWM
PB5/AN5/COMP1
27
14
P11/AEVL/FTCI (/IRQ1)
PB4/AN4/COMP0
28
13
P10/AEVH/FTIOA/TMOW/CLKOUT
PB3/AN3
29
12
P82/FTIOB
PB2/AN2
30
11
P83/FTIOC
PB1/AN1/IRQ1
31
10
P84/FTIOD
PB0/AN0/IRQ0
32
9
1
2
3
4
5
6
7
8
X1
X2
RES
OSC2
VSS
OSC1
Vcc
32P6U-A
(Top view)
AVcc
1.3
TEST/ADTRG
Figure 1.3 Pin Assignment of H8/38602R Group (32P6U-A)
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Section 1 Overview
1.4
Pin Functions
Table 1.1
Pin Functions
Type
Symbol
Pin No. I/O
Functions
Power
supply pins
Vcc
8
Input
Power supply pin. Connect this pin to the system
power supply.
Vss
6
Input
Ground pin. Connect this pin to the system power
supply (0 V).
AVcc
1
Input
Analog power supply pin for the A/D converter.
When the A/D converter is not used, connect this
pin to the system power supply.
OSC1
7
Input
OSC2
5
Output
These pins connect with crystal or ceramic
resonator for the system clock, or can be used to
input an external clock.
Clock pins
See section 4, Clock Pulse Generators, for a typical
connection.
System
control
X1
2
Input
X2
3
Output
These pins connect with a 32.768- or 38.4-kHz
crystal resonator for the subclock. See section 4,
Clock Pulse Generators, for a typical connection.
CLKOUT
13
Output
Clock output pin.
RES
4
Input
Reset pins. The power-on reset circuit is
incorporated. When externally driven low, the chip
is reset.
TEST
9
Input
Test pins. Also used as the ADTRG pin. When this
pin is not used as the ADTRG pin, users cannot
use this pin. Connect this pin to Vss. When this pin
is used as the ADTRG pin, see section 17.4.2,
External Trigger Input Timing.
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Section 1 Overview
Type
Symbol
Interrupt pins NMI
Pin No. I/O
Functions
16
NMI interrupt request pin.
Input
Non-maskable interrupt request input pin.
In the F-ZTAT version, the level on this pin
determines whether to enter the user or boot mode
when the reset state is released. To enter the user
mode, pull up this pin to the Vcc level.
IRQ0
32
Input
(22, 26)
IRQ1
31
Input
(14, 23)
IRQAEC
15
Input
External interrupt request input pins.
Can select the rising or falling edge.
Interrupt input pin for the asynchronous event
counter.
This pin enables the asynchronous event input.
Timer W
FTCI
14
Input
External event input pin.
FTIOA to
FTIOD
13 to
10
I/O
Output compare output/input capture input/PWM
output pins.
Asynchronous event
counter
(AEC)
AEVL
14
Input
AEVH
13
Input
Event input pins for input to the asynchronous event
counter.
AECPWM
15
Output
PWM output pin for the AEC.
RTC
TMOW
13
Output
Divided clock output pin for the RTC.
Serial
communication
interface 3
(SCI3)
SCK3
26
I/O
SCI3 clock I/O pin.
RXD3/
IrRXD
25
Input
SCI3 data input pins or data input pins for the IrDA
format.
TXD3/
IrTXD
24
Output
SCI3 data output pins or data output pins for the
IrDA format.
Synchronous serial
communication unit
(SSU)
SCS
20
I/O
SSU chip select I/O pin.
SSCK
21
I/O
SSU clock I/O pin.
SSI
23
I/O
SSU transmit/receive data I/O pins.
SSO
22
I/O
SDA
21
I/O
IIC data I/O pin.
SCL
20
I/O
IIC clock I/O pin.
2
I C bus
interface 2
(IIC2)
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Section 1 Overview
Type
Symbol
Pin No. I/O
Functions
A/D
converter
AN0 to
AN5
32 to
27
Input
Analog data input pins for the A/D converter.
ADTRG
9
Input
External trigger input pin for the A/D converter.
28
Input
Analog data input pins for the comparator.
Input
Reference voltage pin for external input of threshold
voltage of the comparator analog input pins.
P10 to P12 13 to
15
I/O
3-bit I/O pins. Input or output can be designated for
each bit by means of the port control register 1
(PCR1).
P30 to P32 26 to
24
I/O
3-bit I/O pins. Input or output can be designated for
each bit by means of the port control register 3
(PCR3).
P82 to P84 12 to
10
I/O
3-bit I/O pins. Input or output can be designated for
each bit by means of the port control register 8
(PCR8).
P90 to P93 20 to
23
I/O
4-bit I/O pins. Input or output can be designated for
each bit by means of the port control register 9
(PCR9).
PB0 to PB5 32 to
27
Input
6-bit input-only pins.
E7_0

E7 emulator interface pins. E7_2 selects whether
the on-chip oscillator is used. E7_2 is pulled up or
down by a 100-kΩ resistance. For details, see
section 4, Clock Pulse Generators.
Comparators COMP0
I/O ports
E7
COMP1
27
VCref
26
E7_1
19 to
17
E7_2
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Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward compatible with
the H8/300 CPU, and supports only normal mode, which has a 64-Kbyte address space.
• Upward-compatible with H8/300 CPUs
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers,
or eight 32-bit registers
• Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 64-Kbyte address space
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 2 states
8 × 8-bit register-register multiply:
14 states
16 ÷ 8-bit register-register divide:
14 states
16 × 16-bit register-register multiply:
22 states
32 ÷ 16-bit register-register divide:
22 states
CPU30H2C_000120030300
Rev. 3.00 May 15, 2007 Page 7 of 516
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Section 2 CPU
• Power-down state
Transition to power-down state by SLEEP instruction
2.1
Address Space and Memory Map
The address space of this LSI is 64 Kbytes, which includes the program area and the data area.
Figure 2.1 shows the memory map.
H'0000
H'0050
HD64F38602R
HD64338602R
HD64338600R
(Flash memory version)
(Masked ROM version)
(Masked ROM version)
Interrupt vector
H'0000
H'0050
On-chip ROM
(16 Kbytes)
H'3FFF
Interrupt vector
On-chip ROM
(16 Kbytes)
H'0000
H'0050
Interrupt vector
On-chip ROM
(8 Kbytes)
H'1FFF
H'3FFF
H'F020
H'F020
Internal I/O registers
H'F100
Not used
Not used
Not used
H'F020
Internal I/O registers
H'F100
Not used
Internal I/O registers
H'F100
Not used
Not used
H'FB80
H'FB80
On-chip RAM
(1 Kbyte)
H'FF80
On-chip RAM
(1 Kbyte)
H'FF80
Internal I/O registers
H'FFFF
H'FF80
Internal I/O registers
H'FFFF
Figure 2.1 Memory Map
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H'FD80
On-chip RAM
(512 bytes)
Internal I/O registers
H'FFFF
Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition-code register (CCR).
General Registers (ERn)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7
E7
R7H
R7L
(SP)
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
[Legend]
SP:
PC:
CCR:
I:
UI:
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Figure 2.2 CPU Registers
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Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between the stack pointer and the stack area.
Empty area
SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
Rev. 3.00 May 15, 2007 Page 11 of 516
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Section 2 CPU
Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
6
UI
Undefined R/W
5
H
Undefined R/W
4
U
Undefined R/W
3
N
Undefined R/W
2
Z
Undefined R/W
1
V
Undefined R/W
0
C
Undefined R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
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2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1
General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
General Register
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Lower
0
Don't care
MSB
LSB
Figure 2.5 General Register Data Formats (1)
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Data Type
General
Register
Word data
Rn
Data Format
15
Word data
MSB
En
15
MSB
Longword
data
0
LSB
0
LSB
ERn
31
16 15
MSB
[Legend]
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.5 General Register Data Formats (2)
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0
LSB
Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
LSB
Address 2N+3
Figure 2.6 Memory Data Formats
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2.4
Instruction Set
2.4.1
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined below.
Table 2.1
Operation Notation
Symbol
Description
Rd
Rs
Rn
ERn
(EAd)
(EAs)
CCR
N
Z
V
C
PC
SP
#IMM
disp
+
–
×
÷
∧
∨
⊕
→
¬
:3/:8/:16/:24
General register (destination)*
General register (source)*
General register*
General register (32-bit register or address register)
Destination operand
Source operand
Condition-code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Stack pointer
Immediate data
Displacement
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Logical XOR
Move
NOT (logical complement)
3-, 8-, 16-, or 24-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
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Table 2.2
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd
Cannot be used in this LSI.
MOVTPE
B
Rs → (EAs)
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note:
* Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the
SUBX or ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note:
* Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3
Arithmetic Operations Instructions (2)
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Note:
* Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note:
* Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note:
* Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.6
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note:
* Refers to the operand size.
B: Byte
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Section 2 CPU
Table 2.6
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
* Refers to the operand size.
B: Byte
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Section 2 CPU
Table 2.7
Branch Instructions
Instruction
Size
Function
Bcc*

Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP

Branches unconditionally to a specified address.
BSR

Branches to a subroutine at a specified address.
JSR

Branches to a subroutine at a specified address.
RTS

Returns from a subroutine
Note:
*
Bcc is the general name for conditional branch instructions.
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Section 2 CPU
Table 2.8
System Control Instructions
Instruction
Size*
Function
TRAPA

Starts trap-instruction exception handling
RTE

Returns from an exception-handling routine.
SLEEP

Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is written
by word access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the CCR with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the CCR with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically XORs the CCR with immediate data.
NOP

PC + 2 → PC
Only increments the program counter.
Note:
* Refers to the operand size.
B: Byte
W: Word
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Table 2.9
Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B

if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
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2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
• Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA(disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA(disp)
BRA d:8
Figure 2.7 Instruction Formats
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2.5
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.
2.5.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.10 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:24,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
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Section 2 CPU
Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
• Register indirect with pre-decrement@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
Absolute Address—@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits (@aa:8), 16 bits (@aa:16), or 24 bits (@aa:24).
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
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Section 2 CPU
The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the
upper 8 bits are ignored.
Table 2.11 Absolute Address Access Ranges
Absolute Address
Access Range
8 bits (@aa:8)
H'FF00 to H'FFFF
16 bits (@aa:16)
H'0000 to H'FFFF
24 bits (@aa:24)
H'0000 to H'FFFF
Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in
memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the
address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
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Section 2 CPU
Specified
by @aa:8
Dummy
Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
2.5.2
Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct(Rn)
rm
Operand is general register contents.
rn
Register indirect(@ERn)
0
31
23
0
23
0
23
0
23
0
General register contents
op
3
r
Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
0
31
General register contents
op
r
disp
0
31
Sign extension
4
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
op
31
0
General register contents
r
•Register indirect with pre-decrement @-ERn
disp
1, 2, or 4
31
0
General register contents
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
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Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
8 7
23
op
abs
0
H'FFFF
@aa:16
23
op
abs
16 15
0
Sign extension
@aa:24
op
0
23
abs
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC) @(d:16,PC)
op
disp
23
0
Sign
extension
8
disp
23
0
Memory indirect @@aa:8
8 7
23
op
abs
0
abs
H'0000
15
0
Memory contents
[Legend]
r, rm,rn :
op :
disp :
IMM :
abs :
23
16 15
0
H'00
Register field
Operation field
Displacement
Immediate data
Absolute address
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Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φ or φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 20.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Bus cycle
T1 state
T2 state
T3 state
φ or φ SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. For the program halt state, there are sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in
figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and
program halt state, refer to section 5, Power-Down Modes. For details on exception handling, refer
to section 3, Exception Handling.
CPU state
Reset state
The CPU is initialized
Program execution state
Active (high-speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active (medium-speed) mode
Subactive mode
The CPU executes successive
program instructions at reduced
speed, synchronized by the subclock
Program halt state
A state in which the CPU
operation is stopped to
reduce power consumption
Sleep (high-speed) mode
Sleep (medium-speed) mode
Standby mode
Watch mode
Subsleep mode
Exception-handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operating States
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Power-down modes
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Section 2 CPU
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
Program halt state
Interrupt
source
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.12 State Transitions
2.8
2.8.1
Usage Notes
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2
EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4 or
R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4, R4L,
and R6 so that the end address of the destination address (value of R6 + R4L or R6 + R4) does not
exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution).
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Section 2 CPU
2.8.3
Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address, or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.
Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit-manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration
with Two Registers Allocated to Same Address
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Section 2 CPU
Example 2: When the BSET instruction is executed for port 5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
• Prior to executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
• BSET instruction executed instruction
BSET
#0,
@PDR5
The BSET instruction is executed for port 5.
• After executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
0
1
0
0
0
0
0
1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
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Section 2 CPU
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
Prior to executing BSET instruction
MOV.B
MOV.B
MOV.B
#H'80, R0L
R0L,
@RAM0
R0L,
@PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
• BSET instruction executed
BSET
#0,
@RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
• After executing BSET instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PDR5
The work area (RAM0) value is written to PDR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
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Section 2 CPU
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
• BCLR instruction executed
BCLR
#0,
@PCR5
The BCLR instruction is executed for PCR5.
• After executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
1
1
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
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Section 2 CPU
• Prior to executing BCLR instruction
MOV.B
MOV.B
MOV.B
#H'3F, R0L
R0L,
@RAM0
R0L,
@PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
1
• BCLR instruction executed
BCLR
#0,
@RAM0
The BCLR instructions executed for the PCR5 work area
(RAM0).
• After executing BCLR instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PCR5
The work area (RAM0) value is written to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
0
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling is caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts after the reset state is
cleared by a negation of the RES signal. Exception handling is also started when the watchdog
timer overflows. The exception handling executed at this time is the same as that for a reset by
the RES pin.
• Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. A vector address
corresponding to a vector number from 0 to 3 which are specified in the instruction code is
generated. Exception handling can be executed at all times in the program execution state,
regardless of the setting of the I bit in CCR.
• Interrupts
External interrupts other than the NMI and internal interrupts are masked by the I bit in CCR,
and kept pending while the I bit is set to 1. Exception handling starts when the current
instruction or exception handling ends, if an interrupt is requested.
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Section 3 Exception Handling
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1
Exception Sources and Vector Address
Source Origin
Exception Sources
Vector
Number
Vector Address
Priority
Reset pin/
watchdog timer

External interrupt
Trap instruction
TRAPA #0
Reset
0
H'0000 to H'0001
High
Reserved for system use
NMI
Trap instruction #0
1 to 6
7
8
H'0002 to H'000D
H'000E to H'000F
H'0010 to H'0011
Trap instruction
TRAPA #1
Trap instruction
TRAPA #2
Trap instruction
TRAPA #3
Trap instruction #1
9
H'0012 to H'0013
Trap instruction #2
10
H'0014 to H'0015
Trap instruction #3
11
H'0016 to H'0017

CPU
Reserved for system use
Direct transition by executing the
SLEEP instruction
Reserved for system use
IRQ0
IRQ1
IRQAEC
Reserved for system use
COMP0
COMP1
0.25-second overflow
0.5-second overflow
Second periodic overflow
Minute periodic overflow
Hour periodic overflow
Day-of-week periodic overflow
Week periodic overflow
Free-running overflow
12
13
H'0018 to H'0019
H'001A to H'001B
14, 15
16
17
18
19, 20
21
22
23
24
25
26
27
28
29
30
H'001C to H'001F
H'0020 to H'0021
H'0022 to H'0023
H'0024 to H'0025
H'0026 to H'0029
H'002A to H'002B
H'002C to H'002D
H'002E to H'002F
H'0030 to H'0031
H'0032 to H'0033
H'0034 to H'0035
H'0036 to H'0037
H'0038 to H'0039
H'003A to H'003B
H'003C to H'003D Low

External interrupts

Comparators
RTC
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Section 3 Exception Handling
Source Origin
Exception Sources
Vector
Number
Vector Address
Priority
WDT
WDT overflow (interval timer)
31
H'003E to H'003F
High
Asynchronous
event counter
Timer B1
Synchronous serial
communication unit
(SSU)/
Asynchronous event counter
overflow
Overflow
32
H'0040 to H'0041
33
H'0042 to H'0043
34
H'0044 to H'0045
IIC2*
Transmit data empty (IIC2)
Transmit end (IIC2)
Receive data full (IIC2)
NACK detection (IIC2)
Arbitration (IIC2)
Overrun error (IIC2)
Input capture A/compare match A
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Overflow
Reserved for system use
Transmit end
Transmit data empty
Receive data full
Overrun error
Framing error
Parity error
A/D conversion end
Reserved for system use
35
H'0046 to H'0047
36
H'0048 to H'0049
37
H'004A to H'004B
38
39
H'004C to H'004D
H'004E to H'004F Low
Timer W

SCI3
A/D converter

Note:
*
Overrun error (SSU)
Transmit data empty (SSU)
Transmit end (SSU)
Receive data full (SSU)
Conflict error (SSU)/
The SSU and IIC share the same vector address. When using the IIC, shift the SSU to
standby mode using CKSTPR2.
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Section 3 Exception Handling
3.2
Reset
A reset has the highest exception priority.
There are three sources to generate a reset. Table 3.2 lists the reset sources.
Table 3.2
Reset Sources
Reset Source
Description
RES pin
Power-on reset circuit
Low level input
When the power supply voltage (Vcc) rises
For details, see section 19, Power-On Reset Circuit.
When the counter overflows
For details, see section 12, Watchdog Timer.
Watchdog timer
3.2.1
Reset Exception Handling
When a reset source is generated, all the processing in execution is terminated and this LSI enters
the reset state. The internal state of the CPU and the registers of the on-chip peripheral modules
are initialized by a reset.
To ensure that this LSI is reset, handle the RES pin as shown below.
• When power is supplied, or the system clock oscillator is stopped
Hold the RES pin low until oscillation of the system clock oscillator has stabilized.
• When the system clock oscillator is operating
Hold the RES pin low for the tREL state, which is specified as the electrical characteristics.
After a reset source is generated, this LSI starts reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, and the I bit in CCR is set to 1.
2. The reset exception handling vector address (H'0000 and H'0001) is read and transferred to the
PC, and then program execution starts from the address indicated by the PC.
The reset exception handling sequence by the RES pin is shown in figure 3.1.
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Section 3 Exception Handling
Reset cleared
Initial program
instruction prefetch
Vector fetch Internal
processing
RES
φ
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
Figure 3.1 Reset Exception Handling Sequence
3.2.2
Interrupt Immediately after Reset
Immediately after a reset, if an interrupt is accepted before the stack pointer (SP) is initialized, PC
and CCR will not be pushed onto the stack correctly, resulting in program runaway. To prevent
this, immediately after reset exception handling all interrupts are masked. For this reason, the
initial program instruction is always executed immediately after a reset. This instruction should
initialize the stack pointer (e.g. MOV.L #xx: 32, SP).
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Section 3 Exception Handling
3.3
Input/Output Pins
Table 3.3 shows the pin configuration of the interrupt controller.
Table 3.3
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt pin
Rising or falling edge can be selected
IRQAEC
Input
Maskable external interrupt pin
Rising, falling, or both edges can be selected
IRQ1
Input
IRQ0
Input
Maskable external interrupt pins
Rising or falling edge can be selected
3.4
Register Descriptions
The interrupt controller has the following registers.
•
•
•
•
•
Interrupt edge select register (IEGR)
Interrupt enable register 1 (IENR1)
Interrupt enable register 2 (IENR2)
Interrupt flag register 1 (IRR1)
Interrupt flag register 2 (IRR2)
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Section 3 Exception Handling
3.4.1
Interrupt Edge Select Register (IEGR)
IEGR selects whether interrupt requests of the NMI, ADTRG, IRQ1, and IRQ0 pins are generated
at the rising edge or falling edge.
Bit
Bit Name
Initial
Value
R/W
Descriptions
7
NMIEG
0
R/W
NMI Edge Select
0: Detects a falling edge of the NMI pin input
1: Detects a rising edge of the NMI pin input
6

0

Reserved
This bit is always read as 0.
5
ADTRGNEG 0
R/W
ADTRG Edge Select
0: Detects a falling edge of the ADTRG pin input
1: Detects a rising edge of the ADTRG pin input
4 to 2

All 0

Reserved
The write value should always be 0.
1
IEG1
0
R/W
IRQ1 Edge Select
0: Detects a falling edge of the IRQ1 pin input
1: Detects a rising edge of the IRQ1 pin input
0
IEG0
0
R/W
IRQ0 Edge Select
0: Detects a falling edge of the IRQ0 pin input
1: Detects a rising edge of the IRQ0 pin input
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Section 3 Exception Handling
3.4.2
Interrupt Enable Register 1 (IENR1)
IENR1 enables the RTC, IRQAEC, IRQ1, and IRQ0 interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
IENRTC
0
R/W
RTC Interrupt Request Enable
The RTC interrupt request is enabled when this bit is set
to 1.
6 to 3

All 0

Reserved
The write value should always be 0.
2
IENEC2
0
R/W
IRQAEC Interrupt Request Enable
The IRQAEC interrupt request is enabled when this bit is
set to 1.
1
IEN1
0
R/W
IRQ1 Interrupt Request Enable
The IRQ1 interrupt request is enabled when this bit is set
to 1.
0
IEN0
0
R/W
IRQ0 Interrupt Request Enable
The IRQ0 interrupt request is enabled when this bit is set
to 1.
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Section 3 Exception Handling
3.4.3
Interrupt Enable Register 2 (IENR2)
IENR2 enables the A/D converter, timer B1, and asynchronous event counter interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
The write value should always be 0.
6
IENAD
0
R/W
A/D Converter Interrupt Request Enable
The A/D converter interrupt request is enabled when this
bit is set to 1.
5 to 3

All 0

Reserved
The write value should always be 0.
2
IENTB1
0
R/W
Timer B1 Interrupt Request Enable
The timer B1 interrupt request is enabled when this bit is
set to 1.
1

0

Reserved
The write value should always be 0.
0
IENEC
0
R/W
Asynchronous Event Counter Interrupt Request Enable
The asynchronous event counter interrupt request is
enabled when this bit is set to 1.
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3.4.4
Interrupt Flag Register 1 (IRR1)
IRR1 indicates the IRQAEC, IRQ1, and IRQ0 interrupt request status.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3

All 0

Reserved
The write value should always be 0.
2
IRREC2
0
R/(W)* IRQAEC Interrupt Request Flag
[Setting condition]
When the P12 pin is set to the IRQAEC/AECPWM pin
and the specified edge is detected as the pin state
[Clearing condition]
When 0 is written to this bit
1
IRRI1
0
R/(W)* IRQ1 Interrupt Request Flag
[Setting condition]
When the IRQ1 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
0
IRRI0
0
R/(W)* IRQ0 Interrupt Request Flag
[Setting condition]
When the IRQ0 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
Note:
*
Only 0 can be written to clear the flag.
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Section 3 Exception Handling
3.4.5
Interrupt Flag Register 2 (IRR2)
IRR2 indicates the interrupt request status of the A/D converter, timer B1, and asynchronous event
counter.
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
6
IRRAD
0
R/(W)* A/D Converter Interrupt Request Flag
The write value should always be 0.
[Setting condition]
When A/D conversion ends
[Clearing condition]
When 0 is written to this bit

5 to 3
All 0

Reserved
The write value should always be 0.
2
IRRTB1
0
R/(W)* Timer B1 Interrupt Request Flag
[Setting condition]
When the timer B1 compare match or overflow occurs
[Clearing condition]
When 0 is written to this bit
1

0

0
IRREC
0
R/(W)* Asynchronous Event Counter Interrupt Request Flag
Reserved
The write value should always be 0.
[Setting condition]
When the asynchronous event counter overflows
[Clearing condition]
When 0 is written to this bit
Note:
*
Only 0 can be written to clear the flag.
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Section 3 Exception Handling
3.5
3.5.1
Interrupt Sources
External Interrupts
There are four external interrupts: NMI, IRQAEC, IRQ1, and IRQ0.
(1)
NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of
the I bit in CCR. The NMIEG bit in IEGR can be used to select whether an interrupt is requested
at a rising edge or a falling edge on the NMI pin.
(2)
IRQ1 and IRQ0 Interrupts
IRQ1 and IRQ0 interrupts are requested by input signals at IRQ1 and IRQ0 pins.
Using the IEG1 and IEG0 bits in IEGR, it is possible to select whether an interrupt is generated by
a rising or falling edge at IRQ1 and IRQ0 pins.
When the specified edge is input while the IRQ1 and IRQ0 pin functions are selected by PFCR
and PMRB, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated.
Clearing the IEN1 and IEN0 bits in IENR1 to 0 disables the interrupt request to be accepted.
Setting the I bit in CCR to 1 masks all interrupts.
(3)
IRQAEC Interrupts
An IRQAEC interrupt is requested by an input signal at the IRQAEC pin or IECPWM (PWM
output for the AEC). When the IRQAEC pin is used as an external interrupt pin, clear the
ECPWME bit in AEGSR to 0.
Using the AIEGS1 and AIEGS0 bits in AEGSR, it is possible to select whether an interrupt is
generated by a rising edge, falling edge, or both edges.
When the IENEC2 bit in IENR1 is set to 1 and the specified edge is input, the corresponding bit in
IRR1 is set to 1 and an interrupt request is generated. For details, see section 13, Asynchronous
Event Counter (AEC).
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3.5.2
Internal Interrupts
Internal interrupts generated from the on-chip peripheral modules have the following features:
• For each on-chip peripheral module, there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. Internal interrupts can be
controlled independently. If an enable bit is set to 1, an interrupt request is sent to the interrupt
controller.
3.6
Operation
NMI interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and
on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an
enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable
bits are set to 1 are controlled by the interrupt controller.
Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to
interrupt acceptance.
Interrupt operation is described as follows.
1. If an interrupt source whose interrupt enable register bit is set to 1 occurs, an interrupt request
is sent to the interrupt controller.
2. When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
3. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending (see table 3.1).
4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
5. If the interrupt request is accepted, after processing of the current instruction is completed,
both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in
figure 3.5. The PC value pushed onto the stack is the address of the first instruction to be
executed upon return from interrupt handling.
6. The I bit of CCR is set to 1, masking further interrupts.
7. The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
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Section 3 Exception Handling
Priority decision logic
Interrpt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I
CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
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Section 3 Exception Handling
Program execution state
No
NMI
Yes
No
IRRI0 = 1
Yes
No
IEN0 = 1
Yes
IRRI1 = 1
No
Yes
IEN1 = 1
Yes
No
IRREC2 = 1
No
Yes
IENEC2 = 1
Yes
No
IRRAD = 1
No
Yes
IENAD = 1
No
Yes
No
I=0
Yes
PC contents saved
CCR contents saved
I←1
Branch to interrupt handling routine
[Legend]
PC: Program counter
CCR: Condition code register
I:
I bit of CCR
Figure 3.3 Flow up to Interrupt Acceptance
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Internal
data bus
(4)
High
(3)
(6)
(5)
(8)
(7)
(10)
Vector fetch
Figure 3.4 Interrupt Exception Handling Sequence
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((11) = (10))
First instruction of interrupt handling rou
(11):
(12):
(6)(8):
(7):
Saved PC and saved CCR
SP-4
SP-2
Instruction prefetch address (Not executed.)
(10):
(5):
(3):
(12)
(11)
Vector address
(9)
Instruction prefetch
of interrupt handling
routine
(9):
Instruction prefetch address (Not executed. This is the contents of the saved PC and the return address.)
(2)
(1)
Stack
Internal
processing
(2)(4): Instruction code (Not executed.)
(1):
Internal
write signal
Internal
read signal
Internal
address
bus
Internal
processing
3.6.1
Interrupt
request
signal
φ
Interrupt accepted
Interrupt level determination
Instruction
Wait for end of instruction
prefetch
Section 3 Exception Handling
Interrupt Exception Handling Sequence
Figure 3.4 shows the interrupt exception handling sequence. The example shown is for the case
where the program area and stack area are in a 16-bit and 2-state access space.
Section 3 Exception Handling
3.7
Stack Status after Exception Handling
Figures 3.5 shows the stack after completion of interrupt exception handling.
SP – 4
SP (R7)
CCR
SP – 3
SP + 1
CCR*
SP – 2
SP + 2
PCH
SP – 1
SP + 3
PCL
SP (R7)
SP + 4
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
Even address
After completion of interrupt
exception handling
[Legend]
PCH: Upper 8 bits of program counter (PC)
PCL: Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
2. Register contents must always be saved and restored by word length, starting from
an even-numbered address.
* Ignored when returning from the interrupt handling routine.
Figure 3.5 Stack Status after Exception Handling
3.7.1
Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.4
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 23
15 to 37
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note:
*
Excluding EEPMOV instruction.
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Section 3 Exception Handling
3.8
Usage Notes
3.8.1
Notes on Stack Area Use
When word data is accessed in this LSI, the least significant bit of the address is regarded as 0.
Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never
indicate an odd address. To save register values, use PUSH.W Rn (MOV.W Rn, @–SP) or
PUSH.L ERn (MOV.L ERn, @–SP). To restore register values, use POP.W Rn (MOV.W @SP+,
Rn) or POP.L ERn (MOV.L @SP+, ERn).
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
SP →
PC H
SP →
PC L
R1L
H'FEFC
PC L
H'FEFD
SP →
H'FEFF
MOV. B R1L, @-R7
BSR instruction
SP set to H'FEFF
Stack accessed beyond SP
Contents of PC areHlost
[Legend]
PC H: Upper byte of program counter
PC L: Lower byte of program counter
R1L: General register R1L
Stack pointer
SP:
Figure 3.6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
an RTE instruction is executed, this also takes place in word size. Both the upper and lower bytes
of word data are saved to the stack; on return, the even address contents are restored to CCR while
the odd address contents are ignored.
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3.8.2
Notes on Switching Functions of External Interrupt Pins
When PFCR and PMRB are rewritten to switch the functions of external interrupt pins and when
the value of the ECPWME bit in AEGSR is rewritten to switch between selection and nonselection of IRQAEC, the following points should be observed.
When a pin function is switched by rewriting PFCR or PMRB that controls an external interrupt
pin (IRQAEC, IRQ1, or IRQ0), the interrupt request flag is set to 1 at the time the pin function is
switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to
0 after switching the pin function. When the value of the ECPWME bit in AEGSR that sets
selection or non-selection of IRQAEC is rewritten, the interrupt request flag may be set to 1, even
if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM output for the AEC).
Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function.
Figure 3.7 shows the procedure for setting a bit in PFCR and PMRB and clearing the interrupt
request flag. This procedure also applies to AEGSR setting.
When switching a pin function, mask the interrupt before setting the bit in PFCR and PMRB (or
AEGSR). After accessing PFCR and PMRB (or AEGSR), execute at least one instruction (e.g.,
NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag to 0 is
executed immediately after PFCR and PMRB (or AEGSR) access without executing an
instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level. However, the procedure in figure 3.7 is
recommended because IECPWM is an internal signal and determining its value is complicated.
I bit in CCR ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in the
interrupt enable register 1.)
Set PFCR and PMRB (or AEGSR) bit
Execute NOP instruction
After setting PFCR and PMRB
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Clear interrupt request flag to 0
I bit in CCR ← 0
Interrupt mask cleared
Figure 3.7 PFCR and PMRB (or AEGSR) Setting
and Interrupt Request Flag Clearing Procedure
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Section 3 Exception Handling
3.8.3
Method for Clearing Interrupt Request Flags
Use the recommended method given below when clearing the flags in interrupt request registers
(IRR1 and IRR2).
• Recommended method
Use a single instruction to clear flags. The bit manipulation instruction and byte-size data
transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 in
IRR1) are given below.
Example 1:
BCLR #1, @IRR1:8
Example 2:
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
• Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during
execution of the instructions, even though they are currently set, and this will cause a
malfunction.
Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1
(bit 1 in IRR1).
MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time
AND.B #B'11111101,R1L ..... Here, IRRI0 = 1
MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0
In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B
instruction is executing.
The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1,
IRRI0 is also cleared.
3.8.4
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction
such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the
interrupt concerned will still be enabled on completion of the instruction, and so interrupt
exception handling for that interrupt will be executed on completion of the instruction. When an
interrupt source flag is cleared to 0, the interrupt concerned will be ignored.
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3.8.5
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC.
When an interrupt request is generated, an interrupt is requested to the CPU. At that time, if the
CPU is executing an instruction that disables interrupts, the CPU always executes the next
instruction after the instruction execution is completed.
3.8.6
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during transfer is
not accepted until the transfer is completed.
With the EEPMOV.W instruction, even if an interrupt request other than the NMI is issued during
transfer, the interrupt is not accepted until the transfer is completed. If the NMI interrupt request is
issued, NMI exception handling starts at a break in the transfer cycle. The PC value saved on the
stack in this case is the address of the next instruction.
Therefore, if an NMI interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
3.8.7
MOV.W
R4,R4
BNE
L1
IENR Clearing
When an interrupt request is disabled by clearing the interrupt enable register or when the interrupt
flag register is cleared, the interrupt request should be masked (I bit = 1). If the above operation is
executed while the I bit is 0 and conflict between the instruction execution and the interrupt
request generation occurs, exception handling, which corresponds to the interrupt request
generated after instruction execution of the above operation is completed, is executed.
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Section 3 Exception Handling
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Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
The clock pulse generator is provided on-chip, including both a system clock pulse generator and
a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator,
system clock divider, and on-chip oscillator. The subclock pulse generator consists of a subclock
oscillator, on-chip oscillator clock divider, and subclock divider. Figure 4.1 shows a block
diagram of the clock pulse generators.
E7_2
OSC1
OSC2
System
clock
oscillator
φOSC
φOSC
(fOSC)
(fOSC)
Rosc
On-chip
oscillator (fROSC)
System clock pulse
generator
X1
X2
Subclock
oscillator
φW
System
clock
divider
φOSC
φOSC/8
φOSC/16
φOSC/32
φOSC/64
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
Rosc
On-chip
oscillator Rosc/32
clock divider
φW
φW
(fW)
(fW)
φW/2
Subclock φW/4
divider φW/8
φSUB
φW/2
φW/4
OSCCR
Prescaler W
(8 bits)
Subclock pulse generator
φW/8
to
φW/1024
[Legend]
OSCCR: Oscillator control register
Figure 4.1 Block Diagram of Clock Pulse Generators
The reference clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2. φW/4, which is
1/4th of the watch clock φW, is divided by prescaler W to become a clock signal from φW/1024 to
φW/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.
CPG0200A_000020020200
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Section 4 Clock Pulse Generators
4.1
Register Description
• Oscillator control register (OSCCR)
4.1.1
Oscillator Control Register (OSCCR)
OSCCR controls the subclock oscillator, on-chip feedback resistance, and on-chip oscillator.
Bit
Bit Name
Initial
Value
R/W
Description
7
SUBSTP
0
R/W
Subclock Oscillator Control
Controls start and stop of the subclock oscillator. When
the subclock is not used, set this bit to 1.
0: Subclock oscillator operates
1: Subclock oscillator stops
6
RFCUT
0
R/W
On-chip Feedback Resistance Control
Selects whether the on-chip feedback resistance in the
system clock oscillator is used when an external clock
is input or when the on-chip oscillator is used.
After setting this bit in the state in which an external
clock is input or the on-chip oscillator is used,
temporarily transit to standby mode, watch mode, or
subactive mode. The setting of whether the feedback
resistance in the system clock oscillator is used or not
takes effect when standby mode, watch mode, or
subactive mode is entered.
0: On-chip feedback resistance in system clock
oscillator is used
1: On-chip feedback resistance in system clock
oscillator is not used
5
SUBSEL
0
R/W
Subclock Select
Selects by which oscillator the subclock pulse
generator operates.
0: Subclock oscillator operates
1: On-chip oscillator operates
Note: The SUBSEL bit setting can be changed only
when the subclock is not being used.
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Section 4 Clock Pulse Generators
Bit
Bit Name
Initial
Value
R/W
Description
4, 3

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
2

0

1
OSCF
*
R
Reserved
The write value should always be 0.
OSC Flag
Indicates by which oscillator the system clock pulse
generator operates.
0: System clock oscillator operates
1: On-chip oscillator operates (system clock oscillator is
halted)

0
0

Reserved
The write value should always be 0.
Note:
*
The value depends on the state of the E7_2 pin. Refer to table 4.1.
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Section 4 Clock Pulse Generators
4.2
System Clock Oscillator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input.
Either the system clock oscillator or on-chip oscillator can be selected, as shown in figure 4.1. For
the selecting method, see section 4.2.4, On-Chip Oscillator Selection Method.
4.2.1
Connecting Crystal Resonator
Figure 4.2 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance
crystal resonator should be used. For notes on connecting, refer to section 4.5.2, Notes on Board
Design.
C1
OSC1
C2
OSC2
Frequency
Manufacturer
4.194304 MHz NIHON DEMPA KOGYO CO.,LTD.
Product Type
C1, C2 Recommendation Value
NR-18
12 pF ±20%
Figure 4.2 Typical Connection to Crystal Resonator
4.2.2
Connecting Ceramic Resonator
Figure 4.3 shows a typical method of connecting a ceramic resonator. For notes on connecting,
refer to section 4.5.2, Notes on Board Design.
C1
OSC1
C2
OSC2
Frequency
Manufacturer
4.19 MHz
Murata Manufacturing Co., Ltd. 15 pF (on-chip)
47 pF (on-chip)
C1, C2 Recommendation Value
Figure 4.3 Typical Connection to Ceramic Resonator
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Section 4 Clock Pulse Generators
4.2.3
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.4 shows a
typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
OSC2
External clock input
Open
Figure 4.4 Example of External Clock Input
4.2.4
On-Chip Oscillator Selection Method
The on-chip oscillator is selected by the E7_2 pin input level during a reset. The methods for
selecting the system clock oscillator and on-chip oscillator are shown in table 4.1. The input level
on the E7_2 pin during a reset is pulled up or down using a resistor according to the selected
oscillator, and fixed on exit from the reset state.
When the on-chip oscillator is selected, a resonator no longer needs to be connected to the OSC1
and OSC2 pins. In such a case, fix the OSC1 pin to GND or leave it open, and leave the OSC2 pin
open.
Notes: 1. When programming or erasing the flash memory, such as performing on-board
programming, the system clock oscillator must be selected. When the on-chip emulator
is used, even though the on-chip oscillator is selected, connect a resonator or input an
external clock.
2. When the on-chip debugger is connected, the value of the resistor should be high.
When not connected, it is specified according to the selected oscillator.
Table 4.1
Methods for Selecting System Clock Oscillator and On-Chip Oscillator
Oscillator in System Clock Pulse
E7_2 Pin Input Level (during Reset) Generator
OSCF
0
On-chip oscillator
1
1
System clock oscillator
0
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Section 4 Clock Pulse Generators
4.3
Subclock Oscillator
A subclock can be provided by connecting a crystal resonator or inputting an external clock.
Either the subclock oscillator or on-chip oscillator can be selected, as shown in figure 4.1. For the
selecting method, see section 4.3.4, On-Chip Oscillator Selection Method.
4.3.1
Connecting 32.768-kHz/38.4-kHz Crystal Resonator
Figure 4.5 shows an example of connecting a 32.768-kHz or 38.4-kHz crystal resonator. Notes
described in section 4.5.2, Notes on Board Design also apply to this connection.
C1
X1
X2
C2
Frequency
Manufacturer
38.4 kHz
EPSON TOYOCOM CORPORATION
32.768 kHz EPSON TOYOCOM CORPORATION
Products Name Equivalent Series Resistance
C-4-TYPE
30 kΩ (max.)
C-001R
35 kΩ (max.)
C 1 = C 2 = 7 pF (typ.)
Note: Consult with the crystal resonator manufacturer to determine the parameters.
Figure 4.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator
1. When the resonator other than ones listed above is used, perform matching evaluation with the
crystal resonator manufacture and connect it under the optimum condition. Even when the
resonator listed above or the equivalent is used, as the oscillation characteristics depend on the
board specification, perform matching evaluation on the mounting board.
2. Perform matching evaluation in the reset state (the RES pin is low) and on exit from the reset
state (the RES pin is driven from low to high).
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Section 4 Clock Pulse Generators
Figure 4.6 shows the equivalent circuit of the crystal resonator.
CS
LS
RS
X1
X2
CO
CO = 1.5 pF (typ.)
RS = 14 kΩ (typ.)
fW = 32.768 kHz/38.4 kHz
Figure 4.6 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator
4.3.2
Pin Connection when not Using Subclock
When the subclock is not used, connect the X1 pin to GND and leave the X2 pin open, as shown
in figure 4.7.
X1
GND
X2
Open
Figure 4.7 Pin Connection when not Using Subclock
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Section 4 Clock Pulse Generators
4.3.3
External Clock Input Method
Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.8.
X1
External clock input
X2
Open
Figure 4.8 Pin Connection when Inputting External Clock
Frequency
Watch Clock (φW)
Duty
45% to 55%
4.3.4
On-Chip Oscillator Selection Method
The on-chip oscillator is selected by the SUBSEL bit in OSCCR. When the on-chip oscillator is
selected, a resonator no longer needs to be connected to the X1 and X2 pins. In such a case, fix the
X1 pin at GND.
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Section 4 Clock Pulse Generators
4.4
Prescalers
This LSI is equipped with two on-chip prescalers (prescaler S and prescaler W), which have
different input clocks.
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs
provide internal clock signals for on-chip peripheral modules. Prescaler W is an 8-bit counter
using φW/4, which is 1/4th of the watch clock φW, as its input clock. Its prescaled outputs provide
internal clock signals for on-chip peripheral modules.
4.4.1
Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. A divided output is
used as an internal clock of an on-chip peripheral module. Prescaler S is initialized to H'0000 at a
reset, and starts counting up on exit from the reset state. In standby mode, watch mode, subactive
mode, and subsleep mode, prescaler S stops and is initialized to H'0000. The CPU cannot read
from or write to prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. In active (mediumspeed) mode and sleep (medium-speed) mode, the clock input to prescaler S is determined by the
division ratio designated by the MA1 and MA0 bits in SYSCR1.
4.4.2
Prescaler W
Prescaler W is an 8-bit counter using φW/4, which is 1/4th of the watch clock φW, as its input clock.
A divided output is used as an internal clock of an on-chip peripheral module. Prescaler W is
initialized to H'00 at a reset, and starts counting up on exit from the reset state. In standby mode,
prescaler W is halted. Even when transiting to watch mode, subactive mode, and subsleep mode,
prescaler W continues operation.
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Section 4 Clock Pulse Generators
4.5
4.5.1
Usage Notes
Note on Resonators and Resonator Circuits
Resonator characteristics are closely related to board design. Therefore, resonators should be
assigned after being carefully evaluated by the user in the masked ROM version and flash memory
version, with referring to the examples shown in this section. Resonator circuit constants will
differ depending on a resonator, stray capacitance in its mounting circuit, and other factors.
Suitable constants should be determined in consultation with the resonator manufacturer. Design
the circuit so that the oscillator pin is never applied voltages exceeding its maximum rating.
Vcc
OSC1
Vss
OSC2
RES
X2
X1
AVcc
(Vss)
Figure 4.9 Example of Crystal and Ceramic Resonator Assignment
Rev. 3.00 May 15, 2007 Page 72 of 516
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Section 4 Clock Pulse Generators
Figure 4.10 (1) shows an example measuring circuit with the negative resistance recommended by
the resonator manufacturer. Note that if the negative resistance of the circuit is less than that
recommended by the resonator manufacturer, it may be difficult to start the main oscillator.
If it is determined that oscillation does not occur because the negative resistance is lower than the
level recommended by the resonator manufacturer, the circuit must be modified as shown in figure
4.10 (2) through (4). Which of the modification suggestions to use and the capacitor capacitance
should be decided based upon evaluation results such as the negative resistance and the frequency
deviation.
Modification
point
OSC1
OSC1
C1
C1
OSC2
OSC2
C2
C2
Negative resistance,
addition of -R
(1) Negative Resistance Measuring Circuit
(2) Oscillator Circuit Modification Suggestion 1
Modification
point
Modification
point
C3
OSC1
C1
C2
OSC1
C1
OSC2
OSC2
(3) Oscillator Circuit Modification Suggestion 2
C2
(4) Oscillator Circuit Modification Suggestion 3
Figure 4.10 Negative Resistance Measurement and Circuit Modification Suggestions
Rev. 3.00 May 15, 2007 Page 73 of 518
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Section 4 Clock Pulse Generators
4.5.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the
resonator circuit to prevent induction from interfering with correct oscillation (see figure 4.11).
Avoid
Signal A
Signal B
C1
OSC1
C2
OSC2
Figure 4.11 Example of Incorrect Board Design
Note: When a crystal resonator or ceramic resonator is connected, consult with the crystal
resonator and ceramic resonator manufacturers to determine the circuit constants because
the constants differ according to the resonator, stray capacitance of the mounting circuit,
and so on.
4.5.3
Definition of Oscillation Stabilization Wait Time
Figure 4.12 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an resonator connected to the system clock
oscillator.
As shown in figure 4.12, when a transition is made to active (high-speed/medium-speed) mode,
from standby mode, watch mode, or subactive mode, in which the system clock oscillator is
halted, the sum of the following two times (oscillation start time and wait time) is required.
(1)
Oscillation Start Time
The time from the point at which the system clock oscillator oscillation waveform starts to change
when an interrupt is generated, until the system clock starts to be generated.
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Section 4 Clock Pulse Generators
(2)
Wait Time
After the system clock is generated, the time required for the amplitude of the oscillation
waveform to increase, the oscillation frequency to stabilize, and the CPU and peripheral functions
to begin operating.
Oscillation waveform
(OSC2)
System clock (φ)
Oscillation
start time
Wait time
Operating mode
Standby mode,
watch mode,
or subactive
mode
Oscillation stabilization wait time
Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 4.12 Oscillation Stabilization Wait Time
As the oscillation stabilization wait time required is the same as the oscillation stabilization time
(trc) at power-on, specified in the AC characteristics, set the STS2 to STS0 bits in SYSCR1 to
specify the time longer than the oscillation stabilization time (trc).
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an resonator connected to the system clock
oscillator, careful evaluation must be carried out on the mounting circuit before deciding the
oscillation stabilization wait time. For the wait time, secure the time required for the amplitude of
the oscillation waveform to increase and the oscillation frequency to stabilize. In addition, since
the oscillation start time differs according to mounting circuit constants, stray capacitance, and so
forth, suitable constants should be determined in consultation with the resonator manufacturer.
Rev. 3.00 May 15, 2007 Page 75 of 518
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Section 4 Clock Pulse Generators
4.5.4
Note on Subclock Stop State
To stop the subclock, a state transition should not be made except to mode in which the system
clock operates. If the state transition is made to other mode, it may result in incorrect operation.
4.5.5
Note on the Oscillation Stabilization of Resonators
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual resonator characteristics, the
oscillation waveform amplitude may not be sufficiently large immediately after the oscillation
stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in
the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an
unstable system clock and incorrect operation of the microcomputer.
If incorrect operation occurs, change the setting of the standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in the system control register 1 (SYSCR1)) to give a longer wait time.
For example, if incorrect operation occurs with a wait time setting of 512 states, check the
operation with a wait time setting of 1,024 states or more.
If the same kind of incorrect operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
4.5.6
Note on Using Power-On Reset
The power-on reset circuit in this LSI adjusts the reset clear time by the capacitor capacitance,
which is externally connected to the RES pin. The external capacitor capacitance should be
adjusted to secure the oscillation stabilization time before reset clearing. For details, refer to
section 19, Power-On Reset Circuit.
4.5.7
Note on Using On-Chip Emulator
When the on-chip emulator is used, system clock accuracy is necessary for flash memory
programming/erasing. The frequency of the on-chip oscillator differs depending on the voltage
and temperature conditions. Therefore, when using the on-chip emulator, the resonator must be
connected to the OSC1 and OSC2 pins or an external clock must be supplied. In this case, the onchip oscillator is used for user program execution, and the system clock is used for flash memory
programming/erasing. This control is handled when the E7_2 pin is fixed to high level during a
reset by the on-chip emulator.
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Section 5 Power-Down Modes
Section 5 Power-Down Modes
This LSI has eight modes of operation after a reset. These include a normal active (high-speed)
mode and seven power-down modes, in which power consumption is significantly reduced. The
module standby function reduces power consumption by selectively halting on-chip module
functions.
• Active (medium-speed) mode
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φOSC/8, φOSC/16, φOSC/32, and φOSC/64.
• Subactive mode
The CPU and all on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φW, φW/2, φW/4, and φW/8.
• Sleep (high-speed) mode
The CPU halts. On-chip peripheral modules are operable on the system clock.
• Sleep (medium-speed) mode
The CPU halts. On-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φOSC/8, φOSC/16, φOSC/32, and φOSC/64.
• Subsleep mode
The CPU halts. The on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φW, φW/2, φW/4, and φW/8.
• Watch mode
The CPU halts. The on-chip peripheral modules are operable on the subclock.
• Standby mode
The CPU and all on-chip peripheral modules halt.
• Module standby function
Independent of the above modes, power consumption can be reduced by halting on-chip
peripheral modules that are not used in module units.
Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively
called active mode.
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Section 5 Power-Down Modes
5.1
Register Descriptions
The registers related to power-down modes are as follows.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2)
5.1.1
System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit
Bit Name
Initial
Value
R/W
Description
7
SSBY
0
R/W
Software Standby
Selects the mode to transit after the execution of the
SLEEP instruction.
0: A transition is made to sleep mode or subsleep
mode.
1: A transition is made to standby mode or watch mode.
For details, see table 5.2.
6
STS2
0
R/W
Standby Timer Select 2 to 0
5
STS1
0
R/W
4
STS0
0
R/W
Designate the time the CPU and peripheral modules
wait for stable clock operation after exiting from standby
mode, subactive mode, or watch mode to active mode
or sleep mode due to an interrupt. The designation
should be made according to the operating frequency
so that the waiting time is at least equal to the
oscillation stabilization time. The relationship between
the specified value and the number of wait states is
shown in table 5.1.
When an external clock is to be used, the minimum
value (STS2 = 1, STS1 = 1, and STS0 = 1) is
recommended. When the on-chip oscillator is to be
used, the minimum value (STS2 = 1, STS1 = 1, and
STS0 = 1) is recommended. If a setting other than the
recommended value is made, operation may start
before the end of the waiting time.
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Section 5 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
3
LSON
0
R/W
Selects the system clock (φ) or subclock (φSUB) as the
CPU operating clock when watch mode is cleared.
0: The CPU operates on the system clock (φ)
1: The CPU operates on the subclock (φSUB)
2
TMA3
0
R/W
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY and
LSON in SYSCR1 and bits DTON and MSON in
SYSCR2. For details, see table 5.2.
1
MA1
1
R/W
Active Mode Clock Select 1 and 0
0
MA0
1
R/W
Select the operating clock frequency in active (mediumspeed) mode and sleep (medium-speed) mode. The
MA1 and MA0 bits should be written to in active (highspeed) mode or subactive mode.
00: φOSC/8
01: φOSC/16
10: φOSC/32
11: φOSC/64
Table 5.1
Operating Frequency and Waiting Time
Bit
STS2
0
STS1
0
1
1
0
1
Operating Frequency and Waiting Time
STS0
0
Waiting States
8,192 states
10 MHz
819.2
8 MHz
6 MHz
1
1,024.0*
1
1,365.3*
5 MHz
4.194MHz 3 MHz
1,638.4
1953.3
2 MHz
2,730.7
4,096.0
1
16,384 states
1,638.4
2,048.0
2,730.7
3,276.8
3906.5
5,461.3*
8,192.0*1
0
1,024 states
102.4
128.0
170.7
204.8
244.2
341.3
512.0
1
2,048 states
204.8
256.0
341.3
488.3
682.7
1,024.0
409.6
1
1
1
0
4,096 states
409.6
512.0
682.7*
819.2*
976.6
1,365.3
2,048.0
1
256 states
25.6
32.0
42.7*2
51.2*2
61.0
85.3*2
128.0*2
2
2
0
512 states
51.2
64.0*
85.3*
102.4
122.1
170.7
256.0
1
16 states
1.6
2.0
2.7
3.2
3.8
5.3
8.0
Notes: Time unit is µs.
: Recommended value when crystal resonator is used (Vcc = 2.7 V to 3.6 V)
: Recommended value when ceramic resonator is used (Vcc = 2.2 V to 3.6 V)
1. Reference value when crystal resonator is used
2. Reference value when ceramic resonator is used
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Section 5 Power-Down Modes
5.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
4
NESEL
1
R/W
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φW) and the system clock pulse generator
generates the oscillator clock (φOSC). This bit selects the
sampling frequency of φOSC when φW is sampled. When a
system clock is used, clear this bit to 0.When the onchip oscillator is selected, set this bit to 1.
0: Sampling rate is φOSC/16.
1: Sampling rate is φOSC/4.
3
DTON
0
R/W
Direct Transfer on Flag
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY,
TMA3, and LSON in SYSCR1 and bit MSON in
SYSCR2. For details, see table 5.2.
2
MSON
0
R/W
Medium Speed on Flag
After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed)
mode.
0: Operation in active (high-speed) mode
1: Operation in active (medium-speed) mode
1
SA1
0
R/W
Subactive Mode Clock Select 1 and 0
0
SA0
0
R/W
Select the operating clock frequency in subactive and
subsleep modes. The operating clock frequency
changes to the set frequency after the SLEEP
instruction is executed.
00: φW/8
01: φW/4
10: φW/2
11: φW
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Section 5 Power-Down Modes
5.1.3
Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2)
CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter the standby state in
module units.
• CKSTPR1
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
This bit is always read as 0 and cannot be modified.
6
S3CKSTP
0
R/W
SCI3 Module Standby*1
SCI3 enters standby mode when this bit is cleared to 0.
5

0

Reserved
4
ADCKSTP
0
R/W
A/D Converter Module Standby
This bit is always read as 0 and cannot be modified.
A/D converter enters standby mode when this bit is
cleared to 0.
3

0

Reserved
2
TB1CKSTP
0
R/W
Timer B1 Module Standby
This bit is always read as 0 and cannot be modified.
Timer B1 enters standby mode when this bit is cleared
to 0.
1
2
FROMCKSTP*
1
R/W
Flash Memory Module Standby
Flash memory enters standby mode when this bit is
cleared to 0.
0
RTCCKSTP
1
R/W
RTC Module Standby
RTC enters standby mode when this bit is cleared to 0.
Rev. 3.00 May 15, 2007 Page 81 of 516
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Section 5 Power-Down Modes
• CKSTPR2
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
6
TWCKSTP
0
R/W
Timer W Module Standby
This bit is always read as 0 and cannot be modified.
Timer W enters standby mode when this bit is cleared
to 0.
5
IICCKSTP
0
R/W
IIC2 Module Standby
The IIC2 enters standby mode when this bit is cleared
to 0.
4
SSUCKSTP
0
R/W
SSU Module Standby
The SSU enters standby mode when this bit is cleared
to 0.
3
AECCKSTP
0
R/W
Asynchronous Event Counter Module Standby
The asynchronous event counter enters standby mode
when this bit is cleared to 0.
2
WDCKSTP
1
R/W*3
Watchdog Timer Module Standby
The watchdog timer enters standby mode when this bit
is cleared to 0.
1
COMPCKSTP
0
R/W
Comparator Module Standby
The comparators enter standby mode when this bit is
cleared to 0.
0

0

Reserved
This bit is always read as 0 and cannot be modified.
Notes: 1. When the SCI3 module standby is set, all registers in the SCI3 enter the reset state.
2. When using the on-chip emulator, set this bit to 1.
3. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the
WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0.
However, the watchdog timer does not enter module standby mode and continues
operating. When the WDON bit is cleared to 0 by software, this bit is valid and the
watchdog timer enters module standby mode.
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Section 5 Power-Down Modes
5.2
Mode Transitions and States of LSI
Figure 5.1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state of the program by executing a SLEEP
instruction. Interrupts allow for returning from the program halt state to the program execution
state of the program. A direct transition between active mode and subactive mode, which are both
program execution states, can be made without halting the program. The operating frequency can
also be changed in the same modes by making a transition directly from active mode to active
mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to
the reset state. Table 5.2 shows the transition conditions of each mode after the SLEEP instruction
is executed and a mode to return by an interrupt. Table 5.3 shows the internal states of the LSI in
each mode.
Rev. 3.00 May 15, 2007 Page 83 of 516
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Section 5 Power-Down Modes
Program
execution state
Reset state
Program
halt state
SLEEP d
instruction
Standby
mode
Active
(high-speed
mode)
instruction
a
EP ion
E
t
SL truc
s
in
g
P n
EE tio
SL truc
s
in
f
SLEEP
SLEEP instruction
instruction
4
1
S
ins LE
tru EP
cti
on
1
e
SLEEP
instruction
3
Sleep
(medium-speed)
mode
h
SLEEP
instruction
i1
SLEEP
instruction
SLEEP
instruction
i2
SLEEP
c
instruction
2
Subactive
mode
1
: Transition is made after exception handling
is executed.
Mode Transition Conditions (1)
LSON
b
j
SLEEP
instruction
e
Watch
mode
SLEEP b
instruction
Active
(medium-speed)
mode
e
SLEEP
instruction
Sleep
(high-speed)
mode
3
4
d SLEEP
Program
halt state
SLEEP
instruction a
Subsleep
mode
Power-down modes
Mode Transition Conditions (2)
Interrupt Sources
MSON SSBY TMA3 DTON
a
b
c
d
e
0
0
1
0
x
0
1
x
x
x
0
0
0
1
1
x
x
1
0
1
0
0
0
0
0
f
g
0
0
0
1
0
0
x
x
1
1
h
i1
i2
j
0
1
1
0
1
x
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
4
NMI, IRQ0, IRQ1, IRQAEC, COMP, RTC, WDT,
AEC, and timer B1
All interrupts except IIC2
All interrupts
NMI, IRQ0, IRQ1, IRQAEC, COMP, WDT, and
AEC
x: Don't care
Note: A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupt handling is accepted.
Figure 5.1 Mode Transition Diagram
Rev. 3.00 May 15, 2007 Page 84 of 516
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Section 5 Power-Down Modes
Table 5.2
Active (highspeed) mode
Active
(mediumspeed) mode
Subactive
mode
[Legend]
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
LSON
MSON SSBY
TMA3
DTON
Transition Mode after SLEEP
Instruction Execution
Transition Mode due to
Interrupt
0
0
0
x
0
Sleep (high-speed) mode
Active (high-speed) mode
0
1
0
x
0
Sleep (medium-speed) mode
Active (medium-speed) mode
0
0
1
0
0
Standby mode
Active (high-speed) mode
0
1
1
0
0
Standby mode
Active (medium-speed) mode
0
0
1
1
0
Watch mode
Active (high-speed) mode
0
1
1
1
0
Watch mode
Active (medium-speed) mode
1
x
1
1
0
Watch mode
Subactive mode
0
0
0
x
1
Active (high-speed) mode (direct
transition)

0
1
0
x
1
Active (medium-speed) mode
(direct transition)


1
x
1
1
1
Subactive mode (direct transition)
0
0
0
x
0
Sleep (high-speed) mode
Active (high-speed) mode
0
1
0
x
0
Sleep (medium-speed) mode
Active (medium-speed) mode
0
0
1
0
0
Standby mode
Active (high-speed) mode
0
1
1
0
0
Standby mode
Active (medium-speed) mode
0
0
1
1
0
Watch mode
Active (high-speed) mode
0
1
1
1
0
Watch mode
Active (medium-speed) mode
1
1
1
1
0
Watch mode
Subactive mode
0
0
0
x
1
Active (high-speed) mode (direct
transition)

0
1
0
x
1
Active (medium-speed) mode
(direct transition)

1
1
1
1
1
Subactive mode (direct transition)

1
x
0
1
0
Subsleep mode
Subactive mode
0
0
1
1
0
Watch mode
Active (high-speed) mode
0
1
1
1
0
Watch mode
Active (medium-speed) mode
1
x
1
1
0
Watch mode
Subactive mode
0
0
1
1
1
Active (high-speed) mode (direct
transition)

0
1
1
1
1
Active (medium-speed) mode
(direct transition)

1
x
1
1
1
Subactive mode (direct transition)

x: Don’t care.
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Section 5 Power-Down Modes
Table 5.3
Internal State in Each Operating Mode
Active Mode
Sleep Mode
High-
Medium-
High-
Medium-
Watch
Subactive Subsleep
Standby
Function
speed
speed
speed
speed
Mode
Mode
Mode
Mode
System clock oscillator
Functions
Functions
Functions
Functions
Halted
Halted
Halted
Halted
Functions
Functions
Subclock oscillator
CPU
Instructions
Functions/ Functions/ Functions/
Functions/ Functions
Halted
Halted
Halted
Halted
Functions
Functions
Halted
Halted
Halted
Retained
Retained
Retained
RAM
Functions/
Halted
Functions
Halted
Halted
Retained
Retained
Registers
Retained*1
I/O
External
interrupts
NMI
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions/ Retained
IRQ0
IRQ1
IRQAEC
Peripheral Timer B1
modules
Timer W
Functions/
Functions/
Retained*2
Retained*2 Retained*2
Retained
Functions/
Functions/ Retained
Retained*3 Retained*3
WDT
RTC
Asynchro-
Functions/
Functions/
Retained*5
Retained*5 Retained*5 Retained*4
Functions/ Functions/
Functions/
Functions/
Retained*6
Retained*6 Retained*6
Functions
Functions
Functions
Functions/
Functions/ Reset
Functions/ Retained
Functions
nous event
counter
SCI3/
Reset
Retained*7 Retained*7
IrDA
IIC2
Retained
Retained
Retained
Retained
SSU
Retained
Functions/
Functions/ Retained
Retained*8 Retained*8
A/D
Retained
Functions/
Functions/ Retained
Retained*9 Retained*9
Comparator
Functions
Functions
Functions
Functions
Notes: 1. Register contents are retained. Output is the high-impedance state.
2. Functions if φW/256 or φW/1024 is selected as an internal clock. Halted and retained
otherwise.
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Section 5 Power-Down Modes
3. Functions if φW, φW/4, or φW/16 is selected as an internal clock. Halted and retained
otherwise.
4. Functions if the on-chip oscillator is selected. Halted and retained otherwise.
5. Functions if the on-chip oscillator is selected or if φW/16 or φW/256 is selected as an
internal clock. Halted and retained otherwise.
6. Functions if the 32.768-kHz RTC is selected as an internal clock. Halted and retained
otherwise.
7. Functions if φW is selected as an internal clock. Halted and retained otherwise.
8. Functions if φSUB/2 is selected as an internal clock. Halted and retained otherwise.
9. Functions if φW/2 is selected as an internal clock. Halted and retained otherwise.
5.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and
on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral
modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register
contents are retained.
Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and
interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the
requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition
is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed)
mode to active (medium-speed) mode.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an
interrupt request signal is synchronous with the system clock, the maximum time of 2/φ (s) may be
delayed from the point at which an interrupt request signal occurs until the interrupt exception
handling is started.
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Section 5 Power-Down Modes
5.2.2
Standby Mode
In standby mode, the system clock oscillator stops, and the CPU and on-chip peripheral modules
stop functioning except for the WDT, asynchronous event counter, and comparators. However, as
long as the rated voltage is supplied, the contents of CPU registers and some on-chip peripheral
module registers are retained. On-chip RAM contents will be retained as long as the voltage set by
the RAM data retention voltage is provided. The I/O ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is
cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made
to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2.
Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by
the interrupt enable bit.
When a reset source is generated in standby mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
5.2.3
Watch Mode
In watch mode, the system clock oscillator and CPU operation stop, and on-chip peripheral
modules stop functioning except for the WDT, RTC, timer B1, asynchronous event counter, and
comparators. However, as long as the rated voltage is supplied, the contents of CPU registers,
some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain
their state before the transition.
Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and
interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is
made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on
the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is
made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt
exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When a reset source is generated in watch mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
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Section 5 Power-Down Modes
5.2.4
Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules function except for the
IIC2. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM,
and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states
as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to
subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When a reset source is generated in subsleep mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
5.2.5
Subactive Mode
In subactive mode, the system clock oscillator stops but on-chip peripheral modules function
except for the IIC2. As long as a required voltage is applied, the contents of some registers of the
on-chip peripheral modules are retained.
Subactive mode is cleared by the SLEEP instruction. When subactive mode is cleared, a transition
to subsleep mode, active mode, or watch mode is made, depending on the combination of bits
SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2.
When a reset source is generated in subactive mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
The operating frequency of subactive mode is selected from φW (watch clock), φW/2, φW/4, and φW/8
by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating
frequency changes to the frequency which is set before the execution.
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Section 5 Power-Down Modes
5.2.6
Active (Medium-Speed) Mode
In active (medium-speed) mode, the clock set by the MA1 and MA0 bits in SYSCR1 is used as the
system clock, and the CPU and on-chip peripheral modules function.
Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed)
mode is cleared, a transition to standby mode is made depending on the combination of bits
SSBY, LSON, and TMA3 in SYSCR1, a transition to watch mode is made depending on the
combination of bits SSBY and TMA3 in SYSCR1, or a transition to sleep mode is made
depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to
active (high-speed) mode or subactive mode is made by a direct transition. When the RES pin
goes low, the CPU goes into the reset state and active (medium-sleep) mode is cleared.
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Section 5 Power-Down Modes
5.3
Direct Transition
The CPU can execute programs in two modes: active and subactive modes. A direct transition is
made between these two modes without stopping program execution. A direct transition can also
be made when the operating clock is changed in active and subactive modes. The transition is
made via the sleep or watch mode, by setting the DTON bit in SYSCR2 to 1 to execute a SLEEP
instruction. After the mode transition, direct transition interrupt exception handling starts.
Note that if a direct transition is attempted while the I bit in CCR is 1, the transition is made to the
sleep or watch mode, though not returning from the mode.
5.3.1
Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON
bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are set to 1, a
transition is made to active (medium-speed) mode via sleep mode.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (1).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tcyc before transition) + (Number of interrupt
exception handling execution states) × (tcyc after transition)…………(1)
Example:
When φosc/8 is selected as the CPU operating clock after the transition
Direct transition time = (2 + 1) × 1tosc + 14 × 8tosc = 115tosc
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
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Section 5 Power-Down Modes
5.3.2
Direct Transition from Active (High-Speed) Mode to Subactive Mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3, and
LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made
to subactive mode via watch mode.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (2).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tcyc before transition) + (Number of interrupt
exception handling execution states) × (tsubcyc after transition)…..…(2)
Example:
When φw/8 is selected as the subactive operating clock after the transition
Direct transition time = (2 + 1) × 1tosc + 14 × 8tw = 3tosc + 112tw
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
5.3.3
Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (3).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tcyc before transition) + (Number of interrupt
exception handling execution states) × (tcyc after transition)………..(3)
Example:
When φosc/8 is selected as the CPU operating clock before the transition
Direct transition time = (2 + 1) × 8tosc + 14 × 1tosc = 38tosc
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
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Section 5 Power-Down Modes
5.3.4
Direct Transition from Active (Medium-Speed) Mode to Subactive Mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, LSON,
and TMA3 bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is
made to subactive mode via watch mode.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (4).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tcyc before transition) + (Number of interrupt
exception handling execution states) × (tsubcyc after transition)……(4)
Example:
When φosc/8 and φw/8 are selected as the CPU operating clock before and after
the transition, respectively
Direct transition time = (2 + 1) × 8tosc + 14 × 8tw = 24tosc + 112tw
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
5.3.5
Direct Transition from Subactive Mode to Active (High-Speed) Mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in
SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is
cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (highspeed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has
elapsed.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (5).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tsubcyc before transition) + (Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states) × (tcyc after transition)………………………………………..(5)
Example:
When φw/8 is selected as the CPU operating clock after the transition and wait
time = 8192 states
Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 1tosc = 24tw + 8206tosc
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
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Section 5 Power-Down Modes
5.3.6
Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in
SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in
SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode
after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (6).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tsubcyc before transition) + (Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states) × (tcyc after transition)……………………….………………..(6)
Example:
When φw/8 and φosc/8 are selected as the CPU operating clock before and after
the transition, respectively, and wait time = 8192 states
Direct transition time = (2 + 1) × 8tw + 8192 × 1tosc + 14 × 8tosc = 24tw + 8304tosc
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
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Section 5 Power-Down Modes
5.3.7
Notes on External Input Signal Changes before/after Direct Transition
• Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External
Input Signal Changes before/after Standby Mode.
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Section 5 Power-Down Modes
5.4
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the
clock supply to modules stops to enter the power-down mode. Module standby mode enables each
on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each
module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section
5.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).)
5.5
On-Chip Oscillator and Operation Mode
The on-chip oscillator can be used as the clock source for the watchdog timer (WDT), subclock
generation circuit (φW = ROSC/32), and system clock generation circuit (φOSC = ROSC).
When the on-chip oscillator is used as the clock source for the watchdog timer (WDT), it operates
in any modes, such as active, sleep, subactive, subsleep, watch, and standby modes.
When the on-chip oscillator is used as the clock source for the subclock generation circuit, it stops
in standby mode and operates in other modes.
When the on-chip oscillator is used only as the clock source for the system clock generation
circuit, it operates in active and sleep modes but halts the operation in subactive, subsleep, watch,
and standby modes.
When the on-chip oscillator is not used as the clock source for the watchdog timer (WDT),
subclock generation circuit, or system clock generation circuit, it halts the operation.
The on-chip oscillator operates at a reset and after a reset, because the watchdog timer (WDT)
selects the on-chip oscillator as the clock source for the initial value.
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Section 5 Power-Down Modes
5.6
Usage Notes
5.6.1
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while the SSBY and TMA3 bits in SYSCR1 and the LSON bit in SYSCR1 are cleared to 0,
a transition is made to standby mode. At the same time, pins go to the high-impedance state
(except pins for which the pull-up MOS is designated as on). Figure 5.2 shows the timing in this
case.
φ
Internal data bus
SLEEP instruction fetch
Next instruction fetch
SLEEP instruction execution
Pins
Internal
processing
Port output
High-impedance
Active (high-speed) mode or active (medium-speed) mode
Standby mode
Figure 5.2 Standby Mode Transition and Pin States
5.6.2
(1)
Notes on External Input Signal Changes before/after Standby Mode
When External Input Signal Changes before/after Standby Mode or Watch Mode
When an external input signal such as NMI, IRQ0, IRQ1, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB
(referred to together in this section as the internal clock). As the internal clock stops in standby
mode and watch mode, the width of external input signals requires careful attention when a
transition is made via these operating modes. Ensure that external input signals conform to the
conditions stated in (3), Recommended Timing of External Input Signals, below.
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Section 5 Power-Down Modes
(2)
When External Input Signals cannot be Captured because Internal Clock Stops
The case of falling edge capture is shown in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active mode or subactive mode, after oscillation is started by an
interrupt via a different signal, the external input signal cannot be captured if the high-level width
at that point is less than 2 tcyc or 2 tsubcyc.
(3)
Recommended Timing of External Input Signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of at
least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as
shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case 2"
and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
Active (high-speed, medium-speed)
mode or subactive mode
Operating mode
tcyc
tsubcyc
tcyc
tsubcyc
Standby mode or
watch mode
Wait for oscillation
stabilization
Active (high-speed, medium-speed)
mode or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
φ or φSUB
External input signal
Capture possible: case 1
Capture possible: case 2
Capture possible: case 3
Capture not possible
Interrupt by different signal
Figure 5.3 External Input Signal Capture when Signal Changes
before/after Standby Mode or Watch Mode
(4)
Input Pins to which these Notes Apply
NMI, IRQ0, IRQ1, IRQAEC, and ADTRG
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Section 6 ROM
Section 6 ROM
The features of the 16-Kbyte flash memory built into the flash memory (F-ZTAT) version are
summarized below.
• Programming/erasing methods
The flash memory is programmed 128 bytes at a time. Erasure is performed in single-block
units. The flash memory is configured as follows: 1 Kbyte × 4 blocks and 12 Kbytes × 1 block.
To erase the entire flash memory, each block must be erased in turn.
• On-board programming
On-board programming/erasure can be done in boot mode, in which the boot program built
into this LSI is started to erase or program of the entire flash memory. In normal user program
mode, individual blocks can be erased or programmed.
• Automatic bit rate adjustment
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the
transfer bit rate of the host.
• Programming/erasing protection
Sets software protection against flash memory programming/erasure.
• Power-down mode
Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash
memory can be read with low power consumption.
• Module standby mode
Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.) However, when
using the on-chip emulator debugger, set the FROMCKSTP bit in clock halt register 1 to 1.
Note: The system clock oscillator must be used when programming or erasing the flash memory.
ROM3560A_000120030300
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Section 6 ROM
6.1
Block Configuration
Figure 6.1 shows the block configuration of flash memory. The thick lines indicate erasing a
block, the narrow lines indicate programming units, and the values are addresses. The 16-Kbyte
flash memory is divided into 1 Kbyte × 4 blocks and 12 Kbytes × 1 block. Erasure is performed in
these units. Programming is performed in 128-byte units starting from an address with lower eight
bits H'00 or H'80.
Erasing unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'00FF
H'0380
H'0381
H'0382
H'03FF
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'0780
H'0781
H'0782
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'3F80
H'3F81
H'3F82
H'3FFF
Programming unit: 128 bytes
H'007F
1 Kbyte
Erasing unit
Programming unit: 128 bytes
H'047F
H'04FF
1 Kbyte
Erasing unit
H'07FF
Programming unit: 128 bytes
H'087F
H'08FF
1 Kbyte
Erasing unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 Kbyte
Erasing unit
H'0FFF
Programming unit: 128 bytes
H'107F
12 Kbytes
Figure 6.1 Flash Memory Block Configuration
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Section 6 ROM
6.2
Register Descriptions
The flash memory has the following registers.
•
•
•
•
•
Flash memory control register 1 (FLMCR1)
Flash memory control register 2 (FLMCR2)
Erase block register 1 (EBR1)
Flash memory power control register (FLPWCR)
Flash memory enable register (FENR)
6.2.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory enter the programming mode, programmingverifying mode, erasing mode, or erasing-verifying mode. For details on register setting, refer to
section 6.4, Flash Memory Programming/Erasure.
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
This bit is always read as 0.
6
SWE
0
R/W
Software Write Enable
When this bit is set to 1, flash memory
programming/erasure is enabled. When this bit is cleared
to 0, other FLMCR1 register bits and all EBR1 bits cannot
be set.
5
ESU
0
R/W
Erase Setup
When this bit is set to 1, the flash memory enters to the
erasure setup state. When it is cleared to 0, the erasure
setup state is released. Set this bit to 1 before setting the
E bit in FLMCR1 to 1.
4
PSU
0
R/W
Program Setup
When this bit is set to 1, the flash memory enters to the
programming setup state. When it is cleared to 0, the
programming setup state is released. Set this bit to 1
before setting the P bit in FLMCR1 to 1.
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Section 6 ROM
Bit
Bit Name
Initial
Value
R/W
Description
3
EV
0
R/W
Erase-Verify
When this bit is set to 1, the flash memory enters to
erasing-verifying mode. When it is cleared to 0, erasingverifying mode is released.
2
PV
0
R/W
Program-Verify
When this bit is set to 1, the flash memory enters the
programming-verifying mode. When it is cleared to 0,
programming-verifying mode is released.
1
E
0
R/W
Erase
When this bit is set to 1 while SWE=1 and ESU=1, the
flash memory enters the erasing mode. When it is cleared
to 0, the erasing mode is released.
0
P
0
R/W
Program
When this bit is set to 1 while SWE=1 and PSU=1, the
flash memory enters the programming mode. When it is
cleared to 0, the programming mode is released.
6.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that indicates the state of flash memory programming/erasure. FLMCR2 is a
read-only register, and should not be written to.
Bit
Bit Name
Initial
Value
R/W
7
FLER
0
R
Description
Flash Memory Error
Indicates that an error has occurred during programming
or erasing flash memory. When this bit is set to 1, flash
memory enters the error-protection state.
See section 6.5.3, Error Protection, for details.
6 to 0

All 0

Reserved
These bits are always read as 0.
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6.2.3
Erase Block Register 1 (EBR1)
EBR1 specifies the erase block of flash memory. EBR1 is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be
automatically cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 0

4
EB4
0
R/W
3
EB3
0
R/W
Reserved
Although these bits are readable/writable, only 0 should
be written to.
When this bit is set to 1, a12-Kbyte area of H'1000 to
H'3FFF will be erased.
When this bit is set to 1, a 1-Kbyte area of H'0C00 to
H'0FFF will be erased.
2
EB2
0
R/W
1
EB1
0
R/W
0
EB0
0
R/W
6.2.4
Flash Memory Power Control Register (FLPWCR)
When this bit is set to 1, a 1-Kbyte area of H'0800 to
H'0BFF will be erased.
When this bit is set to 1, a 1-Kbyte area of H'0400 to
H'07FF will be erased.
When this bit is set to 1, a 1-Kbyte area of H'0000 to
H'03FF will be erased.
FLPWCR enables or disables a transition to the flash memory power-down mode when this LSI
enters the subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PDWND
0
R/W
6 to 0

All 0

Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to subactive
mode.
Reserved
These bits are always read as 0.
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Section 6 ROM
6.2.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit
Bit Name
Initial
Value
R/W
Description
7
FLSHE
0
R/W
Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
6 to 0

All 0

Reserved
These bits are always read as 0.
6.3
On-Board Programming Modes
The available mode for programming/erasing of the flash memory is boot mode, which enables
on-board programming/erasure. On-board programming/erasure can also be performed in user
program mode. When this LSI starts after releasing the reset state, it enters a mode depending on
the signal levels on the TEST, NMI , and E7_0 pins, as shown in table 6.1. The input level of each
pin must be stable four states before the reset ends.
When entering the boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for initializing flash memory mounted on the user board or for a forcible
recovery if flash memory cannot be programmed or erased in user program mode. In user program
mode, individual blocks can be erased and programmed by branching to the user
programming/erasing control program prepared by the user.
Table 6.1
Setting Programming Modes
TEST
NMI
E7_0
LSI State after Reset Released
0
1
x
User Mode
0
0
1
Boot Mode
[Legend]
x: Don’t care.
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Section 6 ROM
6.3.1
Boot Mode
Table 6.2 shows the boot mode operations between a reset released and a branch to the
programming control program.
This LSI includes a system clock oscillator which is operated by a resonator or an external clock
and on-chip oscillator.
In Boot Mode, since the system clock oscillator is selected, connect a resonator to OSC1 and
OSC2, or an external clock signal to OSC1.
1. When the boot mode is used, the flash memory programming control program must be
prepared in the host beforehand. Prepare a programming control program in accordance with
the description in section 6.4, Flash Memory Programming/Erasure.
2. SCI3 is set to the asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit,
and no parity. The inversion function of the TXD and RXD pins by SPCR is set to “Not to be
inverted,” so do not put inverters between the host and this LSI.
3. When the boot program is initiated, this LSI measures the low-level period of serial
communication data (H'00) continuously transmitted in asynchronous mode from the host.
This LSI then calculates the bit rate of the transfer from the host, and adjusts the SCI3 bit rate
to match that of the host. The reset signal should be negated while the RXD pin is driven high.
The RXD and TXD pins should be pulled up on the board if necessary. After the reset signal is
negated, it takes approximately 100 states before this LSI is ready to measure the low-level
period.
4. After matching the bit rates, SCI3 transmits one byte of H'00 to the host to indicate the
completion of bit rate adjustment. The host should confirm that it has received this adjustment
end code (H'00) normally and then transmit one byte of H'55 to this LSI. If reception could not
be performed normally, initiate the boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and this LSI. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 6.3.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The programming
control program transmitted from the host can be stored in the area from H'FB80 to H'FF7F.
The boot program area cannot be used until control of the execution is switched from the boot
program to the programming control program.
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6. Before branching to the programming control program, this LSI terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR3 to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for
transferring program data or verify data to the host. The TXD pin is driven high (PCR32 = 1,
P32 = 1). The contents of the CPU general registers are undefined immediately after branching
to the programming control program. These registers must be initialized at the beginning of the
programming control program because the stack pointer (SP), in particular, is used implicitly
in subroutine calls, etc.
7. The boot mode can be released by a reset. Hold the reset signal low at least 20 states and then
set the NMI pin before negating the reset signal. The boot mode is also released when a WDT
overflow occurs.
8. Do not change the TEST pin and NMI pin input levels in boot mode.
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Section 6 ROM
Boot Mode Operation
Host Operation
Processing Contents
Communication
Contents
Transfer of programming
control program
Flash memory erase
Bit rate adjustment
Boot mode initiation
Item
Table 6.2
LSI Operation
Processing Contents
Branches to boot program after releasing
reset state.
Boot program initiation
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'00, H'00 . . . H'00
H'00
H'55
Boot program
erase error
H'AA reception
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(lower byte following upper byte)
Transmits 1-byte of programming
control program (repeated for N times)
H'AA reception
H'FF
H'AA
Low-order byte
and high-order byte
Echoback
H'XX
Echoback
H'AA
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end code.
H'55 reception.
Checks flash memory data, erases all flash
memory blocks when data has been written
to and then transmits data H'AA to host.
(If erasure fails, transmits data of H'FF to
host and aborts operation.)
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Transmits data H'AA to host.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
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Section 6 ROM
Table 6.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate
System Clock Frequency Range of LSI
9,600 bps
8 to 10 MHz
4,800 bps
4 to 10 MHz
2,400 bps
2 to 10 MHz
6.3.2
Programming/Erasure in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user programming/erasing control program. The user must
prepare the settings for branching to the user programming/erasing control program and means to
transfer programming data for on-board programming. The flash memory must contain the user
programming/erasing control program or a program that transfer the user programming/erasing
control program from external memory. Since the flash memory cannot be read during
programming/erasure, transfer the user programming/erasing control program to on-chip RAM, as
in boot mode. Figure 6.2 shows a sample procedure for programming/erasure in user program
mode. Prepare a user programming/erasing control program in accordance with the description in
section 6.4, Flash Memory Programming/Erasure.
The system clock oscillator must be used when programming or erasing the flash memory.
Starting after releasing reset state
No
Programming or erasure?
Yes
Transfer user programming/erasing
control program to RAM
Branch to flash memory application program
Branch to user programming/erasing
control program in RAM
Execute user programming/erasing control
program (flash memory programmed)
Branch to flash memory application program
Figure 6.2 Programming/Erasing Flowchart Example in User Program Mode
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Section 6 ROM
6.4
Flash Memory Programming/Erasure
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Programming mode, programming-verifying mode, erasing mode,
and erasing-verifying mode. The programming control program in boot mode and the user
programming/erasing control program in user program mode use these operating modes in
combination to perform programming/erasure. Flash memory programming and erasing should be
performed in accordance with the descriptions in section 6.4.1, Programming/ProgrammingVerifying and section 6.4.2, Erasing/Erasing-Verifying, respectively.
6.4.1
Programming/Programming-Verifying
When writing data or programs to the flash memory, the programming/programming-verifying
flowchart shown in figure 6.3 should be followed. Performing programming operations according
to this flowchart will enable data or programs to be written to the flash memory without subjecting
the chip to voltage stress or sacrificing program data reliability.
1. Programming must be performed on an erased area. Do not reprogram an address to which
data has already been programmed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if programming fewer than 128 bytes. In this case, the remaining area must be
filled with H'FF.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 6.4, and additional programming data
computation according to table 6.5.
4. Consecutively transfer 128 bytes of data in bytes from the reprogramming data area or
additional-programming data area to the flash memory. The programming address and 128byte data are latched in the flash memory. The lower eight bits of the start address in the flash
memory destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 6.6 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verifying address, write 1-byte of data H'FF to an address whose lower
two bits are B'00. Verifying data can be read in words or in longwords from the address to
which a dummy write was performed.
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Section 6 ROM
8. The maximum number of repetitions of the programming/programming-verifying sequence of
the same bit is 1,000.
Write pulse application subroutine
Apply Write Pulse
START
Enable WDT
Set SWE bit to 1
Wait 1 µs
Set PSU bit to 1
*
Wait 50 µs
Store 128-byte programming data in programming
data area and reprogramming data area
n=1
Set P bit to 1
m=0
Wait (Wait time = programming time)
Clear P bit to 0
Write 128-byte reprogramming data in RAM
consecutively to flash memory
Wait 5 µs
Apply Write pulse
Clear PSU bit to 0
Set PV bit to 1
Wait 4 µs
Wait 5 µs
Disable WDT
Set block start address as
verifying address
End Sub
Dummy write H'FF to verifying address
n←n+1
Wait 2 µs
*
Read verifying data
Increment address
No
Verifying data =
write data?
m=1
Yes
n≤6?
Yes
No
Additional-programming data computation
Reprogramming data computation
No
128-byte of
data verified?
Yes
Clear PV bit to 0
Wait 2 µs
n ≤ 6?
Yes
No
Write 128-byte additional-programming data
in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m=0?
Yes
Clear SWE bit to 0
No
n ≤ 1000 ?
No
Clear SWE bit to 0
Wait 100 µs
Wait 100 µs
End of programming
Programming failure
Note: * The RTS instruction must not be used during the following periods.
1. A period from programming 128-byte data to flash memory until clearing the P bit
2. A period from dummy-writing of H'FF to a verifying address until reading verifying data
Figure 6.3 Program/Program-Verify Flowchart
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Yes
Section 6 ROM
Table 6.4
Reprogramming Data Computation Table
Programming Data
Verifying Data
Reprogramming Data Comments
0
0
1
Programming completed
0
1
0
Needs to be programmed
1
0
1

1
1
1
Remains in erased state
Table 6.5
Additional-Program Data Computation Table
Reprogram Data
Verify Data
Additional-Program
Data
0
0
0
Needs to be programmed
additionally
0
1
1
No additional programming
1
0
1
No additional programming
1
1
1
No additional programming
Table 6.6
Comments
Programming Time
n (Programming
Count)
Programming
Time
Additional
Programming Time
1 to 6 times
30 µs
10 µs
7 to 1,000 times
200 µs

Comments
Note: Time shown in µs.
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Section 6 ROM
6.4.2
Erasing/Erasing-Verifying
When erasing flash memory, the erasing/erasing-verifying flowchart shown in figure 6.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasure is performed in block units. Select a single block to be erased through erase block
register 1 (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erasing time.
4. The watchdog timer (WDT) is set to prevent the flash memory overerasing due to program
crush, etc. An overflow cycle of approximately 19.8 ms is adequate.
5. For writing dummy data to a verifying address, write one byte of data H'FF to an address
whose lower two bits are B'00. Verifying data can be read in longwords from the address to
which a dummy data is written.
6. If the read data is not erased successfully, set erasing mode again, and repeat the
erasing/erasing-verifying sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is 100.
6.4.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts including the NMI interrupt are disabled while flash memory is being programmed
or erased or while the boot program is executed for the following three reasons.
1. An interrupt during programming/erasure may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before programming the vector address or during
programming/erasure, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
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Section 6 ROM
Erase start
Set SWE bit to 1
Wait 1 µs
n=1
Set EBR1
Enable WDT
Set ESU bit to 1
Wait 100 µs
Set E bit to 1
Wait 10 ms
Clear E bit to 0
Wait 10 µs
Clear ESU bit to 0
Wait 10 µs
Disable WDT
Set EV bit to 1
Wait 20 µs
Set block start address to verifying address
Dummy write H'FF to verifying address
Wait 2 µs
*
n←n+1
Read verifying data
No
Verifying data = all 1s ?
Increment address
Yes
No
Last address of block ?
Yes
No
Clear EV bit to 0
Clear EV bit to 0
Wait 4 µs
Wait 4µs
All erase block erased ?
n ≤100 ?
Yes
Clear SWE bit to 0
Yes
No
Clear SWE bit to 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Note: *The RTS instruction must not be used during a period from dummy-writing of H'FF to a verifying address until reading verifying data
Figure 6.4 Erase/Erase-Verify Flowchart
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Section 6 ROM
6.5
Programming/Erasing Protection
There are three types of flash memory programming/erasing protection; hardware protection,
software protection, and error protection.
6.5.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to the reset state, subactive mode, subsleep mode,
watch mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control
register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. For a reset by the RES
pin, the reset state is entered when the RES signal is held low until oscillation stabilizes after
switching on. For a reset during operation, hold the RES signal low for the RES pulse width
specified in the AC Characteristics section.
6.5.2
Software Protection
Software protection can protect programming/erasing of all flash memory blocks by clearing the
SWE bit in FLMCR1. When software protection is enabled, setting the P or E bit in FLMCR1
does not cause a transition to programming mode or erasing mode. By setting the erase block
register 1 (EBR1), erasing protection can be set for individual blocks. When EBR1 is set to H'00,
erasing protection is set for all blocks.
6.5.3
Error Protection
Error protection is a state in which programming/erasure is forcibly aborted when an error is
detected because CPU crush occurs during flash memory programming/erasure, or operation is not
performed in accordance with the programming/erasing algorithm. Aborting programming/erasure
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory address being programmed or erased is read (including vector read
and instruction fetch)
• Exception handling excluding a reset is started during programming/erasure
• When the SLEEP instruction is executed during programming/erasure
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Section 6 ROM
The FLMCR1, FLMCR2, and EBR1 settings are retained, however programming mode or erasing
mode is aborted when the error occurred. Programming mode or erasing mode cannot be reentered by re-setting the P or E bit. However, settings of the PV and EV bits are retained, and a
transition can be made to the verifying mode. The error protection state can be cleared only by a
reset.
6.6
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read at high speed.
• Power-down operating mode
The power supply circuit of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.7 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from the
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the
external clock is being used.
Table 6.7
Flash Memory Operating States
Flash Memory Operating State
LSI Operating State
PDWND = 0 (Initial Value)
PDWND = 1
Active mode
Normal operating mode
Normal operating mode
Subactive mode
Power-down mode
Normal operating mode
Sleep mode
Normal operating mode
Normal operating mode
Subsleep mode
Standby mode
Standby mode
Watch mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
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Section 6 ROM
6.7
Notes on Setting Module Standby Mode
When the flash memory is set to enter the module standby mode, the system clock supply is
stopped to the module, the function is stopped, and the state is the same as that in standby mode.
Also programming is stopped in the flash memory. Therefore operation program should be
transferred to the RAM and the program should run in the RAM. Then the flash memory should
be set to enter the module standby mode.
If an interrupt is generated in module standby mode, the vector address cannot be fetched. As a
result, the program may run away.
Before the flash memory is set to enter module standby mode, the corresponding bit in the
interrupt enable register should be cleared to 0 and the I bit in CCR should be set to 1. Then after
the flash memory enters the module standby mode, the NMI interrupt request should not be
generated.
Transfer execution program
to RAM (user area)
Clear corresponding bit in
interrupt enable register to 0
Set I bit in CCR to 1
Jump to address of
execution program in RAM
Clear FROMCKSTP
bit in CRSTPR1 to 0
Figure 6.5 Module Standby Mode Setting
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Section 7 RAM
Section 7 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification
RAM Size RAM Address
Flash memory version
H8/38602RF
1 Kbyte
H'FB80 to H'FF7F
Masked ROM version
H8/38602R
1 Kbyte
H'FB80 to H'FF7F
H8/38600R
512 bytes
H'FD80 to H'FF7F
RAM0500A_000120030300
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Section 7 RAM
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Section 8 I/O Ports
Section 8 I/O Ports
The H8/38602R Group has 13 general I/O ports and six general input-only ports. Port 8 is a large
current port, which can drive 15 mA (@VOL = 1.0 V) when a low level signal is output. Any of
these ports can become an input port immediately after a reset. They can also be used as I/O pins
of the on-chip peripheral modules or external interrupt input pins, and these functions can be
switched depending on the register settings. The registers for selecting these functions can be
divided into two types: those included in I/O ports and those included in each on-chip peripheral
module. General I/O ports are comprised of the port control register for controlling inputs/outputs
and the port data register for storing output data and can select inputs/outputs in bit units.
For details on the execution of bit manipulation instructions to the port data register (PDR), see
section 2.8.3, Bit-Manipulation Instruction.
For details on block diagrams for each port, see appendix B.1, I/O Port Block Diagrams.
8.1
Port 1
Port 1
Port 1 is an I/O port also functioning as an asynchronous event counter input pin, timer W I/O pin,
RTC output pin, CLKOUT output pin, and interrupt input pin. Figure 8.1 shows its pin
configuration.
P12/IRQAEC/AECPWM
P11/AEVL/FTCI (/IRQ1)
P10/AEVH/FTIOA/TMOW/CLKOUT
Figure 8.1 Port 1 Pin Configuration
Port 1 has the following registers.
•
•
•
•
Port data register 1 (PDR1)
Port control register 1 (PCR1)
Port pull-up control register 1 (PUCR1)
Port mode register 1 (PMR1)
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Section 8 I/O Ports
8.1.1
Port Data Register 1 (PDR1)
PDR1 is a register that stores data of port 1.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3



Reserved
The read value is undefined. These bits cannot be
modified.
2
P12
0
R/W
1
P11
0
R/W
0
P10
0
R/W
8.1.2
If port 1 is read while PCR1 bits are set to 1, the values
stored in PDR1 are read, regardless of the actual pin
states. If port 1 is read while PCR1 bits are cleared to 0,
the pin states are read.
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3



Reserved
The read value is undefined. These bits cannot be
modified.
2
PCR12
0
W
1
PCR11
0
W
0
PCR10
0
W
Setting a PCR1 bit to 1 makes the corresponding pin
(P12 to P10) an output pin, while clearing the bit to 0
makes the pin an input pin. The settings in PCR1 and in
PDR1 are valid when the corresponding pin is
designated as a general I/O pin.
PCR3 is a write-only register. The read value is
undefined.
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Section 8 I/O Ports
8.1.3
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS of the port 1 pins in bit units.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3



Reserved
The read value is undefined. These bits cannot be
modified.
2
PUCR12
0
R/W
1
PUCR11
0
R/W
0
PUCR10
0
R/W
8.1.4
When a PCR1 bit is cleared to 0, setting the
corresponding PUCR1 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
Port Mode Register 1 (PMR1)
PMR1 controls the selection of functions for port 1 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6



Reserved
The read value is undefined. These bits cannot be
modified.
5
IRQAEC
0
R/W
P12/IRQAEC/AECPWM Pin Function Switch
0: P12 I/O pin
1: IRQAEC input pin or AECPWM output pin
4
FTCI*
0
R/W
P11/AEVL/FTCI/IRQ1 Pin Function Switch
3
AEVL*
0
R/W
00: P11 I/O pin
01: AEVL input pin
1x: FTCI input pin
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Section 8 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
2
CLKOUT
0
R/W
1
TMOW
0
R/W
P10/AEVH/FTIOA/TMOW/CLKOUT Pin Function
Switch
0
AEVH
0
R/W
000: P10 I/O pin and FTIOA I/O pin
001: AEVH input pin
01x: TMOW pin
100: CLKOUT output pin (φOSC)
101: CLKOUT output pin (φOSC/2)
110: CLKOUT output pin (φOSC/4)
111: Setting prohibited
[Legend]
Note: *
8.1.5
x: Don't care.
When the IRQ1S1 and IRQ1S0 bits in PFCR are set to B'10, the pin function becomes
the IRQ1 input pin regardless of the setting of these bits.
Pin Functions
The relationship between the register settings and the port functions is shown below.
• P12/IRQAEC/AECPWM pin
Register Name
Bit Name
PMR1
AEGSR
PCR1
IRQAEC
ECPWME
PCR12
0
x
0
P12 input pin
1
P12 output pin
1
x
AECPWM output pin
0
x
IRQAEC input pin
Setting
1
[Legend]
x: Don't care.
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Pin Function
Section 8 I/O Ports
• P11/AEVL/FTCI (/IRQ1) pin
Register Name
PFCR
PMR1
Bit Name
IRQ1S1 and
IRQ1S0
Setting
Other than
B'10
Pin Function
FTCI
AEVL
PCR11
0
0
0
P11 input pin
B'10
[Legend]
PCR1
1
P11 output pin
1
x
AEVL input pin
1
x
x
FTCI input pin
x
x
x
IRQ1 input pin
x: Don't care.
• P10/AEVH/FTIOA/TMOW/CLKOUT pin
Register Name
Bit Name
Setting
PMR1
CLKOUT TMOW AEVH IOA2 IOA1 IOA0 PCR10
0
1
0
0
0
0
0
0
P10 input pin
1
P10 output pin
1
x
FTIOA output pin
1
0
x
FTIOA output pin
1
x
x
0
P10 input/FTIOA input pin
1
x
x
1
P10 output/FTIOA input pin
1
x
x
x
x
AEVH input pin
1
x
x
x
x
x
TMOW pin
0
0
x
x
x
x
CLKOUT output pin (φOSC)*
1
x
x
x
x
CLKOUT output pin (φOSC/2)*
0
x
x
x
x
CLKOUT output pin (φOSC/4)*
1
[Legend]
Note: *
PCR1 Pin Function
TIOR0
x: Don't care.
Switching the clock (φOSC, φOSC/2, or φOSC/4) for CLKOUT output must be performed when
CLKOUT output is halted (CLKOUT = 0).
When making a transition to a power-down mode wherein the system clock oscillator is
halted, the output level is retained. (In standby mode, output is the high-impedance
state.)
When making a transition from a power-down mode wherein the system clock oscillator
is halted, to the active mode wherein the system clock oscillator operates, halt CLKOUT
output (CLKOUT = 0) before the transition.
Rev. 3.00 May 15, 2007 Page 123 of 516
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Section 8 I/O Ports
8.1.6
Input Pull-Up MOS
Port 1 has an on-chip input pull-up MOS function that can be controlled by software. When a
PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 2 to 0)
PCR1n
0
PUCR1n
Input Pull-Up MOS
[Legend]
8.2
1
0
1
x
Off
On
Off
x: Don't care.
Port 3
Port 3 is an I/O port also functioning as an SCI3/IrDA I/O pin, comparator reference voltage pin
and interrupt pin. Figure 8.2 shows its pin configuration.
Port 3
P32/TXD3/IrTXD
P31/RXD3/IrRXD
P30/SCK3/VCref (/IRQ0)
Figure 8.2 Port 3 Pin Configuration
Port 3 has the following registers.
•
•
•
•
Port data register 3 (PDR3)
Port control register 3 (PCR3)
Port pull-up control register 3 (PUCR3)
Port mode register 3 (PMR3)
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Section 8 I/O Ports
8.2.1
Port Data Register 3 (PDR3)
PDR3 is a register that stores data of port 3.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3



Reserved
The read value is undefined. These bits cannot be
modified.
2
P32
0
R/W
1
P31
0
R/W
0
P30
0
R/W
8.2.2
If port 3 is read while PCR3 bits are set to 1, the values
stored in PDR3 are read, regardless of the actual pin
states. If port 3 is read while PCR3 bits are cleared to 0,
the pin states are read.
Port Control Register 3 (PCR3)
PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3



Reserved
The read value is undefined. These bits cannot be
modified.
2
PCR32
0
W
1
PCR31
0
W
0
PCR30
0
W
Setting a PCR3 bit to 1 makes the corresponding pin
(P32 to P30) an output pin, while clearing the bit to 0
makes the pin an input pin. The settings in PCR3 and in
PDR3 are valid when the corresponding pin is
designated as a general I/O pin.
PCR3 is a write-only register. The read value is
undefined.
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Section 8 I/O Ports
8.2.3
Port Pull-Up Control Register 3 (PUCR3)
PUCR3 controls the pull-up MOS of the port 3 pins in bit units.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3



Reserved
The read value is undefined. These bits cannot be
modified.
2
PUCR32
0
R/W
1
PUCR31
0
R/W
0
PUCR30
0
R/W
8.2.4
When a PCR3 bit is cleared to 0, setting the
corresponding PUCR3 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
Port Mode Register 3 (PMR3)
PMR3 controls the selection of functions for port 3 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1



Reserved
The read value is undefined. These bits cannot be
modified.
0
VCref
0
R/W
P30/SCK3/VCref Pin Function Switch
0: P30 and SCK3 I/O pin
1: Comparator reference voltage (VCref) pin
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Section 8 I/O Ports
8.2.5
Pin Functions
The relationship between the register settings and the port functions is shown below.
• P32/TXD3/IrTXD pin
Register Name
Bit Name
Setting
[Legend]
SPCR
SPC3
0
IrCR
IrE
x
1
0
1
Pin Function
PCR3
PCR32
0
1
x
x
P32 input pin
P32 output pin
TXD3 output pin
IrTXD output pin
x: Don't care.
• P31/RXD3/IrRXD pin
Register Name
SCR3
IrCR
PCR3
RE
IrE
PCR31
0
x
1
0
1
0
1
x
x
Bit Name
Setting
[Legend]
Pin Function
P31 input pin
P31 output pin
RXD3 input pin
IrRXD input pin
x: Don't care.
• P30/SCK3/VCref (/IRQ0) pin
Register Name
Bit Name
PFCR
IRQ0S1 and
IRQ0S0
Setting
Other than
B'10
[Legend]
B'10
x: Don't care.
PMR3
VCref
0
1
x
SCR3
CKE1 CKE0
SMR3 PCR3 Pin Function
COM PCR30
0
0
0
1
x
x
1
0
x
x
1
x
x
x
x
0
1
x
x
x
x
x
P30 input pin
P30 output pin
SCK3 output pin
SCK3 output pin
SCK3 input pin
VCref pin
IRQ0 input pin
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Section 8 I/O Ports
8.2.6
Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When a
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 2 to 0)
PCR3n
0
PUCR3n
Input Pull-Up MOS
[Legend]
8.3
1
0
1
x
Off
On
Off
x: Don't care.
Port 8
Port 8 is an I/O port also functioning as a timer W I/O pin. Figure 8.3 shows its pin configuration.
Port 8
P84/FTIOD
P83/FTIOC
P82/FTIOB
Figure 8.3 Port 8 Pin Configuration
Port 8 has the following registers.
• Port data register 8 (PDR8)
• Port control register 8 (PCR8)
• Port pull-up control register 8 (PUCR8)
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Section 8 I/O Ports
8.3.1
Port Data Register 8 (PDR8)
PDR8 is a register that stores data of port 8.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5



Reserved
The read value is undefined. These bits cannot be
modified.
4
P84
0
R/W
3
P83
0
R/W
2
P82
0
R/W
If port 8 is read while PCR8 bits are set to 1, the values
stored in PDR8 are read, regardless of the actual pin
states. If port 8 is read while PCR8 bits are cleared to 0,
the pin states are read.
1, 0



Reserved
The read value is undefined. These bits cannot be
modified.
8.3.2
Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5



Reserved
The read value is undefined. These bits cannot be
modified.
4
PCR84
0
W
3
PCR83
0
W
2
PCR82
0
W
Setting a PCR8 bit to 1 makes the corresponding pin
(P84 to P82) an output pin, while clearing the bit to 0
makes the pin an input pin. The settings in PCR8 and in
PDR8 are valid when the corresponding pin is
designated as a general I/O pin.
PCR8 is a write-only register. The read value is
undefined.
1, 0



Reserved
The read value is undefined. These bits cannot be
modified.
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Section 8 I/O Ports
8.3.3
Port Pull-Up Control Register 8 (PUCR8)
PUCR8 controls the pull-up MOS of the port 8 pins in bit units.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5



Reserved
The read value is undefined. These bits cannot be
modified.
4
PUCR84
0
R/W
3
PUCR83
0
R/W
2
PUCR82
0
R/W
When a PCR8 bit is cleared to 0, setting the
corresponding PUCR8 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
1, 0



Reserved
The read value is undefined. These bits cannot be
modified.
8.3.4
Pin Functions
The relationship between the register settings and the port functions is shown below.
• P84/FTIOD pin
TMRW
Bit Name
PWMD
IOD2
IOD1
IOD0
PCR84
0
0
0
0
0
P84 input pin
1
P84 output pin
1
x
FTIOD output pin
1
x
x
FTIOD output pin
x
x
0
P84 input/FTIOD input
pin
1
P84 output/FTIOD
input pin
x
FTIOD output pin
Setting
TIOR1
1
1
[Legend]
x
x: Don't care.
Rev. 3.00 May 15, 2007 Page 130 of 516
REJ09B0152-0300
x
PCR8
Pin Function
Register Name
x
Section 8 I/O Ports
• P83/FTIOC pin
Register Name
TMRW
Bit Name
PWMC
IOC2
IOC1
IOC0
PCR83
0
0
0
0
0
P83 input pin
1
P83 output pin
Setting
TIOR1
1
1
[Legend]
x
PCR8
Pin Function
1
x
FTIOC output pin
1
x
x
FTIOC output pin
x
x
0
P83 input/FTIOC input
pin
1
P83 output/FTIOC
input pin
x
FTIOC output pin
x
x
x: Don't care.
• P82/FTIOB pin
TMRW
Bit Name
PWMB
IOB2
IOB1
IOB0
PCR82
0
0
0
0
0
P82 input pin
1
P82 output pin
x
FTIOB output pin
Setting
TIOR0
PCR8
Pin Function
Register Name
1
1
1
[Legend]
x
1
x
x
FTIOB output pin
x
x
0
P82 input/FTIOB input
pin
1
P82 output/FTIOB
input pin
x
FTIOB output pin
x
x
x: Don't care.
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Section 8 I/O Ports
8.3.5
Input Pull-Up MOS
Port 8 has an on-chip input pull-up MOS function that can be controlled by software. When a
PCR8 bit is cleared to 0, setting the corresponding PUCR8 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 4 to 2)
PCR8n
0
PUCR8n
Input Pull-Up MOS
[Legend]
8.4
1
0
1
x
Off
On
Off
x: Don't care.
Port 9
P93/SSI (IRQ1)
P93/SCS (IRQ1)
P92/SSO (IRQ0)
P92/SSCK (IRQ0)
P91/SSCK/SDA
Port 9
Port 9
Port 9 is an I/O port also functioning as an SSU I/O pin, IIC2 I/O pin and interrupt pin. Figure 8.4
shows its pin configuration.
P90/SCS/SCL
(1) SSUS = 0
P91/SSO/SDA
P90/SSI/SCL
(2) SSUS = 1
Figure 8.4 Port 9 Pin Configuration
Port 9 has the following registers.
•
•
•
•
Port data register 9 (PDR9)
Port control register 9 (PCR9)
Port open-drain control register 9 (PODR9)
Port pull-up control register 9 (PUCR9)
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Section 8 I/O Ports
8.4.1
Port Data Register 9 (PDR9)
PDR9 is a register that stores data of port 9.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4



Reserved
The read value is undefined. These bits cannot be
modified.
3
P93
0
R/W
2
P92
0
R/W
1
P91
0
R/W
0
P90
0
R/W
8.4.2
If port 9 is read while PCR9 bits are set to 1, the values
stored in PDR9 are read, regardless of the actual pin
states. If port 9 is read while PCR9 bits are cleared to 0,
the pin states are read.
Port Control Register 9 (PCR9)
PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4



Reserved
The read value is undefined. These bits cannot be
modified.
3
PCR93
0
W
2
PCR92
0
W
1
PCR91
0
W
0
PCR90
0
W
Setting a PCR9 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR9 and in PDR9 are valid
when the corresponding pin is designated as a general
I/O pin.
PCR9 is a write-only register. The read value is
undefined.
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Section 8 I/O Ports
8.4.3
Port Open-Drain Control Register 9 (PODR9)
PODR9 selects the output format for port 9 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4



Reserved
The read value is undefined. These bits cannot be
modified.
3
P93ODR
0
R/W
2
P92ODR
0
R/W
1
P91ODR
0
R/W
0
P90ODR
0
R/W
8.4.4
When a bit among the P93ODR to P90ODR bits is set
to 1, the corresponding pin among P93 to P90 functions
as the NMOS open-drain output. When cleared to 0, the
corresponding pin functions as the CMOS output.
Port Pull-Up Control Register 9 (PUCR9)
PUCR9 controls the pull-up MOS of the port 9 pins in bit units.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4



Reserved
The read value is undefined. These bits cannot be
modified.
3
PUCR93
0
R/W
2
PUCR92
0
R/W
1
PUCR91
0
R/W
0
PUCR90
0
R/W
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When a PCR9 bit is cleared to 0, setting the
corresponding PUCR9 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
Section 8 I/O Ports
8.4.5
Pin Functions
The relationship between the register settings and the port functions is shown below.
Note on the followings when port 9 is used.
1. When IIC is used, SSU should not be set.
2. When SSU is used, the ICE bit in IIC should be set to 0.
3. The port corresponding to the pins for SSU communication data (SSI and SSO) should not be
set.
4. When the pins for communication data (SSI and SSO) are set to open-drain output with the
SOOS bit in the SSCRH register of SSU, they are set to open-drain output regardless of the TE
and RE bit settings in the SSER register.
• P93/SSI (/IRQ1) pin
Register Name
PFCR
Bit Name
IRQ1S1 and
IRQ1S0
Setting
Other than
B'01
B'01
PCR9
SSUS
PCR93
x
0
Pin Function
P93 input pin
1
P93 output pin
0
x
SSI I/O pin
1
x
SCS I/O pin
x
x
IRQ1 input pin
[Legend] x: Don't care.
Note: When this pin is used as the SSI/SCS pin, register settings of the SSU are required. For
details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3,
Port 9 Related Register Settings and Pin Functions.
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Section 8 I/O Ports
• P92/SSO (/IRQ0) pin
Register Name
PFCR
Bit Name
IRQ0S1 and
IRQ0S0
Setting
Other than
B'01
B'01
PCR9
SSUS
PCR92
x
0
Pin Function
P92 input pin
1
P92 output pin
0
x
SSO I/O pin
1
x
SSCK I/O pin
x
x
IRQ0 input pin
[Legend] x: Don't care.
Note: When this pin is used as the SSO/SSCK pin, register settings of the SSU are required. For
details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3,
Port 9 Related Register Settings and Pin Functions.
• P91/SSCK/SDA pin
Pin Function
Register Name
PFCR
PCR9
Bit Name
SSUS
PCR91
x
0
P91 input pin
1
P91 output pin
0
x
SSCK I/O pin
1
x
SSO I/O pin
x
x
SDA I/O pin
Setting
[Legend] x: Don't care.
Note: When this pin is used as the SSO/SSCK pin, register settings of the SSU are required. For
details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3,
Port 9 Related Register Settings and Pin Functions. When this pin is used as the SDA pin,
2
register settings of the IIC2 are required. For details, see section 16.3.1, I C Bus Control
Register 1 (ICCR1).
Note that the priority when pin functions conflict is SSU pin > IIC2 pin > P91.
Rev. 3.00 May 15, 2007 Page 136 of 516
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Section 8 I/O Ports
• P90/SCS/SCL pin
Pin Function
Register Name
PFCR
PCR9
Bit Name
SSUS
PCR90
x
0
P90 input pin
1
P90 output pin
x
SCS I/O pin
Setting
0
1
x
SSI I/O pin
x
x
SCL I/O pin
[Legend] x: Don't care.
Note: When this pin is used as the SCS/SSI pin, register settings of the SSU are required. For
details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3,
Port 9 Related Register Settings and Pin Functions. When this pin is used as the SCL pin,
2
register settings of the IIC2 are required. For details, see section 16.3.1, I C Bus Control
Register 1 (ICCR1).
Note that the priority when pin functions conflict is SSU pin > IIC2 pin > P90.
8.4.6
Input Pull-Up MOS
Port 9 has an on-chip input pull-up MOS function that can be controlled by software. When a
PCR9 bit is cleared to 0, setting the corresponding PUCR9 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 3 to 0)
PCR9n
0
PUCR9n
Input Pull-Up MOS
[Legend]
1
0
1
x
Off
On
Off
x: Don't care.
Rev. 3.00 May 15, 2007 Page 137 of 516
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Section 8 I/O Ports
8.5
Port B
Port B is an input-only port also functioning as an interrupt input pin, analog input pin, and
comparator pin. Figure 8.5 shows its pin configuration.
PB5/AN5/COMP1
Port B
PB4/AN4/COMP0
PB3/AN3
PB2/AN2
PB1/AN1/IRQ1
PB0/AN0/IRQ0
Figure 8.5 Port B Pin Configuration
Port B has the following registers.
• Port data register B (PDRB)
• Port mode register B (PMRB)
8.5.1
Port Data Register B (PDRB)
PDRB is a register that stores data of port B.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6



Reserved
The read value is undefined. These bits cannot be
modified.
5
PB5
Undefined
R
4
PB4
Undefined
R
3
PB3
Undefined
R
2
PB2
Undefined
R
1
PB1
Undefined
R
0
PB0
Undefined
R
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Reading PDRB always gives the pin states. However, if
a port B pin is selected as an analog input channel by
the CH3 to CH0 bits in AMR of the A/D converter, that
pin is read as 0 regardless of the input voltage.
Section 8 I/O Ports
8.5.2
Port Mode Register B (PMRB)
PMRB controls the selection of the port B pin functions.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4



Reserved
The read value is undefined. These bits cannot be
modified.
3
ADTSTCHG 0
R/W
TEST/ADTRG Pin Function Switch
Selects whether pin TEST/ADTRG is used as TEST or
as ADTRG.
0: TEST pin
1: ADTRG input pin
For details on the setting of the ADTRG input pin, refer
to section 17.4.2, External Trigger Input Timing.

2


Reserved
The read value is undefined. This bit cannot be
modified.
1
IRQ1
0
R/W
PB1/AN1/IRQ1 Pin Function Switch
Selects whether pin PB1/AN1/IRQ1 is used as
PB1/AN1 or as IRQ1.
0: PB1/AN1 input pin
1: IRQ1 input pin*
0
IRQ0
0
R/W
PB0/AN0/IRQ0 Pin Function Switch
Selects whether pin PB0/AN0/IRQ0 is used as
PB0/AN0 or as IRQ0.
0: PB0/AN0 input pin
1: IRQ0 input pin*
Note:
*
When the IRQnS1 and IRQnS0 (n = 1 or 0) bits in PFCR are set to a value other than
B'00, these bits should not be set since the IRQn pin is assigned to another port.
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Section 8 I/O Ports
8.5.3
Pin Functions
The relationship between the register settings and the port functions is shown below.
• PB5/AN5/COMP1 pin
Register Name
AMR
Pin Function
Bit Name
CH3 to CH0
Setting
Other than B'1001
PB5/COMP1 input pin
B'1001
AN5 input pin
[Legend]
x: Don't care.
• PB4/AN4/COMP0 pin
Pin Function
Register Name
AMR
Bit Name
CH3 to CH0
Setting
Other than B'1000
PB4/COMP0 input pin
B'1000
AN4 input pin
[Legend]
x: Don't care.
• PB3/AN3 pin
Pin Function
Register Name
AMR
Bit Name
CH3 to CH0
Setting
Other than B'0111
PB3 input pin
B'0111
AN3 input pin
[Legend]
x: Don't care.
• PB2/AN2 pin
Pin Function
Register Name
AMR
Bit Name
CH3 to CH0
Setting
Other than B'0110
PB2 input pin
B'0110
AN2 input pin
[Legend]
x: Don't care.
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Section 8 I/O Ports
• PB1/AN1/IRQ1 pin
Register Name
PMRB
Bit Name
IRQ1
Setting
0
1
[Legend]
AMR
PFCR
Pin Function
CH3 to CH0
IRQ1S1 and
IRQ1S0
Other than
B'0101
B'xx
PB1 input pin
B'0101
B'xx
AN1 input pin
B'xxxx
B'00
IRQ1 input pin
Other than
B'00
Setting prohibited
x: Don't care.
• PB0/AN0/IRQ0 pin
Register Name
PMRB
Bit Name
IRQ0
Setting
0
1
[Legend]
AMR
PFCR
Pin Function
CH3 to CH0
IRQ0S1 and
IRQ0S0
Other than
B'0100
B'xx
PB0 input pin
B'0100
B'xx
AN0 input pin
B'xxxx
B'00
IRQ0 input pin
Other than
B'00
Setting prohibited
x: Don't care.
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Section 8 I/O Ports
8.6
Input/Output Data Inversion
8.6.1
Serial Port Control Register (SPCR)
SPCR switches input/output data inversion of the RXD3 (IrRXD) and TXD3 (IrTXD) pins.
SCINV0
RXD3/IrRXD
P31/RXD3/IrRXD
SCINV1
P32/TXD3/IrTXD
TXD3/IrTXD
Figure 8.6 Input/Output Data Inversion Function
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
4
SPC3
0
R/W
P32/TXD3/IrTXD Pin Function Switch
Selects whether pin P32/TXD3/IrTXD is used as P32 or
as TXD3/IrTXD.
0: P32 I/O pin
1: TXD3/IrTXD output pin*
Note: * Set the TE bit in SCR3 after setting this bit to 1.
3, 2

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
1
SCINV1
0
R/W
TXD3/IrTXD Pin Output Data Inversion Switch
Specifies whether the logic level of output data of the
TXD3/IrTXD pin is to be inverted or not.
0: TXD3/IrTXD output data is not inverted
1: TXD3/IrTXD output data is inverted
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Section 8 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
0
SCINV0
0
R/W
RXD3/IrRXD Pin Input Data Inversion Switch
Specifies whether the logic level of input data of the
RXD3/IrRXD pin is to be inverted or not.
0: RXD3/IrRXD input data is not inverted
1: RXD3/IrRXD input data is inverted
Note: When the serial port control register is modified, the data being input or output up to that
point is inverted immediately after the modification, and an invalid data change is input or
output. When modifying the serial port control register, modification must be made in a state
in which data changes are invalidated.
8.6.2
Port Function Control Register (PFCR)
PFCR changes the SSU pin assignments, and assigns the IRQ0 and IRQ1 input pins to other ports.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 0

4
SSUS
0
R/W
3
2
IRQ1S1
IRQ1S0
0
0
R/W
R/W
1
0
IRQ0S1
IRQ0S0
0
0
R/W
R/W
Reserved
These bits are always read as 0. These bits cannot be
modified.
SSU Pin Select
Changes the SSU pin assignments.
0: SSI is assigned to P93
SSO is assigned to P92
SSCK is assigned to P91
SCS is assigned to P90
1: SSI is assigned to P90
SSO is assigned to P91
SSCK is assigned to P92
SCS is assigned to P93
IRQ1 Select 1, 0
00: IRQ1 is input from PB1
01: IRQ1 is input from P93
10: IRQ1 is input from P11
11: Setting prohibited
IRQ0 Select 1, 0
00: IRQ0 is input from PB0
01: IRQ0 is input from P92
10: IRQ0 is input from P30
11: Setting prohibited
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Section 8 I/O Ports
8.7
8.7.1
Usage Notes
How to Handle Unused Pin
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, handle it in one of the following ways:
 Pull it up to Vcc with an on-chip pull-up MOS.
 Pull it up to Vcc with an external resistor of approximately 100 kΩ.
 Pull it down to Vss with an external resistor of approximately 100 kΩ.
 For a pin also used by the A/D converter, pull it up to AVcc with an external resistor of
approximately 100 kΩ.
• If an unused pin is an output pin, handle it in one of the following ways:
 Set the output of the unused pin to high and pull it up to Vcc with an external resistor of
approximately 100 kΩ.
 Set the output of the unused pin to low and pull it down to GND with an external resistor of
approximately 100 kΩ.
8.7.2
Input Characteristics Difference due to Pin Function
When the functions of pins IRQ0, IRQ1, IRQAEC, AEVL, AEVH, SCK3, FTIOA to FTIOD,
FTCI, SSCK, SCS, SDA, and SCL are selected, the corresponding pins have the schmitt-trigger
input characteristics, which are different from the ones when they are used as the port input pins.
For example, the input high voltage and the input low voltage of the PB0/AN0/IRQ0 pin differ
when the pin is used as PB0 input or IRQ0 input. For details, refer to table 21.2 which lists the DC
characteristics for F-ZTAT version, and table 21.13 which lists the DC characteristics for masked
ROM version.
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Section 9 Timer B1
Section 9 Timer B1
Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two
operating modes, interval and auto reload. Figure 9.1 shows a block diagram of timer B1.
9.1
Features
• Selection of eight internal clock sources (φ/8192, φ/2048, φ/256, φ/64, φ/16, φ/4, φW/1024, and
φW/256).
• An interrupt is generated when the counter overflows.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (Timer B1 is halted as the initial value. For details, refer to section 5.4, Module
Standby Function.)
φ
PSS
TCB1
φw
1/4
φw/4
PSW
[φw/1024, φw/256]
Internal data bus
TMB1
TLB1
[Legend]
TMB1:
TCB1:
TLB1:
IRRTB1:
PSS:
PSW:
Timer mode register B1
Timer counter B1
Timer load register B1
Time B1 interrupt request flag
Prescaler S
Prescaler W
IRRTB1
Figure 9.1 Block Diagram of Timer B1
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Section 9 Timer B1
9.2
Register Descriptions
Timer B1 has the following registers.
• Timer mode register B1 (TMB1)
• Timer counter B1 (TCB1)
• Timer load register B1 (TLB1)
9.2.1
Timer Mode Register B1 (TMB1)
TMB1 selects the auto-reload function and input clock.
Bit
Bit Name
Initial
Value
R/W
Description
7
TMB17
0
R/W
Auto-Reload Function Select
0: Interval timer function selected
1: Auto-reload function selected
6
TMB16
0
R/W
Counter Operation/Stop Select
0: Counter stopped
1: Counter operates
5 to 3

All 1

Reserved
These bits are always read as 1.
2
TMB12
0
R/W
Counter Clock Select
1
TMB11
0
R/W
000: Internal clock: φ/8192
0
TMB10
0
R/W
001: Internal clock: φ/2048
010: Internal clock: φ/256
011: Internal clock: φ/64
100: Internal clock: φ/16
101: Internal clock: φ/4
110: Internal clock: φW/1024
111: Internal clock: φW/256
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Section 9 Timer B1
9.2.2
Timer Counter B1 (TCB1)
TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can
be read by the CPU. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the
IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is
initialized to H'00.
9.2.3
Timer Load Register B1 (TLB1)
TLB1 is an 8-bit write-only register for setting the reload value of TCB1. Setting the reload value
to TLB1 must be done when bit TMB16 in TMB1 is cleared to 0. When a reload value is set in
TLB1, the same value is loaded into TCB1 as well, and TCB1 starts counting up from that value.
When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded into
TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. TLB1
is allocated to the same address as TCB1. TLB1 is initialized to H'00.
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Section 9 Timer B1
9.3
Usage Method
Figure 9.2 shows the initial setting flow of timer B1 after a reset, and figure 9.3 shows the
processing flow for changing a setting during counter operation. Bit TMB16 in TMB1 must be
cleared to 0 when setting timer B1, as shown in the figures. Operation is not guaranteed when a
setting is made with bit TMB16 in TMB1 set to 1.
Cancel the module standby mode of timer B1
*1
Set counter function with bit TMB17
in TMB1 and counter clock with bits
TMB12 to TMB10 in TMB1
(bit TMB16 must be cleared to 0
when writing to these bits)
Set reload value to
TLB1 when auto-reload function is selected
Set bit TMB16 in TMB1 to 1
to start counter operation
(bits other than TMB16 must have
the same values set at *1)
Figure 9.2 Timer B1 Initial Setting Flow
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Section 9 Timer B1
Clear bit TMB16 in TMB1 to 0
to stop counter operation
*2
To modify the counter clock, change
the value in bits TMB12 to TMB10 in TMB1
(bit TMB16 must be cleared to 0
when writing to these bits)
To change the reload value,
set a new reload value in TLB1
Set bit TMB16 in TMB1 to
1 to start counter operation
(bits other than TMB16 must have
the same values set at *2)
Figure 9.3 Processing Flow When Changing Setting during Counter Operation
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Section 9 Timer B1
9.4
9.4.1
Operation
Interval Timer Operation
When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon
reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so the interval timer function is
selected immediately after a reset. The operating clock of timer B1 is selected from eight internal
clock signals output by prescaler S or prescaler W. The selection is made by bits TMB12 to
TMB10 in TMB1.
After bit TMB16 in TMB1 is set to 1 to start the counter operation and the count value in TMB1
reaches H'FF, the next clock signal input causes timer B1 to overflow, setting flag IRRTB1 in
IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to the CPU.
At overflow, TCB1 returns to H'00 and starts counting up again. Even though interval timer
operation (TMB17 = 0) is selected, when a value is set in TLB1 with bit TMB16 in TMB1 cleared
to 0, the same value is set in TCB1.
9.4.2
Auto-Reload Timer Operation
Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When
a reload value is set in TLB1 with bit TMB16 in TMB1 cleared to 0, the same value is loaded into
TCB1. After bit TMB16 in TMB1 is set to 1 to start the counter operation and the count value in
TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is
then loaded into TCB1, and the count continues from that value. The overflow period can be set
within a range from 1 to 256 input clocks, depending on the TLB1 value.
The clock sources and interrupts in auto-reload mode are the same as in interval mode. To set a
new value in TLB1 in auto-reload mode (TMB17 = 1), clear bit TMB16 in TMB1 to 0 before
making the new setting.
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Section 9 Timer B1
9.5
Timer B1 Operating Modes
Table 9.1 shows the timer B1 operating modes.
Table 9.1
Timer B1 Operating Modes
Active
Sleep
Oscillation Stabilization Time
Subsleep Watch
Clock
High-
Medium-
High-
Source
speed
speed
speed speed
φw/256, ο
φw/1024
ο
ο
φ/4, φ/16, ο
φ/64,
φ/256,
φ/2048,
φ/8192
ο
ο
[Legend]
Medium-
Sub-
Sub-
Standby
to
to
Watch active
sleep Standby
to Active
Active
Active
ο
ο
ο
ο
×
×
ο
ο
ο
×
×
×
×
×
×
×
ο: Counting enabled
×: Counting disabled (Counter value retained)
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Section 9 Timer B1
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Section 10 Timer W
Section 10 Timer W
The timer W has a 16-bit timer having output compare and input capture functions. The timer W
can count external events and output pulses with an arbitrary duty cycle by compare match
between the timer counter and four general registers. Thus, it can be applied to various systems.
10.1
Features
• Selection of eight counter clock sources: seven internal clocks (φ, φ/2, φ/4, φ/8, φW, φW/4, and
φW/16) and an external clock (external events can be counted)
• Capability to process up to four pulse outputs or four pulse inputs
• Four general registers:
 Independently assignable output compare or input capture functions
 Usable as two pairs of registers; one register of each pair operates as a buffer for the output
compare or input capture register
• Four selectable operating modes:
 Waveform output by compare match
Selection of 0 output, 1 output, or toggle output
 Input capture function
Rising edge, falling edge, or both edges
 Counter clearing function
Counters can be cleared by compare match
 PWM mode
Up to three-phase PWM output can be provided with desired duty ratio.
• Any initial timer output value can be set
• Five interrupt sources
Four compare match/input capture interrupts and an overflow interrupt.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The timer W is halted as the initial value. For details, refer to section 5.4,
Module Standby Function.)
Table 10.1 summarizes the timer W functions, and figure 10.1 shows a block diagram of the timer
W.
TIM08W0A_000020020200
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Section 10 Timer W
Table 10.1 Timer W Functions
Input/Output Pins
Item
Counter
Count clock
Internal clocks: φ, φ/2, φ/4, φ/8, φW, φW/4, and φW/16
External clock: FTCI
General registers
(output compare/input
capture registers)
Period
GRA
specified in
GRA
GRB
GRC (buffer
register for
GRA in
buffer mode)
GRD (buffer
register for
GRB in
buffer mode)
Counter clearing function
GRA
compare
match
GRA
compare
match
—
—
—
Initial output value
setting function
—
Yes
Yes
Yes
Yes
Buffer function
—
Yes
Yes
—
—
0
—
Yes
Yes
Yes
Yes
1
—
Yes
Yes
Yes
Yes
Toggle
—
Yes
Yes
Yes
Yes
Input capture function
—
Yes
Yes
Yes
Yes
PWM mode
—
—
Yes
Yes
Yes
Interrupt sources
Overflow
Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
Compare
match output
Rev. 3.00 May 15, 2007 Page 154 of 516
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FTIOA
FTIOB
FTIOC
FTIOD
Section 10 Timer W
Internal clock: φ
φ/2
φ/4
φ/8
φW
φW/4
φW/16
External clock: FTCI
FTIOA
Clock
selector
FTIOB
FTIOC
Control logic
FTIOD
Comparator
TIOR
TSRW
TIERW
TCRW
TMRW
GRD
GRC
GRB
Bus interface
[Legend]
TMRW:
TCRW:
TIERW:
TSRW:
TIOR:
TCNT:
GRA:
GRB:
GRC:
GRD:
IRRTW:
GRA
TCNT
IRRTW
Internal
data bus
Timer mode register W (8 bits)
Timer control register W (8 bits)
Timer interrupt enable register W (8 bits)
Timer status register W (8 bits)
Timer I/O control register (8 bits)
Timer counter (16 bits)
General register A (input capture/output compare register: 16 bits)
General register B (input capture/output compare register: 16 bits)
General register C (input capture/output compare register: 16 bits)
General register D (input capture/output compare register: 16 bits)
Timer W interrupt request
Figure 10.1 Timer W Block Diagram
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Section 10 Timer W
10.2
Input/Output Pins
Table 10.2 shows the pin configuration of the timer W.
Table 10.2 Pin Configuration
Name
Abbreviation
Input/Output
Function
External clock input
FTCI
Input
External clock input pin
Input capture/output
compare A
FTIOA
Input/output
Output pin for GRA output compare
or input pin for GRA input capture
Input capture/output
compare B
FTIOB
Input/output
Output pin for GRB output compare,
input pin for GRB input capture, or
PWM output pin in PWM mode
Input capture/output
compare C
FTIOC
Input/output
Output pin for GRC output compare,
input pin for GRC input capture, or
PWM output pin in PWM mode
Input capture/output
compare D
FTIOD
Input/output
Output pin for GRD output compare,
input pin for GRD input capture, or
PWM output pin in PWM mode
10.3
Register Descriptions
The timer W has the following registers.
•
•
•
•
•
•
•
•
•
•
•
Timer mode register W (TMRW)
Timer control register W (TCRW)
Timer interrupt enable register W (TIERW)
Timer status register W (TSRW)
Timer I/O control register 0 (TIOR0)
Timer I/O control register 1 (TIOR1)
Timer counter (TCNT)
General register A (GRA)
General register B (GRB)
General register C (GRC)
General register D (GRD)
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Section 10 Timer W
10.3.1
Timer Mode Register W (TMRW)
TMRW selects the general register functions and the timer output mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
CTS
0
R/W
Counter Start
The counter operation is halted when this bit is 0,
while it can be performed when this bit is 1.
6

1

Reserved
This bit is always read as 1.
5
BUFEB
0
R/W
Buffer Operation B
Selects the GRD function.
0: GRD operates as an input capture/output compare
register
1: GRD operates as the buffer register for GRB
4
BUFEA
0
R/W
Buffer Operation A
Selects the GRC function.
0: GRC operates as an input capture/output compare
register
1: GRC operates as the buffer register for GRA
3

1

Reserved
2
PWMD
0
R/W
PWM Mode D
This bit is always read as 1.
Selects the output mode of the FTIOD pin.
0: FTIOD operates normally (output compare output)
1: PWM output
1
PWMC
0
R/W
PWM Mode C
Selects the output mode of the FTIOC pin.
0: FTIOC operates normally (output compare output)
1: PWM output
0
PWMB
0
R/W
PWM Mode B
Selects the output mode of the FTIOB pin.
0: FTIOB operates normally (output compare output)
1: PWM output
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Section 10 Timer W
10.3.2
Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer
output levels.
Bit
Bit Name
Initial
Value
R/W
Description
7
CCLR
0
R/W
6
5
4
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Counter Clear
The TCNT value is cleared by compare match A when
this bit is 1. When it is 0, TCNT operates as a freerunning counter.
Clock Select 2 to 0
Select the TCNT clock source.
000: Internal clock: counts on φ
001: Internal clock: counts on φ/2
010: Internal clock: counts on φ/4
011: Internal clock: counts on φ/8
100: Internal clock: counts on φW
101: Internal clock: counts on φW/4
110: Internal clock: counts on φW/16
111: Counts on rising edges of the external event
(FTCI)
With a setting of 0xx, the timer W can be used only in
active mode or sleep mode. Do not make this setting in
subactive mode or subsleep mode.
When 100 is set in subactive mode or subsleep mode,
the timer W can be used only when φW is selected as
the CPU operating clock.
When 101 is set in subactive mode or subsleep mode,
the timer W can be used only when φW or φW/2 is
selected as the CPU operating clock.
3
TOD
0
R/W
2
TOC
0
R/W
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Timer Output Level Setting D
Sets the output value of the FTIOD pin until the first
compare match D is generated.
0: Output value is 0*
1: Output value is 1*
Timer Output Level Setting C
Sets the output value of the FTIOC pin until the first
compare match C is generated.
0: Output value is 0*
1: Output value is 1*
Section 10 Timer W
Bit
Bit Name
Initial
Value
R/W
Description
1
TOB
0
R/W
Timer Output Level Setting B
Sets the output value of the FTIOB pin until the first
compare match B is generated.
0: Output value is 0*
1: Output value is 1*
0
TOA
0
R/W
Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
[Legend]
Note: *
10.3.3
x: Don't care.
The change of the setting is immediately reflected in the output value.
Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit
Bit Name
Initial
Value
R/W
Description
7
OVIE
0
R/W
6 to 4

All 1

3
IMIED
0
R/W
2
IMIEC
0
R/W
1
IMIEB
0
R/W
0
IMIEA
0
R/W
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by
OVF flag in TSRW is enabled.
Reserved
These bits are always read as 1.
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
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Section 10 Timer W
10.3.4
Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
7
OVF
0
R/(W)*
Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
6 to 4

All 1

Reserved
These bits are always read as 1.
3
IMFD
0
R/(W)*
Input Capture/Compare Match Flag D
[Setting conditions]
•
TCNT = GRD when GRD functions as an output
compare register
•
The TCNT value is transferred to GRD by an input
capture signal when GRD functions as an input
capture register
[Clearing condition]
Read IMFD when IMFD = 1, then write 0 in IMFD
2
IMFC
0
R/(W)*
Input Capture/Compare Match Flag C
[Setting conditions]
•
TCNT = GRC when GRC functions as an output
compare register
•
The TCNT value is transferred to GRC by an input
capture signal when GRC functions as an input
capture register
[Clearing condition]
Read IMFC when IMFC = 1, then write 0 in IMFC
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Section 10 Timer W
Bit
Bit Name
Initial
Value
R/W
1
IMFB
0
R/(W)* Input Capture/Compare Match Flag B
Description
[Setting conditions]
•
TCNT = GRB when GRB functions as an output
compare register
•
The TCNT value is transferred to GRB by an input
capture signal when GRB functions as an input
capture register
[Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
0
IMFA
0
R/(W)* Input Capture/Compare Match Flag A
[Setting conditions]
•
TCNT = GRA when GRA functions as an output
compare register
•
The TCNT value is transferred to GRA by an input
capture signal when GRA functions as an input
capture register
[Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
Note:
10.3.5
*
Only 0 can be written to clear the flag.
Timer I/O Control Register 0 (TIOR0)
TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and
FTIOB pins.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

6
IOB2
0
R/W
Reserved
This bit is always read as 1.
I/O Control B2
Selects the GRB function.
0: GRB functions as an output compare register
1: GRB functions as an input capture register
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Section 10 Timer W
Bit
Bit Name
Initial
Value
R/W
Description
5
4
IOB1
IOB0
0
0
R/W
R/W
3

1

2
IOA2
0
R/W
1
0
IOA1
IOA0
0
0
R/W
R/W
I/O Control B1 and B0
When IOB2 = 0,
00: No output at compare match
01: 0 output to the FTIOB pin at GRB compare match
10: 1 output to the FTIOB pin at GRB compare match
11: Output toggles to the FTIOB pin at GRB compare
match
When IOB2 = 1,
00: Input capture at rising edge at the FTIOB pin
01: Input capture at falling edge at the FTIOB pin
1x: Input capture at rising and falling edges of the
FTIOB pin
Reserved
This bit is always read as 1.
I/O Control A2
Selects the GRA function.
0: GRA functions as an output compare register
1: GRA functions as an input capture register
I/O Control A1 and A0
When IOA2 = 0,
00: No output at compare match
01: 0 output to the FTIOA pin at GRA compare match
10: 1 output to the FTIOA pin at GRA compare match
11: Output toggles to the FTIOA pin at GRA compare
match
When IOA2 = 1,
00: Input capture at rising edge of the FTIOA pin
01: Input capture at falling edge of the FTIOA pin
1x: Input capture at rising and falling edges of the
FTIOA pin
[Legend]
x: Don't care.
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Section 10 Timer W
10.3.6
Timer I/O Control Register 1 (TIOR1)
TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and
FTIOD pins.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

6
IOD2
0
R/W
5
4
IOD1
IOD0
0
0
R/W
R/W
3

1

2
IOC2
0
R/W
Reserved
This bit is always read as 1.
I/O Control D2
Selects the GRD function.
0: GRD functions as an output compare register
1: GRD functions as an input capture register
I/O Control D1 and D0
When IOD2 = 0,
00: No output at compare match
01: 0 output to the FTIOD pin at GRD compare match
10: 1 output to the FTIOD pin at GRD compare match
11: Output toggles to the FTIOD pin at GRD compare
match
When IOD2 = 1,
00: Input capture at rising edge at the FTIOD pin
01: Input capture at falling edge at the FTIOD pin
1x: Input capture at rising and falling edges at the FTIOD
pin
Reserved
This bit is always read as 1.
I/O Control C2
Selects the GRC function.
0: GRC functions as an output compare register
1: GRC functions as an input capture register
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Section 10 Timer W
Bit
Bit Name
Initial
Value
R/W
Description
1
0
IOC1
IOC0
0
0
R/W
R/W
I/O Control C1 and C0
When IOC2 = 0,
00: No output at compare match
01: 0 output to the FTIOC pin at GRC compare match
10: 1 output to the FTIOC pin at GRC compare match
11: Output toggles to the FTIOC pin at GRC compare
match
When IOC2 = 1,
00: Input capture to GRC at rising edge of the FTIOC pin
01: Input capture to GRC at falling edge of the FTIOC pin
1x: Input capture to GRC at rising and falling edges of
the FTIOC pin
[Legend]
10.3.7
x: Don't care.
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to
CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting
the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF
flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is
generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.
TCNT is initialized to H'0000 by a reset.
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Section 10 Timer W
10.3.8
General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and
TIOR1.
When a general register is used as an output-compare register, its value is constantly compared
with the TCNT value. When the two values match (a compare match), the corresponding flag
(IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this
time, when IMIEA, IMIEB, IMIEC, or IMIED in TIERW is set to 1. Compare match output can
be selected in TIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TCNT value is stored in the general register. The corresponding flag
(IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit
(IMIEA, IMIEB, IMIEC, or IMIED) in TIERW is set to 1 at this time, an interrupt request is
generated. The edge of the input-capture signal is selected in TIOR.
GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA
and BUFEB in TMRW.
For example, when GRA is set as an output-compare register and GRC is set as the buffer register
for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is
generated.
When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the
value in TCNT is transferred to GRA and the value in GRA is transferred to GRC whenever an
input capture is generated.
GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are
initialized to H'FFFF by a reset.
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Section 10 Timer W
10.4
Operation
The timer W has the following operating modes.
• Normal Operation
• PWM Operation
10.4.1
Normal Operation
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count.
When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE
in TIERW is set to 1, an interrupt request is generated. Figure 10.2 shows free-running counting.
TCNT value
H'FFFF
H'0000
Time
CTS bit
Flag cleared
by software
OVF
Figure 10.2 Free-Running Counter Operation
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Section 10 Timer W
Periodic counting operation can be performed when GRA is set as an output compare register and
CCLR bit in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the
IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt
request is generated. TCNT continues counting from H'0000. Figure 10.3 shows periodic
counting.
TCNT value
GRA
H'0000
Time
CTS bit
Flag cleared
by software
IMFA
Figure 10.3 Periodic Counter Operation
By setting a general register as an output compare register, compare match A, B, C, or D can
cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle.
Figure 10.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1
output is selected for compare match A, and 0 output is selected for compare match B. When
signal is already at the selected output level, the signal level does not change at compare match.
TCNT value
H'FFFF
GRA
GRB
Time
H'0000
FTIOA
FTIOB
No change
No change
No change
No change
Figure 10.4 0 and 1 Output Example (TOA = 0, TOB = 1)
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Section 10 Timer W
Figure 10.5 shows an example of toggle output when TCNT operates as a free-running counter,
and toggle output is selected for both compare match A and B.
TCNT value
H'FFFF
GRA
GRB
Time
H'0000
FTIOA
Toggle output
FTIOB
Toggle output
Figure 10.5 Toggle Output Example (TOA = 0, TOB = 1)
Figure 10.6 shows another example of toggle output when TCNT operates as a periodic counter,
cleared by compare match A. Toggle output is selected for both compare match A and B.
TCNT value
Counter cleared by compare match with GRA
H'FFFF
GRA
GRB
H'0000
Time
FTIOA
Toggle
output
FTIOB
Toggle
output
Figure 10.6 Toggle Output Example (TOA = 0, TOB = 1)
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Section 10 Timer W
The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a
signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can
take place on the rising edge, falling edge, or both edges. By using the input-capture function, the
pulse width and periods can be measured. Figure 10.7 shows an example of input capture when
both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates
as a free-running counter.
TCNT value
H'FFFF
H'F000
H'AA55
H'55AA
H'1000
H'0000
Time
FTIOA
GRA
H'1000
H'F000
H'55AA
FTIOB
GRB
H'AA55
Figure 10.7 Input Capture Operating Example
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Section 10 Timer W
Figure 10.8 shows an example of buffer operation when the GRA is set as an input-capture
register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter,
and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation,
the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
TCNT value
H'FFFF
H'DA91
H'5480
H'0245
H'0000
Time
FTIOA
GRA
H'0245
GRC
H'5480
H'DA91
H'0245
H'5480
Figure 10.8 Buffer Operation Example (Input Capture)
10.4.2
PWM Operation
In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB,
GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and
FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register
functions as an output compare register automatically. The output level of each pin depends on the
corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the
FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the
FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare
match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode.
If the same value is set in the cycle register and the duty register, the output does not change when
a compare match occurs.
Figure 10.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT
is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D
(TOB, TOC, and TOD = 1: initial output values are set to 1).
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Section 10 Timer W
TCNT value
Counter cleared by compare match A
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 10.9 PWM Mode Example (1)
Figure 10.10 shows another example of operation in PWM mode. The output signals go to 0 and
TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and
D (TOB, TOC, and TOD = 0: initial output values are set to 0).
TCNT value
Counter cleared by compare match A
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 10.10 PWM Mode Example (2)
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Section 10 Timer W
Figure 10.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
GRB
H'0520
H'0450
H'0200
Time
H'0000
GRD
GRB
H'0450
H'0200
H'0200
H'0520
H'0450
H'0520
FTIOB
Figure 10.11 Buffer Operation Example (Output Compare)
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Section 10 Timer W
Figures 10.12 and 10.13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.
TCNT value
Write to GRB
GRA
GRB
Write to GRB
H'0000
Time
Duty 0%
FTIOB
TCNT value
Write to GRB
GRA
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Write to GRB
Write to GRB
GRB
H'0000
Time
Duty 100%
FTIOB
TCNT value
Write to GRB
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
GRA
Write to GRB
Write to GRB
GRB
H'0000
FTIOB
Time
Duty 100%
Duty 0%
Figure 10.12 PWM Mode Example
(TOB, TOC, and TOD = 0: initial output values are set to 0)
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Section 10 Timer W
TCNT value
Write to GRB
GRA
GRB
Write to GRB
H'0000
Time
Duty 100%
FTIOB
TCNT value
Write to GRB
GRA
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Write to GRB
Write to GRB
GRB
H'0000
Time
Duty 0%
FTIOB
TCNT value
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Write to GRB
GRA
Write to GRB
Write to GRB
GRB
H'0000
Time
Duty 0%
FTIOB
Duty 100%
Figure 10.13 PWM Mode Example
(TOB, TOC, and TOD = 1: initial output values are set to 1)
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Section 10 Timer W
10.5
Operation Timing
10.5.1
TCNT Count Timing
Figure 10.14 shows the TCNT count timing when the internal clock source is selected. Figure
10.15 shows the timing when the external clock source is selected. The pulse width of the external
clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted
correctly.
φ
Internal
clock
Rising edge
TCNT input
clock
TCNT
N
N+1
N+2
Figure 10.14 Count Timing for Internal Clock Source
φ
External
clock
Rising edge
Rising edge
TCNT input
clock
TCNT
N
N+1
N+2
Figure 10.15 Count Timing for External Clock Source
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Section 10 Timer W
10.5.2
Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when
TCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TIOR is output at the compare match output pin (FTIOA,
FTIOB, FTIOC, or FTIOD).
When TCNT matches GR, the compare match signal is generated only after the next counter clock
pulse is input.
Figure 10.16 shows the output compare timing.
φ
TCNT input
clock
TCNT
N
GRA to GRD
N
N+1
Compare
match signal
FTIOA to FTIOD
Figure 10.16 Output Compare Output Timing
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Section 10 Timer W
10.5.3
Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 10.17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
φ
Input capture
input
Input capture
signal
N–1
TCNT
N
N+1
N+2
N
GRA to GRD
Figure 10.17 Input Capture Input Signal Timing
10.5.4
Timing of Counter Clearing by Compare Match
Figure 10.18 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N + 1.
φ
Compare
match signal
TCNT
N
GRA
N
H'0000
Figure 10.18 Timing of Counter Clearing by Compare Match
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Section 10 Timer W
10.5.5
Buffer Operation Timing
Figures 10.19 and 10.20 show the buffer operation timing.
φ
Compare
match signal
N+1
TCNT
N
GRC, GRD
M
M
GRA, GRB
Figure 10.19 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
GRA, GRB
M
GRC, GRD
N+1
N
N+1
M
N
Figure 10.20 Buffer Operation Timing (Input Capture)
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Section 10 Timer W
10.5.6
Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Figure 10.21 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
N
GRA to GRD
N
N+1
Compare
match signal
IMFA to IMFD
IRRTW
Figure 10.21 Timing of IMFA to IMFD Flag Setting at Compare Match
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Section 10 Timer W
10.5.7
Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
10.22 shows the timing of the IMFA to IMFD flag setting at input capture.
φ
Input capture
signal
TCNT
N
N
GRA to GRD
IMFA to IMFD
IRRTW
Figure 10.22 Timing of IMFA to IMFD Flag Setting at Input Capture
10.5.8
Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 10.23 shows the status flag clearing timing.
TSRW write cycle
T1
T2
φ
TSRW address
Address
Write signal
IMFA to IMFD
IRRTW
Figure 10.23 Timing of Status Flag Clearing by CPU
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Section 10 Timer W
10.6
Timer W Operating Modes
Table 10.3 shows the timer W operating modes.
Table 10.3 Timer W Operating Modes
Active
Medium-
Sleep
Oscillation Stabilization Time
Clock
High-
High-
Medium-
Source
speed speed
speed
speed
Watch active
Sub-
Subsleep
Standby Active
Standby to Subsleep to Watch to
Active
Active
FTCI
ο
ο
ο
ο
×
ο
ο
×
×
×
×
φw, φw/4,
ο
ο
ο
ο
×
ο
ο
×
×
×
×
φ, φ/2, φ/4, ο
ο
ο
ο
×
×
×
×
×
×
×
φw/16
φ/8
[Legend]
10.7
ο: Counting enabled
×: Counting disabled (Counter value retained)
Usage Notes
The following types of contention or operation can occur in timer W operation.
1. The pulse width of the input clock signal and the input capture signal must be at least two
system clock cycles; shorter pulses will not be detected correctly. The system clock described
here indicates the clock set for the CPU operation. For example, in the φw/8 operation, at least
φw x 16 clock cycles are required as the pulse width.
2. Writing to registers is performed in the T2 state of a TCNT write cycle.
If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 10.24. If counting-up is
generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes
precedence.
3. Depending on the timing, TCNT may be incremented by a switch between different internal
clock sources. When TCNT is internally clocked, an increment pulse is generated from the
rising edge of an internal clock signal, that is, the divided system clock (φ). Therefore, as
shown in figure 10.25 the switch is from a low clock signal to a high clock signal, the
switchover is seen as a rising edge, causing TCNT to increment.
4. If timer W enters module standby mode while an interrupt request is generated, the interrupt
request cannot be cleared. Before entering module standby mode, disable interrupt requests.
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Section 10 Timer W
5. When an input capture function is specified, inputting a valid edge to the FTIOA to FTIOD
pins sets the status bit of the corresponding TSRW, even if the CTS bit in TMRW is 0
(counting disabled state). When the relevant interrupt is enabled, this inputting generates an
interrupt.
6. When the input capture timing conflicts with the corresponding GRA to GRD write timing,
a. the written values are reflected in GRA to GRD.
b. the status flag of the corresponding TSRW is set.
7. When the input capture timing conflicts with the GRA to GRD read timing, the read values are
ones before capturing. The captured values can be read one clock after the capturing.
8. When the input capture A or B conflicts with the GRC or GRD write timing as the input
capture operation in buffer mode,
a. the captured values are reflected in GRA or GRB.
b. the written values are reflected in GRC or GRD. (The values in GRC or GRD are not ones
in GRA or GRB before capturing.)
9. When the compare match timing conflicts with the GRA to GRD write timing as the compare
match operation,
a. the written values are reflected in GRA to GRD.
b. the FTIOA to FTIOD output changes by the compare match.
10. When the compare match A or B conflicts with the GRA or GRB write timing as the compare
match operation in buffer mode,
a. the written values are reflected in GRA or GRB. (The values in GRA or GRB are not ones
in GRC or GRD of the buffer register.)
b. the FTIOA or FTIOB output changes by the compare match.
11. When the compare match A or B conflicts with the GRC or GRD write timing as the compare
match operation in buffer mode,
a. the values in GRA or GRB are ones in GRC or GRD before writing.
b. the FTIOA or FTIOB output changes by the compare match.
12. When GRC or GRD is specified to the compare match output as the compare match operation
in buffer mode, FTIOC or FTIOD output changes by the GRC or GRD compare match.
13. When φw, φw/4, φw/16, or FTCI input is selected as the count clock, counting is enabled even
in subactive and subsleep modes. Counting is disabled during the oscillation stabilization time
in transition to the active mode.
14. When φw, φw/4, φw/16, or FTCI input is selected as the count clock, counting is enabled in
active and sleep modes although counting may be misaligned by one in transition from the
active to subactive mode.
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Section 10 Timer W
TCNT write cycle
T2
T1
φ
TCNT address
Address
Write signal
Counter clear
signal
N
TCNT
H'0000
Figure 10.24 Contention between TCNT Write and Clear
Previous clock
New clock
Count clock
TCNT
N
N+1
N+2
N+3
The change in signal level at clock switching is
assumed to be a rising edge, and TCNT
increments the count.
Figure 10.25 Internal Clock Switching and TCNT Operation
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Section 10 Timer W
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Section 11 Realtime Clock (RTC)
Section 11 Realtime Clock (RTC)
The realtime clock (RTC) is a timer used to count time ranging from a second to a week.
Interrupts can be generated ranging from 0.25 seconds to a week. Figure 11.1 shows the block
diagram of the RTC.
11.1
•
•
•
•
•
•
•
•
Features
Counts seconds, minutes, hours, and day-of-week
Start/stop function
Reset function
Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes
Periodic (0.25 seconds, 0.5 seconds, one second, minute, hour, day, and week) interrupts
8-bit free running counter
Selection of clock source
Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The RTC is operating as the initial value. For details, refer to section 5.4,
Module Standby Function.)
RTC3000A_000120030300
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Section 11 Realtime Clock (RTC)
RTCCSR
PSS
32-kHz
oscillator
circuit
RSECDR
1/4
RHRDR
TMOW
Clock count
control circuit
RWKDR
Internal data bus
RMINDR
RTCCR1
RTCCR2
RTCFLG
Interrupt
control circuit
[Legend]
RTCCSR:
RSECDR:
RMINDR:
RHRDR:
RWKDR:
RTCCR1:
RTCCR2:
RTCFLG:
PSS:
Clock source select register
Second date register/free running counter data register
Minute date register
Hour date register
Day-of-week date register
RTC control register 1
RTC control register 2
RTC interrupt flag register
Prescaler S
Figure 11.1 Block Diagram of RTC
11.2
Input/Output Pin
Table 11.1 shows the pin configuration of the RTC.
Table 11.1 Pin Configuration
Name
Abbreviation I/O
Function
Clock output
TMOW
RTC divided clock output
Output
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Interrupt
Section 11 Realtime Clock (RTC)
11.3
Register Descriptions
The RTC has the following registers.
•
•
•
•
•
•
•
•
Second data register/free running counter data register (RSECDR)
Minute data register (RMINDR)
Hour data register (RHRDR)
Day-of-week data register (RWKDR)
RTC control register 1 (RTCCR1)
RTC control register 2 (RTCCR2)
Clock source select register (RTCCSR)
RTC interrupt flag register (RTCFLG)
11.3.1
Second Data Register/Free Running Counter Data Register (RSECDR)
RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit
read register used as a counter, when it operates as a free running counter. For more information
on reading seconds, minutes, hours, and day-of-week, see section 11.4.3, Data Reading Procedure.
Bit
Bit Name
Initial
Value
R/W
7
BSY
—/(0)*
R
Description
RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6
SC12
—/(0)*
R/W
Counting Ten's Position of Seconds
5
SC11
—/(0)*
R/W
Counts on 0 to 5 for 60-second counting.
4
SC10
—/(0)*
R/W
3
SC03
—/(0)*
R/W
Counting One's Position of Seconds
2
SC02
—/(0)*
R/W
1
SC01
—/(0)*
R/W
Counts on 0 to 9 once per second. When a carry is
generated, 1 is added to the ten's position.
0
SC00
—/(0)*
R/W
Note:
*
Initial value after a reset caused by the RST bit in RTCCR1.
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Section 11 Realtime Clock (RTC)
11.3.2
Minute Data Register (RMINDR)
RMINDR counts the BCD-coded minute value on the carry generated once per minute by the
RSECDR counting. The setting range is decimal 00 to 59.
Bit
Bit Name
Initial
Value
R/W
Description
7
BSY
—/(0)*
R
RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6
MN12
—/(0)*
R/W
Counting Ten's Position of Minutes
5
MN11
—/(0)*
R/W
Counts on 0 to 5 for 60-minute counting.
4
MN10
—/(0)*
R/W
3
MN03
—/(0)*
R/W
Counting One's Position of Minutes
2
MN02
—/(0)*
R/W
1
MN01
—/(0)*
R/W
Counts on 0 to 9 once per minute. When a carry is
generated, 1 is added to the ten's position.
0
MN00
—/(0)*
R/W
Note:
*
Initial value after a reset caused by the RST bit in RTCCR1.
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Section 11 Realtime Clock (RTC)
11.3.3
Hour Data Register (RHRDR)
RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR.
The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in
RTCCR1.
Bit
Bit Name
Initial
Value
R/W
Description
7
BSY
—/(0)*
R
RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6
—
0
—
Reserved
This bit is always read as 0.
5
HR11
—/(0)*
R/W
Counting Ten's Position of Hours
4
HR10
—/(0)*
R/W
Counts on 0 to 2 for ten's position of hours.
3
HR03
—/(0)*
R/W
Counting One's Position of Hours
2
HR02
—/(0)*
R/W
1
HR01
—/(0)*
R/W
Counts on 0 to 9 once per hour. When a carry is
generated, 1 is added to the ten's position.
0
HR00
—/(0)*
R/W
Note:
*
Initial value after a reset caused by the RST bit in RTCCR1.
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Section 11 Realtime Clock (RTC)
11.3.4
Day-of-Week Data Register (RWKDR)
RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by
RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0.
Bit
Bit Name
Initial
Value
R/W
Description
7
BSY
—/(0)*
R
RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6 to 3
—
All 0
—
Reserved
These bits are always read as 0.
2
WK2
—/(0)*
R/W
Day-of-Week Counting
1
WK1
—/(0)*
R/W
Day-of-week is indicated with a binary code
0
WK0
—/(0)*
R/W
000: Sunday
001: Monday
010: Tuesday
011: Wednesday
100: Thursday
101: Friday
110: Saturday
111: Reserved (setting prohibited)
Note:
*
Initial value after a reset caused by the RST bit in RTCCR1.
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Section 11 Realtime Clock (RTC)
11.3.5
RTC Control Register 1 (RTCCR1)
RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see
figure 11.2.
Bit
Bit Name
Initial
Value
R/W
Description
7
RUN
—/(0)*
R/W
6
12/24
—/(0)*
R/W
5
PM
—/(0)*
R/W
4
RST
0
R/W
3
INT
—/(0)*
R/W
RTC Operation Start
0: Stops RTC operation
1: Starts RTC operation
Operating Mode
0: RTC operates in 12-hour mode. RHRDR counts on 0
to 11.
1: RTC operates in 24-hour mode. RHRDR counts on 0
to 23.
A.M./P.M.
0: Indicates a.m. when RTC is in the 12-hour mode.
1: Indicates p.m. when RTC is in the 12-hour mode.
Reset
0: Normal operation
1: Resets registers and control circuits except RTCCSR
and this bit. Clear this bit to 0 after having been set to
1.
Interrupt Occurrence Timing
0: Periodic interrupts of second, minute, hour, and day-ofweek occur during the RTC busy period.
1: Periodic interrupts of second, minute, hour, and day-ofweek occur immediately after the RTC busy period
finishes.
2 to 0
—
All 0
—
Note:
*
Reserved
These bits are always read as 0.
Initial value after a reset caused by the RST bit in RTCCR1.
Noon
24-hour count
12-hour count
PM
0
0
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
0 (Morning)
9 10 11 12 13 14 15 16 17
9 10 11 0 1 2 3 4 5
1 (Afternoon)
24-hour count 18 19 20 21 22 23 0
12-hour count 6 7 8 9 10 11 0
1 (Afternoon)
0
PM
Figure 11.2 Definition of Time Expression
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Section 11 Realtime Clock (RTC)
11.3.6
RTC Control Register 2 (RTCCR2)
RTCCR2 controls RTC periodic interrupts of week, day, hour, minute, one second, 0.5 seconds,
and 0.25 seconds. Enabling interrupts of week, day, hour, minute, one second, 0.5 seconds, and
0.25 seconds sets the corresponding flag to 1 in the RTC interrupt flag register (RTCFLG) when
an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC
operates as a free running counter.
Bit
Bit Name
Initial
Value
R/W
Description
7
FOIE
—/(0)*
R/W
Free Running Counter Overflow Interrupt Enable
0: Disables an overflow interrupt
1: Enables an overflow interrupt
6
WKIE
—/(0)*
R/W
Week Periodic Interrupt Enable
0: Disables a week periodic interrupt
1: Enables a week periodic interrupt
5
DYIE
—/(0)*
R/W
Day Periodic Interrupt Enable
0: Disables a day periodic interrupt
1: Enables a day periodic interrupt
4
HRIE
—/(0)*
R/W
Hour Periodic Interrupt Enable
0: Disables an hour periodic interrupt
1: Enables an hour periodic interrupt
3
MNIE
—/(0)*
R/W
Minute Periodic Interrupt Enable
0: Disables a minute periodic interrupt
1: Enables a minute periodic interrupt
2
1SEIE
—/(0)*
R/W
One-Second Periodic Interrupt Enable
0: Disables a one-second periodic interrupt
1: Enables a one-second periodic interrupt
1
05SEIE
—/(0)*
R/W
0.5-Second Periodic Interrupt Enable
0: Disables a 0.5-second periodic interrupt
1: Enables a 0.5-second periodic interrupt
0
025SEIE
—/(0)*
R/W
0.25-Second Periodic Interrupt Enable
0: Disables a 0.25-second periodic interrupt
1: Enables a 0.25-second periodic interrupt
Note:
*
Initial value after a reset caused by the RST bit in RTCCR1.
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Section 11 Realtime Clock (RTC)
11.3.7
Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by
the RUN bit in RTCCR1. When a clock other than φW/4 is selected, the RTC is disabled and
operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter,
RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the
FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock
generated by dividing the system clock by 32, 16, 8, or 4 is output in active or sleep mode. φW is
output in active, sleep, subactive, subsleep, or watch mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0.
6
RCS6
0
R/W
Clock Output Selection
5
RCS5
0
R/W
4
SUB32K
0
R/W
Select a clock output from the TMOW pin when enabling
TMOW output in PMR1.
000: φ/4
010: φ/8
100: φ/16
110: φ/32
xx1: φW
3
RCS3
1
R/W
Clock Source Selection
2
RCS2
0
R/W
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1
RCS1
0
R/W
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0
RCS0
0
R/W
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1000: φW/4⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ RTC operation
1001 to 1111: Setting prohibited
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Section 11 Realtime Clock (RTC)
11.3.8
RTC Interrupt Flag Register (RTCFLG)
RTCFLG sets the corresponding flag when an interrupt occurs. Each flag is not cleared
automatically even if the interrupt is accepted. To clear the flag, 0 should be written to the flag.
Bit
7
Bit Name
FOIFG
Initial
Value
R/W
1
—/(0)*
Description
2
R/(W)* [Setting condition]
When a free running counter overflows
[Clearing condition]
0 is written to FOIFG when FOIFG = 1
6
WKIFG
1
—/(0)*
2
R/(W)* [Setting condition]
When a week periodic interrupt occurs
[Clearing condition]
0 is written to WKIFG when WKIFG = 1
5
DYIFG
1
—/(0)*
2
R/(W)* [Setting condition]
When a day periodic interrupt occurs
[Clearing condition]
0 is written to DYIFG when DYIFG = 1
4
HRIFG
1
—/(0)*
2
R/(W)* [Setting condition]
When an hour periodic interrupt occurs
[Clearing condition]
0 is written to HRIFG when HRIFG = 1
3
MNIFG
1
—/(0)*
2
R/(W)* [Setting condition]
When a minute periodic interrupt occurs
[Clearing condition]
0 is written to MNIFG when MNIFG = 1
2
1SEIFG
—/(0)*1
R/(W)*2 [Setting condition]
When a one-second periodic interrupt occurs
[Clearing condition]
0 is written to 1SEIFG when 1SEIFG = 1
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Section 11 Realtime Clock (RTC)
Bit
1
Bit Name
05SEIFG
Initial
Value
R/W
1
—/(0)*
Description
2
R/(W)* [Setting condition]
When a 0.5-second periodic interrupt occurs
[Clearing condition]
0 is written to 05SEIFG when 05SEIFG = 1
0
1
025SEIFG —/(0)*
2
R/(W)* [Setting condition]
When a 0.25-second periodic interrupt occurs
[Clearing condition]
0 is written to 025SEIFG when 025SEIFG = 1
Notes: 1. Initial value after a reset caused by the RST bit in RTCCR1.
2. Only 0 can be written to clear the flag.
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Section 11 Realtime Clock (RTC)
11.4
Operation
11.4.1
Initial Settings of Registers after Power-On
The RTC registers that store second, minute, hour, and day-of-week data, control registers, and
interrupt registers are not reset by a RES input, or by a reset source caused by a watchdog timer.
Therefore, all registers must be set to their initial values after power-on. Once the register setting
are made, the RTC provides an accurate time as long as power is supplied regardless of a RES
input.
11.4.2
Initial Setting Procedure
Figure 11.3 shows the procedure for the initial setting of the RTC. To set the RTC again, also
follow this procedure.
RUN in RTCCR1 = 0
RTC operation is stopped.
RST in RTCCR1 = 1
RTC registers and clock count
controller are reset.
RST in RTCCR1 = 0
Set RTCCSR, RSECDR,
RMINDR, RHRDR,
RWKDR, 12/24 in
RTCCR1, and PM
RUN in RTCCR1 = 1
Clock output and clock source are
selected and second, minute, hour,
day-of-week, operating mode, and
a.m/p.m are set.
RTC operation is started.
Figure 11.3 Initial Setting Procedure
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Section 11 Realtime Clock (RTC)
11.4.3
Data Reading Procedure
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read,
the data obtained may not be correct, and so the time data must be read again. Figure 11.4 shows
an example in which correct data is not obtained. In this example, since only RSECDR is read
after data update, about 1-minute inconsistency occurs.
To avoid reading in this timing, the following processing must be performed.
1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the
second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY
bit is set to 1, the registers are updated, and the BSY bit is cleared to 0.
2. When INT in RTCCR1 is cleared to 0 and an interrupt is used, read from the second, minute,
hour, and day-of-week registers after the relevant flag in RTCFLG is set to 1 and the BSY bit
is confirmed to be 0.
When INT in RTCCR1 is set to 1 and an interrupt is used, read from the second, minute, hour,
and day-of-week registers after the relevant flag in RTCFLG is set to 1.
3. Read from the second, minute, hour, and day-of-week registers twice in a row, and if there is
no change in the read data, the read data is used.
Before update
RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59
Processing flow
BSY bit = 0
(1) Day-of-week data register read
H'03
(2) Hour data register read
H'13
(3) Minute data register read
H'46
BSY bit -> 1 (under data update)
After update
RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00
BSY bit -> 0
(4) Second data register read
H'00
Figure 11.4 Example: Reading of Inaccurate Time Data
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Section 11 Realtime Clock (RTC)
11.5
Interrupt Sources
There are eight kinds of RTC interrupts: a free-running counter overflow, week interrupt, day
interrupt, hour interrupt, minute interrupt, one-second interrupt, 0.5-second interrupt, and 0.25second interrupt.
When using an interrupt, set the IENRTC (RTC interrupt request enable) bit in IENR1 to 1 last
after other registers are set.
When an interrupt request of the RTC occurs, the corresponding flag in RTCFLG is set to 1. When
clearing the flag, write 0.
Table 11.2 Interrupt Sources
Interrupt Name
Interrupt Source
Interrupt Enable Bit
Overflow interrupt
Occurs when the free running counter is
overflowed.
FOIE
Week periodic interrupt
Occurs every week when the day-of-week date WKIE
register value becomes 0.
Day periodic interrupt
Occurs every day when the day-of-week date
register is counted.
Hour periodic interrupt
Occurs every hour when the hour date register HRIE
is counted.
Minute periodic interrupt
Occurs every minute when the minute date
register is counted.
MNIE
One-second periodic
interrupt
Occurs every second when the one-second
date register is counted.
1SEIE
0.5-second periodic
interrupt
Occurs every 0.5 seconds.
05SEIE
0.25-second periodic
interrupt
Occurs every 0.25 seconds.
025SEIE
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DYIE
Section 11 Realtime Clock (RTC)
11.6
Usage Notes
11.6.1
Note on Clock Count
The subclock must be connected to the 32.768-kHz resonator. When the 38.4-kHz resonator etc. is
connected, the correct time count is not possible.
11.6.2
Note when Using RTC Interrupts
The RTC registers are not reset by a RES input, power-on, or overflow of the watchdog timer, and
their values are undefined after power-on.
When using RTC interrupts, make sure to initialize the values before setting the IENRTC bit in
IENR1 to 1.
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Section 11 Realtime Clock (RTC)
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Section 12 Watchdog Timer
Section 12 Watchdog Timer
This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an
internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus
allowing it to overflow.
When this watchdog timer function is not needed, the WDT can be used as an interval timer. In
interval timer operation, an interval timer interrupt is generated each time the counter overflows.
12.1
Features
The WDT features are described below.
• Selectable from eleven counter input clocks
Ten internal clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φW/16,
and φW/256) or the on-chip oscillator (ROSC/2048) can be selected as the timer-counter clock.
• Watchdog timer mode
If the counter overflows, this LSI is internally reset.
• Interval timer mode
If the counter overflows, an interval timer interrupt is generated.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The WDT is operating as the initial value. For details, refer to section 5.4,
Module Standby Function.)
WDT0110A_000020020200
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Section 12 Watchdog Timer
Figure 12.1 shows a block diagram of the WDT.
ROSC
On-chip
oscillator
φ
PSS
TCSRWD1
TCWD
Internal data bus
TMWD
TCSRWD2
[φw/16 or φw/256]
Interrupt/reset control
[Legend]
TCSRWD1:
TCSRWD2:
TCWD:
TMWD:
PSS:
Timer control/status register WD1
Timer control/status register WD2
Timer counter WD
Timer mode register WD
Prescaler S
Figure 12.1 Block Diagram of Watchdog Timer
12.2
Register Descriptions
The watchdog timer has the following registers.
•
•
•
•
Timer control/status register WD1 (TCSRWD1)
Timer control/status register WD2 (TCSRWD2)
Timer counter WD (TCWD)
Timer mode register WD (TMWD)
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Internal reset signal or
interrupt request signal
Section 12 Watchdog Timer
12.2.1
Timer Control/Status Register WD1 (TCSRWD1)
TCSRWD1 performs the TCSRWD1 and TCWD write control. TCSRWD1 also controls the
watchdog timer operation and indicates the operating state. TCSRWD1 must be rewritten by using
the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit
Bit Name
Initial
Value
R/W
Description
7
B6WI
1
R/W
Bit 6 Write Inhibit
The TCWE bit can be written only when the write value of
the B6WI bit is 0.
This bit is always read as 1.
6
TCWE
0
R/W
Timer Counter WD Write Enable
TCWD can be written when the TCWE bit is set to 1.
When writing data to this bit, the write value for bit 7 must
be 0.
5
B4WI
1
R/W
Bit 4 Write Inhibit
The TCSRWE bit can be written only when the write
value of the B4WI bit is 0. This bit is always read as 1.
4
TCSRWE
0
R/W
Timer Control/Status Register WD Write Enable
The WDON and WRST bits can be written when the
TCSRWE bit is set to 1.
When writing data to this bit, the write value for bit 5 must
be 0.
3
B2WI
1
R/W
Bit 2 Write Inhibit
The WDON bit can be written only when the write value
of the B2WI bit is 0. This bit is always read as 1.
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Section 12 Watchdog Timer
Bit
Bit Name
Initial
Value
R/W
Description
2
WDON
1
R/W
Watchdog Timer On
TCWD starts counting up when the WDON bit is set to 1
and halts when the WDON bit is cleared to 0.
[Setting condition]
•
When 1 is written to the WDON bit and 0 to the B2WI
bit while the TCSRWE bit is 1
•
Reset by RES pin
[Clearing conditions]
•
1
B0WI
1
R/W
When 0 is written to the WDON bit and 0 to the B2WI
bit while the TCSRWE bit is 1
Bit 0 Write Inhibit
The WRST bit can be written only when the write value of
the B0WI bit is 0. This bit is always read as 1.
0
WRST
0
R/W
Watchdog Timer Reset
Indicates whether a reset caused by the watchdog timer
is generated. This bit is not cleared by a reset caused by
the watchdog timer.
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
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•
Reset by RES pin
•
When 0 is written to the WRST bit and 0 to the B0WI
bit while the TCSRWE bit is 1
Section 12 Watchdog Timer
12.2.2
Timer Control/Status Register WD2 (TCSRWD2)
TCSRWD2 performs the TCSRWD2 write control, mode switching, and interrupt control.
TCSRWD2 must be rewritten by using the MOV instruction. The bit manipulation instruction
cannot be used to change the setting value.
Bit
7
Bit Name
OVF
Initial
Value
0
R/W
Description
1
R/(W)* Overflow Flag
Indicates that TCWD has overflowed (changes from H'FF
to H'00).
[Setting condition]
When TCWD overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, this bit is cleared automatically by
the internal reset after it has been set.
[Clearing condition]
•
6
B5WI
1
When TCSRWD2 is read when OVF = 1, then 0 is
written to OVF
R/(W)*2 Bit 5 Write Inhibit
The WT/IT bit can be written only when the write value of
the B5WI bit is 0. This bit is always read as 1.
5
WT/IT
0
R/(W)*3 Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Watchdog timer mode
1: Interval timer mode
4
B3WI
1
2
R/(W)* Bit 3 Write Inhibit
The IEOVF bit can be written only when the write value of
the B3WI bit is 0. This bit is always read as 1.
3
IEOVF
0
R/(W)*3 Overflow Interrupt Enable
Enables or disables an overflow interrupt request in
interval timer mode.
0: Disables an overflow interrupt
1: Enables an overflow interrupt
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Section 12 Watchdog Timer
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0

All 1

Reserved
These bits are always read as 1.
Notes: 1. Only 0 can be written to clear the flag.
2. Write operation is necessary because this bit controls data writing to other bit. This bit is
always read as 1.
3. Writing is possible only when the write conditions are satisfied.
12.2.3
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD1 is set to 1. TCWD is initialized
to H'00.
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Section 12 Watchdog Timer
12.2.4
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

All 1

Reserved
These bits are always read as 1.
3
CKS3
0
R/W
Clock Select 3 to 0
2
CKS2
0
R/W
Select the clock to be input to TCWD.
1
CKS1
0
R/W
00xx: On-chip oscillator: counts on ROSC/2048
0
CKS0
0
R/W
0100: Internal clock: counts on φW/16
0101: Internal clock: counts on φW/256
011x: Reserved
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ8192
For the on-chip oscillator overflow periods, see section
21, Electrical Characteristics.
In active (medium-speed), sleep (medium-speed),
subactive, and subsleep modes, the 00xx value and the
interval timer mode cannot be set simultaneously.
In subactive and subsleep modes, when the subclock
frequency is φW/8, the 010x value and the interval timer
mode cannot be set simultaneously.
[Legend]
x: Don't care.
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Section 12 Watchdog Timer
12.3
12.3.1
Operation
Watchdog Timer Mode
The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear
the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is
written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in
TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write
accesses to TCSRWD1 are required.) When a clock pulse is input after the TCWD count value has
reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal
reset signal is output for a period of 512 clock cycles by the on-chip oscillator (ROSC). TCWD is a
writable counter, and when a value is set in TCWD, the count-up starts from that value. An
overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the
TCWD set value.
Figure 12.2 shows an example of watchdog timer operation.
Example:
With 30-ms overflow period when φ = 4 MHz
4 × 106
8192
× 30 × 10–3 = 14.6
Therefore, 256 – 15 = 241 (H'F1) is set in TCWD.
TCWD overflow
H'FF
H'F1
TCWD
count value
H'00
Start
H'F1 written
to TCWD
H'F1 written to TCWD
Reset generated
Internal reset
signal
512 clock cycles by Rosc
Figure 12.2 Example of Watchdog Timer Operation
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Section 12 Watchdog Timer
12.3.2
Interval Timer Mode
Figure 12.3 shows the operation in interval timer mode. To use the WDT as an interval timer, set
the WT/IT bit in TCSRWD2 to 1.
When the WDT is used as an interval timer, an interval timer interrupt request is generated each
time the TCWD overflows. Therefore, an interval timer interrupt can be generated at intervals.
H'FF
TCWD
count value
Time
H'00
WT/IT = 1
Interval timer
Interval timer
Interval timer
Interval timer
Interval timer
interrupt
interrupt
interrupt
interrupt
interrupt
request generated request generated request generated request generated request generated
Figure 12.3 Interval Timer Mode Operation
12.3.3
Timing of Overflow Flag (OVF) Setting
Figure 12.4 shows the timing of the OVF flag setting. The OVF flag in TCSRWD2 is set to 1 if
TCWD overflows. At the same time, a reset signal is output in watchdog timer mode and an
interval timer interrupt is generated in interval timer mode.
φ
H'FF
TCWD
H'00
Overflow signal
OVF
Figure 12.4 Timing of OVF Flag Setting
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Section 12 Watchdog Timer
12.4
Interrupt
During interval timer mode operation, an overflow generates an interval timer interrupt. The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSRWD2. The OVF
flag must be cleared to 0 in the interrupt handling routine.
12.5
12.5.1
Usage Notes
Switching between Watchdog Timer Mode and Interval Timer Mode
If modes are switched between watchdog timer and interval timer, while the WDT is operating, an
error may occur in the count value. Software must stop the watchdog timer (by clearing the
WDON bit to 0) before switching modes.
12.5.2
Module Standby Mode Control
The WDCKSTP bit in CKSTPR2 is valid when the WDON bit in the timer control/status register
WD1 (TCSRWD1) is cleared to 0. The WDCKSTP bit can be cleared to 0 while the WDON bit is
set to 1 (while the watchdog timer is operating). However, the watchdog timer does not enter
module standby mode but continues operating. When the WDON bit is cleared to 0 by software
after the watchdog timer stops operating, the WDCKSTP bit is valid at the same time and the
watchdog timer enters module standby mode.
12.5.3
Clearing the WT/IT or IEOVF Bit in TCSRWD2 to 0
When clearing the WT/IT or IEOVF bit in the timer control/status register WD2 (TCSRWD2) to
0, the corresponding bit may not be cleared to 0 depending on the program address. In particular,
if lower two bits in the address of the MOV.B instruction to transfer a value to TCSRWD2 are
B'10, the WT/IT or IEOVF bit is successfully cleared to 0, whereas if lower two bits in the address
are B'00, the WT/IT or IEOVF bit may not be cleared to 0. To avoid this failure, make sure to use
the assembly program shown in table 12.1, when clearing the WT/IT or IEOVF bit to 0. Specify
TCSRWD2 by the 8-bit absolute address, and LABEL by the 16-bit absolute address. Don't
change nor add instructions. The value of "xx" in line 1 and line 4 must be set according to table
12.2. Use an arbitrary 8-bit general register for Rn and Rm. In addition, Address1 in table 12.1
shows an example when the WT/IT or IEOVF bit is cleared to 0 successfully by the MOV.B
instruction in line 2. Address2 in table 12.1 shows an example when the WT/IT or IEOVF bit fails
to be cleared to 0 by the MOV.B instruction in line 2, but cleared to 0 by the MOV.B instruction
in line 6.
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Section 12 Watchdog Timer
Table 12.1 Assembly Program for Clearing WT/IT or IEOVF Bit to 0
Address1 Address2 Assembly Program
H'00A0
H'0232
MOV.B #H'xx,Rn
H'00A2
H'0234
MOV.B Rn,@TCSRWD2:8 ; Clear success in case of Address1
and failure in case of Address2
H'00A4
H'0236
MOV.B @TCSRWD2:8,Rm ; TCSRWD2 read
H'00A6
H'0238
AND.B #H'xx,Rm
; Judgment of clear
H'00A8
H'023A
BEQ
; Jumps to LABEL if it is a clear
success
H'00AC
H'023E
MOV.B Rn,@TCSRWD2:8 ; Clear success in case of Address2
H'00AE
H'0240
LABEL:16
LABEL NOP
Table 12.2 The Value of "xx"
Bit(s) Cleared to 0
The Value of "xx" in Line 1
The Value of "xx" in Line 4
Both WT/IT and IEOVF
07
28
Only WT/IT
17
20
Only IEOVF
47
08
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Section 12 Watchdog Timer
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Section 13 Asynchronous Event Counter (AEC)
Section 13 Asynchronous Event Counter (AEC)
The asynchronous event counter (AEC) is an event counter that is incremented by external event
clock or internal clock input. Figure 13.1 shows a block diagram of the asynchronous event
counter.
13.1
Features
• Can count asynchronous events
Can count external events input asynchronously without regard to the operation of system
clocks (φ) or subclocks (φSUB).
• Can be used as two-channel independent 8-bit event counter or single-channel independent 16bit event counter.
• Event/clock input is enabled when IRQAEC goes high or event counter PWM output
(IECPWM) goes high.
• Both rising and falling edge sensing can be used for IRQAEC or event counter PWM output
(IECPWM) interrupts. When the asynchronous counter is not used, they can be used as
independent interrupts.
• When an event counter PWM is used, event clock input enabling/disabling can be controlled at
a constant cycle.
An event counter PWM can be output to the AECPWM pin.
• Selection of four clock sources
Three internal clocks (φ/2, φ/4, or φ/8) or external event can be selected.
• Both rising and falling edge counting is possible for the AEVL and AEVH pins.
• Counter resetting and halting of the count-up function can be controlled by software.
• Automatic interrupt generation on detection of an event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The asynchronous event counter is halted as the initial value. For details, refer
to section 5.4, Module Standby Function.)
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Section 13 Asynchronous Event Counter (AEC)
IRREC
φ
ECCR
PSS
ECCSR
φ/2
φ/4, φ/8
OVH
ECH
(8 bits)
CK
ECL
(8 bits)
CK
AEVH
OVL
Edge sensing
circuit
AEVL
IRQAEC
Edge sensing
circuit
To CPU interrupt
(IRREC2)
IECPWM
AECPWM
ECPWCR
PWM waveform
generator
φw/16
φ/2, φ/4,
φ/8, φ/16,
φ/32, φ/64
ECPWDR
AEGSR
[Legend]
ECPWCR:
ECPWDR:
AEGSR:
ECCSR:
Event counter PWM compare register
Event counter PWM data register
Input pin edge select register
Event counter control/status register
ECL:
ECCR:
ECH:
PSS:
Event counter L
Event counter control register
Event counter H
Prescaler s
Figure 13.1 Block Diagram of Asynchronous Event Counter
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Internal data bus
Edge sensing
circuit
Section 13 Asynchronous Event Counter (AEC)
13.2
Input/Output Pins
Table 13.1 shows the pin configuration of the asynchronous event counter.
Table 13.1 Pin Configuration
Name
Abbreviation I/O
Function
Asynchronous event AEVH
input H
Input
Event input pin for input to event counter H
Asynchronous event AEVL
input L
Input
Event input pin for input to event counter L
Event input enable
interrupt input
Input
Input pin for interrupt enabling event input
Output
Event counter PWM output pin
IRQAEC
Event counter PWM AECPWM
output
13.3
Register Descriptions
The asynchronous event counter has the following registers.
•
•
•
•
•
•
•
Event counter PWM compare register (ECPWCR)
Event counter PWM data register (ECPWDR)
Input pin edge select register (AEGSR)
Event counter control register (ECCR)
Event counter control/status register (ECCSR)
Event counter H (ECH)
Event counter L (ECL)
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Section 13 Asynchronous Event Counter (AEC)
13.3.1
Event Counter PWM Compare Register (ECPWCR)
ECPWCR sets the one conversion period of the event counter PWM waveform.
Bit
Bit Name
Initial
Value
R/W
Description
15
ECPWCR15
1
R/W
14
ECPWCR14
1
R/W
One Conversion Period of Event Counter PWM
Waveform
13
ECPWCR13
1
R/W
12
ECPWCR12
1
R/W
11
ECPWCR11
1
R/W
10
ECPWCR10
1
R/W
9
ECPWCR9
1
R/W
8
ECPWCR8
1
R/W
7
ECPWCR7
1
R/W
6
ECPWCR6
1
R/W
5
ECPWCR5
1
R/W
4
ECPWCR4
1
R/W
3
ECPWCR3
1
R/W
2
ECPWCR2
1
R/W
1
ECPWCR1
1
R/W
0
ECPWCR0
1
R/W
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When the ECPWME bit in AEGSR is 1, the event
counter PWM is operating and therefore ECPWCR
should not be modified.
When changing the conversion period, the event
counter PWM must be halted by clearing the ECPWME
bit in AEGSR to 0 before modifying ECPWCR.
Section 13 Asynchronous Event Counter (AEC)
13.3.2
Event Counter PWM Data Register (ECPWDR)
ECPWDR controls data of the event counter PWM waveform generator.
Bit
Bit Name
Initial
Value
R/W
Description
15
ECPWDR15
0
W
14
ECPWDR14
0
W
Data Control of Event Counter PWM Waveform
Generator
13
ECPWDR13
0
W
12
ECPWDR12
0
W
11
ECPWDR11
0
W
10
ECPWDR10
0
W
9
ECPWDR9
0
W
8
ECPWDR8
0
W
7
ECPWDR7
0
W
6
ECPWDR6
0
W
5
ECPWDR5
0
W
4
ECPWDR4
0
W
3
ECPWDR3
0
W
2
ECPWDR2
0
W
1
ECPWDR1
0
W
0
ECPWDR0
0
W
When the ECPWME bit in AEGSR is 1, the event
counter PWM is operating and therefore ECPWDR
should not be modified.
When changing the conversion cycle, the event
counter PWM must be halted by clearing the ECPWME
bit in AEGSR to 0 before modifying ECPWDR.
The read value is undefined.
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Section 13 Asynchronous Event Counter (AEC)
13.3.3
Input Pin Edge Select Register (AEGSR)
AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins, and
controls IRQAEC/IECPWM.
Bit
Bit Name
Initial
Value
R/W
Description
7
AHEGS1
0
R/W
AEC Edge Select H
6
AHEGS0
0
R/W
Select rising, falling, or both edge sensing for the AEVH
pin.
00: Falling edge on AEVH pin is sensed
01: Rising edge on AEVH pin is sensed
10: Both edges on AEVH pin are sensed
11: Setting prohibited
5
ALEGS1
0
R/W
AEC Edge Select L
4
ALEGS0
0
R/W
Select rising, falling, or both edge sensing for the AEVL
pin.
00: Falling edge on AEVL pin is sensed
01: Rising edge on AEVL pin is sensed
10: Both edges on AEVL pin are sensed
11: Setting prohibited
3
AIEGS1
0
R/W
IRQAEC Edge Select
2
AIEGS0
0
R/W
Select rising, falling, or both edge sensing for the
IRQAEC pin.
00: Falling edge on IRQAEC pin is sensed
01: Rising edge on IRQAEC pin is sensed
10: Both edges on IRQAEC pin are sensed
11: Setting prohibited
1
ECPWME
0
R/W
Event Counter PWM Enable
Controls operation of event counter PWM and selection
of IRQAEC.
0: AEC PWM halted, IRQAEC selected
1: AEC PWM enabled, IRQAEC not selected
0

0
R/W
Reserved
Although this bit is readable/writable, only 0 should be
written to.
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Section 13 Asynchronous Event Counter (AEC)
13.3.4
Event Counter Control Register (ECCR)
ECCR controls the counter input clock and PWM clock.
Bit
Bit Name
Initial
Value
R/W
Description
7
ACKH1
0
R/W
AEC Clock Select H
6
ACKH0
0
R/W
Select the clock used by ECH.
00: AEVH pin input
01: φ/2
10: φ/4
11: φ/8
5
ACKL1
0
R/W
AEC Clock Select L
4
ACKL0
0
R/W
Select the clock used by ECL.
00: AEVL pin input
01: φ/2
10: φ/4
11: φ/8
3
PWCK2
0
R/W
Event Counter PWM Clock Select
2
PWCK1
0
R/W
Select the event counter PWM clock.
1
PWCK0
0
R/W
000: φ/2
001: φ/4
010: φ/8
011: φ/16
100: φ/32
101: φ/64
110: φW/16
111: Setting prohibited
When changing the event counter PWM clock, the
ECPWME bit in AEGSR must be cleared to 0 to stop
the PWM before rewriting this setting.
0

0
R/W
Reserved
Although this bit is readable/writable, only 0 should be
written to.
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Section 13 Asynchronous Event Counter (AEC)
13.3.5
Event Counter Control/Status Register (ECCSR)
ECCSR controls counter overflow detection, counter resetting, and count-up function.
Bit
Bit Name
Initial
Value
R/W
Description
7
OVH
0
R/W*
Counter Overflow H
This is a status flag indicating that ECH has overflowed.
[Setting condition]
When ECH overflows from H’FF to H’00
[Clearing condition]
When this bit is written to 0 after reading OVH = 1
6
OVL
0
R/W*
Counter Overflow L
This is a status flag indicating that ECL has overflowed.
[Setting condition]
When ECL overflows from H'FF to H'00 while CH2 is
set to 1
[Clearing condition]
When this bit is written to 0 after reading OVL = 1
5

0
R/W
Reserved
Although this bit is readable/writable, only 0 should be
written to.
4
CH2
0
R/W
Channel Select
Selects how ECH and ECL event counters are used
0: ECH and ECL are used together as a single-channel
16-bit event counter
1: ECH and ECL are used as two-channel 8-bit event
counter
3
CUEH
0
R/W
Count-Up Enable H
Enables event clock input to ECH.
0: ECH event clock input is disabled (ECH value is
retained)
1: ECH event clock input is enabled
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Section 13 Asynchronous Event Counter (AEC)
Bit
Bit Name
Initial
Value
R/W
Description
2
CUEL
0
R/W
Count-Up Enable L
Enables event clock input to ECL.
0: ECL event clock input is disabled (ECL value is
retained)
1: ECL event clock input is enabled
1
CRCH
0
R/W
Counter Reset Control H
Controls resetting of ECH.
0: ECH is reset
1: ECH reset is cleared and count-up function is
enabled
0
CRCL
0
R/W
Counter Reset Control L
Controls resetting of ECL.
0: ECL is reset
1: ECL reset is cleared and count-up function is
enabled
Note:
*
Only 0 can be written to clear the flag.
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Section 13 Asynchronous Event Counter (AEC)
13.3.6
Event Counter H (ECH)
ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH
also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination
with ECL.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECH7
0
R
6
ECH6
0
R
5
ECH5
0
R
4
ECH4
0
R
Either the external asynchronous event AEVH pin, φ/2,
φ/4, or φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source.
ECH can be cleared to H'00 when the CRCH bit in
ECCSR is cleared to 0.
3
ECH3
0
R
2
ECH2
0
R
1
ECH1
0
R
0
ECH0
0
R
13.3.7
Event Counter L (ECL)
ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL
also operates as the lower 8-bit up-counter of a 16-bit event counter configured in combination
with ECH.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECL7
0
R
6
ECL6
0
R
5
ECL5
0
R
Either the external asynchronous event AEVL pin, φ/2,
φ/4, or φ/8 can be selected as the input clock source.
ECL can be cleared to H'00 when the CRCL bit in
ECCSR is cleared to 0.
4
ECL4
0
R
3
ECL3
0
R
2
ECL2
0
R
1
ECL1
0
R
0
ECL0
0
R
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Section 13 Asynchronous Event Counter (AEC)
13.4
13.4.1
Operation
16-Bit Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected
with bits ALEGS1 and ALEGS0.
Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 13.2 shows the software procedure when ECH and ECL are used as a 16-bit event
counter.
Start
Clear CH2 to 0
Set ACKL1, ACKL0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 13.2 Software Procedure when Using ECH and ECL as 16-Bit Event Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to B′00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing).
When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and
ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL
count values each return to H'00, and counting up is restarted. When an overflow occurs, the
IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is
sent to the CPU.
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Section 13 Asynchronous Event Counter (AEC)
13.4.2
8-Bit Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is
selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits
ALEGS1 and ALEGS0 when AEVL pin input is selected.
Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 13.3 shows the software procedure when ECH and ECL are used as 8-bit event
counters.
Start
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0,
AHEGS1, AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 13.3 Software Procedure when Using ECH and ECL as 8-Bit Event Counters
When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH
flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted.
Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows,
the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is
restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2
is 1 at this time, an interrupt request is sent to the CPU.
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Section 13 Asynchronous Event Counter (AEC)
13.4.3
IRQAEC Operation
When the ECPWME bit in AEGSR is 0, the ECH and ECL input clocks are enabled when
IRQAEC goes high. When IRQAEC goes low, the input clocks are not input to the counters, and
so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from
outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
interrupt request flag IRREC2 in IRR1 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIEGS1
and AIEGS0 in AEGSR.
13.4.4
Event Counter PWM Operation
When the ECPWME bit in AEGSR is 1, the ECH and ECL input clocks are enabled when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically by controlling event counter PWM. In this case, ECH and ECL cannot be
controlled individually.
IECPWM can also operate as an interrupt source.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
interrupt request flag IRREC2 in IRR1 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIEGS1 and AIEGS0 in AEGSR.
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Section 13 Asynchronous Event Counter (AEC)
Figure 13.4 and table 13.2 show examples of event counter PWM operation.
ton:
toff:
toff = T × (Ndr +1)
Clock input enable time
Clock input disable time
tcm: One conversion period
T:
ECPWM input clock cycle
Ndr: Value of ECPWDR
ton
Ncm: Value of ECPWCR
tcm = T × (Ncm +1)
Figure 13.4 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this
condition, event counter PWM output (IECPWM) is fixed low.
Table 13.2 Examples of Event Counter PWM Operation
Conditions:
fOSC = 4 MHz, fφ = 4 MHz, fW = 32.768 kHz, fφW = 32.768 kHz, high-speed
active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3
Clock
Source
Selection
Clock
Source
Cycle (T)*
ECPWCR Value
(Ncm)
ECPWDR
Value (Ndr)
toff = T × (Ndr
+ 1)
tcm = T × (Ncm ton = tcm –
toff
+ 1)
φ/2
0.5 µs
H'7A11
H'16E3
2.93 ms
15.625 ms
12.695 ms
φ/4
1 µs
D'31249
D'5859
5.86 ms
31.25 ms
25.39 ms
φ/8
2 µs
11.72 ms
62.5 ms
50.78 ms
φ/16
4 µs
23.44 ms
125.0 ms
101.56 ms
φ/32
8 µs
46.88 ms
250.0 ms
203.12 ms
φ/64
16 µs
93.76 ms
500.0 ms
406.24 ms
φW/16
488 µs
2861.59 ms
15260.19 ms
12398.60 ms
Note:
*
toff minimum width
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Section 13 Asynchronous Event Counter (AEC)
13.4.5
Operation of Clock Input Enable/Disable Function
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1.
As this function forcibly terminates the clock input by each signal, a maximum error of one count
will occur depending on the IRQAEC or IECPWM timing. Figure 13.5 shows an example of the
operation.
Input event
IRQAEC or
IECPWM
Edge generated by clock return
Actually counted
clock source
Counter value
N
N+1
N+2
N+3
N+4
N+5
N+6
Clock stopped
Figure 13.5 Example of Clock Control Operation
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Section 13 Asynchronous Event Counter (AEC)
13.5
Operating States of Asynchronous Event Counter
The operating states of the asynchronous event counter are shown in table 13.3.
Table 13.3 Operating States of Asynchronous Event Counter
Active
Sleep
Clock
High-
Medium
High-
Counter
Source
speed
-speed
speed speed
ECH,
AEVH,
ο
ο
ο
ECL
AEVL
φ/2, φ/4, ο
ο
ο
φ/2, φ/4, ο
Oscillation Stabilization Time
Standby
Subsleep Watch
to
to
to
Standby
Active
Active
Active
Remarks
ο
ο
ο
ο
ο
*
×
×
×
×
×
×
ο
ο
ο
×
×
ο
ο
×
×
×`
×
×
×
×
Medium-
Sub-
Sub-
Watch
active
sleep
ο
ο
ο
ο
ο
×
ο
ο
ο
ο
ο
ο
1
φ/8
PWM
φw/16
φ/8,
φ/16,
φ/32,
φ/64
ο: Counting enabled
×: Counting disabled (Counter value retained)
Notes: 1. The count-up function is enabled only when IRQAEC/IECPWM = 1.
2. Output is in the high-impedance state during standby mode or the oscillation
stabilization time from standby mode.
[Legend]
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2
*
Section 13 Asynchronous Event Counter (AEC)
13.6
Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in
8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the
counter. The correct value will not be returned if the event counter increments while being
read.
2. For input to the AEVH and AEVL pins, use a clock with a frequency of up to 4.2 MHz within
the range from 1.8 to 3.6 V and up to 10 MHz within the range from 2.7 to 3.6 V. For the high
and low widths of the clock, see section 21, Electrical Characteristics. The duty cycle is
arbitrary.
Table 13.4 Maximum Clock Frequency
Mode
Maximum Clock Frequency
Input to AEVH/AEVL Pin
Active (high-speed), sleep (high-speed)
4 to 10 MHz (2.7 to 3.6 V)
2 to 4.2 MHz (1.8 to 3.6 V)
Active (medium-speed), sleep (medium-speed)
(φOSC/8) 2 · fOSC
(φOSC/16) fOSC
fOSC = 4 MHz to 10 MHz (2.7 to 3.6 V)
(φOSC/32) 1/2 · fOSC
fOSC = 2 MHz to 4.2 MHz (1.8 to 3.6 V)
(φOSC/64) 1/4 · fOSC
Watch, subactive, subsleep, standby
φW = 32.768 kHz or 38.4 kHz
(φW)
2000 kHz
(φW/2)
1000 kHz
(φW/4)
500 kHz
(φW/8)
250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1
second, or set both CUEH and CRCH to 1 at same time before clock input. When AEC is
operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR
and ECPWDR should not be modified.
When changing the data, clear the ECPWME bit in AEGSR to 0 (halt the event counter PWM)
before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
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Section 13 Asynchronous Event Counter (AEC)
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc or 1tsubcyc will occur between clock halting and interrupt
acceptance.
7. When pins in port 1 are used for AEC input/output, the PFCR and PMR1 registers should be
set in the following order.
a. Set the PFCR register.
b. Set bits 4 to 0 after bit 5 (IRQAEC bit) in the PMR1 register has been cleared to 0.
c. Set bit 5 (IRQAEC bit) in the PMR1 register to 1. At this time, bits 4 to 0 should not be
changed and remain the same.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
The serial communication interface 3 (SCI3) can handle both asynchronous and clock
synchronous serial communication. In the asynchronous method, serial data communication can
be carried out using standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface
Adapter (ACIA).
The SCI3 can transmit and receive IrDA communication waveforms based on the Infrared Data
Association (IrDA) standard version 1.0.
14.1
Features
• Choice of asynchronous or clock synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• On-chip baud rate generator, internal clock, or external clock can be selected as a transfer
clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The SCI3 is halted as the initial value. For details, refer to section 5.4, Module
Standby Function.)
Asynchronous mode
•
•
•
•
•
Data length: 7, 8, or 5 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RXD3 pin level directly in the case of a
framing error
SCI0012A_000020020900
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Clock synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Note: When using serial communication interface 3, the system clock oscillator or subclock
oscillator must be used.
Figure 14.1 shows a block diagram of the SCI3.
SCK3
External clock
Baud rate generator
BRC3
Internal clock
(φ/64, φ/16, φw, φ)
BRR3
Clock
Transmit/receive
control circuit
SMR3
SCR3
SSR3
TSR3
TDR3
RSR3
RDR3
Internal data bus
SEMR
SPCR
TXD3
IrCR
RXD3
[Legend]
RSR3: Receive shift register 3
RDR3: Receive data register 3
TSR3: Transmit shift register 3
TDR3: Transmit data register 3
SMR3: Serial mode register 3
SCR3: Serial control register 3
SSR3: Serial status register 3
BRR3: Bit rate register 3
BRC3: Bit rate counter 3
SPCR: Serial port control register
IrDA control register
IrCR:
SEMR: Serial extended mode register
Figure 14.1 Block Diagram of SCI3
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Interrupt request
(TEI3, TXI3, RXI3, ERI3)
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.2
Input/Output Pins
Table 14.1 shows the pin configuration of the SCI3.
Table 14.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
SCI3 clock
SCK3
I/O
SCI3 clock input/output
SCI3 receive data input
RXD3
Input
SCI3 receive data input
SCI3 transmit data output
TXD3
Output
SCI3 transmit data output
14.3
Register Descriptions
The SCI3 has the following registers for each channel.
•
•
•
•
•
•
•
•
•
•
•
Receive shift register 3 (RSR3)*
Receive data register 3 (RDR3)*
Transmit shift register 3 (TSR3)*
Transmit data register 3 (TDR3)*
Serial mode register 3 (SMR3)*
Serial control register 3 (SCR3)*
Serial status register 3 (SSR3)*
Bit rate register 3 (BRR3)*
Serial port control register (SPCR)
IrDA control register (IrCR)
Serial extended mode register (SEMR)
Note: * These register names are abbreviated to RSR, RDR, TSR, TDR, SMR, SCR, SSR, and
BRR in the text.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register that receives serial data input from the RXD3 pin and converts it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
14.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI3 has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
RDR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
14.3.3
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR automatically, then sends the data that starts from the
LSB to the TXD3 pin. Data transfer from TDR to TSR is not performed if no data has been
written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the CPU.
14.3.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
TDR is initialized to H'FF by a reset or in standby mode, watch mode, or module standby mode.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.5
Serial Mode Register (SMR)
SMR sets the SCI3’s serial communication format and selects the clock source for the on-chip
baud rate generator.
SMR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
COM
0
R/W
Communication Mode
0: Asynchronous mode
1: Clock synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous mode)
0: Selects 8 or 5 bits as the data length.
1: Selects 7 or 5 bits as the data length.
When 7-bit data is selected. the MSB (bit 7) in TDR is
not transmitted. To select 5 bits as the data length, set
1 to both the PE and MP bits. The three most significant
bits (bits 7, 6, and 5) in TDR are not transmitted. In
clock synchronous mode, the data length is fixed to 8
bits regardless of the CHR bit setting.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. In clock synchronous mode,
parity bit addition and checking is not performed
regardless of the PE bit setting.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Bit Name
Initial
Value
R/W
Description
4
PM
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
When even parity is selected, a parity bit is added in
transmission so that the total number of 1 bits in the
transmit data plus the parity bit is an even number, in
reception, a check is carried out to confirm that the
number of 1 bits in the receive data plus the parity bit is
an even number.
When odd parity is selected, a parity bit is added in
transmission so that the total number of 1 bits in the
transmit data plus the parity bit is an odd number, in
reception, a check is carried out to confirm that the
number of 1bits in the receive data plus the parity bit is
an odd number.
If parity bit addition and checking is disabled in clock
synchronous mode and asynchronous mode, the PM bit
setting is invalid.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit
is 0, it is treated as the start bit of the next transmit
character.
2
MP
0
R/W
5-Bit Communication
When this bit is set to 1, the 5-bit communication format
is enabled. Make sure to set bit 5 (PF) to 1 when setting
this bit (MP) to 1.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKS1
0
R/W
Clock Select 0 and 1
0
CKS0
0
R/W
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φW clock (n = 0)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
When the setting value is 01 in subactive mode or
subsleep mode, the SCI3 can be used only when φW is
selected for the CPU operating clock.
For the relationship between the bit rate register setting
and the baud rate, see section 14.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n
in BRR (see section 14.3.8, Bit Rate Register (BRR)).
14.3.6
Serial Control Register (SCR)
SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer
clock source. For details on interrupt requests, refer to section 14.7, Interrupt Requests.
SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, the TXI3 interrupt request is
enabled. TXI3 can be released by clearing the TDRE it
or TI bit to 0.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, the RXI3 and ERI3 interrupt
requests are enabled.
RXI3 and ERI3 can be released by clearing the RDRF
bit or the FER, PER, or OER error flag to 0, or by
clearing the RIE bit to 0.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Bit Name
Initial
Value
R/W
Description
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled. When
this bit is 0, the TDRE bit in SSR is fixed at 1. When
transmit data is written to TDR while this bit is 1, Bit
TDRE in SSR is cleared to 0 and serial data
transmission is started. Be sure to carry out SMR
settings, and setting of bit SPC3 in SPCR, to decide the
transmission format before setting bit TE to 1.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled. In this
state, serial data reception is started when a start bit is
detected in asynchronous mode or serial clock input is
detected in clock synchronous mode. Be sure to carry
out the SMR settings to decide the reception format
before setting bit RE to 1.
Note that the RDRF, FER, PER, and OER flags in SSR
are not affected when bit RE is cleared to 0, and retain
their previous state
3
MPIE
0
R/W
Reserved
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, the TEI3 interrupt request is
enabled. TEI3 can be released by clearing bit TDRE to
0 and clearing bit TEND to 0 in SSR, or by clearing bit
TEIE to 0.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKE1
0
R/W
Clock Enable 0 and 1
0
CKE0
0
R/W
Select the clock source.
Asynchronous mode:
00: Internal baud rate generator (SCK3 pin functions as
an I/O port)
01: Internal baud rate generator (Outputs a clock of the
same frequency as the bit rate from the SCK3 pin)
10: External clock (Inputs a clock with a frequency 16
times the bit rate from the SCK3 pin)
11: Reserved
Clock synchronous mode:
00: Internal clock (SCK3 pin functions as clock output)
01: Reserved
10: External clock (SCK3 pin functions as clock input)
11: Reserved
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.7
Serial Status Register (SSR)
SSR consists of status flags of the SCI3. 1 cannot be written to flags TDRE, RDRF, OER, PER,
and FER; they can only be cleared.
SSR is initialized to H'84 by a reset or in standby mode, watch mode, or module standby mode.
Bit
Bit Name
Initial
Value
R/W
7
TDRE
1
R/(W)* Transmit Data Register Empty
Description
Indicates that transmit data is stored in TDR.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR
[Clearing conditions]
6
RDRF
0
•
When 0 is written to TDRE after reading TDRE = 1
•
When the transmit data is written to TDR
R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
When data is read from RDR
If an error is detected in reception, or if the RE bit in
SCR has been cleared to 0, RDR and bit RDRF are not
affected and retain their previous state.
Note that if data reception is completed while bit RDRF
is still set to 1, an overrun error (OER) will occur and
the receive data will be lost.
Rev. 3.00 May 15, 2007 Page 240 of 516
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Bit Name
Initial
Value
R/W
5
OER
0
R/(W)* Overrun Error
Description
[Setting condition]
•
When an overrun error occurs in reception
[Clearing condition]
•
When 0 is written to OER after reading OER = 1
When bit RE in SCR is cleared to 0, bit OER is not
affected and retains its previous state.
When an overrun error occurs, RDR retains the receive
data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be
continued with bit OER set to 1, and in clock
synchronous mode, transmission cannot be continued
either.
4
FER
0
R/(W)* Framing Error
[Setting condition]
•
When a framing error occurs in reception
[Clearing condition]
•
When 0 is written to FER after reading FER = 1
When bit RE in SCR is cleared to 0, bit FER is not
affected and retains its previous state.
Note that, in 2-stop-bit mode, only the first stop bit is
checked for a value of 1, and the second stop bit is not
checked. When a framing error occurs, the receive data
is transferred to RDR but bit RDRF is not set.
Reception cannot be continued with bit FER set to 1. In
clock synchronous mode, neither transmission nor
reception is possible when bit FER is set to 1.
Rev. 3.00 May 15, 2007 Page 241 of 518
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit
Bit Name
Initial
Value
R/W
3
PER
0
R/(W)* Parity Error
Description
[Setting condition]
•
When a parity error is generated during reception
[Clearing condition]
•
When 0 is written to PER after reading PER = 1
When bit RE in SCR is cleared to 0, bit PER is not
affected and retains its previous state.
•
2
TEND
1
R
Receive data in which a parity error has occurred is
still transferred to RDR, but bit RDRF is not set.
Reception cannot be continued with bit PER set to
1. In clock synchronous mode, neither transmission
nor reception is possible when bit PER is set to 1.
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the transmit data is written to TDR
1
MPBR
0
R
Reserved
0
MPBT
0
R/W
Reserved
This bit is always read as 0 and cannot be modified.
The write value should always be 0.
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 242 of 516
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.8
Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF.
Tables 14.2 and 14.3 show the relationship between the N setting in BRR and the n setting in bits
CKS1 and CKS0 in SMR in asynchronous mode. Table 14.5 shows the maximum bit rate for each
frequency in asynchronous mode. The values shown in these tables are values in active (highspeed) mode. When the ABCS bit in SEMR is set to 1 in asynchronous mode, the maximum bit
rate in table 14.5 is doubled. Table 14.6 shows the relationship between the N setting in BRR and
the n setting in bits CKS1 and CKS0 in SMR in clock synchronous mode. The values shown in
table 14.6 are values in active (high-speed) mode. The N setting in BRR and error for other
operating frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode and ABCS Bit is 0]
N=
φ
–1
32 × 22n × B
Error (%) =
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 14.2)
R (bit rate in left-hand column in table 14.2)
× 100
[Asynchronous Mode and ABCS Bit is 1]
N=
φ
–1
16 × 22n × B
Error (%) =
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 14.3)
R (bit rate in left-hand column in table 14.3)
× 100
[Legend]
B:
Bit rate (bit/s)
N:
BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ:
Operating frequency (Hz)
n:
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 14.4)
Rev. 3.00 May 15, 2007 Page 243 of 518
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 0) (1)
32.8 kHz
Bit Rate
(bit/s)
n
110
150
38.4 kHz
2 MHz
2.097152 MHz
N
Error
(%)
n



0
6
−2.38
200
0
4
2.50
0
5
0.00
2
19
−2.34
2
19
2.40
250
0
3
2.50



0
249
0.00
2
15
2.40
300



0
3
0.00
0
207
0.16
0
217
0.21
600



0
1
0.00
0
103
0.16
0
108
0.21
1200



0
0
0.00
0
51
0.16
0
54
–0.70
2400






0
25
0.16
0
26
1.14
4800






0
12
0.16
0
13
–2.48
9600









0
6
–2.48
19200









—
—
—
31250






0
1
0.00
—
—
—
38400









—
—
—
N
Error
(%)
n
0
10
−0.83
0
7
0.00
N
Error
(%)
n
N
Error
(%)
2
35
−1.36
2
36
0.64
2
25
0.16
2
26
1.14
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 0) (2)
2.4576 MHz
3 MHz
3.6864 MHz
4 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
43
–0.83
2
52
0.50
2
64
0.70
2
70
0.03
150
2
31
0.00
2
38
0.16
2
47
0.00
2
51
0.16
200
2
23
0.00
2
28
1.02
2
35
0.00
2
38
0.16
250
2
18
1.05
2
22
1.90
2
28
–0.69
2
30
0.81
300
0
255
0.00
2
19
–2.34
2
23
0.00
2
25
0.16
600
0
127
0.00
0
155
0.16
0
191
0.00
0
207
0.16
1200
0
63
0.00
0
77
0.16
0
95
0.00
0
103
0.16
2400
0
31
0.00
0
38
0.16
0
47
0.00
0
51
0.16
4800
0
15
0.00
0
19
–2.34
0
23
0.00
0
25
0.16
9600
0
7
0.00
0
9
–2.34
0
11
0.00
0
12
0.16
19200
0
3
0.00
0
4
–2.34
0
5
0.00
—
—
—
31250
—
—
—
0
2
0.00
—
—
—
0
3
0.00
38400
0
1
0.00
—
—
—
0
2
0.00
—
—
—
Rev. 3.00 May 15, 2007 Page 244 of 516
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 0) (3)
4.194304 MHz
Bit Rate
(bit/s)
n
110
150
4.9152 MHz
N
Error
(%)
n
2
73
0.64
2
54
–0.70
200
2
40
250
2
32
300
2
600
0
1200
5 MHz
N
Error
(%)
n
2
86
0.31
2
63
0.00
–0.10
2
47
–0.70
2
37
26
1.14
2
217
0.21
0
0
108
0.21
2400
0
54
4800
0
26
9600
0
19200
31250
38400
6 MHz
N
Error
(%)
n
N
Error
(%)
2
88
–0.25
2
106
–0.44
2
64
0.16
2
77
0.16
0.00
2
48
–0.35
2
58
–0.69
1.05
2
38
0.16
2
46
-0.27
31
0.00
2
32
–1.36
2
38
0.16
255
0.00
2
15
1.73
2
19
–2.34
0
127
0.00
0
129
0.16
0
155
0.16
–0.70
0
63
0.00
0
64
0.16
0
77
0.16
1.14
0
31
0.00
0
32
–1.36
0
38
0.16
13
–2.48
0
15
0.00
0
15
1.73
0
19
–2.34
0
6
–2.48
0
7
0.00
0
7
1.73
0
9
–2.34
—
—
—
0
4
–1.70
0
4
0.00
0
5
0.00
—
—
—
0
3
0.00
0
3
1.73
0
4
–2.34
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 0) (4)
6.144 MHz
Bit Rate
(bit/s)
n
N
110
2
150
2
200
250
Error
(%)
7.3728 MHz
8 MHz
n
N
Error
(%)
n
N
108 0.08
2
130 –0.07
2
79
0.00
2
95
0.00
2
2
59
0.00
2
71
0.00
2
47
0.00
2
57
–0.69
300
2
39
0.00
2
47
0.00
600
2
19
0.00
2
23
0.00
1200
0
159 0.00
0
191 0.00
2400
0
79
0.00
0
95
0.00
4800
0
39
0.00
0
47
9600
0
19
0.00
0
23
19200
0
9
0.00
0
11
31250
0
5
2.40
— —
38400
0
4
0.00
0
5
Error
(%)
9.8304 MHz
10 MHz
n
N
Error
(%)
n
N
Error
(%)
141 0.03
2
174 –0.26
2
177 –0.25
103 0.16
2
127 0.00
2
129 0.16
2
77
0.16
2
95
0.00
2
97
2
62
-0.79
2
76
-0.26
2
77
0.16
2
51
0.16
2
63
0.00
2
64
0.16
2
25
0.16
2
31
0.00
2
32
–1.36
0
207 0.16
0
255 0.00
2
15
1.73
0
103 0.16
0
127 0.00
0
129 0.16
0.00
0
51
0.16
0
63
0.00
0
64
0.16
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
0.00
0
12
0.16
0
15
0.00
0
15
1.73
—
0
7
0.00
0
9
–1.70
0
9
0.00
0.00
—
—
—
0
7
0.00
0
7
1.73
–0.35
Rev. 3.00 May 15, 2007 Page 245 of 518
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 1) (1)
32.8 kHz
Bit Rate
(bit/s)
38.4 kHz
2 MHz
2.097152 MHz
n
N
Error
(%)
0
0
0
0
0
—
—
—
18
13
9
7
6
—
—
—
–1.91
–2.38
2.50
2.50
–2.38
—
—
—
0
0
0
—
0
0
0
0
21
15
11
—
7
3
1
0
-0.83
0.00
0.00
—
0.00
0.00
0.00
0.00
2
2
2
2
2
0
0
0
70
51
38
30
25
207
103
51
0.03
0.16
0.16
0.81
0.16
0.16
0.16
0.16
2
2
2
2
2
0
0
0
73
54
40
32
26
217
108
54
0.64
–0.70
–0.10
–0.70
1.14
0.21
0.21
-0.70
31250
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
—
0
25
12
—
3
0.16
0.16
—
0.00
0
0
0
—
26
13
6
—
1.14
–2.48
–2.48
—
38400
—
—
—
—
—
—
—
—
—
—
—
—
110
150
200
250
300
600
1200
2400
4800
9600
19200
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 1) (2)
2.4576 MHz
3 MHz
3.6864 MHz
4 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
150
200
250
300
600
1200
2400
2
2
2
2
2
0
0
0
86
63
47
37
31
255
127
63
0.31
0.00
0.00
1.05
0.00
0.00
0.00
0.00
2
2
2
2
2
2
0
0
106
77
58
46
38
19
155
77
–0.44
0.16
–0.69
–0.27
0.16
–2.34
0.16
0.16
2
2
2
2
2
2
0
0
130
95
71
57
47
23
191
95
-0.07
0.00
0.00
-0.69
0.00
0.00
0.00
0.00
2
2
2
2
2
2
0
0
141
103
77
62
51
25
207
103
0.03
0.16
0.16
–0.79
0.16
0.16
0.16
0.16
4800
9600
19200
31250
38400
0
0
0
0
0
31
15
7
4
3
0.00
0.00
0.00
–1.70
0.00
0
0
0
0
0
38
19
9
5
4
0.16
–2.34
–2.34
0.00
–2.34
0
0
0
—
0
47
23
11
—
5
0.00
0.00
0.00
—
0.00
0
0
0
0
—
51
25
12
7
—
0.16
0.16
0.16
0.00
—
Rev. 3.00 May 15, 2007 Page 246 of 516
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 1) (3)
4.194304 MHz
Bit Rate
(bit/s)
n
110
150
200
250
300
600
1200
2400
4.9152 MHz
N
Error
(%)
n
2
2
2
2
2
2
0
0
148
108
81
65
54
26
217
108
–0.04
0.21
–0.10
–0.70
–0.70
1.14
0.21
0.21
4800
9600
19200
31250
0
0
0
—
54
26
13
—
38400
0
6
5 MHz
N
Error
(%)
n
2
2
2
2
2
2
0
0
174
127
95
76
63
31
255
127
–0.26
0.00
0.00
–0.26
0.00
0.00
0.00
0.00
–0.70
1.14
–2.48
—
0
0
0
0
63
31
15
9
-2.48
0
7
6 MHz
N
Error
(%)
n
N
Error
(%)
2
2
2
2
2
2
2
0
177
129
97
77
64
32
15
129
–0.25
0.16
–0.35
0.16
0.16
–1.36
1.73
0.16
2
2
2
2
2
2
2
0
212
155
116
93
77
38
19
155
0.03
0.16
0.16
–0.27
0.16
0.16
–2.34
0.16
0.00
0.00
0.00
–1.70
0
0
0
0
64
32
15
9
0.16
–1.36
1.73
0.00
0
0
0
0
77
38
19
11
0.16
0.16
–2.34
0.00
0.00
0
7
1.73
0
9
–2.34
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and
ABCS Bit is 1) (4)
6.144 MHz
7.3728 MHz
8 MHz
9.8304 MHz
10 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
150
200
250
300
600
1200
2400
2
2
2
2
2
2
2
0
217
159
119
95
79
39
19
159
0.08
0.00
0.00
0.00
0.00
0.00
0.00
0.00
3
2
2
2
2
2
2
0
64
191
143
114
95
47
23
191
0.70
0.00
0.00
0.17
0.00
0.00
0.00
0.00
3
2
2
2
2
2
2
0
70
207
155
124
103
51
25
207
0.03
0.16
0.16
0.00
0.16
0.16
0.16
0.16
3
2
2
2
2
2
2
0
86
255
191
153
127
63
31
255
0.31
0.00
0.00
-0.26
0.00
0.00
0.00
0.00
3
3
2
2
2
2
2
2
88
64
194
155
129
64
32
15
–0.25
0.16
0.16
0.16
0.16
0.16
–1.36
1.73
4800
9600
19200
31250
38400
0
0
0
0
0
79
39
19
11
9
0.00
0.00
0.00
2.40
0.00
0
0
0
0
0
95
47
23
14
11
0.00
0.00
0.00
–1.70
0.00
0
0
0
0
0
103
51
25
15
12
0.16
0.16
0.16
0.00
0.16
0
0
0
0
0
127
63
31
19
15
0.00
0.00
0.00
–1.70
0.00
0
0
0
0
0
129
64
32
19
15
0.16
0.16
–1.36
0.00
1.73
Rev. 3.00 May 15, 2007 Page 247 of 518
REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.4 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φw*
0
1
2
φ/16
1
0
3
φ/64
1
1
Note:
*
In subactive or subsleep mode, the SCI3 can be operated only when the CPU operating
clock is φW.
Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate (bit/s)
Setting
φ (MHz)
ABCS = 0
ABCS = 1
n
N
0.0328*
1025
2050
0
0
0.0384*
1200
2400
0
0
2
62500
125000
0
0
2.097152
65536
131072
0
0
2.4576
76800
153600
0
0
3
93750
187500
0
0
3.6864
115200
230400
0
0
4
125000
250000
0
0
4.194304
131072
262144
0
0
4.9152
153600
307200
0
0
5
156250
312500
0
0
6
187500
375000
0
0
6.144
192000
384000
0
0
7.3728
230400
460800
0
0
8
250000
500000
0
0
9.8304
307200
614400
0
0
10
312500
625000
0
0
Note:
*
When CKS1 = 0 and CKS0 = 1 in SMR
Rev. 3.00 May 15, 2007 Page 248 of 516
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1)
φ
32.8 kHz
38.4 kHz
2 MHz
Bit Rate (bit/s)
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
200
0
40
0.00
0
47
0.00
2
155
0.16
250
0
32
−0.61
0
37
1.05
2
124
0.00
300
0
26
1.23
0
31
0.00
2
103
0.16
500
0
15
2.50
0
18
1.05
2
62
−0.79
1k
0
7
2.50



2
30
0.81
2.5k






0
199
0.00
5k






0
99
0.00
10k






0
49
0.00
25k






0
19
0.00
50k






0
9
0.00
100k






0
4
0.00
250k






0
1
0.00
500k






0*
0*
0.00*
1M









Note:
*
Continuous transmission/reception is not possible.
Rev. 3.00 May 15, 2007 Page 249 of 518
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2)
φ
4 MHz
Bit Rate (bit/s)
n
N
200
250
300
500
1k
2.5k
5k
10k
25k
50k
100k
250k
500k
1M
3
2
2
2
2
2
0
0
0
0
0
0
0
0*
77
0.16
249 0.00
207 0.16
124 0.00
62
−0.79
24
0.00
199 0.00
99
0.00
39
0.00
19
0.00
9
0.00
3
0.00
1
0.00
0*
0.00*
Note:
Error (%)
8 MHz
n
N
3
3
3
2
2
2
2
0
0
0
0
0
0
0
155 0.16
124 0.00
103 0.16
249 0.00
124 0.00
49
0.00
24
0.00
199 0.00
79
0.00
39
0.00
19
0.00
7
0.00
3
0.00
1
0.00
Error (%)
10 MHz
n
N
Error (%)
3
3
3
3
2
2
2
0
0
0
0
0
0

194
155
129
77
155
62
30
249
99
49
24
9
4

0.16
0.16
0.16
0.16
0.16
−0.79
0.81
0.00
0.00
0.00
0.00
0.00
0.00

* Continuous transmission/reception is not possible.
The value set in BRR is given by the following formula:
N=
φ
–1
4 × 22n × B
B:
N:
φ:
n:
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (Hz)
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 14.7.)
Table 14.7 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
0
2
3
φ
φW*
φ/16
φ/64
0
0
1
1
0
1
0
1
Note:
*
In subactive or subsleep mode, the SCI3 can be operated only when the CPU operating
clock is φW.
Rev. 3.00 May 15, 2007 Page 250 of 516
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.9
Serial Port Control Register (SPCR)
SPCR selects the function of the TXD3 (IrTXD) pin and whether to invert the input/output data of
the RXD3 (IrRXD) and TXD3 (IrTXD) pins.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
5

0

Reserved
This bit is always read as 0 and cannot be modified.
4
SPC3
0
R/W
P32/TXD3/IrTXD Pin Function Switch
Selects whether pin P32/TXD3/IrTXD is used as P32 or
as TXD3/IrTXD.
0: P32 I/O pin
1: TXD3/IrTXD output pin
Set the TE bit in SCR after setting this bit to 1.
3, 2

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
1
SCINV1
0
R/W
TXD3/IrTXD Pin Output Data Inversion Switch
Selects whether output data of the TXD3/IrTXD pin is
inverted or not.
0: Output data of TXD3/IrTXD pin is not inverted.
1: Output data of TXD3/IrTXD pin is inverted.
0
SCINV0
0
R/W
RXD3/IrRXD Pin Input Data Inversion Switch
Selects whether input data of the RXD3/IrRXD pin is
inverted or not.
0: Input data of RXD3/IrRXD pin is not inverted.
1: Input data of RXD3/IrRXD pin is inverted.
Note: When the serial port control register is modified, the data being input or output up to that
point is inverted immediately after the modification, and an invalid data change is input or
output. When modifying the serial port control register, modification must be made in a state
in which data changes are invalidated.
Rev. 3.00 May 15, 2007 Page 251 of 518
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.10
IrDA Control Register (IrCR)
IrCR controls the IrDA operation of the SCI3.
Bit
Bit Name
Initial
Value
R/W
Description
7
IrE
0
R/W
IrDA Enable
Selects whether the SCI3 I/O pins function as the SCI3
or IrDA.
0: TXD3/IrTXD and RXD3/IrRXD pins function as TXD3
and RXD3
1: TXD3/IrTXD and RXD3/IrRXD pins function as IrTXD
and IrRXD
6
IrCKS2
0
R/W
IrDA Clock Select
5
IrCKS1
0
R/W
4
IrCKS0
0
R/W
If the IrDA function is enabled, these bits set the highpulse width when encoding the IrTXD output pulse.
000: Bit rate × 3/16
001: φ/2
010: φ/4
011: φ/8
100: φ/16
101: Setting prohibited
11x: Setting prohibited
3 to 0

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
[Legend] x: Don’t care.
Rev. 3.00 May 15, 2007 Page 252 of 516
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.11
Serial Extended Mode Register (SEMR)
SEMR sets the basic clock used in asynchronous mode.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
3
ABCS
0
R/W
Asynchronous Mode Basic Clock Select
Selects the basic clock for the bit period in
asynchronous mode.
This setting is enabled only in asynchronous mode
(COM bit in SMR3 is 0).
0: Operates on a basic clock with a frequency of 16
times the transfer rate
1: Operates on a basic clock with a frequency of eight
times the transfer rate
Clear the ABCS bit to 0, when the IrDA function is
enabled.
2 to 0

All 0

Reserved
These bits are always read as 0 and cannot be
modified.
14.4
Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling
edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a
frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.
When the ABCS bit in SEMR is 1, the data is sampled on the 4th pulse of a clock with a
frequency eight times the bit period. Inside the SCI3, the transmitter and receiver are independent
units, enabling full duplex. Both the transmitter and the receiver also have a double-buffered
structure, so data can be read or written during transmission or reception, enabling continuous data
transfer. Table 14.8 shows the 16 data transfer formats that can be set in asynchronous mode. The
format is selected by the settings in SMR as shown in table 14.9.
Rev. 3.00 May 15, 2007 Page 253 of 518
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
LSB
MSB
Serial Start
data
bit
Transmit/receive data
5, 7, or 8 bits
1 bit
1
Parity
bit
1 bit,
or none
Stop bit
Mark state
1 or
2 bits
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication
14.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock source, according to the setting of the
COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the
SCK3 pin, the clock frequency should be 16 times the bit rate used (when the ABCS bit in SEMR
is 1, the clock frequency should be eight times the bit rate used). For details on selection of the
clock source, see table 14.10. When the SCI3 is operated on an internal clock, the clock can be
output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate,
and the phase is such that the rising edge of the clock is in the middle of the transfer data, as
shown in figure 14.3.
Clock
Serial data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (frame)
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 3.00 May 15, 2007 Page 254 of 516
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.8 Data Transfer Formats (Asynchronous Mode)
SMR
Serial Data Transfer Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
START
8-bit data
STOP
0
0
0
1
START
8-bit data
STOP
STOP
0
0
1
0
Setting prohibited
0
0
1
1
Setting prohibited
0
1
0
0
START
8-bit data
P
STOP
0
1
0
1
START
8-bit data
P
STOP
0
1
1
0
START
5-bit data
STOP
0
1
1
1
START
5-bit data
STOP
1
0
0
0
START
7-bit data
STOP
1
0
0
1
START
7-bit data
STOP
STOP
1
0
1
0
Setting prohibited
1
0
1
1
Setting prohibited
1
1
0
0
START
7-bit data
P
STOP
1
1
0
1
START
7-bit data
P
STOP
1
1
1
0
START
5-bit data
P
STOP
1
1
1
1
START
5-bit data
P
STOP
2
3
4
5
6
7
8
9
10
11
12
STOP
STOP
STOP
STOP
[Legend]
START: Start bit
STOP:
Stop bit
P:
Parity bit
Rev. 3.00 May 15, 2007 Page 255 of 518
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.9 SMR Settings and Corresponding Data Transfer Formats
SMR
Data Transfer Format
Bit 7
Bit 6
Bit 2
Bit 5
Bit 3
COM
CHR
MP
PE
STOP
Mode
Data Length
Parity
Bit
0
0
0
0
0
Asynchronous
mode
8-bit data
No
1
1
0
0
Yes
0
7-bit data
No
1
0
1 bit
2 bits
Yes
0
1
0
1 bit
2 bits
1
1
1 bit
2 bits
1
1
Stop Bit
Length
1 bit
2 bits
0
Setting prohibited
1
1
5-bit data
0
No
1
0
1
1 bit
2 bits
0
Setting prohibited
1
1
0
5-bit data
Yes
1
1
x
[Legend]
0
x
x
x: Don’t care.
Rev. 3.00 May 15, 2007 Page 256 of 516
REJ09B0152-0300
1 bit
2 bits
Clock
synchronous
mode
8-bit data
No
No
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.10 SMR and SCR Settings and Clock Source Selection
SMR
SCR
Bit 7
Bit 1
Bit 0
COM
CKE1
CKE0
Mode
Clock Source
0
0
0
Asynchronous
mode
Internal
1
1
Transmit/Receive Clock
SCK Pin Function
I/O port (SCK3 pin not used)
Outputs a clock with the same
frequency as the bit rate
1
0
External
0
0
Inputs a clock with a frequency
16 times the bit rate*
1
0
Clock synchronous Internal
mode
External
0
1
1
Reserved (Do not specify these combinations)
1
0
1
1
1
1
Note:
*
Outputs the serial clock
Inputs the serial clock
When the ABCS bit in SEMR is 1, inputs a clock with a frequency eight times the bit
rate.
Rev. 3.00 May 15, 2007 Page 257 of 518
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.4.2
SCI3 Initialization
Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to
0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of
the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization. When the external
clock is used in clock synchronous mode, the clock must not be supplied during initialization.
Start initialization
[1]
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR3
[1]
Set data transfer format in SMR
[2]
Set value in BRR
[3]
Wait
No
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in clock
synchronous mode, clock is output
immediately after CKE1, CKE0, and RE
are set to 1.
[2]
Set the data transfer format in SMR.
[3]
Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4]
Wait at least one bit interval, then set the
TE bit or RE bit in SCR to 1. Setting bits
TE and RE enables the TXD3 and RXD3
pins to be used. Also set the RIE, TIE,
and TEIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
transmission and idled at reception to
wait for the start bit.
1-bit interval elapsed?
Yes
Set SPC3 bit in SPCR to 1
Set TE and RE bits in
SCR to 1, and set RIE, TIE
and TEIE bits.
<Initialization completion>
[4]
Set the clock selection in SCR.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
Figure 14.4 Sample SCI3 Initialization Flowchart
Rev. 3.00 May 15, 2007 Page 258 of 516
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.4.3
Data Transmission
Figure 14.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI3 interrupt request is
generated. Continuous transmission is possible because the TXI3 interrupt routine writes next
transmit data to TDR before transmission of the current transmit data has been completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
1 frame
Parity Stop Start
bit
bit bit
0/1
1
0
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
Mark
state
1
1 frame
TDRE
TEND
LSI
TXI3 interrupt
operation request
generated
User
processing
TDRE flag
cleared to 0
TXI3 interrupt request
generated
TEI3 interrupt request
generated
Data written
to TDR
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 3.00 May 15, 2007 Page 259 of 518
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission
[1]
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR. When data is written to TDR, the
TDRE flag is automatically cleared to 0.
(After the TE bit is set to 1, one frame of
1 is output, then transmission is
possible.)
[2]
To continue serial transmission, read 1
from the TDRE flag to confirm that
writing is possible, then write data to
TDR. When data is written to TDR, the
TDRE flag is automatically cleared to 0.
[3]
To output a break in serial transmission,
after setting PCR to 1 and PDR to 0,
clear the SPC3 bit in SPCR and the TE
bit in SCR to 0.
Set SPC3 bit in SPCR to 1
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR
Yes
[2]
All data transmitted?
No
Read TEND flag in SSR
Note: * When the SPC3 bit in SPCR is cleared to 0,
the pin functions as an I/O port.
No
TEND = 1
Yes
No
[3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
Clear SPC3 bit in SPCR and
TE bit in SCR to 0*
<End>
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
Rev. 3.00 May 15, 2007 Page 260 of 516
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.4.4
Serial Data Reception
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
• Parity check
The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or
even) set in bit PM in the serial mode register (SMR).
• Stop bit check
The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred
from RSR to RDR.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI3 interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is
generated. Continuous reception is possible because the RXI3 interrupt routine reads the
receive data transferred to RDR before reception of the next receive data has been completed.
Rev. 3.00 May 15, 2007 Page 261 of 518
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start
bit
Serial
data
1
0
Receive
data
D0
D1
Parity Stop Start
bit
bit bit
D7
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
Mark state
(idle state)
0
1
1 frame
RDRF
FER
LSI
operation
RXI3 interrupt
request
generated
User
processing
RDRF flag
cleared to 0
0 stop bit
detected
RDR data read
ERI request in
response to
framing error
Framing error
processing
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Table 14.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample
flowchart for serial data reception.
Table 14.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
OER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error
+ parity error
Note:
*
The RDRF flag retains the state it had before data reception. However, note that if RDR
is read after an overrun error has occurred in a frame because reading of the receive
data in the previous frame was delayed, the RDRF flag will be cleared to 0.
Rev. 3.00 May 15, 2007 Page 262 of 516
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start reception
Read OER, PER, and
FER flags in SSR
[1]
Yes
OER+PER+FER = 1
[4]
No
Error processing
(Continued on next page)
Read RDRF flag in SSR
[2]
No
RDRF = 1
Yes
Read receive data in RDR
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
[2] Read SSR and check that RDRF = 1,
then read the receive data in RDR.
The RDRF flag is cleared automatically.
[3] To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag and read
RDR.
The RDRF flag is cleared automatically.
[4] If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the OER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RXD3 pin.
Yes
All data received?
(A)
[3]
No
Clear RE bit in SCR to 0
<End>
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
[4]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and
FER flags in SSR to 0
<End>
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5
Operation in Clock Synchronous Mode
Figure 14.9 shows the general format for clock synchronous communication. In clock
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clock
synchronous serial communication, data on the transmission line is output from one falling edge of
the serial clock to the next. In clock synchronous mode, the SCI3 receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clock synchronous mode, no parity bit is added. Inside the SCI3, the transmitter and
receiver are independent units, enabling full-duplex communication through the use of a common
clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be
read or written during transmission or reception, enabling continuous data transfer.
8-bit
One unit of transfer data (character or frame)
*
*
Synchronization
clock
LSB
Bit 0
Serial data
MSB
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 14.9 Data Format in Clock Synchronous Communication
14.5.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR. When the SCI3 is operated on an internal clock, the
serial clock is output from the SCK3 pin. Eight serial clock pulses are output in the transfer of one
character, and when no transfer is performed the clock is fixed high.
14.5.2
SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 14.4.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.3
Serial Data Transmission
Figure 14.10 shows an example of SCI3 operation for transmission in clock synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data
has been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at
this time, a TXI3 interrupt request is generated.
3. 8-bit data is sent from the TXD3 pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD3
pin.
4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI3 interrupt
request is generated.
7. The SCK3 pin is fixed high.
Figure 14.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial
clock
Serial
data
Bit 0
Bit 1
Bit 7
Bit 0
1 frame
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
LSI
TXI3
operation interrupt
request
generated
User
processing
TDRE flag
cleared
to 0
TXI3 interrupt request
generated
TEI3 interrupt request
generated
Data written
to TDR
Figure 14.10 Example of SCI3 Operation in Transmission in Clock Synchronous Mode
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission
Set SPC3 bit in SPCR to 1
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
[2]
Yes
Write transmit data to TDR
[2]
All data transmitted?
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0. When clock
output is selected and data is written to
TDR, clocks are output to start the data
transmission.
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Yes
No
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Figure 14.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.4
Serial Data Reception (Clock Synchronous Mode)
Figure 14.12 shows an example of SCI3 operation for reception in clock synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronous clock input or
output, starts receiving data.
2. The SCI3 stores the received data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI3 interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is
generated.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
1 frame
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
User
processing
RXI3
interrupt
request
generated
RDRF flag
cleared
to 0
RDR data read
ERI3 interrupt request
generated by
overrun error
RXI3 interrupt
request generated
RDR data has
not been read
(RDRF = 1)
Overrun error
processing
Figure 14.12 Example of SCI3 Reception Operation in Clock Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart
for serial data reception.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start reception
[1]
[1]
Read OER flag in SSR
[2]
Yes
OER = 1?
[4]
No
Overrun error processing
[3]
(Continued below)
Read RDRF flag in SSR
[2]
[4]
No
RDRF = 1?
Yes
Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.
Read receive data in RDR
Yes
Data reception continued?
[3]
No
Clear RE bit in SCR to 0
<End>
[4]
Start overrun error processing
Overrun error processing
Clear OER flag in SSR to 0
<End>
Figure 14.13 Sample Serial Reception Flowchart (Clock Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.5
Simultaneous Serial Data Transmission and Reception
Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mode, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Start transmission/reception
Set SPC3 bit in SPCR to 1
Read TDRE flag in SSR
[1]
[1]
No
TDRE = 1
Yes
Write transmit data to TDR
Read OER flag in SSR
Yes
OER = 1
No
[4]
Overrun error processing
Read RDRF flag in SSR
[2]
No
RDRF = 1
Yes
Read receive data in RDR
Yes
Data transmission/reception
continued?
[3]
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[4] If an overrun error occurs, read the
OER flag in SSR, and after performing
the appropriate error processing, clear
the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 14.13.
No
Clear TE and RE bits in SCR to 0
<End>
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clock Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.6
IrDA Operation
IrDA operation can be used with the SCI3. Figure 14.15 shows an IrDA block diagram.
If the IrDA function is enabled using the IrE bit in IrCR, the TXD3 and RXD3 pins in the SCI3
are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function
as the IrTXD and IrRXD pins). Connecting these pins to the infrared data transceiver/receiver
achieves infrared data communication based on the system defined by the IrDA standard version
1.0.
In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate
of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not
incorporate the capability of automatic modification of the transfer rate; the transfer rate must be
modified through programming.
IrDA
TXD3/IrTXD
Phase inversion
Pulse encoder
RXD3/IrRXD
Phase inversion
Pulse decoder
SCI3
TXD
RXD
IrCR
Figure 14.15 IrDA Block Diagram
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.6.1
Transmission
During transmission, the output signals from the SCI3 (UART frames) are converted to IR frames
using the IrDA interface (see figure 14.16).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
IrCR.
According to the standard, the high-level pulse width is defined to be 1.41 µs at minimum and
(3/16 + 2.5%) × bit rate or (3/16 × bit rate) +1.08 µs at maximum. For example, when the
frequency of system clock φ is 10 MHz, being equal to or greater than 1.41 µs, the high-level pulse
width at minimum can be specified as 1.6 µs.
For serial data of level 1, no pulses are output.
UART frame
Data
Start
bit
0
1
0
1
0
0
Stop
bit
1
Transmission
1
0
1
Reception
IR frame
Data
Start
bit
0
1
Bit
cycle
0
1
0
0
Stop
bit
1
1
0
Pulse width is 1.6 µs to
3/16 bit cycle
Figure 14.16 IrDA Transmission and Reception
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1
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.6.2
Reception
During reception, IR frames are converted to UART frames using the IrDA interface before
inputting to the SCI3.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 µs, the
minimum width allowed, the pulse is recognized as level 0.
14.6.3
High-Level Pulse Width Selection
Table 14.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this
LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit
rate in transmission.
Table 14.12 IrCKS2 to IrCKS0 Bit Settings
Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row)
Operating
Frequency
2400
9600
19200
38400
φ (MHz)
78.13
19.53
9.77
4.88
2
010
010
010
010
2.097152
010
010
010
010
2.4576
010
010
010
010
3
011
011
011
011
3.6864
011
011
011
011
4.9152
011
011
011
011
5
011
011
011
011
6
100
100
100
100
6.144
100
100
100
100
7.3728
100
100
100
100
8
100
100
100
100
9.8304
100
100
100
100
10
100
100
100
100
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.7
Interrupt Requests
The SCI3 creates the following six interrupt requests: transmit end, transmit data empty, receive
data full, and receive errors (overrun error, framing error, and parity error). Table 14.13 shows the
interrupt sources.
Table 14.13 SCI3 Interrupt Requests
Interrupt Requests
Abbreviation
Interrupt Sources
Receive Data Full
RXI
Setting RDRF in SSR
Transmit Data Empty
TXI
Setting TDRE in SSR
Transmission End
TEI
Setting TEND in SSR
Receive Error
ERI
Setting OER, FER, and PER in SSR
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR.
When the TDRE bit in SSR is set to 1, a TXI3 interrupt is requested. When the TEND bit in SSR
is set to 1, a TEI3 interrupt is requested. These two interrupts are generated during transmission.
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR is set to 1 before
transferring the transmit data to TDR, a TXI3 interrupt request is generated even if the transmit
data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR
is set to 1 before transferring the transmit data to TDR, a TEI3 interrupt request is generated even
if the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent
the generation of these interrupt requests (TXI3 and TEI3), clear the enable bits (TIE and TEIE)
that correspond to these interrupt requests to 0, after transferring the transmit data to TDR.
When the RDRF bit in SSR is set to 1, an RXI3 interrupt is requested, and if any of bits OER,
PER, and FER is set to 1, an ERI3 interrupt is requested. These two interrupt requests are
generated during reception.
The SCI3 can carry out continuous reception using an RXI3 and continuous transmission using a
TXI3.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
These interrupts are shown in table 14.14.
Table 14.14 Transmit/Receive Interrupts
Interrupt
Flags
Interrupt Request Conditions
Notes
RXI3
RDRF
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, an
RXI3 is enabled and an interrupt is
requested. (See figure 14.17 (a).)
The RXI3 interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by repeating
the above operations until reception of the
next RSR data is completed.
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, a TXI3 is
enabled and an interrupt is requested.
(See figure 14.17 (b).)
The TXI3 interrupt routine writes the next
transmit data to TDR and clears bit TDRE
to 0. Continuous transmission can be
performed by repeating the above
operations until the data transferred to
TSR has been transmitted.
When the last bit of the character in TSR
is transmitted, if bit TDRE is set to 1, bit
TEND is set to 1. If bit TEIE is set to 1 at
this time, a TEI3 is enabled and an
interrupt is requested. (See figure 14.17
(c).)
A TEI3 indicates that the next transmit
data has not been written to TDR when
the last bit of the transmit character in
TSR is transmitted.
RIE
TXI3
TDRE
TIE
TEI31
TEND
TEIE
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
RDR
RDR
RSR (reception in progress)
↑
RSR (reception completed, transfer)
RXD3 pin
→
RXD3 pin
RDRF
RDRF = 0
1
(RXI3 request when RIE = 1)
Figure 14.17 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TDR
TSR (transmission in progress)
↓
TSR (transmission completed, transfer)
TXD3 pin
TXD3 pin
TDRE
→
TDRE = 0
1
(TXI3 request when TIE = 1)
Figure 14.17 (b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmission in progress)
TSR (transmission completed)
TXD3 pin
TEND = 0
TEND
→
TXD3 pin
1
(TEI3 request when TEIE = 1)
Figure 14.17 (c) TEND Setting and TEI Interrupt
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8
14.8.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD3 pin
value directly. In a break, the input from the RXD3 pin becomes all 0, setting the FER flag, and
possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a
break, even if the FER flag is cleared to 0, it will be set to 1 again.
14.8.2
Mark State and Break Sending
When the SPC3 bit in SPCR is 0, the TXD3 pin functions as an I/O port whose direction (input or
output) and level are determined by PCR and PDR, regardless of the TE setting. This can be used
to set the TXD3 pin to the mark state (high level) or send a break during data transmission. To
maintain the communication line at the mark state until the SPC3 bit in SPCR is set to 1, set both
PCR and PDR to 1. As the SPC3 bit in SPCR is cleared to 0 at this point, the TXD3 pin functions
as an I/O port, and 1 is output from the TXD3 pin. To send a break during data transmission, first
set PCR to 1 and PDR to 0, and then clear the SPC3 and TE bits to 0. When the TE bit is cleared
to 0 directly after the SPC3 bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state after the TE bit is cleared, the TXD3 pin functions as an I/O port after the SPC3
bit is cleared, and 0 is output from the TXD3 pin.
14.8.3
Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.18.
Thus, the reception margin in asynchronous mode is given by formula (1) below.


1
D – 0.5
M = (0.5 –
)–
– (L – 0.5) F × 100(%)
2N
N


Where N:
D:
L:
F:
... Formula (1)
Ratio of bit rate to clock (N = 16)
Clock duty (D = 0.5 to 1.0)
Frame length (L = 9 to 12)
Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RXD3)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.18 Receive Data Sampling Timing in Asynchronous Mode
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.5
Note on Switching SCK3 Pin Function
If the SCK3 pin is used as a clock output pin by the SCI3 in clock synchronous mode and is then
switched to a general input/output pin (a pin with a different function), the SCK3 pin outputs a
low level signal for half a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
(1)
When SCK3 Pin Function is Switched from Clock Output to Non Clock-Output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR to 1 and 0, respectively.
In this case, bit COM in SMR should be left 1. The above prevents the SCK3 pin from being used
as a general input/output pin. To avoid an intermediate level of voltage from being applied to the
SCK3 pin, the line connected to the SCK3 pin should be pulled up to the VCC level via a resistor, or
supplied with output from an external device.
(2)
When SCK3 Pin Function is Switched from Clock Output to General Input/Output
When stopping data transfer,
1. Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1
and 0, respectively.
2. Clear bit COM in SMR to 0
3. Clear bits CKE1 and CKE0 in SCR to 0. Note that special care is also needed here to avoid an
intermediate level of voltage from being applied to the SCK3 pin.
14.8.6
Relation between Writing to TDR and Bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet
been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably,
you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not
two or more times).
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.7
Relation between RDR Reading and bit RDRF
In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0
when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is
read more than once, the second and subsequent read operations will be performed while bit
RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0,
if the read operation coincides with completion of reception of a frame, the next frame of data may
be read. This is shown in figure 14.19.
Communication line
Frame 1
Frame 2
Frame 3
Data 1
Data 2
Data 3
Data 1
Data 2
RDRF
RDR
(A)
RDR read
(B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 14.19 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To be
precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clock
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.8
Transmit and Receive Operations when Making State Transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
14.8.9
Setting in Subactive or Subsleep Mode
In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is φW. The SA1 and
SA0 bits in SYSCR2 should be set to 1.
14.8.10
Oscillator when Serial Communication Interface 3 is Used
When serial communication interface 3 is used, the system clock oscillator or subclock oscillator
must be used. Do not use the on-chip oscillator. For details on selecting the system clock oscillator
or on-chip oscillator, see section 4.2.4, On-Chip Oscillator Selection Method. For details on
selecting the subclock oscillator or on-chip oscillator, see section 4.1.1, Oscillator Control
Register (OSCCR).
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Section 14 Serial Communication Interface 3 (SCI3, IrDA)
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Section 15 Synchronous Serial Communication Unit (SSU)
Section 15 Synchronous Serial Communication Unit (SSU)
The synchronous serial communication unit (SSU) can handle clocked synchronous serial data
communication.
Figure 15.1 shows a block diagram of the SSU.
15.1
Features
• Can be operated in clocked synchronous communication mode or four-line bus communication
mode (including bidirectional communication mode)
• Can be operated as a master or a slave device
• Choice of eight internal clocks (φ/256, φ/128, φ/64, φ/32, φ/16, φ/8, φ/4, and φSUB/2) and an
external clock as a clock source
• Clock polarity and phase of SSCK can be selected
• Choice of data transfer direction (MSB-first or LSB-first)
• Receive error detection: overrun error
• Multimaster error detection: conflict error
• Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and
conflict error
• Continuous transmission and reception of serial data are enabled since both transmitter and
receiver have buffer structure
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The SSU is halted as the initial value. For details, refer to section 5.4, Module
Standby Function.)
SCIAAU1A_000120030300
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Section 15 Synchronous Serial Communication Unit (SSU)
Internal clock
SSCK
Multiplexer
SSMR
SSCRL
SSCRH
Transmission/
reception
control circuit
SSER
SSSR
SSTDR
SSO
SSTRSR
Selector
SSI
Internal data bus
SCS
SSRDR
Interrupt request
(TXI, TEI, RXI, OEI, CEI)
[Legend]
SSMR:
SSCRL:
SSCRH:
SSER:
SSSR:
SSTDR:
SSTRSR:
SSRDR:
SS mode register
SS control register L
SS control register H
SS enable register
SS status register
SS transmit data register
SS shift register
SS receive data register
Figure 15.1 Block Diagram of SSU
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the SSU.
Table 15.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
SSU clock
SSCK
I/O
SSU clock input/output
SSU data input/output
SSI
I/O
SSU data input/output
SSU data input/output
SSO
I/O
SSU data input/output
SSU chip select input/output
SCS
I/O
SSU chip select input/output
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Section 15 Synchronous Serial Communication Unit (SSU)
15.3
Register Descriptions
The SSU has the following registers.
•
•
•
•
•
•
•
•
SS control register H (SSCRH)
SS control register L (SSCRL)
SS mode register (SSMR)
SS enable register (SSER)
SS status register (SSSR)
SS receive data register (SSRDR)
SS transmit data register (SSTDR)
SS shift register (SSTRSR)
15.3.1
SS Control Register H (SSCRH)
SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects
open-drain output of the serial data output pin, selects an output value of the serial data output pin,
selects the SSCK pin, and selects the SCS pin.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSS
0
R/W
Master/Slave Device Select
Selects whether this module is used as a master device
or a slave device. When this module is used as a master
device, transfer clock is output from the SSCK pin. When
the CE bit in SSSR is set, this bit is automatically
cleared.
0: Operates as a slave device
1: Operates as a master device
6
BIDE
0
R/W
Bidirectional Mode Enable
Selects whether the serial data input pin and the output
pin are both used or only one pin is used. For details,
refer to section 15.4.3, Relationship between Data
Input/Output and Shift Register. When the SSUMS bit in
SSCRL is 0, this setting is invalid.
0: Normal mode. Communication is performed by using
two pins.
1: Bidirectional mode. Communication is performed by
using only one pin.
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Section 15 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
5
SOOS
0
R/W
Serial Data Open-Drain Output Select
Selects whether the serial data output pin is CMOS
output or NMOS open-drain output. The serial data
output pin is changed according to the register setting
value. For details, refer to section 15.4.3, Relationship
between Data Input/Output and Shift Register.
0: CMOS output
1: NMOS open-drain output
4
SOL
0
R/W
Serial Data Output Level Setting
Although the value in the last bit of transmit data is
retained in the serial data output after the end of
transmission, the output level of serial data can be
changed by manipulating this bit before or after
transmission. When the output level is changed, the
SOLP bit should be cleared to 0 and the MOV instruction
should be used. If this bit is written during data transfer,
erroneous operation may occur. Therefore this bit must
not be manipulated during transmission.
0: Shows serial data output level to low in reading.
Changes serial data output level to low in writing
1: Shows serial data output level to high in reading.
Changes serial data output level to high in writing
3
SOLP
1
R/W
SOL Write Protect
When output level of serial data is changed, the MOV
instruction is used to set the SOL bit to 1 and clear this
bit to 0 or to clear the SOL bit and this bit to 0.
0: In writing, output level can be changed according to
the value of the SOL bit.
1: In reading, this bit is always read as 1. In writing,
output level cannot be changed. (See section 15.5,
Usage Note.)
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Section 15 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
2
SCKS
0
R/W
SSCK Pin Select
Selects whether the SSCK pin functions as a port or a
serial clock pin.
0: Functions as a port
1: Functions as a serial clock pin
1
CSS1
0
R/W
SCS Pin Select
0
CSS0
0
R/W
Selects whether the SCS pin functions as a port, an SCS
input, or SCS output. When the SSUMS bit in SSCRL is
0, the SCS pin functions as a port regardless of the
setting of this bit.
00: Functions as a port
01: Functions as an SCS input
1x: Functions as an SCS output (however, functions as
an SCS input before starting transfer)
[Legend] x: Don't care.
15.3.2
SS Control Register L (SSCRL)
SSCRL is a register that controls mode, software reset, and open-drain output of the SSCK and
SCS pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0.
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Section 15 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
6
SSUMS
0
R/W
SSU Mode Select
Selects which combination of the serial data input pin
and serial data output pin is used.
For details, refer to section 15.4.3, Relationship between
Data Input/Output and Shift Register.
0: Clocked synchronous communication mode
Data input: SSI pin, Data output: SSO pin
1: Four-line bus communication mode
When MSS = 1 and BIDE = 0 in SSCRH:
Data input: SSI pin, Data output: SSO pin
When MSS = 0 and BIDE = 0 in SSCRH:
Data input: SSO pin, Data output: SSI pin
When BIDE = 1 in SSCRH:
Data input and output: SSO pin
5
SRES
0
R/W
Software Reset
When this bit is set to 1, the SSU internal sequencer is
forcibly reset. Then this bit is automatically cleared. The
register value in the SSU is retained.
4
SCKOS
0
R/W
SSCK Pin Open-Drain Output Select
Selects whether the SSCK pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output
3
CSOS
0
R/W
SCS Pin Open-Drain Output Select
Selects whether the SCS pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output
2 to 0

All 0

Reserved
These bits are always read as 0.
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Section 15 Synchronous Serial Communication Unit (SSU)
15.3.3
SS Mode Register (SSMR)
SSMR is a register that selects MSB-first or LSB-first, clock polarity, clock phase, and transfer
clock rate.
Bit
Bit Name
Initial
Value
R/W
Description
7
MLS
0
R/W
MSB-First/LSB-First Select
Selects whether data transfer is performed in MSB-first
or LSB-first.
0: LSB-first
1: MSB-first
6
CPOS
0
R/W
Clock Polarity Select
Selects the clock polarity of SSCK.
0: Idle state = high
1: Idle state = low
5
CPHS
0
R/W
Clock Phase Select
Selects the clock phase of SSCK.
0: Data change at first edge
1: Data latch at first edge
4, 3

All 0

Reserved
These bits are always read as 0.
2
CKS2
0
R/W
Transfer clock rate select
1
CKS1
0
R/W
0
CKS0
0
R/W
Sets transfer clock rate (prescaler division ratio) when
the internal clock is selected.
The system clock (φ) is halted in subactive mode or
subsleep mode. Select φSUB/2 in these modes.
000: φ/256
001: φ/128
010: φ/64
011: φ/32
100: φ/16
101: φ/8
110: φ/4
111: φSUB/2
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Section 15 Synchronous Serial Communication Unit (SSU)
15.3.4
SS Enable Register (SSER)
SSER is a register that sets transmit enable, receive enable, and interrupt enable.
Bit
Bit Name
Initial
Value
R/W
Description
7
TE
0
R/W
Transmit enable
When this bit is 1, transmit operation is enabled.
6
RE
0
R/W
Receive enable
When this bit is 1, receive operation is enabled.
5
RSSTP
0
R/W
Receive single stop
When this bit is 1, receive operation is completed after
receiving one byte.
4
—
0
—
Reserved
This bit is always read as 0.
3
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an RXI and an OEI interrupt
requests are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
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Section 15 Synchronous Serial Communication Unit (SSU)
15.3.5
SS Status Register (SSSR)
SSSR is a register that sets interrupt flags.
Bit
Bit Name
Initial
Value
R/W
7
—
0
—
Description
Reserved
This bit is always read as 0.
6
ORER
0
R/(W)*
Overrun Error Flag
Indicates that the RDRF bit is abnormally terminated in
reception because an overrun error has occurred.
SSRDR retains received data before the overrun error
occurs and the received data after the overrun error
occurs is lost. When this bit is set to 1, subsequent serial
reception cannot be continued. When the MSS bit in
SSCRH is 1, this is also applied to serial transmission.
[Setting condition]
•
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
•
5, 4

All 0

When 0 is written to this bit after reading 1
Reserved
These bits are always read as 0.
3
TEND
0
R/(W)*
Transmit End
[Setting condition]
•
When the last bit of data is transmitted, the TDRE bit
is 1
[Clearing conditions]
•
When 0 is written to this bit after reading 1
•
When data is written in SSTDR
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Section 15 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
2
TDRE
1
R/(W)*
Transmit Data Empty
[Setting conditions]
•
When the TE bit in SSER is 0
•
When data transfer is performed from SSTDR to
SSTRSR and data can be written in SSTDR
[Clearing conditions]
1
RDRF
0
R/(W)*
•
When 0 is written to this bit after reading 1
•
When data is written in SSTDR
Receive Data Register Full
[Setting condition]
•
When serial reception is completed normally and
receive data is transferred from SSTRSR to SSRDR
[Clearing conditions]
0
CE
0
R/(W)*
•
When 0 is written to this bit after reading 1
•
When data is read from SSRDR
Conflict Error Flag
[Setting conditions]
•
When serial communication is started while SSUMS
= 1 and MSS =1, the SCS pin input is low
•
When the SCS pin level changes from low to high
during transfer while SSUMS = 1 and MSS = 0
[Clearing condition]
•
Note:
*
When 0 is written to this bit after reading 1
Only 0 can be written to clear the flag.
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Section 15 Synchronous Serial Communication Unit (SSU)
15.3.6
SS Receive Data Register (SSRDR)
SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of
serial data, it transfers the received serial data from SSTRSR and the data is stored. After this,
SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in this way,
continuous receive operations are possible. SSRDR is a read-only register and cannot be written to
by the CPU. SSRDR is initialized to H'00.
15.3.7
SS Transmit Data Register (SSTDR)
SSTDR is an 8-bit register that stores serial data for transmission. SSTDR can be read or written
to by the CPU at all times. When the SSU detects that SSTRSR is empty, it transfers the transmit
data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has
already been written to SSTDR during serial transmission, continuous serial transmission is
possible. SSTDR is initialized to H'00.
15.3.8
SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data. When transmit data is transferred
from SSTDR to SSTRSR, bit 0 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in
SSMR is 0 (LSB-first transfer) and bit 7 in SSTDR is transferred to bit 0 in SSTRSR while the
MLS bit in SSMR is 1 (MSB-first transfer). SSTRSR cannot be directly accessed by the CPU.
15.4
Operation
15.4.1
Transfer Clock
Transfer clock can be selected from eight internal clocks and an external clock. When this module
is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSCRH to 1.
When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output
state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to
CKS0 bits in SSMR. When the MSS bit is 0, an external clock is selected and the SSCK pin is in
the input state.
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.2
Relationship between Clock Polarity and Phase, and Data
Relationship between clock polarity and phase, and transfer data changes according to a
combination of the SSUMS bit in SSCRL and the CPOS and CPHS bits in SSMR. Figure 15.2
shows the relationship.
MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR.
When the MLS bit is 0, transfer is started from LSB to MSB. When the MLS bit is 1, transfer is
started from MSB to LSB.
(1) When CPHS = 0, CPOS =0, and SSUMS = 0:
SSCK
Bit 0
SSO, SSI
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CPHS = 0 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
SCS
(3) When CPHS = 1 and SSUMS = 1:
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSO, SSI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
SCS
Figure 15.2 Relationship between Clock Polarity and Phase, and Data
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.3
Relationship between Data Input/Output and Shift Register
Relationship of connection between the data input/output pin and SSTRSR changes according to a
combination of the MSS bit in SSCRH and the SSUMS bit in SSCRL. It also changes by the
BIDE bit in SSCRH. Figure 15.3 shows the relationship.
(1) When SSUMS = 0:
Shift register
(SSTRSR)
(2) When SSUMS = 1, BIDE = 0, and MSS = 1:
SSO
Shift register
(SSTRSR)
SSO
SSI
(3) When SSUMS = 1, BIDE = 0, and MSS = 0:
Shift register
(SSTRSR)
SSI
(4) When SSUMS = 1 and BIDE = 1:
SSO
Shift register
(SSTRSR)
SSO
SSI
SSI
Figure 15.3 Relationship between Data Input/Output Pin and Shift Register
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.4
Communication Modes and Pin Functions
The SSU switches functions of the input/output pin in each communication mode according to the
settings of the MSS bit in SSCRH and the RE and TE bits in SSER. Figure 15.2 shows the
relationship between communication modes and the input/output pins. In bidirectional
communication mode, neither TE nor RE should be set to 1.
Table 15.2 Relationship between Communication Modes and Input/Output Pins
Communication
Mode
Clocked
Synchronous
Communication
Mode
Register State
SSUMS
BIDE
MSS
TE
RE
SSI
SSO
SSCK
0
x
0
0
1
In

In
1
0

Out
In
1
In
Out
In
0
1
In

Out
1
0

Out
Out
1
In
Out
Out
0
1

In
In
1
0
Out

In
1
Out
In
In
0
1
In

Out
1
0

Out
Out
1
In
Out
Out
0
1

In
In
1
0

Out
In
0
1

In
Out
1
0

Out
Out
1
Four-Line Bus
Communication
Mode
1
0
0
1
Four-Line Bus
(Bidirectional)
Communication
Mode
[Legend]
1
1
0
1
x: Don't care.
: Can be used as a general I/O port.
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Pin State
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.5
Operation in Clocked Synchronous Communication Mode
Initialization in Clocked Synchronous Communication Mode: Figure 15.4 shows the
initialization in clocked synchronous communication mode. Before transmitting and receiving
data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE bits in SSER to 0
Clear SSUMS bit in SSCRL to 0
Clear CPOS and CPHS bits to 0 and set
MLS and CKS2 to CKS0 bits in SSMR
Set SCKS bit in SSCRH to 1
and set MSS and SOOS bits
Clear ORER bit in SSSR to 0
Set the TE and RE bits in SSER to 1
and set RIE, TIE, TEIE, and RSSTP
bits according to transmission/
reception/transmission and reception
End
Figure 15.4 Initialization in Clocked Synchronous Communication Mode
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Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission: Figure 15.5 shows an example of the SSU operation for transmission.
In serial transmission, the SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, it outputs data in synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
Figure 15.6 shows a sample flowchart for serial data transmission.
SSCK
SSO
Bit 0
Bit 1
Bit 7
Bit 0
One frame
Bit 1
Bit 7
One frame
TDRE
TEND
LSI Operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
Write data
in SSTDR
Figure 15.5 Example of Operation in Data Transmission
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TEI generated
Section 15 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Read TDRE bit in SSSR
No
TDRE = 1?
[1] After reading SSSR and confirming
that the TDRE bit is 1, write transmit
data in SSTDR. Then the TDRE bit is
automatically cleared to 0.
Yes
Write transmit data
in SSTDR
[2]
Data transmission
continued?
Yes
[2] Determine whether data transmission
is continued.
No
[3]
Read TEND bit in SSSR
No
TEND = 1?
[3] Read 1 from the TEND bit in SSSR
to confirm that data transmission is
completed. After the TEND bit is set to 1,
clear the TEND bit and TE bit in SSER
to 0 and transmit mode is ended.
Yes
Clear TEND bit and
TE bit in SSER to 0
End
Figure 15.6 Sample Serial Transmission Flowchart
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Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Reception: Figure 15.7 shows an example of the SSU operation for reception. In
serial reception, the SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, it inputs data in synchronized with the input clock. When the SSU is
set as a master device, it outputs a receive clock and starts reception by performing dummy read
on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, a RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
Figure 15.8 shows a sample flowchart for serial data reception.
SSCK
SSO
Bit 0
Bit 7
Bit 0
One frame
Bit 7
Bit 0
Bit 7
One frame
RDRF
RSSTP
LSI operation
User
processing
RXI generated
Dummy read
on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1Read data
in SSRDR
Figure 15.7 Example of Operation in Data Reception (MSS = 1)
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RXI generated
Section 15 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Dummy read on SSRDR
[2]
Last reception?
[1] After setting each register in the SSU,
dummy read on SSRDR is performed
and reception is started.
Yes
No
[2] Determine whether the last one byte of
data is received. When the last one byte
of data is received, set to stop reception
after the data is received.
Read ORER
[3]
ORER = 1?
Yes
[3][6] When a receive error occurs, clear the
ORER flag to 0 after the ORER flag in
SSSR is read and an appropriate error
processing is performed. When the ORER
flag is set to 1, transmission/reception
cannot be started again.
No
Read RDRF
[4]
No
RDRF = 1?
[4] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
Yes
Read receive data
in SSRDR
[5]
[5] Before the last one byte of data is received,
set the RSSTP bit to 1 and reception is stopped
after the data is received.
Set RSSTP to 1
Read ORER
Yes
[6]
ORER = 1?
No
Read RDRF
No
RDRF = 1?
[7]
Yes
RE = 0, RSSTP = 0
[7] Confirm that the RDRF bit is 1. To end
reception, clear the RE and RSSTP bits to
0 and then read the last receive data. If the
Overrun error
SSRDR bit is read before clearing the RE bit,
processing
reception is started again.
Read receive data
in SSRDR
End
Figure 15.8 Sample Serial Reception Flowchart (MSS = 1)
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Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission and Reception: Data transmission and reception is a combined
operation of data transmission and reception which are described before. Transmission and
reception is started by writing data in SSTDR. When the eighth clock rises or the ORER bit is set
to 1 while the TDRE bit is set to 1, transmission and reception is stopped.
To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode
(TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND,
RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1.
Figure 15.9 shows a sample flowchart for serial transmit and receive operations.
Start
Initialization
[1]
Read TDRE in SSSR
No
TDRE = 1?
[1] After reading SSSR and confirming that
the TDRE bit is 1, write transmit data in
SSTDR. Then the TDRE bit is automatically
cleared to 0.
Yes
Write transmit data
in SSTDR
[2]
[2] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
Read RDRF in SSSR
No
RDRF = 1?
Yes
Read receive data
in SSRDR
[3]
Data transmission
continued?
[4]
Clear TEND to 0 and
clear TE and RE in
SSER to 0
Yes
[3] Determine whether data transmission is continued.
No
[4] To end transmit and receive mode, clear the
TEND bit to 0 and clear the TE and RE bits in
SSER to 0.
End
Figure 15.9 Sample Flowchart for Serial Transmit and Receive Operations
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.6
Operation in Four-Line Bus Communication Mode
Four-line bus communication mode is a mode which communicates with the four-line bus; a clock
line, a data input line, a data output line, and a chip select line. This mode includes bidirectional
mode in which the data input line and the data output line function as a single pin. The data input
line and the data output line are changed according to the settings of the MSS and BIDE bits in
SSCRH. For details, refer to section 15.4.3, Relationship between Data Input/Output and Shift
Register. In this mode, relationship between clock polarity and phase, and data can be set by the
CPOS and CPHS bits in SSMR. For details, refer to section 15.4.2, Relationship between Clock
Polarity and Phase, and Data.
When the SSU is set as a master device, the chip select line controls output. When the SSU is set
as a slave device, the chip select line controls input. When the SSU is set as a master device, the
chip select line controls output of the SCS pin or controls output of a general port by setting the
CSS1 bit in SSCRH to 1. When the SSU is set as a slave device, the chip select line sets the SCS
pin as an input pin by setting the CSS1 and CSS0 bits in SSCRH to 01.
In four-line bus communication mode, the MLS bit in SSMR is set to 1 and transfer is performed
in MSB-first order.
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.7
Initialization in Four-Line Bus Communication Mode
Figure 15.10 shows the initialization in four-line bus communication mode. Before transmitting
and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be
initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE in SSER to 0
Set SSUMS in SSCRL to 1
[1]
Set MLS in SSMR to 1 and
set CPOS, CPHS, and
CKS2 to CKS0
[2]
Set SCKS in SSCRH to 1 and
set BIDE, MSS, SOOS, CSS1,
and CSS0
[1] The MLS bit is set to 1 for MSB-first transfer.
The clock polarity and phase are set in the
CPOS and CPHS bits.
[2] In bidirectional mode, the BIDE bit is set
to 1 and input/output of the SCS pin is set
by the CSS1 and CSS0 bits.
Clear ORER in SSSR to 0
Set TE and RE in SSER to 1 and
set RIE, TIE, TEIE, and RSSTP
according to transmission/reception/
transmission and reception
End
Figure 15.10 Initialization in Four-Line Bus Communication Mode
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.8
Serial Data Transmission
Figure 15.11 shows an example of the SSU operation for transmission. In serial transmission, the
SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is
set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in
synchronized with the input clock.
When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is
automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the
TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is
generated.
When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to
SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while
the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in
SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is
fixed high and the SCS pin goes high. When continuous transmission is performed with the SCS
pin low, the next data should be written to SSTDR before transmitting the eighth bit of the frame.
While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that
the ORER bit is cleared to 0 before transmission.
The difference between this mode and clocked synchronous communication mode is as follows:
when the SSU is set as a master device, the SSO pin is in the Hi-Z state if the SCS pin is in the HiZ state and when the SSU is set as a slave device, the SSI pin is in the Hi-Z state if the SCS pin is
in the high-input state. The sample flowchart for serial data transmission is the same as that in
clocked synchronous communication mode.
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Section 15 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0:
SCS
(output)
(Hi-Z)
SSCK
SSO
Bit 7
Bit 6
Bit 0
Bit 7
One frame
Bit 6
Bit 0
One frame
TDRE
TEND
LSI operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
TEI generated
Write data
in SSTDR
(2) When CPOS = 0 and CPHS = 1:
SCS
(output)
(Hi-Z)
SSCK
Bit 7
SSO
Bit 6
Bit 0
Bit 7
One frame
Bit 6
Bit 0
One frame
TDRE
TEND
LSI operation
User
processing
TXI generated
Write data
in SSTDR
TXI generated
TEI generated
Write data
in SSTDR
Figure 15.11 Example of Operation in Data Transmission (MSS = 1)
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.9
Serial Data Reception
Figure 15.12 shows an example of the SSU operation for reception. In serial reception, the SSU
operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized
with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts
reception by performing dummy read on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, an RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
The set timings of the RDRF and ORER flags differ according to the CPHS setting. These timings
are shown in figure 15.12. When the CPHS bit is set to 1, the flag is set during the frame.
Therefore care should be taken at the end of reception.
The sample flowchart for serial data reception is the same as that in clocked synchronous
communication mode.
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Section 15 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0:
SCS
(output)
(Hi-Z)
SSCK
SSI
Bit 7
Bit 0
Bit 7
One frame
Bit 0
Bit 7
Bit 0
One frame
RDRF
RSSTP
LSI operation
User
processing
RXI generated
Dummy read on SSRDR
RXI generated
Read data in SSRDR
RXI generated
Set RSSTP to 1Read data in SSRDR
(2) When CPOS = 0 and CPHS = 1:
SCS
(output)
(Hi-Z)
SSCK
Bit 7
SSI
Bit 0
One frame
Bit 7
Bit 0
Bit 7
Bit 0
One frame
RDRF
RSSTP
LSI operation
User
processing
RXI generated
Dummy read on SSRDR
RXI generated
Read data in SSRDR
Set RSSTP to 1Read data in SSRDR
Figure 15.12 Example of Operation in Data Reception (MSS = 1)
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RXI generated
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.10 SCS Pin Control and Arbitration
When the SSUMS bit in SSCRL is set to 1 and the CSS1 bit in SSCRH is set to 1, the MSS bit in
SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer.
If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in
SSSR is set and the MSS bit is cleared.
Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the
CE bit must be cleared to 0 before starting transmission.
When the multimaster error is used, the CSOS bit in SSCRL should be set to 1.
SCS input
Internal SCS
(synchronized)
MSS
Transfer start
Write data
in SSTDR
CE
SCS output
(Hi-Z)
Maximum time of SCS internal synchronization
Arbitration detection
period
Figure 15.13 Arbitration Check Timing
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Section 15 Synchronous Serial Communication Unit (SSU)
15.4.11 Interrupt Requests
The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun
error, and conflict error. Since these interrupt requests are assigned to the common vector address,
interrupt sources must be determined by flags. Table 15.3 lists the interrupt requests.
Table 15.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
Transmit data empty
TXI
(TIE = 1), (TDRE = 1)
Transmit end
TEI
(TEIE = 1), (TEND = 1)
Receive data full
RXI
(RIE = 1), (RDRF = 1)
Overrun error
OEI
(RIE = 1), (ORER = 1)
Conflict error
CEI
(CEIE = 1), (CE = 1)
When an interrupt condition shown in table 15.3 is 1 and the I bit in CCR is 0, the CPU executes
the interrupt exception handling. Each interrupt source must be cleared during the exception
handling. Note that the TDRE and TEND bits are automatically cleared by writing transmit data in
SSTDR and the RDRF bit is automatically cleared by reading SSRDR. When transmit data is
written in SSTDR, the TDRE bit is set again at the same time. Then if the TDRE bit is cleared,
additional one byte of data may be transmitted.
15.5
Usage Note
When writing 1 to the SOLP bit in SSCRH (to enable write protect) after writing 0 to it (to disable
write protect), the SOL bit may be changed without being protected.
To avoid this, before writing 1 to the SOLP bit (to enable write protect), write the current value of
the SOL bit to itself. With this procedure, the write protect can be performed on the SOL bit.
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2
Section 16 I C Bus Interface 2 (IIC2)
Section 16 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The configuration of the registers that control the I2C bus differs partly from
the Philips configuration, however. Figure 16.1 shows a block diagram of the I2C bus interface 2.
Figure 16.2 shows an example of I/O pin connections to external circuits.
16.1
Features
• Selection of I2C format or clock synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The IIC2 is halted as the initial value. For details, refer to section 5.4, Module
Standby Function.)
I2C bus format
•
•
•
•
Start and stop conditions generated automatically in master mode
Selection of acknowledge output levels when receiving
Automatic loading of acknowledge bit when transmitting
Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• Direct bus drive
Two pins, SCL and SDA pins, function as CMOS outputs in normal operation (when the
port/serial function is selected) and NMOS outputs when the bus drive function is selected.
Clock synchronous format
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
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Section 16 I C Bus Interface 2 (IIC2)
Transfer clock
generation
circuit
Transmission/
reception
control circuit
Output
control
SCL
ICCR1
ICCR2
ICMR
Internal data bus
Noise canceler
ICDRT
Output
control
SDA
ICDRS
SAR
Address
comparator
Noise canceler
ICDRR
Bus state
decision circuit
Arbitration
decision circuit
ICSR
ICIER
[Legend]
2
ICCR1 : I C bus control register 1
ICCR2 : I2C bus control register 2
ICMR : I2C bus mode register
ICSR : I2C bus status register
ICIER : I2C bus interrupt enable register
ICDRT : I2C bus transmit data register
ICDRR : I2C bus receive data register
ICDRS : I2C bus shift register
SAR : Slave address register
Interrupt
generator
Figure 16.1 Block Diagram of I2C Bus Interface 2
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Interrupt
request
2
Section 16 I C Bus Interface 2 (IIC2)
Vcc
SCL in
Vcc
SCL
SCL
SDA
SDA
SCL out
SDA in
SCL in
SCL out
SCL
SDA
(Master)
SCL
SDA
SDA out
SCL in
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
(Slave 2)
Figure 16.2 External Circuit Connections of I/O Pins
16.2
Input/Output Pins
Table 16.1 shows the pin configuration of the I2C bus interface 2.
Table 16.1 Pin Configuration
Name
Abbreviation
I/O
Function
Serial clock pin
SCL
I/O
IIC serial clock input/output
Serial data pin
SDA
I/O
IIC serial data input/output
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Section 16 I C Bus Interface 2 (IIC2)
16.3
Register Descriptions
The I2C bus interface 2 has the following registers.
•
•
•
•
•
•
•
•
•
I2C bus control register 1 (ICCR1)
I2C bus control register 2 (ICCR2)
I2C bus mode register (ICMR)
I2C bus interrupt enable register (ICIER)
I2C bus status register (ICSR)
Slave address register (SAR)
I2C bus transmit data register (ICDRT)
I2C bus receive data register (ICDRR)
I2C bus shift register (ICDRS)
16.3.1
I2C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
ICE
0
R/W
I2C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to
the port/serial function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W
Reception Disable
This bit enables or disables the next operation when
TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
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Section 16 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
5
MST
0
R/W
Master/Slave Select
4
TRS
0
R/W
Transmit/Receive Select
2
In master mode with the I C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data
agree with the slave address that is set to SAR and the
eighth bit is 1, TRS is automatically set to 1. If an
overrun error occurs in master mode with the clock
synchronous serial format, MST is cleared to 0 and
slave receive mode is entered.
Operating modes are described below according to
MST and TRS combination. When clock synchronous
serial format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
CKS3
0
R/W
Transfer Clock Select 3 to 0
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits are valid only in master mode and should be
set according to the necessary transfer rate (refer to
table 16.2). These bit are used to specify the data setup
time in slave transmit mode. The data setup time is
secured for 10tcyc when CKS3 = 0 and for 20tcyc when
CKS3 = 1.
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Section 16 I C Bus Interface 2 (IIC2)
Table 16.2 Transfer Rate
Bit 3
Bit 2
Bit 1
Bit 0
CKS3
CKS2
CKS1
CKS0
Clock
φ = 2 MHz
φ = 5 MHz
φ = 10 MHz
0
0
0
0
φ/28
71.4 kHz
179 kHz
357 kHz
1
φ/40
50.0 kHz
125 kHz
250 kHz
1
1
0
1
1
0
0
1
1
0
1
0
φ/48
41.7 kHz
104 kHz
208 kHz
1
φ/64
31.3 kHz
78.1 kHz
156 kHz
0
φ/80
25.0 kHz
62.5 kHz
125 kHz
1
φ/100
20.0 kHz
50.0 kHz
100 kHz
0
φ/112
17.9 kHz
44.6 kHz
89.3 kHz
1
φ/128
15.6 kHz
39.1 kHz
78.1 kHz
0
φ/56
35.7 kHz
89.3 kHz
179 kHz
1
φ/80
25.0 kHz
62.5 kHz
125 kHz
0
φ/96
20.8 kHz
52.1 kHz
104 kHz
1
φ/128
15.6 kHz
39.1 kHz
78.1 kHz
0
φ/160
12.5 kHz
31.3 kHz
62.5 kHz
1
φ/200
10.0 kHz
25.0 kHz
50.0 kHz
0
φ/224
8.9 kHz
22.3 kHz
44.6 kHz
1
φ/256
7.8 kHz
19.5 kHz
39.1 kHz
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Transfer Rate
2
Section 16 I C Bus Interface 2 (IIC2)
16.3.2
I2C Bus Control Register 2 (ICCR2)
ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the control part of the I2C bus interface 2.
Bit
Bit Name
Initial
Value
R/W
Description
7
BBSY
0
R/W
Bus Busy
2
This bit enables to confirm whether the I C bus is
occupied or released and to issue start/stop conditions
in master mode. With the clock synchronous serial
2
format, this bit has no meaning. With the I C bus format,
this bit is set to 1 when the SDA level changes from
high to low under the condition of SCL = high, assuming
that the start condition has been issued. This bit is
cleared to 0 when the SDA level changes from low to
high under the condition of SCL = high, assuming that
the stop condition has been issued. Write 1 to BBSY
and 0 to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start condition.
Write 0 in BBSY and 0 in SCP to issue a stop condition.
To issue start/stop conditions, use the MOV instruction.
6
SCP
1
R/W
Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A repeated start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
5
SDAO
1
R/W
SDA Output Value Control
This bit is used with SDAOP when modifying output
level of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
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Section 16 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
4
SDAOP
1
R/W
SDAO Write Protect
This bit controls change of output level of the SDA pin
by modifying the SDAO bit. To change the output level,
clear SDAO and SDAOP to 0 or set SDAO to 1 and
clear SDAOP to 0 by the MOV instruction. This bit is
always read as 1.
3
SCLO
1
R
This bit monitors SCL output level. When SCLO is 1,
SCL pin outputs high. When SCLO is 0, SCL pin
outputs low.
2

1

Reserved
This bit is always read as 1, and cannot be modified.
1
IICRST
0
R/W
IIC Control Part Reset
2
This bit resets the control part except for I C registers. If
this bit is set to 1 when hang-up occurs because of
2
2
communication failure during I C operation, I C control
part can be reset without setting ports and initializing
registers.
0

1

Reserved
This bit is always read as 1, and cannot be modified.
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Section 16 I C Bus Interface 2 (IIC2)
I2C Bus Mode Register (ICMR)
16.3.3
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Bit
Bit Name
Initial
Value
R/W
7
MLS
0
R/W
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I2C bus format is used.
6
WAIT
0
R/W
Wait Insertion Bit
2
In master mode with the I C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of
the clock for the final data bit, low period is extended for
two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no
wait inserted.
The setting of this bit is invalid in slave mode with the
2
I C bus format or with the clock synchronous serial
format.
5, 4

All 1

Reserved
These bits are always read as 1, and cannot be
modified.
3
BCWP
1
R/W
BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0
and use the MOV instruction. In clock synchronous
serial mode, BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
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Section 16 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
2
BC2
0
R/W
Bit Counter 2 to 0
1
BC1
0
R/W
0
BC0
0
R/W
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
is indicated. With the I2C bus format, the data is
transferred with one addition acknowledge bit. Bit BC2
to BC0 settings should be made during an interval
between transfer frames. If bits BC2 to BC0 are set to a
value other than 000, the setting should be made while
the SCL pin is low. The value returns to 000 at the end
of a data transfer, including the acknowledge bit. With
the clock synchronous serial format, these bits should
not be modified.
2
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I C Bus Format
Clock Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bits
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
2
Section 16 I C Bus Interface 2 (IIC2)
I2C Bus Interrupt Enable Register (ICIER)
16.3.4
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables
or disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
6
TEIE
0
R/W
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) at the rising of the ninth clock while the TDRE bit
in ICSR is 1. TEI can be canceled by clearing the TEND
bit or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5
RIE
0
R/W
Receive Interrupt Enable
This bit enables or disables the receive data full
interrupt request (RXI) and the overrun error interrupt
request (ERI) with the clock synchronous format, when
a receive data is transferred from ICDRS to ICDRR and
the RDRF bit in ICSR is set to 1. RXI can be canceled
by clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clock
synchronous format are disabled.
1: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clock
synchronous format are enabled.
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Section 16 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
4
NAKIE
0
R/W
NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) and the overrun error (setting of the
OVE bit in ICSR) interrupt request (ERI) with the clock
synchronous format, when the NACKF and AL bits in
ICSR are set to 1. NAKI can be canceled by clearing
the NACKF, OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgment Select
0: The value of the receive acknowledge bit is ignored,
and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous
transfer is halted.
1
ACKBR
0
R
Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot
be modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at
the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
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Section 16 I C Bus Interface 2 (IIC2)
16.3.5
I2C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit
Bit Name
Initial
Value
R/W
7
TDRE
0
R/(W)* Transmit Data Register Empty
Description
[Setting conditions]
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
•
When TRS is set
•
When a start condition (including re-transfer) has
been issued
•
When transmit mode is entered from receive mode
in slave mode
[Clearing conditions]
6
TEND
0
•
When 0 is written in TDRE after reading TDRE = 1
•
When data is written to ICDRT with an instruction
R/(W)* Transmit End
[Setting conditions]
•
When the ninth clock of SCL rises with the I C bus
format while the TDRE flag is 1
•
When the final bit of transmit frame is sent with the
clock synchronous serial format
2
[Clearing conditions]
5
RDRF
0
•
When 0 is written in TEND after reading TEND = 1
•
When data is written to ICDRT with an instruction
R/(W)* Receive Data Register Full
[Setting condition]
•
When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
•
When 0 is written in RDRF after reading RDRF = 1
•
When ICDRR is read with an instruction
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Section 16 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
4
NACKF
0
R/(W)* No Acknowledge Detection Flag
Description
[Setting condition]
•
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
[Clearing condition]
•
3
STOP
0
When 0 is written in NACKF after reading NACKF =
1
R/(W)* Stop Condition Detection Flag
[Setting conditions]
•
In master mode, when a stop condition is detected
after the completion of frame transfer
•
In slave mode, when a stop condition is detected,
after the slave address of the first byte, following the
general call and the detection of the start condition,
matches the address set in SAR
[Clearing condition]
•
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When 0 is written in STOP after reading STOP = 1
2
Section 16 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
2
AL/OVE
0
R/(W)* Arbitration Lost Flag/Overrun Error Flag
Description
This flag indicates that arbitration was lost in master
2
mode with the I C bus format and that the final bit has
been received while RDRF = 1 with the clock
synchronous format.
When two or more master devices attempt to seize the
2
bus at nearly the same time, if the I C bus interface
detects data differing from the data it sent, it sets AL to
1 to indicate that the bus has been taken by another
master.
[Setting conditions]
•
If the internal SDA and SDA pin disagree at the rise
of SCL in master transmit mode
•
When the SDA pin outputs high in master mode
while a start condition is detected
•
When the final bit is received with the clock
synchronous format while RDRF = 1
[Clearing condition]
•
1
AAS
0
When 0 is written in AL/OVE after reading AL/OVE
=1
R/(W)* Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA6 to
SVA0 in SAR.
[Setting conditions]
•
When the slave address is detected in slave receive
mode
•
When the general call address is detected in slave
receive mode.
[Clearing condition]
•
When 0 is written in AAS after reading AAS = 1
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Section 16 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
0
ADZ
0
R/(W)* General Call Address Recognition Flag
Description
2
This bit is valid in I C bus format slave receive mode.
[Setting condition]
•
When the general call address is detected in slave
receive mode
[Clearing condition]
•
Note:
*
When 0 is written in ADZ after reading ADZ = 1
Only 0 can be written to clear the flag.
16.3.6
Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode
with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
received after a start condition, the chip operates as the slave device.
Initial
Value
R/W
Description
SVA6 to
SVA0
All 0
R/W
Slave Address 6 to 0
FS
0
Bit
Bit Name
7 to 1
0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
2
connected to the I C bus.
R/W
Format Select
2
0: I C bus format is selected.
1: Clock synchronous serial format is selected.
16.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1
and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H'FF. The initial value of ICDRT is H'FF.
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Section 16 I C Bus Interface 2 (IIC2)
16.3.8
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR
is H'FF.
16.3.9
I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
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Section 16 I C Bus Interface 2 (IIC2)
16.4
Operation
The I2C bus interface 2 can communicate either in I2C bus mode or clock synchronous serial mode
by setting FS in SAR.
I2C Bus Format
16.4.1
Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame
following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0)
S
1
SLA
7
R/W
1
A
1
DATA
n
A
1
1
A/A
1
P
1
n: Transfer bit count
(n = 1 to 8)
m: Transfer frame count
(m ≥ 1)
m
(b) I2C bus format (Repeated start condition, FS = 0)
S
1
SLA
7
R/W
1
A
1
DATA
n1
1
A/A
1
S
1
SLA
7
m1
R/W
1
A
1
DATA
n2
1
A/A
1
P
1
m2
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 16.3 I2C Bus Formats
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
DATA
8
9
A
1-7
DATA
8
9
A
P
Figure 16.4 I2C Bus Timing
[Legend]
S:
SLA:
R/W:
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P:
Stop condition. The master device drives SDA from low to high while SCL is high.
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Section 16 I C Bus Interface 2 (IIC2)
16.4.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to
figures 16.5 and 16.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting)
2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the
transmit data is prepared or the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 16 I C Bus Interface 2 (IIC2)
SCL
(Master output)
1
2
3
4
5
6
SDA
(Master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
7
8
Bit 1
Slave address
9
1
Bit 0
Bit 7
2
Bit 6
R/W
SDA
(Slave output)
A
TDRE
TEND
Address + R/W
ICDRT
ICDRS
User
processing
Data 1
Address + R/W
Data 2
Data 1
[2] Instruction of start
condition issuance
[4] Write data to ICDRT (second byte)
[5] Write data to ICDRT (third byte)
[3] Write data to ICDRT (first byte)
Figure 16.5 Master Transmit Mode Operation Timing (1)
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
1
2
3
4
5
6
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
8
9
Bit 0
A/A
A
TDRE
TEND
Data n
ICDRT
ICDRS
Data n
User
[5] Write data to ICDRT
processing
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
Figure 16.6 Master Transmit Mode Operation Timing (2)
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Section 16 I C Bus Interface 2 (IIC2)
16.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 16.7 and 16.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
This enables the issuance of the stop condition after the next reception.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
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Section 16 I C Bus Interface 2 (IIC2)
Master transmit mode
SCL
(Master output)
Master receive mode
9
1
2
3
4
5
6
7
8
SDA
(Master output)
9
1
A
SDA
(Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
User
processing
Data 1
[3] Read ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
Figure 16.7 Master Receive Mode Operation Timing (1)
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Section 16 I C Bus Interface 2 (IIC2)
SCL
(Master output)
9
SDA
(Master output)
A
SDA
(Slave output)
1
2
3
4
5
6
7
8
9
A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
Data n
ICDRS Data n-1
ICDRR
User
processing
Data n
Data n-1
[5] Read ICDRR after setting RCVD
[7] Read ICDRR,
and clear RCVD
[6] Issue stop
condition
[8] Set slave
receive mode
Figure 16.8 Master Receive Mode Operation Timing (2)
16.4.4
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 16.9 and 16.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
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Section 16 I C Bus Interface 2 (IIC2)
Slave transmit
mode
Slave receive
mode
SCL
(Master output)
9
1
2
3
4
5
6
7
8
9
SDA
(Master output)
1
A
SCL
(Slave output)
SDA
(Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
Data 1
ICDRT
ICDRS
Data 2
Data 1
Data 3
Data 2
ICDRR
User
processing
[2] Write data to ICDRT (data 1)
[2] Write data to ICDRT (data 2)
[2] Write data to ICDRT (data 3)
Figure 16.9 Slave Transmit Mode Operation Timing (1)
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Section 16 I C Bus Interface 2 (IIC2)
Slave receive
mode
Slave transmit mode
SCL
(Master output)
9
SDA
(Master output)
A
1
2
3
4
5
6
7
8
9
A
SCL
(Slave output)
SDA
(Slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDRE
TEND
TRS
ICDRT
ICDRS
Data n
ICDRR
User
processing
[3] Clear TEND
[4] Read ICDRR (dummy read)
after clearing TRS
[5] Clear TDRE
Figure 16.10 Slave Transmit Mode Operation Timing (2)
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Section 16 I C Bus Interface 2 (IIC2)
16.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
Bit 7
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 1
ICDRR
User
processing
Data 1
[2] Read ICDRR (dummy read)
Figure 16.11 Slave Receive Mode Operation Timing (1)
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Data 2
[2] Read ICDRR
2
Section 16 I C Bus Interface 2 (IIC2)
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 2
Data 1
ICDRR
Data 1
User
processing
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 16.12 Slave Receive Mode Operation Timing (2)
16.4.6
Clock Synchronous Serial Format
This module can be operated with the clock synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1)
Data Transfer Format
Figure 16.13 shows the clock synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6
Bit 7
Figure 16.13 Clock Synchronous Serial Transfer Format
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Section 16 I C Bus Interface 2 (IIC2)
(2)
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 16.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
SCL
1
2
7
8
1
7
8
1
SDA
(Output)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
TRS
TDRE
Data 1
ICDRT
Data 1
ICDRS
User
processing
Data 2
[3] Write data [3] Write data
to ICDRT
to ICDRT
[2] Set TRS
Data 3
Data 2
Data 3
[3] Write data
to ICDRT
Figure 16.14 Transmit Mode Operation Timing
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[3] Write data
to ICDRT
2
Section 16 I C Bus Interface 2 (IIC2)
(3)
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 16.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
fixed high after receiving the next byte data.
SCL
1
2
7
8
1
7
8
1
2
SDA
(Input)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
Bit 1
MST
TRS
RDRF
ICDRS
Data 1
Data 1
ICDRR
User
processing
Data 2
[2] Set MST
(when outputting the clock)
[3] Read ICDRR
Data 3
Data 2
[3] Read ICDRR
Figure 16.15 Receive Mode Operation Timing
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Section 16 I C Bus Interface 2 (IIC2)
16.4.7
Noise Canceler
The logic levels on the SCL and SDA pins are internally latched via noise cancelers. Figure 16.16
shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
SCL or SDA
input signal
D
C
Q
Latch
Q
D
Latch
Match detector
Internal
SCL or SDA
signal
System clock
period
Sampling
clock
Figure 16.16 Block Diagram of Noise Conceler
16.4.8
Example of Use
Flowcharts in respective modes that use the I2C bus interface 2 are shown in figures 16.17 to
16.20.
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Section 16 I C Bus Interface 2 (IIC2)
Start
Initialize
Read BBSY in ICCR2
[1]
Test the status of the SCL and SDA lines.
[2]
Set master transmit mode.
[3]
Issue the start condition.
[4]
Set the first byte (slave address + R/W) of transmit data.
[5]
Wait for 1 byte to be transmitted.
[6]
Test the acknowledge transferred from the specified slave device.
[7]
Set the second and subsequent bytes (except for the final byte) of transmit data.
[8]
Wait for ICDRT empty.
[9]
Set the last byte of transmit data.
[1]
No
BBSY=0 ?
Yes
Set MST and TRS
in ICCR1 to 1.
[2]
Write 1 to BBSY
and 0 to SCP.
[3]
Write transmit data
in ICDRT
[4]
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Read ACKBR in ICIER
ACKBR=0 ?
No
[10] Wait for last byte to be transmitted.
[6]
[11] Clear the TEND flag.
Yes
Transmit
mode?
Yes
No
Write transmit data in ICDRT
Mater receive mode
[7]
[12] Clear STOP flag.
Read TDRE in ICSR
No
[8]
[14] Wait for the creation of stop condition.
Yes
No
[13] Issue the stop condition.
TDRE=1 ?
[15] Set slave receive mode. Clear TDRE.
Last byte?
Yes
[9]
Write transmit data in ICDRT
Read TEND in ICSR
No
[10]
TEND=1 ?
Yes
Clear TEND in ICSR
[11]
Clear STOP in ISCR
[12]
Write 0 to BBSY
and SCP
[13]
Read STOP in ICSR
No
[14]
STOP=1 ?
Yes
Set MST to 0 and TRS
to 0 in ICCR1
[15]
Clear TDRE in ICSR
End
Figure 16.17 Sample Flowchart for Master Transmit Mode
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Section 16 I C Bus Interface 2 (IIC2)
Master receive mode
[1]
Clear TEND, select master receive mode, and then clear TDRE.*
[2]
Set acknowledge to the transmit device.*
[3]
Dummy-read ICDDR.*
[4]
Wait for 1 byte to be received
[5]
Check whether it is the (last receive - 1).
[6]
Read the receive data last.
[7]
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[8]
Read the (final byte - 1) of receive data.
[9]
Wait for the last byte to be receive.
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
[1]
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
Read RDRF in ICSR
No
[4]
RDRF = 1 ?
Yes
Last receive
- 1?
No
Read ICDRR
Yes
[5]
[10] Clear STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
Set ACKBT in ICIER to 1
[7]
Set RCVD in ICCR1 to 1
Read ICDRR
[13] Read the last byte of receive data.
[14] Clear RCVD.
[8]
[15] Set slave receive mode.
Read RDRF in ICSR
No
RDRF = 1?
Yes
Clear STOP in ICSR
Write 0 to BBSY
and SCP
[9]
[10]
[11]
Read STOP in ICSR
No
[12]
STOP = 1?
Yes
Read ICDRR
[13]
Clear RCVD in ICCR1 to 0
[14]
Clear MST in ICCR1 to 0
[15]
Note: * Do not activate an interrupt during the execution of steps [1] to [3].
End
For single-byte reception, skip steps [2] to [6] after step [1]. Then, jump to
step [7]. Dummy-read in step [8].
Figure 16.18 Sample Flowchart for Master Receive Mode
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Section 16 I C Bus Interface 2 (IIC2)
[1] Clear the AAS flag.
Slave transmit mode
Clear AAS in ICSR
[1]
Write transmit data
in ICDRT
[2]
[3] Wait for ICDRT empty.
[4] Set the last byte of transmit data.
Read TDRE in ICSR
No
[5] Wait for the last byte to be transmitted.
[3]
TDRE=1 ?
Yes
No
[6] Clear the TEND flag .
[7] Set slave receive mode.
Last
byte?
Yes
[2] Set transmit data for ICDRT (except for the last data).
[8] Dummy-read ICDRR to release the SCL line.
[4]
[9] Clear the TDRE flag.
Write transmit data
in ICDRT
Read TEND in ICSR
No
[5]
TEND=1 ?
Yes
Clear TEND in ICSR
[6]
Clear TRS in ICCR1 to 0
[7]
Dummy read ICDRR
[8]
Clear TDRE in ICSR
[9]
End
Figure 16.19 Sample Flowchart for Slave Transmit Mode
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Section 16 I C Bus Interface 2 (IIC2)
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR
[1]
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
[2] Set acknowledge to the transmit device.
[3] Dummy-read ICDRR.
[5] Check whether it is the (last receive - 1).
Read RDRF in ICSR
No
[4]
RDRF = 1?
[6] Read the receive data.
[7] Set acknowledge of the last byte.
Yes
Last receive
- 1?
[4] Wait for 1 byte to be received.
Yes
No
Read ICDRR
[5]
[8] Read the (last byte - 1) of receive data.
[9] Wait the last byte to be received.
[6]
[10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1
[7]
Read ICDRR
[8]
Read RDRF in ICSR
No
[9]
RDRF = 1?
Yes
Read ICDRR
End
[10]
For single-byte reception, skip steps [2] to [6] after
step [1]. Then, jump to step [7]. Dummy-read in step [8].
Figure 16.20 Sample Flowchart for Slave Receive Mode
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Section 16 I C Bus Interface 2 (IIC2)
16.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun. Table 16.3 shows the contents of
each interrupt request.
Table 16.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
I2C Mode
Clock
Synchronous
Mode
Transmit Data Empty
TXI
(TDRE = 1) • (TIE = 1)
{
{
Transmit End
TEI
(TEND = 1) • (TEIE = 1)
{
{
Receive Data Full
RXI
(RDRF = 1) • (RIE = 1)
{
{
STOP Recognition
STPI
(STOP = 1) (STIE = 1)
{
×
NACK Receive
NAKI
{(NACKF = 1) + (AL = 1)}
(NAKIE = 1)
{
×
{
{
Arbitration
Lost/Overrun
•
•
When interrupt conditions described in table 16.3 are 1 and the I bit in CCR is 0, the CPU
executes interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
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Section 16 I C Bus Interface 2 (IIC2)
16.6
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 16.21 shows the timing of the bit synchronous circuit and table 16.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
VIH
SCL
Internal SCL
Figure 16.21 Timing of Bit Synchronous Circuit
Table 16.4 Time for Monitoring SCL
CKS3
CKS2
Time for Monitoring SCL
0
0
7.5 tcyc
1
19.5 tcyc
0
17.5 tcyc
1
41.5 tcyc
1
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Section 16 I C Bus Interface 2 (IIC2)
16.7
16.7.1
Usage Notes
Note on Issuing Stop Condition and Start (Re-Transmit) Condition
The stop condition or start (re-transmit) condition should be issued after recognizing the falling
edge of the ninth clock. The falling edge of the ninth clock can be recognized by checking the
SCLO bit in the I2C control register 2 (ICCR2). Note that if the stop condition or start (retransmit) condition is issued in a particular timing and the situations shown below, these
conditions may not correctly output.
1. The rising edge of the SCL becomes less sharp and longer due to the SCL bus load (load
capacitor and pull-up resistor) than the period defined in section 16.6, Bit Synchronous Circuit.
2. When the slave device elongates the low level period between the eighth and ninth clocks and
activates the bit synchronous circuit.
16.7.2
Note on Setting WAIT Bit in I2C Bus Mode Register (ICMR)
The WAIT bit in the I2C bus mode register (ICMR) should be set to 0. Note that if the WAIT bit is
set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during
the eighth clock, the high level period of the ninth clock may be shorter than a given period.
16.7.3
Restriction on Transfer Rate Setting in Multimaster Operation
In multimaster operation, if the IIC transfer rate setting in this LSI is slower than those of the other
masters, SCL may be output with an unexpected width. To avoid this phenomenon, set the transfer
rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest transfer
rate of the other masters is set to 400 kbps, the IIC transfer rate in this LSI should be set to 223
kbps (= 400/1.18) or more.
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Section 16 I C Bus Interface 2 (IIC2)
16.7.4
Restriction on the Use of Bit Manipulation Instructions for MST and TRS
Setting in Multimaster Operation
In multimaster operation, if the master transmit is set with bit manipulation instructions in the
order from the MST bit to the TRS bit, the AL bit in the ICSR register will be set to 1 but the
master transmit mode (MST = 1, TRS = 1) may be set, depending on the arbitration lost timing. To
avoid this phenomenon, the following actions should be performed:
• In multimaster operation, use the MOV instruction to set bits MST and TRS.
• When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other
than MST = 0 and TRS = 0, set MST = 0 and TRS = 0 again.
16.7.5
Usage Note on Master Receive Mode
In master receive mode, SCL is fixed low on the falling edge of the 8th clock while the RDRF bit
is set to 1. When ICDRR is read around the falling edge of the 8th clock, the clock is only fixed
low in the 8th clock of the next round of data reception. The SCL is then released from its fixed
state without reading ICDRR and the 9th clock is output. As a result, some receive data is lost.
To avoid this phenomenon, the following actions should be performed:
• Read ICDRR in master receive mode before the rising edge of the 8th clock.
• Set RCVD to 1 in master receive mode and perform communication in units of one byte.
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Section 17 A/D Converter
Section 17 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to six
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
17.1.
17.1
Features
•
•
•
•
•
10-bit resolution
Six input channels
High-speed conversion: 12.4 µs per channel (at 10-MHz operation)
Sample and hold function
Conversion start method
A/D conversion can be started by software and external trigger.
• Interrupt source
An A/D conversion end interrupt request can be generated.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The A/D converter is halted as the initial value. For details, refer to section
5.4, Module Standby Function.)
ADTRG
AMR
AN0
AN2
Multiplexer
AN3
AVcc
AN4
AN5
+
Comparator
Control logic
Internal data bus
ADSR
AN1
-
AVCC
Reference
voltage
Vss
ADRR
VSS
[Legend]
AMR:
ADSR:
ADRR:
IRRAD:
A/D mode register
A/D start register
A/D result register
A/D conversion end interrupt request flag
IRRAD
Figure 17.1 Block Diagram of A/D Converter
ADCMS3AA_000020020900
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Section 17 A/D Converter
17.2
Input/Output Pins
Table 17.1 shows the pin configuration of the A/D converter.
Table 17.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVcc
Input
Power supply and reference voltage of
analog part
Ground pin
Vss
Input
Ground and reference voltage
Analog input pin 0
AN0
Input
Analog input pins
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
External trigger input pin
ADTRG
Input
17.3
External trigger input that controls the A/D
conversion start.
Register Descriptions
The A/D converter has the following registers.
• A/D result register (ADRR)
• A/D mode register (AMR)
• A/D start register (ADSR)
17.3.1
A/D Result Register (ADRR)
ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in
the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, but the ADRR value
during A/D conversion is undefined. After A/D conversion is completed, the conversion result is
stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial
value of ADRR is undefined. This register must be read in words.
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Section 17 A/D Converter
17.3.2
A/D Mode Register (AMR)
AMR sets the A/D conversion time, and selects the external trigger and analog input pins.
Bit
Bit Name
Initial
Value
R/W
Description
7

0

Reserved
This bit is always read as 0 and cannot be modified.
6
TRGE
0
R/W
External Trigger Select
Enables or disables the A/D conversion start by the
external trigger input.
0: Disables the A/D conversion start by the external
trigger input.
1: Starts A/D conversion at the rising or falling edge of
the ADTRG pin
The edge of the ADTRG pin is selected by the
ADTRGNEG bit in IEGR.
5
CKS1
0
R/W
Clock Select
4
CKS0
0
R/W
Select the A/D conversion clock source.
00: φ/8
(conversion time = 124 states (max.)
(reference clock = φ)
01: φ/4
(conversion time = 62 states (max.)
(reference clock = φ)
10: φ/2
(conversion time = 31 states (max.)
(reference clock = φ)
11: φw/2
(conversion time = 31 states (max.)
(reference clock = φSUB)
While CKS1 and CKS0 are all 1 in subactive or
subsleep mode, the A/D converter can be used only
when the CPU operating clock is φw.
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Section 17 A/D Converter
Bit
Bit Name
Initial
Value
R/W
Description
3
CH3
0
R/W
Channel Select 3 to 0
2
CH2
0
R/W
Select the analog input channel.
1
CH1
0
R/W
00xx: No channel selected
0
CH0
0
R/W
0100: AN0
0101: AN1
0110: AN2
0111: AN3
1000: AN4
1001: AN5
101x: No channel selected
11xx: No channel selected
The channel selection should be made while the ADSF
bit is cleared to 0.
[Legend] x: Don't care.
17.3.3
A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit
Bit Name
Initial
Value
R/W
Description
7
ADSF
0
R/W
When this bit is set to 1, A/D conversion is started.
When conversion is completed, the converted data is
set in ADRR and at the same time this bit is cleared to
0. If this bit is written to 0, A/D conversion can be
forcibly terminated.
6
LADS
0
R/W
Ladder Resistance Select
0: Ladder resistance operates while the A/D converter
is idle.
1: Ladder resistance is halted while the A/D converter
is idle.
The ladder resistance is always halted in standby
mode, watch mode, or module standby mode, and at a
reset.
5 to 0

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
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Section 17 A/D Converter
17.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing
the conversion time or analog input channel, in order to prevent incorrect operation, first clear the
bit ADSF to 0 in ADSR.
17.4.1
A/D Conversion
1. A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1,
according to software.
2. When A/D conversion is completed, the result is transferred to the A/D result register.
3. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2
is set to 1 at this time, an A/D conversion end interrupt request is generated.
4. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF
bit is automatically cleared to 0 and the A/D converter enters the wait state.
17.4.2
External Trigger Input Timing
The A/D converter can also start A/D conversion by input of an external trigger signal. External
trigger input is enabled at the ADTRG pin when the ADTSTCHG bit in PMRB is set to 1* and the
TRGE bit in AMR is set to 1. Then when the input signal edge designated in the ADTRGNEG bit
in IEGR is detected at the ADTRG pin, the ADSF bit in ADSR will be set to 1, starting A/D
conversion.
Figure 17.2 shows the timing.
Note: * The ADTRG input pin is shared with the TEST pin. Therefore when the pin is used as
the ADTRG pin, reset should be cleared while the 0-fixed signal is input to the TEST
pin. Then the ADTSTCHG bit should be set to 1 after the TEST signal is fixed.
φ
ADTRG
(when
ADTRGNEG = 0)
ADSF
A/D conversion
Figure 17.2 External Trigger Input Timing
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Section 17 A/D Converter
17.4.3
Operating States of A/D Converter
Table 17.2 shows the operating states of the A/D converter.
Table 17.2 Operating States of A/D Converter
Operating
Mode
Reset
Active
Sleep
Watch
AMR
Reset
Functions
Retained
Retained
Subactive
Sub-sleep Standby
Module
Standby
Functions/
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained*2
ADSR
ADRR
Reset
Retained*1
Functions
Functions
Functions
Functions
Retained
Retained
Functions/
Functions/
Retained*2
Retained*2
Functions/
Functions/
Retained*2
Retained*2
Notes: 1. Undefined at a power-on reset.
2. Function if φw/2 is selected as the internal clock. Halted and retained otherwise.
17.5
Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 17.3 shows the operation timing.
1.
2.
3.
4.
5.
6.
Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the
analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D
conversion is started by setting bit ADSF to 1.
When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRR. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the
idle state.
Bit IENAD = 1, so an A/D conversion end interrupt is requested.
The A/D interrupt handling routine starts.
The A/D conversion result is read and processed.
The A/D interrupt handling routine ends.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
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Idle
A/D conversion starts
Set*
Set*
Idle
↓ Read conversion result
A/D conversion result (1)
A/D conversion (1)
Note: * ↓indicates instruction execution by software.
ADRR
Channel 1 (AN1)
operating state
ADSF
IENAD
Interrupt (IRRAD)
A/D conversion (2)
Set*
↓ Read conversion result
A/D conversion result (2)
Idle
Section 17 A/D Converter
Figures 17.4 and 17.5 show flowcharts of procedures for using the A/D converter.
Figure 17.3 Example of A/D Conversion Operation
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Section 17 A/D Converter
Start
Set A/D conversion speed and input channel
Disable A/D conversion end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRR data
Yes
Perform A/D conversion?
No
End
Figure 17.4 Flowchart of Procedure for Using A/D Converter (Polling by Software)
Start
Set A/D conversion speed and input channel
Enable A/D conversion end interrupt
Start A/D conversion
A/D conversion end
interrupt generated?
Yes
Clear IRRAD bit in IRR2 to 0
No
Read ADRR data
Yes
Perform A/D conversion?
No
End
Figure 17.5 Flowchart of Procedure for Using A/D Converter (Interrupts Used)
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Section 17 A/D Converter
17.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.6).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 17.7).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 17.7).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between zero voltage and
full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 17 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
8
2
8
3
8
4
8
5
8
6
8
7 FS
8
Analog
input voltage
Figure 17.6 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 17.7 A/D Conversion Accuracy Definitions (2)
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Section 17 A/D Converter
17.7
17.7.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 10 kΩ or less. This specification is provided to enable
the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling
time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not
be possible to guarantee A/D conversion accuracy. However, with a large capacitance provided
externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and
the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this
case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5
mV/µs or greater) (see figure 17.8). When converting a high-speed analog signal, a lowimpedance buffer should be inserted.
17.7.2
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI
Sensor output
impedance
to 10 kΩ
A/D converter
equivalent circuit
10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
48 pF
Figure 17.8 Example of Analog Input Circuit
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Section 17 A/D Converter
17.7.3
1.
2.
3.
Usage Notes
ADRR should be read only when the ADSF bit in ADSR is cleared to 0.
Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
When A/D conversion is started after clearing module standby mode, wait for 10φ clock
cycles before starting A/D conversion.
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Section 18 Comparators
Section 18 Comparators
This LSI includes comparators to compare the input voltage and reference voltage.
The block diagram of the comparators is shown in figure 18.1.
18.1
Features
• Reference voltage can be specified as internal power supply or external input (VCref).
• When the internal power supply is selected as the reference voltage, programmable selection of
sixteen types of voltages is possible.
• When the internal power supply is selected, the hysteresis characteristics of the comparison
result can be selected.
• Two analog input channels
Each channel includes its own comparator.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (A comparator is halted as the initial value. For details, refer to section 5.4,
Module Standby Function.)
Selector
COMP1
VCref
Comparator
+
Comparator
+
-
CMDR
CMCR0
Internal data bus
Selector
COMP0
CMCR1
26/30
25/30
24/30
4R
R
R
Interrupt
generator
Interrupt
request
10/30
9/30
R
9R
[Legend]
CMDR: Compare data register
CMCR0: Compare control register 0
CMCR1: Compare control register 1
Figure 18.1 Block Diagram of Comparators
ADCMS3AA_000020020900
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Section 18 Comparators
18.2
Input/Output Pins
Table 18.1 shows the pin configuration of the comparators.
Table 18.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Comparator reference
voltage
VCref
Input
Comparator reference voltage pin
(external input)
Analog input channel 0
COMP0
Input
Comparator analog input pin 0
Analog input channel 1
COMP1
Input
Comparator analog input pin 1
18.3
Register Descriptions
The comparators have the following registers. For details on register addresses and register states
during each processing, refer to section 20, List of Registers.
• Compare control registers 0, 1 (CMCR0, CMCR1)
• Compare data register (CMDR)
18.3.1
Compare Control Registers 0, 1 (CMCR0, CMCR1)
CMCR0 and CMCR1 control the comparators.
Bit
Bit Name
Initial
Value
R/W
Description
7
CME
0
R/W
Comparator Enable
0: Comparator halted
1: Comparator operates
6
CMIE
0
R/W
Comparator Interrupt Enable
0: Disables a comparator interrupt
1: Enables a comparator interrupt
5
CMR
0
R/W
Comparator Reference Voltage Select
0: Selects internal power supply as reference voltage
1: Reference voltage is input from VCref pin
For the combination of the CMR and CMLS bits.
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Section 18 Comparators
Bit
Bit Name
Initial
Value
R/W
Description
4
CMLS
0
R/W
Comparator Hysteresis Select
0: Selects non-hysteresis
1: Selects hysteresis
When CMR = 1, clear this bit to 0.
For the combination of the CMR and CMLS bits.
3
CRS3
0
R/W
Internal Reference Voltage Select
2
CRS2
0
R/W
1
CRS1
0
R/W
When CMR = 0 and CMLS = 0, the electric potential of
VIL is selected as the internal power supply.
0
CRS0
0
R/W
When CMR = 0 and CMLS = 1, VIL will be as follows.
When CMR = 1, CRS3 to CRS0 settings are disabled.
VIH
VIL
0000: 11/30Vcc
9/30Vcc
0001: 12/30Vcc
10/30Vcc
0010: 13/30Vcc
11/30Vcc
0011: 14/30Vcc
12/30Vcc
0100: 15/30Vcc
13/30Vcc
0101: 16/30Vcc
14/30Vcc
0110: 17/30Vcc
15/30Vcc
0111: 18/30Vcc
16/30Vcc
1000: 19/30Vcc
17/30Vcc
1001: 20/30Vcc
18/30Vcc
1010: 21/30Vcc
19/30Vcc
1011: 22/30Vcc
20/30Vcc
1100: 23/30Vcc
21/30Vcc
1101: 24/30Vcc
22/30Vcc
1110: 25/30Vcc
23/30Vcc
1111: 26/30Vcc
24/30Vcc
For the selectable range by the CRS bits, see section
21, Electrical Characteristics.
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Section 18 Comparators
Table 18.2 Combination of CMR and CMLS Bits
CMR
CMLS
Function
0
0
Compares the internal power supply (voltage set for VIH by the CRS3
to CRS0 bits) and electric potential of the COMP pin.
No hysteresis.
1
Compares the internal power supply and electric potential of the
COMP pin.
With hysteresis. VIH and VIL are set by the CRS3 to CRS0 bits.
1
0
Compares the electric potential of the VCref and COMP pins.
No hysteresis.
1
18.3.2
Setting prohibited
Compare Data Register (CMDR)
CMDR stores the result of comparing the analog input pin and reference voltage.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0

Reserved
These bits are always read as 0.
5
CMF1
0
1
R/(W)* COMP1 Interrupt Flag
[Setting condition]
When COMP1 interrupt occurs
[Clearing condition]
0 is written to CMF1 after reading CMF1 = 1
4
CMF0
0
1
R/(W)* COMP0 Interrupt Flag
[Setting condition]
When COMP0 interrupt occurs
[Clearing condition]
0 is written to CMF0 after reading CMF0 = 1
3, 2

All 0

Reserved
These bits are always read as 0.
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Section 18 Comparators
Bit
1
Bit Name
Initial
Value
R/W
Description
CDR1
*
R
[Setting condition]
2
COMP1 pin > Reference voltage
[Clearing condition]
COMP1 pin ≤ Reference voltage
0
CDR0
*2
R
[Setting condition]
COMP0 pin > Reference voltage
[Clearing condition]
COMP0 pin ≤ Reference voltage
Notes: 1. Only 0 can be written to clear the flag.
2. Depends on the pin state and reference voltage.
18.4
18.4.1
Operation
Operation Sequence
The operation sequence of a comparator is as follows:
1. When using VCref, the pins to be used are enabled by the corresponding port mode registers.
For details, see section 8, I/O Ports.
2. Select the reference voltage (CMR setting: internal power supply or VCref).
When the internal power supply is selected as the reference voltage, select the hysteresis
characteristics (CMLS setting) and reference voltage (CRS3 to CRS0 setting).
3. Set the comparator enable bit (CME).
4. After setting CME, wait for the conversion time (see section 21, Electrical Characteristics) so
that the comparator becomes stabilized.
5. Read from CDR.
6. After reading the CMF flag, write 0 to it (reading the CMF flag can be performed
simultaneously with step 5).
7. If an interrupt is to be generated, set the comparator interrupt enable bit (CMIE).
Note: Steps 2 and 3 can be done simultaneously by writing to the entire register.
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Section 18 Comparators
18.4.2
Hysteresis Characteristics of Comparator
Figure 18.2 shows CDR when hysteresis is or is not selected by the CMLS bit CMCR and the
input voltage to the COMP pins. The hysteresis characteristics for the comparison result (CDR) by
the comparator can be selected by the CMLS bit, as shown in figure 18.2.
When CMR = 0 and CRS3 to CRS0 = B'1000 (VIH = 19/30Vcc, VIL = 17/30Vcc)
COMP pin input voltage
19/30 Vcc
17/30 Vcc
CDR (CMLS = 0)
CDR (CMLS = 1)
Figure 18.2 Hysteresis/Non-Hysteresis Selection by CDR
18.4.3
Interrupt Setting
When the CDR bit is read while the comparator interrupt is enabled and both the CME and CMIE
bits are set to 1, it is latched in the internal latch. When a difference occurs between the output of
the latch and the CDR bit, the interrupt is generated. While the CDR bit is being read, the interrupt
is masked.
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Section 18 Comparators
To set the interrupt, follow the procedure shown in figure 18.3 or 18.4.
[1]
Set the CME bit. Wait a conversion time for the comparator stabilized.
[2]
Read the CDR bit.
[3]
Set the CMIE bit.
[4]
Read the CDR bit. At this time, the CDR bit is latched in the internal latch for the comparator
and the internal interrupt enable signal is asserted.
[5]
As the relationship between the voltage on the COMP pin and reference voltage is changed,
a difference occurs between the output level of the internal latch and the CDR bit. Then an
interrupt is generated.
[6]
Clear the CMF bit in the interrupt handler. When reading the CMF bit for clearing it, the CDR bit is
also read since those bits are in the same register. Therefore, the output of the internal latch is
updated. Go to step [5] to continue use of the interrupt.
[7]
Clear the CMIE bit to clear the interrupt setting and clear the CME bit to stop the comparator.
Clearing the CMIE bit negates the internal interrupt enable signal.
The interrupt flag may be set depending on the internal states of the comparator, pin states, the
timing of setting the internal interrupt enable signal shown in step [4], and the timing of the CDR bit
latched. To avoid this, execute steps [2] to [4] continuously or ensure that the CMF bit is cleared
using the I bit in CCR as shown in figure 18.4.
When CMR = 0 and CMRS3 to CMRS0 = B'1000 (VIH = 19/30 Vcc)
19/30 Vcc
Voltage on
COMP pin
Conversion time
Conversion time
CDR (CMLS = 0)
CME
[1]
[7]
[3]
[7]
CMIE
Interrupt enable signal
Stabilization time
(conversion time)
CDR read signal
Internal latch
for comparator
[2]
Unstable
[4]
[6]
[6]
[4]
[6]
[6]
CMF
[5]
[6]
[5]
[6]
Figure 18.3 Procedure for Setting Interrupt (1)
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Section 18 Comparators
Set I bit in CCR to 1
Disable interrupts by the I bit.
Set CME bit to 1
Set the comparator enable bit to 1.
Wait for the comparator stabilized.
Set CMIE bit to 1
Enable the interrupt. Actually, the
interrupt is masked by the I bit.
Read CDR bit
The CDR bit is latched in the internal
latch by reading it.
Clear CMF bit
Clear the interrupt request flag.
Clear I bit in CCR to 0
Enable interrupts by the I bit.
Figure 18.4 Procedure for Setting Interrupt (2)
18.5
Usage Notes
1. The COMP pin whose channel is operating as a comparator becomes a comparator analog
input pin. It cannot be used for any other function.
2. When external input is used as the reference voltage (CMR0 = 1 or CMR1 = 1), the VCref pin
cannot be used for any other function.
3. To stop the operation of a comparator, clear the CME0 and CME1 bits in CMCR0 and
CMCR1 to 0, before clearing the COMPCKSTP bit in CKSTPR2 to 0.
4. If the LSI enters the standby mode or watch mode when a comparator is operating, the internal
operation of the comparator is maintained. Since the comparator operates even in standby
mode or watch mode, it returns to the same mode after the specified interrupt is canceled,
though the current for the comparator is consumed.
If a comparator is not required to return to the standby mode or watch mode when an interrupt
is canceled and the current consumption needs to be reduced, stop the comparator by clearing
the CME0 and CME1 bits in CMCR0 and CMCR1 to 0 before shifting the mode.
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Section 19 Power-On Reset Circuit
Section 19 Power-On Reset Circuit
This LSI has an on-chip power-on reset circuit. A block diagram of the power-on reset circuit is
shown in figure 19.1.
19.1
Feature
• Power-on reset circuit
An internal reset signal is generated at turning the power on by externally connecting a
capacitor.
Vcc
φ
Vcc
CK
R
3-bit
counter
COUT
Rp
RES
R
Voltage
detector
Q
S
Internal
reset signal
CRES
Figure 19.1 Power-On Reset Circuit
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Section 19 Power-On Reset Circuit
19.2
Operation
19.2.1
Power-On Reset Circuit
The operation timing of the power-on reset circuit is shown in figure 19.2. As the power supply
voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged
through the on-chip pull-up resistor (Rp). The low level of the RES pin is sent to the LSI and the
whole LSI is reset. When the level of the RES pin reaches to the predetermined level, a voltage
detection circuit detects it. Then a 3-bit counter starts counting up. When the 3-bit counter counts
φ for 8 times, an overflow signal is generated and an internal reset signal is negated.
The capacitance (CRES) which is connected to the RES pin can be computed using the following
formula; where the RES rising time is t. For the on-chip resistor (Rp), see section 21, Electrical
Characteristics. The power supply rising time (t_vtr) should be shorter than half the RES rising
time (t). The RES rising time (t) is also should be longer than the oscillation stabilization time
(trc).
CRES =
t
Rp
(t > trc, t > t_vtr × 2)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
t_vtr
Vcc
t_vtr × 2
RES
V_rst
Internal reset
signal
t_cr
t_out (eight states)
Figure 19.2 Power-On Reset Circuit Operation Timing
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Section 20 List of Registers
Section 20 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1.
•
•
•
•
Register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified by functional modules.
The data bus width is indicated.
The number of access states is indicated.
2.
•
•
•
Register bits
Bit configurations of the registers are described in the same order as the register addresses.
Reserved bits are indicated by  in the bit name column.
When the bit number is in the bit name column, it indicates that the entire register is allocated
to a counter or data.
• When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 20 List of Registers
20.1
Register Addresses (Address Order)
The data bus width indicates the number of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbreviation
Address
Module
Name
Data Bus Access
Width
State
Flash memory control register 1
FLMCR1
H'F020
ROM
8
2
Flash memory control register 2
FLMCR2
H'F021
ROM
8
2
Flash memory power control register
FLPWCR
H'F022
ROM
8
2
Erase block register 1
EBR1
H'F023
ROM
8
2
Flash memory enable register
FENR
H'F02B
ROM
8
2
RTC interrupt flag register
RTCFLG
H'F067
RTC
8
2
Second data register/free running
counter data register
RSECDR
H'F068
RTC
8
2
Minute data register
RMINDR
H'F069
RTC
8
2
Hour data register
RHRDR
H'F06A
RTC
8
2
Day-of-week data register
RWKDR
H'F06B
RTC
8
2
RTC control register 1
RTCCR1
H'F06C
RTC
8
2
RTC control register 2
RTCCR2
H'F06D
RTC
8
2
Clock source select register
RTCCSR
H'F06F
RTC
8
2
I2C bus control register 1
ICCR1
H'F078
IIC2
8
2
2
ICCR2
H'F079
IIC2
8
2
2
ICMR
H'F07A
IIC2
8
2
2
ICIER
H'F07B
IIC2
8
2
2
I C bus status register
ICSR
H'F07C
IIC2
8
2
Slave address register
I C bus control register 2
I C bus mode register
I C bus interrupt enable register
SAR
H'F07D
IIC2
8
2
2
ICDRT
H'F07E
IIC2
8
2
2
ICDRR
H'F07F
IIC2
8
2
I C bus transmit data register
I C bus receive data register
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Section 20 List of Registers
Register Name
Abbreviation
Address
Module
Name
Data Bus Access
Width
State
Port function control register
PFCR
H'F085
System
8
2
Port pull-up control register 8
PUCR8
H'F086
I/O ports
8
2
Port pull-up control register 9
PUCR9
H'F087
I/O ports
8
2
Port open-drain control register 9
PODR9
H'F08C
I/O ports
8
2
Timer mode register B1
TMB1
H'F0D0
Timer B1
8
2
Timer counter B1/
Timer load register B1
TCB1 (R)/
TLB1 (W)
H'F0D1
Timer B1
8
2
Compare control register 0
CMCR0
H'F0DC
Comparator 8
2
Compare control register 1
CMCR1
H'F0DD
Comparator 8
2
Compare data register
CMDR
H'F0DE
Comparator 8
2
SS control register H
SSCRH
H'F0E0
1
8
3
1
SSU*
SS control register L
SSCRL
H'F0E1
SSU*
8
3
SS mode register
SSMR
H'F0E2
SSU*1
8
3
H'F0E3
1
8
3
1
8
3
1
8
3
1
SS enable register
SS status register
SS receive data register
SSER
SSSR
SSRDR
H'F0E4
H'F0E9
SSU*
SSU*
SSU*
SS transmit data register
SSTDR
H'F0EB
SSU*
8
3
Timer mode register W
TMRW
H'F0F0
Timer W
8
2
Timer control register W
TCRW
H'F0F1
Timer W
8
2
Timer interrupt enable register W
TIERW
H'F0F2
Timer W
8
2
Timer status register W
TSRW
H'F0F3
Timer W
8
2
Timer I/O control register 0
TIOR0
H'F0F4
Timer W
8
2
Timer I/O control register 1
TIOR1
H'F0F5
Timer W
8
2
Timer counter
TCNT
H'F0F6
Timer W
16
2
General register A
GRA
H'F0F8
Timer W
16
2
General register B
GRB
H'F0FA
Timer W
16
2
General register C
GRC
H'F0FC
Timer W
16
2
General register D
GRD
H'F0FE
Timer W
16
2
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Section 20 List of Registers
Register Name
Abbreviation
Event counter PWM compare register ECPWCR
Address
Module
Name
Data Bus Access
Width
State
H'FF8C
AEC*2
16
2
2
Event counter PWM data register
ECPWDR
H'FF8E
AEC*
16
2
Serial port control register
SPCR
H'FF91
SCI3
Input pin edge select register
AEGSR
H'FF92
8
2
2
8
2
2
AEC*
Event counter control register
ECCR
H'FF94
AEC*
8
2
Event counter control/status register
ECCSR
H'FF95
AEC*2
8
2
H'FF96
2
8
2
2
Event counter H
ECH
AEC*
Event counter L
ECL
H'FF97
AEC*
8
2
Serial mode register 3
SMR3
H'FF98
SCI3
8
3
Bit rate register 3
BRR3
H'FF99
SCI3
8
3
Serial control register 3
SCR3
H'FF9A
SCI3
8
3
Transmit data register 3
TDR3
H'FF9B
SCI3
8
3
Serial status register 3
SSR3
H'FF9C
SCI3
8
3
Receive data register 3
RDR3
H'FF9D
SCI3
8
3
Serial extended mode register
SEMR
H'FFA6
SCI3
8
3
IrDA control register
IrCR
H'FFA7
IrDA
Timer mode register WD
Timer control/status register WD1
Timer control/status register WD2
TMWD
H'FFB0
TCSRWD1 H'FFB1
TCSRWD2 H'FFB2
8
2
3
8
2
3
8
2
3
8
2
3
WDT*
WDT*
WDT*
Timer counter WD
TCWD
H'FFB3
WDT*
8
2
A/D result register
ADRR
H'FFBC
A/D
converter
16
2
A/D mode register
AMR
H'FFBE
A/D
converter
8
2
A/D start register
ADSR
H'FFBF
A/D
converter
8
2
Rev. 3.00 May 15, 2007 Page 374 of 516
REJ09B0152-0300
Section 20 List of Registers
Register Name
Abbreviation
Address
Module
Name
Data Bus Access
Width
State
Port mode register 1
PMR1
H'FFC0
I/O ports
8
2
Port mode register 3
PMR3
H'FFC2
I/O ports
8
2
Port mode register B
PMRB
H'FFCA
I/O ports
8
2
Port data register 1
PDR1
H'FFD4
I/O ports
8
2
Port data register 3
PDR3
H'FFD6
I/O ports
8
2
Port data register 8
PDR8
H'FFDB
I/O ports
8
2
Port data register 9
PDR9
H'FFDC
I/O ports
8
2
Port data register B
PDRB
H'FFDE
I/O ports
8
2
Port pull-up control register 1
PUCR1
H'FFE0
I/O ports
8
2
Port pull-up control register 3
PUCR3
H'FFE1
I/O ports
8
2
Port control register 1
PCR1
H'FFE4
I/O ports
8
2
Port control register 3
PCR3
H'FFE6
I/O ports
8
2
Port control register 8
PCR8
H'FFEB
I/O ports
8
2
Port control register 9
PCR9
H'FFEC
I/O ports
8
2
System control register 1
SYSCR1
H'FFF0
System
8
2
System control register 2
SYSCR2
H'FFF1
System
8
2
Interrupt edge select register
IEGR
H'FFF2
Interrupts
8
2
Interrupt enable register 1
IENR1
H'FFF3
Interrupts
8
2
Interrupt enable register 2
IENR2
H'FFF4
Interrupts
8
2
Oscillator control register
OSCCR
H'FFF5
System
8
2
Interrupt flag register 1
IRR1
H'FFF6
Interrupts
8
2
Interrupt flag register 2
IRR2
H'FFF7
Interrupts
8
2
Clock stop register 1
CKSTPR1 H'FFFA
System
8
2
Clock stop register 2
CKSTPR2 H'FFFB
System
8
2
Notes: 1. SSU: Synchronous serial communication unit
2. AEC: Asynchronous event counter
3. WDT: Watchdog timer
Rev. 3.00 May 15, 2007 Page 375 of 516
REJ09B0152-0300
Section 20 List of Registers
20.2
Register Bits
Register bit names of the on-chip peripheral modules are described below.
The 16-bit register is indicated in two rows, 8 bits for each row.
Register
Module
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
FLMCR1

SWE
ESU
PSU
EV
PV
E
P
ROM
FLMCR2
FLER







FLPWCR
PDWND







EBR1



EB4
EB3
EB2
EB1
EB0
FENR
FLSHE







RTCFLG
FOIFG
WKIFG
DYIFG
HRIFG
MNIFG
1SEIFG
05SEIFG
025SEIFG
SC00
RSECDR
BSY
SC12
SC11
SC10
SC03
SC02
SC01
RMINDR
BSY
MN12
MN11
MN10
MN03
MN02
MN01
MN00
RHRDR
BSY

HR11
HR10
HR03
HR02
HR01
HR00
RWKDR
BSY




WK2
WK1
WK0
RTCCR1
RUN
12/24
PM
RST
INT



RTCCR2
FOIE
WKIE
DYIE
HRIE
MNIE
1SEIE
05SEIE
025SEIE
RTCCSR

RCS6
RCS5
SUB32K
RCS3
RCS2
RCS1
RCS0
ICCR1
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0

RTC
IIC2
ICCR2
BBSY
SCP
SDAO
SDAOP
SCLO

IICRST
ICMR
MLS
WAIT


BCWP
BC2
BC1
BC0
ICIER
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
ICSR
TDRE
TEND
RDRF
NACKF
STOP
AL/OVE
AAS
ADZ
SAR
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
ICDRT
ICDRT7
ICDRT6
ICDRT5
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
ICDRR
ICDRR7
ICDRR6
ICDRR5
ICDRR4
ICDRR3
ICDRR2
ICDRR1
ICDRR0
PFCR



SSUS
IRQ1S1
IRQ1S0
IRQ0S1
IRQ0S0
System
PUCR8



PUCR84
PUCR83
PUCR82


I/O ports
PUCR9




PUCR93
PUCR92
PUCR91
PUCR90
PODR9




P93ODR
P92ODR
P91ODR
P90ODR
TMB1
TMB17
TMB16



TMB12
TMB11
TMB10
TCB1 (R)/
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TLB1 (W)
Rev. 3.00 May 15, 2007 Page 376 of 516
REJ09B0152-0300
Timer B1
Section 20 List of Registers
Register
Module
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CMCR0
CME0
CMIE0
CMR0
CMLS0
CRS03
CRS02
CRS01
CRS00
Comparator
CMCR1
CME1
CMIE1
CMR1
CMLS1
CRS13
CRS12
CRS11
CRS10
CMDR


CMF1
CMF0


CDR1
CDR0
SSCRH
MSS
BIDE
SOOS
SOL
SOLP
SCKS
CSS1
CSS0
SSCRL

SSUMS
SRES
SCKOS
CSOS
—
—
—
SSMR
MLS
CPOS
CPHS
—
—
CKS2
CKS1
CKS0
SSER
TE
RE
RSSTP
—
TEIE
TIE
RIE
CEIE
SSSR
—
ORER
—
—
TEND
TDRE
RDRF
CE
SSRDR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSTDR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMRW
CTS
—
BUFEB
BUFEA
—
PWMD
PWMC
PWMB
TCRW
CCLR
CKS2
CKS1
CKS0
TOD
TOC
TOB
TOA
TIERW
OVIE
—
—
—
IMIED
IMIEC
IMIEB
IMIEA
TSRW
OVF
—
—
—
IMFD
IMFC
IMFB
IMFA
TIOR0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
TIOR1
—
IOD2
IOD1
IOD0
—
IOC2
IOC1
IOC0
TCNT
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
GRA15
GRA14
GRA13
GRA12
GRA11
GRA10
GRA9
GRA8
GRA7
GRA6
GRA5
GRA4
GRA3
GRA2
GRA1
GRA0
GRB15
GRB14
GRB13
GRB12
GRB11
GRB10
GRB9
GRB8
GRB7
GRB6
GRB5
GRB4
GRB3
GRB2
GRB1
GRB0
GRC15
GRC14
GRC13
GRC12
GRC11
GRC10
GRC9
GRC8
GRC7
GRC6
GRC5
GRC4
GRC3
GRC2
GRC1
GRC0
GRD15
GRD14
GRD13
GRD12
GRD11
GRD10
GRD9
GRD8
GRD7
GRD6
GRD5
GRD4
GRD3
GRD2
GRD1
GRD0
GRA
GRB
GRC
GRD
ECPWCR
ECPWDR
ECPWCR15 ECPWCR14 ECPWCR13 ECPWCR12 ECPWCR11 ECPWCR10 ECPWCR9
ECPWCR8
ECPWCR7
ECPWCR1
ECPWCR0
ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9
ECPWDR8
ECPWDR7
ECPWDR0
ECPWCR6
ECPWDR6
ECPWCR5
ECPWDR5
ECPWCR4
ECPWDR4
ECPWCR3
ECPWDR3
ECPWCR2
ECPWDR2
ECPWDR1
SSU*1
Timer W
AEC*2
Rev. 3.00 May 15, 2007 Page 377 of 516
REJ09B0152-0300
Section 20 List of Registers
Register
Module
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SPCR



SPC3


SCINV1
SCINV0
SCI3
AEGSR
AHEGS1
AHEGS0
ALEGS1
ALEGS0
AIEGS1
AIEGS0
ECPWME

AEC*2
ECCR
ACKH1
ACKH0
ACKL1
ACKL0
PWCK2
PWCK1
PWCK0

ECCSR
OVH
OVL

CH2
CUEH
CUEL
CRCH
CRCL
ECH
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
ECL
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
SMR3
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
BRR3
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Bit 0
Name
SCI3
SCR3
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR3
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR3
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
RDR3
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
SEMR




ABCS



IrCR
IrE
IrCKS2
IrCKS1
IrCKS0




IrDA
TMWD




CKS3
CKS2
CKS1
CKS0
WDT*3
TCSRWD1
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
TCSRWD2
OVF
B5WI
WT/IT
B3WI
IEOVF



TCWD
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
ADRR
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
A/D
ADR1
ADR0






converter
AMR

TRGE
CKS1
CKS0
CH3
CH2
CH1
CH0
ADSR
ADSF
LADS






PMR1


IRQAEC
FTCI
AEVL
CLKOUT
TMOW
AEVH
PMR3







VCref
PMRB




ADTSTCHG

IRQ1
IRQ0
PDR1





P12
P11
P10
PDR3





P32
P31
P30
PDR8



P84
P83
P82


PDR9




P93
P92
P91
P90
PDRB


PB5
PB4
PB3
PB2
PB1
PB0
PUCR1





PUCR12
PUCR11
PUCR10
Rev. 3.00 May 15, 2007 Page 378 of 516
REJ09B0152-0300
I/O ports
Section 20 List of Registers
Register
Module
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PUCR3





PUCR32
PUCR31
PUCR30
I/O ports
PCR1





PCR12
PCR11
PCR10
PCR3





PCR32
PCR31
PCR30
PCR8



PCR84
PCR83
PCR82


PCR9




PCR93
PCR92
PCR91
PCR90
SYSCR1
SSBY
STS2
STS1
STS0
LSON
TMA3
MA1
MA0
SYSCR2



NESEL
DTON
MSON
SA1
SA0
IEGR
NMIEG

ADTRGNEG



IEG1
IEG0
IENR1
IENRTC




IENEC2
IEN1
IEN0
IENR2

IENAD



IENTB1

IENEC
OSCCR
SUBSTP
RFCUT
SUBSEL



OSCF

System
IRR1





IRREC2
IRRI1
IRRI0
Interrupts
IRR2

IRRAD



IRRTB1

IRREC
CKSTPR1

S3CKSTP

ADCKSTP

TB1CKSTP
FROMCKSTP
RTCCKSTP System
CKSTPR2

TWCKSTP
IICCKSTP
SSUCKSTP
AECCKSTP
WDCKSTP
COMPCKSTP

System
Interrupts
Notes: 1. SSU: Synchronous serial communication unit
2. AEC: Asynchronous event counter
3. WDT: Watchdog timer
Rev. 3.00 May 15, 2007 Page 379 of 516
REJ09B0152-0300
Section 20 List of Registers
20.3
Register States in Each Operating Mode
Register
Abbreviation
Reset
Active
Sleep Watch
Subactive Subsleep Standby
Module
FLMCR1
Initialized





Initialized
ROM
FLMCR2
Initialized






FLPWCR
Initialized






EBR1
Initialized





Initialized
FENR
Initialized






RTCFLG







RSECDR







RMINDR







RHRDR







RWKDR







RTCCR1







RTCCR2







RTCCSR
Initialized






ICCR1
Initialized






ICCR2
Initialized






ICMR
Initialized






ICIER
Initialized






ICSR
Initialized






SAR
Initialized






ICDRT
Initialized






ICDRR
Initialized






PFCR
Initialized






System
PUCR8
Initialized






I/O ports
PUCR9
Initialized






PODR9
Initialized






TMB1
Initialized






TCB1/TLB1
Initialized






Rev. 3.00 May 15, 2007 Page 380 of 516
REJ09B0152-0300
RTC
IIC2
Timer B1
Section 20 List of Registers
Register
Abbreviation
Reset
Active
Sleep Watch
Subactive Subsleep Standby
Module
CMCR0
Initialized






Comparator
CMCR1
Initialized






CMDR
Initialized






SSCRH
Initialized






SSCRL
Initialized






SSMR
Initialized






SSER
Initialized






SSSR
Initialized






SSRDR
Initialized






SSTDR
Initialized






TMRW
Initialized






TCRW
Initialized






TIERW
Initialized






TSRW
Initialized






TIOR0
Initialized






TIOR1
Initialized






TCNT
Initialized






GRA
Initialized






GRB
Initialized






GRC
Initialized






GRD
Initialized






ECPWCR
Initialized






ECPWDR
Initialized






SPCR
Initialized






SCI3
AEGSR
Initialized






AEC*
ECCR
Initialized






ECCSR
Initialized






ECH
Initialized






ECL
Initialized






1
SSU*
Timer W
2
AEC*
2
Rev. 3.00 May 15, 2007 Page 381 of 516
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Section 20 List of Registers
Register
Abbreviation
Reset
Active
Sleep Watch
Subactive Subsleep Standby
Module
SCI3
SMR3
Initialized


Initialized


Initialized
BRR3
Initialized


Initialized


Initialized
SCR3
Initialized


Initialized


Initialized
TDR3
Initialized


Initialized


Initialized
SSR3
Initialized


Initialized


Initialized
RDR3
Initialized


Initialized


Initialized
SEMR
Initialized


Initialized


Initialized
IrCR
Initialized


Initialized


Initialized
IrDA
TMWD
Initialized






WDT*
TCSRWD1
Initialized






TCSRWD2
Initialized






TCWD
Initialized






ADRR







AMR
Initialized






ADSR
Initialized






PMR1
Initialized






PMR3
Initialized






PMRB
Initialized






PDR1
Initialized






PDR3
Initialized






PDR8
Initialized






PDR9
Initialized






PDRB
Initialized






PUCR1
Initialized






PUCR3
Initialized






PCR1
Initialized






PCR3
Initialized






PCR8
Initialized






PCR9
Initialized






Rev. 3.00 May 15, 2007 Page 382 of 516
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3
A/D
converter
I/O ports
Section 20 List of Registers
Register
Abbreviation
Reset
Active
Sleep Watch
Subactive Subsleep Standby
Module
SYSCR1
Initialized






System
SYSCR2
Initialized






IEGR
Initialized






IENR1
Initialized






IENR2
Initialized






OSCCR
Initialized






System
IRR1
Initialized






Interrupts
IRR2
Initialized






CKSTPR1
Initialized






CKSTPR2
Initialized






Interrupts
System
Notes:  is not initialized.
1. SSU: Synchronous serial communication unit
2. AEC: Asynchronous event counter
3. WDT: Watchdog timer
Rev. 3.00 May 15, 2007 Page 383 of 516
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Section 20 List of Registers
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Section 21 Electrical Characteristics
Section 21 Electrical Characteristics
21.1
Absolute Maximum Ratings for F-ZTAT Version
Table 21.1 lists the absolute maximum ratings.
Table 21.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +4.3
V
*1
Analog power supply voltage
AVCC
–0.3 to +4.3
V
Input voltage
Other than port B
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
Topr
–20 to +75
(general
2
specifications)*
°C
Operating temperature
–40 to +85
(wide temperature
range
2
specifications)*
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may occur to the LSI if absolute maximum ratings are exceeded.
Normal operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. The operating temperature range for flash memory programming/erasing is Ta = 0 to
+75°C.
Rev. 3.00 May 15, 2007 Page 385 of 516
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Section 21 Electrical Characteristics
21.2
Electrical Characteristics for F-ZTAT Version
21.2.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) System clock oscillator selected (10-MHz version)
fW (kHz)
fosc (MHz)
10.0
38.4
32.768
4.0
1.8
1.8
2.7 3.6 Vcc (V)
• All operating modes
• Refer to note
2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
fW (kHz)
Rosc/32 used (reference value)
81.25
9.375
2.7 3.6 Vcc (V)
1.8
• All operating modes
fW (kHz)
fosc (MHz)
(2) System clock oscillator selected (4-MHz version)
4.2
38.4
32.768
2.0
1.8
2.7 3.6 Vcc (V)
1.8
• All operating modes
• Refer to note
2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
fW (kHz)
Rosc/32 used (reference value)
81.25
9.375
2.7 3.6 Vcc (V)
1.8
• All operating modes
Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation
stabilization time has elapsed after switching on.
Figure 21.1 Power Supply Voltage and Oscillation Frequency Range (1)
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Section 21 Electrical Characteristics
(3) On-chip oscillator selected
fW (kHz)
fosc (MHz)
Rosc used (reference value)
2.6
38.4
32.768
0.3
1.8
2.7
1.8
2.7 3.6 Vcc (V)
• All operating modes
• Refer to note
3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
fW (kHz)
Rosc/32 used (reference value)
81.25
9.375
1.8
2.7 3.6 Vcc (V)
• All operating modes
Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation
stabilization time has elapsed after switching on.
Figure 21.2 Power Supply Voltage and Oscillation Frequency Range (2)
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Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version)
10.0
38.4
32.768
φ (MHz)
φSUB (kHz)
19.2
16.384
9.6
8.192
4.0
4.8
4.096
1.8
2.7 3.6 Vcc (V)
1.8
• Active (high-speed) mode
• Sleep (high-speed) mode
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
1250
φ (kHz)
62.5
φSUB (kHz)
Rosc/32 used (reference value)
1.8
2.7 3.6 Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
81.25
1.172
1.8
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
Figure 21.3 Power Supply Voltage and Operating Frequency Range (1)
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REJ09B0152-0300
Section 21 Electrical Characteristics
(2) System clock oscillator selected (4-MHz version)
38.4
φ SUB (kHz)
32.768
19.2
16.384
9.6
φ (MHz)
8.192
4.2
4.8
4.096
2.0
1.8 2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
1.8 2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
φ (kHz)
525
Rosc/32 used (reference value)
φ SUB (kHz)
31.25
1.8
2.7 3.6 Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
81.25
1.172
1.8
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
Figure 21.4 Power Supply Voltage and Operating Frequency Range (2)
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Section 21 Electrical Characteristics
(3) On-chip oscillator selected
38.4
32.768
φ (MHz)
Rosc used (reference value)
φ SUB (kHz)
19.2
16.384
9.6
8.192
4.8
2.6
4.096
0.3
1.8 2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
1.8 2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Rosc used (reference value)
Rosc/32 used (reference value)
φ SUB (kHz)
φ (kHz)
325
4.6875
1.8
2.7 3.6 Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
81.25
1.172
1.8
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
Figure 21.5 Power Supply Voltage and Operating Frequency Range (3)
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Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version)
38.4
φ SUB (kHz)
φ (MHz)
10.0
4.0
1.8
2.7
32.768
1.8
2.7
• All operating modes
3.6 AVcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
3.6 AVcc (V)
Rosc/32 used (reference value)
φ SUB (kHz)
81.25
9.375
1.8
2.7
• All operating modes
3.6 AVcc (V)
(2) System clock oscillator selected (4-MHz version)
φ SUB (kHz)
φ (MHz)
38.4
4.2
2.0
1.8
2.7
32.768
1.8
2.7
• All operating modes
3.6 AVcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
3.6 AVcc (V)
Rosc/32 used (reference value)
φ SUB (kHz)
81.25
9.375
1.8
2.7
• All operating modes
3.6 AVcc (V)
Figure 21.6 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (1)
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Section 21 Electrical Characteristics
(3) On-chip oscillator selected
φSUB (kHz)
φ (MHz)
Rosc used (reference value)
2.6
38.4
32.768
0.3
1.8
2.7
1.8
3.6 AVcc (V)
2.7
3.6 AVcc (V)
• All operating modes
• Active (high-speed) mode
• Sleep (high-speed) mode
φSUB (kHz)
Rosc/32 used (reference value)
81.25
9.375
1.8
2.7
• All operating modes
3.6 AVcc (V)
Figure 21.7 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (2)
Rev. 3.00 May 15, 2007 Page 392 of 516
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Section 21 Electrical Characteristics
21.2.2
DC Characteristics
Table 21.2 lists the DC characteristics.
Table 21.2 DC Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values
Item
Symbol
Applicable Pins Test Condition
Min.
Typ.
Max.
Unit
Input high
voltage
VIH
RES, TEST,
3
NMI* , AEVL,
AEVH, ADTRG,
SCK3, IRQAEC
0.9VCC
—
VCC + 0.3
V
IRQ0* , IRQ1*
0.9VCC
—
AVCC + 0.3
RXD3, IrRXD
0.8VCC
—
VCC + 0.3
OSC1
0.9VCC
—
VCC + 0.3
4
4
X1
0.9VCC
—
VCC + 0.3
P10 to P12,
P30 to P32,
P82 to P84,
P90 to P93,
SSI, SSO,
SSCK, SCS,
FTCI, FTIOA,
FTIOB, FTIOC,
FTIOD,
E7_0 to E7_2,
SCL, SDA
0.8VCC
—
VCC + 0.3
PB0 to PB5
0.8VCC
—
AVCC + 0.3
Notes
Rev. 3.00 May 15, 2007 Page 393 of 516
REJ09B0152-0300
Section 21 Electrical Characteristics
Values
Item
Symbol
Applicable Pins Test Condition
Min.
Typ.
Max.
Unit
Input low
voltage
VIL
RES, TEST,
3
NMI* , IRQ0,
IRQ1, IRQAEC,
AEVL, AEVH,
ADTRG, SCK3
–0.3
—
0.1VCC
V
RXD3, IrRXD
–0.3
—
0.2VCC
OSC1
–0.3
—
0.1VCC
X1
–0.3
—
0.1VCC
P10 to P12,
P30 to P32,
P82 to P84,
P90 to P93,
SCL, SDA,
PB0 to PB5,
SSI, SSO,
SSCK, SCS,
FTCI, FTIOA,
FTIOB, FTIOC,
FTIOD,
E7_0 to E7_2,
SCL, SDA
–0.3
—
0.2VCC
Output
high
voltage
VOH
Output low VOL
voltage
P10 to P12,
P30 to P32,
P90 to P93
–IOH = 1.0 mA
VCC – 1.0 —
Vcc = 2.7 V to 3.6 V
—
–IOH = 0.1 mA
VCC – 0.3 —
—
P82 to P84
–IOH = 1.0 mA
VCC – 1.0 —
VCC = 2.7 V to 3.6 V
—
–IOH = 0.1 mA
VCC – 0.3 —
—
P10 to P12,
P30 to P32,
P90 to P93
IOL = 0.4 mA
—
—
0.5
P82 to P84
IOL = 15 mA,
—
Vcc = 2.7 V to 3.6 V
—
1.0
IOL = 10 mA,
—
Vcc = 2.2 V to 3.6 V
—
0.5
IOL = 8 mA
—
—
0.5
IOL = 3.0 mA
—
—
0.4
SCL, SDA
Rev. 3.00 May 15, 2007 Page 394 of 516
REJ09B0152-0300
V
V
Notes
Section 21 Electrical Characteristics
Values
Item
Symbol Applicable Pins Test Condition
Min.
Typ.
Max.
Unit
µA
Notes
TEST, NMI* ,
OSC1, X1, P10
to P12,
P30 to P32,
P82 to P84,
P90 to P93,
E7_0 to E7_2
VIN = 0.5 V to
VCC – 0.5 V
—
—
1.0
PB0 to PB5
VIN = 0.5 V to
AVCC – 0.5 V
—
—
1.0
Pull-up MOS –Ip
current
P10 to P12,
P30 to P32,
P82 to P84,
P90 to P93
VCC = 3 V,
VIN = 0 V
30
—
180
µA
Input
CIN
capacitance
All input pins
except power
supply pin
f = 1 MHz,
VIN =0 V,
Ta = 25°C
—
—
15.0
pF
Active mode IOPE1
supply
current
VCC
Active (highspeed) mode,
VCC = 1.8 V,
fOSC = 2 MHz
—
1.1
—
mA
Active (highspeed) mode,
VCC = 3 V,
fOSC = ROSC
—
1.2
—
Max.
guideline =
1.1 ×
1 2
typ.* *
Reference
value
Active (highspeed) mode,
VCC = 3 V,
fOSC = 4.2 MHz
—
2.6
4.0
**
4-MHz
version
Active (highspeed) mode,
VCC = 3 V,
fOSC = 10 MHz
—
6.0
10.0
**
10-MHz
version
Input/output | IIL |
leakage
current
3
Max.
guideline =
1.1 ×
1 2
typ.* *
1 2
1 2
Rev. 3.00 May 15, 2007 Page 395 of 516
REJ09B0152-0300
Section 21 Electrical Characteristics
Values
Item
Symbol Applicable Pins Test Condition
Active mode IOPE2
supply
current
Sleep mode
supply
current
ISLEEP
ISUB
Subactive
mode supply
current
VCC
VCC
VCC
Rev. 3.00 May 15, 2007 Page 396 of 516
REJ09B0152-0300
Min.
Typ.
Max.
Unit Notes
Active (mediumspeed) mode,
VCC = 1.8 V,
fOSC = 2 MHz,
φosc/64
—
0.4
—
mA
Active (mediumspeed) mode,
VCC = 3 V,
fOSC = 4.2 MHz,
φosc/64
—
0.7
1.1
**
4-MHz
version
Active (mediumspeed) mode,
VCC = 3 V,
fOSC = 10 MHz,
φosc/64
—
0.8
1.3
**
10-MHz
version
VCC = 1.8 V,
fOSC = 2 MHz
—
0.9
—
VCC = 3 V,
fOSC = 4.2 MHz
—
2.0
3.2
**
4-MHz
version
VCC = 3 V,
fOSC = 10 MHz
—
4.2
6.4
**
10-MHz
version
VCC = 2.7 V,
32-kHz crystal
resonator (φSUB =
φW/8)
—
7.0
—
VCC = 2.7 V,
32-kHz crystal
resonator (φSUB =
φW/2)
—
25
—
**
Reference
value
VCC = 2.7 V,
on-chip
oscillator/32 (φSUB
= φW = ROSC/32)
—
80
—
**
Reference
value
VCC = 2.7 V,
32-kHz crystal
resonator (φSUB =
φW)
—
45
75
**
Max.
guideline
= 1.1 ×
1 2
typ.* *
1 2
1 2
mA
Max.
guideline
= 1.1 ×
1 2
typ.* *
1 2
1 2
µA
1 2
**
Reference
value
1 2
1 2
1 2
Section 21 Electrical Characteristics
Values
Item
Symbol Applicable Pins Test Condition
ISUBSP
Subsleep
mode supply
current
Watch mode IWATCH
supply
current
Standby
ISTBY
mode supply
current
VCC
VCC
VCC
Min.
Typ.
Max.
Unit Notes
VCC = 2.7 V,
32-kHz crystal
resonator (φSUB =
φW/2)
—
3.5
—
µA
VCC = 2.7 V,
on-chip
oscillator/32 (φSUB
= φW = ROSC/32)
—
34
—
**
Reference
value
VCC = 2.7 V,
32-kHz crystal
resonator (φSUB =
φW)
—
5.1
16.0
**
VCC = 1.8 V,
Ta = 25°C,
32-kHz crystal
resonator
—
0.5
—
VCC = 2.7 V,
32-kHz crystal
resonator
—
1.5
5.0
VCC = 3.0 V,
Ta = 25°C,
32-kHz crystal
resonator not
used
—
0.1
—
32-kHz crystal
resonator not
used
—
1.0
5.0
1 2
1 2
µA
1 2
**
Reference
value
1 2
**
µA
1 2
**
Reference
value
1 2
**
RAM data
retaining
voltage
VRAM
VCC
1.5
—
—
V
Permissible
output low
current
(per pin)
IOL
Output pins
except port 8
—
—
0.5
mA
Port 8
—
—
15.0
Output pins
except port 8
—
—
20.0
Port 8
—
—
45.0
Permissible ∑ IOL
output low
current (total)
1 2
**
Reference
value
mA
Rev. 3.00 May 15, 2007 Page 397 of 516
REJ09B0152-0300
Section 21 Electrical Characteristics
Values
Item
Symbol Applicable Pins Test Condition
Min.
Typ.
Max.
Unit Notes
Permissible
output high
current
(per pin)
–IOH
—
—
2.0
mA
Other than above —
—
0.2
—
—
10.0
Permissible ∑ – IOH
output high
current (total)
All output pins
VCC = 2.7 V to 3.6 V
All output pins
mA
Notes: 1. Pin states during current measurement.
Mode
RES Pin
Internal State
Other Pins
Oscillator Pins
Active (high-speed)
mode (IOPE1)
VCC
Only CPU operates
VCC
System clock
oscillator: Crystal
resonator
Active (medium-speed)
mode (IOPE2)
Sleep mode
VCC
Only on-chip timers
operate
VCC
Subactive mode
VCC
Only CPU operates
VCC
Subsleep mode
VCC
Only on-chip timers
operate, CPU stops
VCC
Watch mode
VCC
Only timer base
VCC
operates, CPU stops
Standby mode
VCC
CPU and timers both VCC
stop, SUBSTP = 1
Subclock oscillator:
Pin X1 = GND
System clock
oscillator: Crystal
resonator
Subclock oscillator:
Crystal resonator
System clock
oscillator: Crystal
resonator
Subclock oscillator:
Pin X1 = Crystal
resonator
2. Excludes current in pull-up MOS transistors and output buffers.
3. Used for the determination of user mode or boot mode when the reset is released.
4. When bits IRQ0S1 and IRQ0S0 are set to B'01 or B'10, and bits IRQ1S1 and IRQ1S0
are set to B'01 or B'10, the maximum value is given VCC + 0.3 (V).
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Section 21 Electrical Characteristics
21.2.3
AC Characteristics
Table 21.3 lists the control signal timing, table 21.4 lists the serial interface timing, table 21.5 lists
the synchronous serial communication unit timing, and table 21.6 lists the I2C bus interface timing.
Table 21.3 Control Signal Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Item
System clock
oscillation
frequency
Values
Applicable
Symbol Pins
Test Condition
Min.
Typ.
Reference
Max. Unit Figure
fOSC
VCC = 2.7 V to 3.6 V
4.0
—
10.0
2.0
—
4.2
100
—
250
238
—
500
OSC1, OSC2
MHz
(10-MHZ version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
OSC clock (φOSC)
cycle time
tOSC
OSC1, OSC2
VCC = 2.7 V to 3.6 V
ns
(10-MHz version)
VCC = 1.8 V to 3.6 V
Figure
21.15
(4-MHz version)
System clock (φ)
cycle time
tcyc
VCC = 2.7 V to 3.6 V
1
—
64
tOSC
—
—
16
µs
—
—
32
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
On-chip oscillator
oscillation
frequency
tROSC
0.3
—
2.6
MHz Reference
value
On-chip oscillator
clock cycle time
tROSC
0.38
—
3.3
µs
Subclock oscillator
oscillation
frequency
fW
X1, X2
—
32.768
or 38.4
—
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5 or
26.0
—
µs
Figure
21.15
Subclock (φSUB)
cycle time
tsubcyc
1
—
8
tW
*
2
—
—
tcyc
tsubcyc
Instruction cycle
time
Reference
value
1
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Section 21 Electrical Characteristics
Item
Oscillation
stabilization time
Values
Applicable
Symbol Pins
Test Condition
Min.
Typ.
Reference
Max. Unit Figure
trc
Ceramic resonator
—
20
45
—
80
—
—
300
800
—
600
1000
Other than above
—
—
50
ms
On-chip
oscillator
At switching on
—
15
25
µs
X1, X2
VCC = 2.2 V to 3.6 V
—
—
2
s
Figures 4.6
and 4.7
Other than above
—
4
—
VCC = 2.7 V to 3.6 V
40
—
—
ns
Figure
21.15
95
—
—
—
15.26 or —
13.02
µs
40
—
—
ns
95
—
—
—
15.26 or —
13.02
µs
—
—
10
ns
—
—
24
—
—
55.0
OSC1, OSC2
µs
(VCC = 2.2 V to 3.6 V)
Ceramic resonator
Figure
21.28
(Other than above)
Crystal resonator
(VCC = 2.7 V to 3.6 V)
Crystal resonator
(VCC = 2.2 V to 3.6 V)
External clock high
width
tCPH
OSC1
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
X1
External clock low
width
tCPL
OSC1
VCC = 2.7 V to 3.6 V
(10-MHz version)
VCC = 1.8 V to 3.6 V
Figure
21.15
(4-MHz version)
X1
External clock rising tCPr
time
OSC1
VCC = 2.7 V to 3.6 V
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
X1
Rev. 3.00 May 15, 2007 Page 400 of 516
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ns
Figure
21.15
Section 21 Electrical Characteristics
Item
External clock
falling time
Values
Applicable
Symbol Pins
Test Condition
Min.
Typ.
Reference
Max. Unit Figure
tCPf
VCC = 2.7 V to 3.6 V
—
—
10
—
—
24
—
—
55.0
ns
trc + 20
× tcyc
—
—
µs
—
—
tcyc
2
—
—
tcyc
Figure
tsubcyc 21.17
50
—
—
ns
110
—
—
2
—
—
tcyc
Figure
tsubcyc 21.17
50
—
—
ns
110
—
—
OSC1
ns
(10-MHz version)
VCC = 1.8 V to 3.6 V
Figure
21.15
(4-MHz version)
X1
RES pin low width
tREL
RES
At switching on or
other than below
Active mode or sleep 20
Figure
2
21.16*
mode
Input pin high width tIH
IRQ0, IRQ1,
NMI, IRQAEC,
ADTRG, FTCI,
FTIOA, FTIOB,
FTIOC, FTIOD
AEVL, AEVH
VCC = 2.7 V to 3.6 V
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
Input pin low width
tIL
IRQ0, IRQ1,
NMI, IRQAEC,
ADTRG, FTCI,
FTIOA, FTIOB,
FTIOC, FTIOD
AEVL, AEVH
VCC = 2.7 V to 3.6 V
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. For details on the power-on reset characteristics, refer to table 21.10 and figure 21.26.
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Section 21 Electrical Characteristics
Table 21.4 Serial Interface Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values
Item
Input clock
cycle
Symbol
Asynchronous
tscyc
Clock
synchronous
Test Condition
Reference
Figure
Min.
Typ.
Max.
Unit
4
—
—
Figure 21.18
6
—
—
tcyc or
tsubcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Figure 21.18
Transmit data delay time
(clock synchronous)
tTXD
—
—
1
tcyc or
tsubcyc
Figure 21.19
Receive data setup time
(clock synchronous)
tRXS
400.0
—
—
ns
Figure 21.19
Receive data hold time
(clock synchronous)
tRXH
400.0
—
—
ns
Figure 21.19
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Section 21 Electrical Characteristics
Table 21.5 Synchronous Serial Communication Unit (SSU) Timing
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, output load = 100 pF, unless otherwise specified.
Values
Item
Symbol
Applicable Test
Pins
Condition
Clock cycle
tsucyc
SSCK
4


tcyc
Clock high pulse width
tHI
SSCK
0.4

0.6
tsucyc
Clock low pulse width
tLO
SSCK
0.4

0.6
tsucyc
tRISE
SSCK


1
tcyc


1.0
µs


1
tcyc
Clock rising
time
Master
Clock falling
time
Master
Slave
Min.
Typ.
Max.
Unit
tFALL
SSCK


1.0
µs
Data input setup time
tSU
SSO
SSI
1


tcyc
Data input hold time
tH
SSO
SSI
1


tcyc
SCS setup
time
Slave
tLEAD
SCS
1tcyc + 
100

ns
SCS hold
time
Slave
tLAG
SCS
1tcyc + 
100

ns
Data output delay time
tOD
SSO
SSI


1
tcyc
Slave access time
tSA
SSI


1tcyc + ns
100
Slave out release time
tOR
SSI


1tcyc +
100
Slave
Reference
Figure
Figures
21.20 to
21.24
ns
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Section 21 Electrical Characteristics
Table 21.6 I2C Bus Interface Timing
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified.
Test
Condition
Values
Item
Symbol
SCL input cycle time
tSCL
SCL input high width
tSCLH
SCL input low width
tSCLL
5tcyc + 300
—
—
ns
Falling time for SCL
and SDA inputs
tSf
—
—
300
ns
Pulse width of spike
on SCL and SDA to
be suppressed
tSP
—
—
1tcyc
ns
SDA input bus-free
time
tBUF
5tcyc
—
—
ns
Start condition input
hold time
tSTAH
3tcyc
—
—
ns
Repeated start
condition input setup
time
tSTAS
3tcyc
—
—
ns
Stop condition input
setup time
tSTOS
3tcyc
—
—
ns
Data-input setup time tSDAS
1tcyc + 20
—
—
ns
Data-input hold time
tSDAH
0
—
—
ns
Capacitive load of
SCL and SDA
Cb
0
—
400
pF
Falling time of SCL
and SDA output
tSf
—
—
300
ns
Rev. 3.00 May 15, 2007 Page 404 of 516
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Min.
Typ.
Reference
Max.
Unit
Figure
12tcyc + 600 —
—
ns
3tcyc + 300
—
ns
Figure
21.25
—
Section 21 Electrical Characteristics
21.2.4
A/D Converter Characteristics
Table 21.7 lists the A/D converter characteristics.
Table 21.7 A/D Converter Characteristics
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Item
Applicable
Symbol Pins
Values
Test Condition
Min.
Typ.
Max.
Unit
Notes
*
1
Analog power AVCC
supply voltage
AVCC
1.8
—
3.6
V
Analog input
voltage
AN0 to AN5
–0.3
—
AVCC +
0.3
V
—
—
1.0
mA
—
600
—
µA
AVIN
Analog power AIOPE
supply current
AISTOP1
AVCC
AVCC = 3.0 V
AVCC
2
*
Reference value
3
AISTOP2
AVCC
—
—
5
µA
Analog input
capacitance
CAIN
AN0 to AN5
—
—
15.0
pF
Permissible
signal source
impedance
RAIN
—
—
10.0
kΩ
—
—
10
Bits
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
—
—
±3.5
LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
—
±5.5
Subclock operating
—
—
±5.5
Subactive or
subsleep mode,
conversion time
= 31/φW
Other than above
—
—
±7.5
*
—
—
±0.5
Resolution
(data length)
Nonlinearity
error
Quantization
error
*
Other than
subclock
operation
4
LSB
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Section 21 Electrical Characteristics
Applicable
Symbol Pins
Item
Absolute
accuracy
Conversion
time
Values
Test Condition
Min.
Typ.
Max.
Unit
Notes
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
—
—
±4.0
LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
—
±6.0
Subclock operating
—
—
±6.0
Subactive or
subsleep mode,
conversion time =
31/φW
Other than above
—
—
±8.0
*
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
12.4
—
124
31
62
124
On-chip oscillator
is selected
Reference value
(fROSC = 1 MHz)
—
807
—
φSUB = 38.4 kHz
—
945
—
φSUB = 32.8 kHz
—
992
—
φSUB = ROSC/32
4
µs
System clock
oscillator is
selected
Reference value
(fROSC = 1 MHz)
Other than
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
29.5
—
124
System clock
oscillator is
selected
31
62
124
On-chip oscillator
is selected
Reference value
(fROSC = 1 MHz)
—
807
—
φSUB = 38.4 kHz
—
945
—
φSUB = 32.8 kHz
—
992
—
φSUB = ROSC/32
Reference value
(fROSC = 1 MHz)
Notes: 1. Connect AVCC to VCC when the A/D converter is not used.
2. AISTOP1 is the current flowing through the ladder resistor while the A/D converter is idle.
3. AISTOP2 is the current flowing at a reset, in standby mode or watch mode, through the
ladder resistor while the A/D converter is idle.
4. Conversion time is 29.5 µs.
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Section 21 Electrical Characteristics
21.2.5
Comparator Characteristics
Table 21.8 shows the comparator characteristics.
Table 21.8 Comparator Characteristics
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values
Item
Test Condition
Min.
Typ.
Max.
Unit
Notes
Accuracy
1LSB = VCC/30
—
1/2
—
LSB
Comparing
with internal
resistor
network
—
—
15
µs
0.9
—
0.9 × VCC
V
0.9
—
26/30 × VCC V
–0.3
—
AVCC + 0.3
V
—
3
—
MΩ
Conversion time
External input reference
voltage
VCref pin
Internal resistance compare
voltage
Comparator input voltage
COMP0 and COMP1
pins
Ladder resistance
21.2.6
Reference
value
Watchdog Timer Characteristics
Table 21.9 shows the watchdog timer characteristics.
Table 21.9 Watchdog Timer Characteristics
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable
Symbol Pins
Item
On-chip
oscillator
overflow time
Note:
*
tOVF
Values
Test Condition
Min.
Typ.
Max.
Unit
Notes
0.2
0.4
—
s
*
Indicates that the period from when the counter starts with 0 to when the counter
reaches 255 and an internal reset occurs while the on-chip oscillator is selected.
Rev. 3.00 May 15, 2007 Page 407 of 516
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Section 21 Electrical Characteristics
21.2.7
Power-On Reset Circuit Characteristics
Table 21.10 lists the power-on reset circuit characteristics.
Table 21.10 Power-On Reset Circuit Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V,
Ta = −20 to +75°C (general specifications), Ta = −40 to +85°C (wide temperature range
specifications), unless otherwise specified.
Values
Symbol Test Condition
Min.
Reset voltage
V_rst
0.7Vcc 0.8Vcc 0.9Vcc V
Power supply
rising time
t_vtr
The Vcc rising time should be
shorter than half the RES rising
time.
Reset count time
t_out
Count start time
t_cr
Pull-up resistance RP
Rev. 3.00 May 15, 2007 Page 408 of 516
REJ09B0152-0300
Typ.
Max.
Unit
Item
0.8
—
4.0
3.2
—
26.7
µs
On-chip oscillator
is selected
(reference value)
Adjustable by the value of the
external capacitor connected to
the RES pin.
60
100
—
Notes
kΩ
Section 21 Electrical Characteristics
21.2.8
Flash Memory Characteristics
Table 21.11 lists the flash memory characteristics.
Table 21.11 Flash Memory Characteristics
AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, VCC = 1.8 V to 3.6 V (operating voltage range in reading),
VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing),
Ta = 0 to +75°C (operating temperature range in programming/erasing)
Values
Test
Item
Symbol Condition
Min.
Typ.
Max.
tP
—
7
200
ms
Erasing time (per block)* * *
tE
—
100
1200
ms
Maximum programming count
NWEC
1000
8 11
**
10000 —
9
*
100
8 12
**
10000 —
9
*
1 2 4
Programming time (per 128 bytes)* * *
1 3 6
Data retention time
Programming
10
Unit
Times
tDRP
10*
—
—
Wait time after setting SWE bit*
x
1
—
—
µs
1
y
50
—
—
µs
1
Wait time after setting PSU bit*
1 4
Wait time after setting P bit* *
1
Wait time after clearing P bit*
Years
z1
1≤n≤6
28
30
32
µs
z2
7 ≤ n ≤ 1000
198
200
202
µs
z3
Additional8
programming
10
12
µs
α
5
—
—
µs
µs
β
5
—
—
Wait time after setting PV bit*
γ
4
—
—
µs
1
ε
2
—
—
µs
1
Wait time after clearing PSU bit*
1
Wait time after dummy write*
η
2
—
—
µs
1
θ
100
—
—
µs
1 4 5
N
—
—
1000
Times
1
Wait time after clearing PV bit*
Wait time after clearing SWE bit*
Maximum programming count* * *
Rev. 3.00 May 15, 2007 Page 409 of 516
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Section 21 Electrical Characteristics
Min.
Typ.
Max.
Wait time after setting SWE bit*
x
1
—
—
µs
1
y
100
—
—
µs
Item
1
Erase
Values
Test
Symbol Condition
Wait time after setting ESU bit*
1 6
Unit
Wait time after setting E bit* *
z
10
—
100
ms
1
α
10
—
—
µs
µs
Wait time after clearing E bit*
β
10
—
—
Wait time after setting EV bit*
γ
20
—
—
µs
1
ε
2
—
—
µs
1
Wait time after clearing ESU bit*
1
Wait time after dummy write*
1
Wait time after clearing EV bit*
1
Wait time after clearing SWE bit*
1 6 7
Maximum erasing count* * *
Notes: 1.
2.
η
4
—
—
µs
θ
100
—
—
µs
N
—
—
120
Times
Make the time settings in accordance with the programming/erasing algorithms.
The programming time for 128 bytes. (Indicates the total time for which the P bit in the
flash memory control register 1 (FLMCR1) is set. The programming-verifying time is
not included.)
3. The time required to erase one block. (Indicates the total time for which the E bit in the
flash memory control register 1 (FLMCR1) is set. The erasing-verifying time is not
included.)
4. Programming time maximum value (tP (max.)) = wait time after setting P bit (z) ×
maximum programming count (N)
5. Set the maximum programming count (N) according to the actual set values of z1, z2,
and z3, so that it does not exceed the programming time maximum value (tP (max.)).
The wait time after setting P bit (z1, z2) should be changed as follows according to the
value of the programming count (n).
Programming count (n)
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erasing time maximum value (tE (max.)) = wait time after setting E bit (z) × maximum
erasing count (N)
7. Set the maximum erasing count (N) according to the actual set value of (z), so that it
does not exceed the erasing time maximum value (tE (max.)).
8. The minimum number of times in which all characteristics are guaranteed following
reprogramming. (The guarantee covers the range from 1 to the minimum value.)
9. Reference value at 25°C. (Guideline showing programming count over which
functioning will be retained under normal circumstances.)
10. Data retention characteristics within the range indicated in the specifications, including
the minimum programming count.
11. Applies to an operating voltage range when reading data of 2.7 to 3.6 V.
12. Applies to an operating voltage range when reading data of 1.8 to 3.6 V.
Rev. 3.00 May 15, 2007 Page 410 of 516
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Section 21 Electrical Characteristics
21.3
Absolute Maximum Ratings for Masked ROM Version
Table 21.12 lists the absolute maximum ratings.
Table 21.12 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +4.3
V
*
Analog power supply voltage
AVCC
–0.3 to +4.3
V
Input voltage
Other than port B
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
Topr
–20 to +75
(general
specifications)
°C
Operating temperature
–40 to +85
(wide temperature
range specifications)
Storage temperature
Note:
*
Tstg
–55 to +125
°C
Permanent damage may occur to the chip if absolute maximum ratings are exceeded.
Normal operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
Rev. 3.00 May 15, 2007 Page 411 of 516
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Section 21 Electrical Characteristics
21.4
Electrical Characteristics for Masked ROM Version
21.4.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) System clock oscillator selected (10-MHz version)
fW (kHz)
fosc (MHz)
10.0
38.4
32.768
4.0
1.8
1.8
2.7 3.6 Vcc (V)
• All operating modes
• Refer to note
2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
fW (kHz)
Rosc/32 used (reference value)
81.25
9.375
2.7 3.6 Vcc (V)
1.8
• All operating modes
fW (kHz)
fosc (MHz)
(2) System clock oscillator selected (4-MHz version)
4.2
38.4
32.768
2.0
1.8
2.7 3.6 Vcc (V)
1.8
• All operating modes
• Refer to note
2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
fW (kHz)
Rosc/32 used (reference value)
81.25
9.375
2.7 3.6 Vcc (V)
1.8
• All operating modes
Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation
stabilization time has elapsed after switching on.
Figure 21.8 Power Supply Voltage and Oscillation Frequency Range (1)
Rev. 3.00 May 15, 2007 Page 412 of 516
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Section 21 Electrical Characteristics
(3) On-chip oscillator selected
fW (kHz)
fosc (MHz)
Rosc used (reference value)
2.6
38.4
32.768
0.3
1.8
2.7
1.8
2.7 3.6 Vcc (V)
• All operating modes
• Refer to note
3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
fW (kHz)
Rosc/32 used (reference value)
81.25
9.375
1.8
2.7 3.6 Vcc (V)
• All operating modes
Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation
stabilization time has elapsed after switching on.
Figure 21.9 Power Supply Voltage and Oscillation Frequency Range (2)
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Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version)
10.0
38.4
32.768
φ (MHz)
φSUB (kHz)
19.2
16.384
9.6
8.192
4.0
4.8
4.096
1.8
2.7 3.6 Vcc (V)
1.8
• Active (high-speed) mode
• Sleep (high-speed) mode
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
1250
φ (kHz)
62.5
φSUB (kHz)
Rosc/32 used (reference value)
1.8
2.7 3.6 Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
81.25
1.172
1.8
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
Figure 21.10 Power Supply Voltage and Operating Frequency Range (1)
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Section 21 Electrical Characteristics
(2) System clock oscillator selected (4-MHz version)
38.4
φ SUB (kHz)
32.768
19.2
16.384
9.6
φ (MHz)
8.192
4.2
4.8
4.096
2.0
1.8 2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
1.8 2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
φ (kHz)
525
Rosc/32 used (reference value)
φ SUB (kHz)
31.25
1.8
2.7 3.6 Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
81.25
1.172
1.8
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
Figure 21.11 Power Supply Voltage and Operating Frequency Range (2)
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Section 21 Electrical Characteristics
(3) On-chip oscillator selected
38.4
32.768
φ (MHz)
Rosc used (reference value)
φ SUB (kHz)
19.2
16.384
9.6
8.192
4.8
2.6
4.096
0.3
1.8 2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
1.8 2.7 3.6 Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Rosc used (reference value)
Rosc/32 used (reference value)
φ SUB (kHz)
φ (kHz)
325
4.6875
1.8
2.7 3.6 Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
81.25
1.172
1.8
2.7 3.6 Vcc (V)
• Subactive mode
• Subsleep mode (other than CPU)
• Watch mode (other than CPU)
Figure 21.12 Power Supply Voltage and Operating Frequency Range (3)
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Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version)
38.4
φ SUB (kHz)
φ (MHz)
10.0
4.0
1.8
2.7
32.768
1.8
2.7
• All operating modes
3.6 AVcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
3.6 AVcc (V)
Rosc/32 used (reference value)
φ SUB (kHz)
81.25
9.375
1.8
2.7
• All operating modes
3.6 AVcc (V)
(2) System clock oscillator selected (4-MHz version)
φ SUB (kHz)
φ (MHz)
38.4
4.2
2.0
1.8
2.7
32.768
1.8
2.7
• All operating modes
3.6 AVcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
3.6 AVcc (V)
Rosc/32 used (reference value)
φ SUB (kHz)
81.25
9.375
1.8
2.7
• All operating modes
3.6 AVcc (V)
Figure 21.13 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (1)
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Section 21 Electrical Characteristics
(3) On-chip oscillator selected
φSUB (kHz)
φ (MHz)
Rosc used (reference value)
2.6
38.4
32.768
0.3
1.8
2.7
1.8
3.6 AVcc (V)
2.7
3.6 AVcc (V)
• All operating modes
• Active (high-speed) mode
• Sleep (high-speed) mode
φSUB (kHz)
Rosc/32 used (reference value)
81.25
9.375
1.8
2.7
• All operating modes
3.6 AVcc (V)
Figure 21.14 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (2)
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Section 21 Electrical Characteristics
21.4.2
DC Characteristics
Table 21.13 lists the DC characteristics.
Table 21.13 DC Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values
Item
Symbol
Applicable Pins Test Condition
Min.
Typ.
Max.
Unit
Input high
voltage
VIH
RES, TEST,
NMI, AEVL,
AEVH, ADTRG,
SCK3, IRQAEC
0.9VCC
—
VCC + 0.3
V
IRQ0* , IRQ1*
0.9VCC
—
AVCC + 0.3
RXD3, IrRXD
0.8VCC
—
VCC + 0.3
OSC1
0.9VCC
—
VCC + 0.3
3
3
X1
0.9VCC
—
VCC + 0.3
P10 to P12,
P30 to P32,
P82 to P84,
P90 to P93,
SSI, SSO,
SSCK, SCS,
FTCI, FTIOA,
FTIOB, FTIOC,
FTIOD,
E7_0 to E7_2,
SCL, SDA
0.8VCC
—
VCC + 0.3
PB0 to PB5
0.8VCC
—
AVCC + 0.3
Notes
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Section 21 Electrical Characteristics
Values
Item
Symbol
Applicable Pins Test Condition
Min.
Typ.
Max.
Unit
Input low
voltage
VIL
TEST, NMI,
IRQ0, IRQ1,
IRQAEC, AEVL,
AEVH, ADTRG,
SCK3
–0.3
—
0.1VCC
V
RXD3, IrRXD
–0.3
—
0.2VCC
OSC1
–0.3
—
0.1VCC
X1
–0.3
—
0.1VCC
P10 to P12,
P30 to P32,
P82 to P84,
P90 to P93,
SCL, SDA,
PB0 to PB5,
SSI, SSO,
SSCK, SCS,
FTCI, FTIOA,
FTIOB, FTIOC,
FTIOD,
E7_0 to E7_2
–0.3
—
0.2VCC
Output
high
voltage
VOH
Output low VOL
voltage
P10 to P12,
P30 to P32,
P90 to P93
–IOH = 1.0 mA
VCC – 1.0 —
Vcc = 2.7 V to 3.6 V
—
–IOH = 0.1 mA
VCC – 0.3 —
—
P82 to P84
–IOH = 1.0 mA
VCC – 1.0 —
VCC = 2.7 V to 3.6 V
—
–IOH = 0.1 mA
VCC – 0.3 —
—
P10 to P12,
P30 to P32,
P90 to P93
IOL = 0.4 mA
—
—
0.5
P82 to P84
IOL = 15 mA,
—
Vcc = 2.7 V to 3.6 V
—
1.0
IOL = 10 mA,
—
Vcc = 2.2 V to 3.6 V
—
0.5
IOL = 8 mA
—
—
0.5
IOL = 3.0 mA
—
—
0.4
SCL, SDA
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V
V
Notes
Section 21 Electrical Characteristics
Values
Item
Symbol Applicable Pins Test Condition
Input/output
leakage
current
| IIL |
Min.
Typ.
Max.
Unit
µA
TEST, NMI,
OSC1, X1, P10
to P12,
P30 to P32,
P82 to P84,
P90 to P93,
E7_0 to E7_2
VIN = 0.5 V to
VCC – 0.5 V
—
—
1.0
PB0 to PB5
VIN = 0.5 V to
AVCC – 0.5 V
—
—
1.0
Pull-up MOS
current
–Ip
P10 to P12,
P30 to P32,
P82 to P84,
P90 to P93
VCC = 3 V,
VIN = 0 V
30
—
180
µA
Input
capacitance
CIN
All input pins
except power
supply pin
f = 1 MHz,
VIN =0 V,
Ta = 25°C
—
—
15.0
pF
VCC
Active (highspeed) mode,
VCC = 1.8 V,
fOSC = 2 MHz
—
0.5
—
mA
Active (highspeed) mode,
VCC = 3 V,
fOSC = ROSC
—
Active (highspeed) mode,
VCC = 3 V,
fOSC = 4.2 MHz
—
Active (highspeed) mode,
VCC = 3 V,
fOSC = 10 MHz
—
Active mode IOPE1
supply current
Notes
Max. guideline
1 2
= 1.1 × typ.* *
0.6
—
Max. guideline
1 2
= 1.1 × typ.* *
Reference value
2.0
3.0
1 2
**
4-MHz version
4.5
6.8
1 2
**
10-MHz version
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Section 21 Electrical Characteristics
Applicable
Item
Symbol
Active mode IOPE2
supply current
Values
Pins
Test Condition
Min.
Typ.
Max.
Unit Notes
VCC
Active (medium-speed)
—
0.1
—
mA
Max. guideline
1 2
= 1.1 × typ. * *
mode,
VCC = 1.8 V,
fOSC = 2 MHz,
φosc/64
Active (medium-speed)
—
0.3
1 2
0.5
**
mode,
4-MHz version
VCC = 3 V,
fOSC = 4.2 MHz,
φosc/64
Active (medium-speed)
—
0.5
1 2
0.7
**
mode,
10-MHz version
VCC = 3 V,
fOSC = 10 MHz,
φosc/64
Sleep mode
ISLEEP
supply current
VCC
VCC = 1.8 V,
—
0.3
—
mA
VCC = 3 V,
1 2
—
1.0
1 2
1.5
**
fOSC = 4.2 MHz
VCC = 3 V,
4-MHz version
—
1.8
1 2
2.7
**
fOSC = 10 MHz
Subactive
mode supply
current
ISUB
VCC
VCC = 1.8 V,
Max. guideline
= 1.1 × typ. * *
fOSC = 2 MHz
10-MHz version
—
4.0
—
32-kHz crystal resonator
µA
1 2
**
Reference value
(φSUB = φW/2)
VCC = 2.7 V,
—
3.6
—
32-kHz crystal resonator
1 2
**
Reference value
(φSUB = φW/8)
VCC = 2.7 V,
—
7.4
—
32-kHz crystal resonator
1 2
**
Reference value
(φSUB = φW/2)
VCC = 2.7 V,
—
40
—
on-chip oscillator/32
1 2
**
Reference value
(φSUB = φW = ROSC/32)
VCC = 2.7 V,
32-kHz crystal resonator
(φSUB = φW)
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—
13
25
1 2
**
Section 21 Electrical Characteristics
Applicable
Item
Symbol Pins
Subsleep mode ISUBSP
supply current
Watch mode
supply current
Standby mode
supply current
IWATCH
ISTBY
VCC
VCC
VCC
Values
Test Condition
Min.
Typ.
Max.
Unit Notes
—
VCC = 2.7 V,
32-kHz crystal
resonator (φSUB = φW/2)
3.1
—
µA
VCC = 2.7 V,
on-chip oscillator/32
(φSUB = φW = ROSC/32)
—
30
VCC = 2.7 V,
32-kHz crystal
resonator (φSUB = φW)
—
5.0
10.0
VCC = 1.8 V,
Ta = 25°C,
32-kHz crystal
resonator
—
0.4
—
VCC = 2.7 V,
32-kHz crystal
resonator
—
1.5
5.0
VCC = 3.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
0.1
—
32-kHz crystal
resonator not used
—
1.0
5.0
1 2
**
Reference
value
1 2
—
**
Reference
value
1 2
**
µA
1 2
**
Reference
value
1 2
**
µA
1 2
**
Reference
value
1 2
**
RAM data
retaining
voltage
VRAM
VCC
1.5
—
—
V
Permissible
output low
current
(per pin)
IOL
Output pins
except port 8
—
—
0.5
mA
Port 8
—
—
15.0
Permissible
output low
current (total)
∑ IOL
Output pins
except port 8
—
—
20.0
Port 8
—
—
45.0
mA
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Section 21 Electrical Characteristics
Applicable
Values
Item
Symbol Pins
Test Condition
Min.
Typ.
Max.
Unit Notes
Permissible
output high
current
(per pin)
–IOH
VCC = 2.7 V to 3.6 V
—
—
2.0
mA
Other than above —
—
0.2
—
—
10.0
Permissible
∑ – IOH
output high
current (total)
All output pins
All output pins
mA
Notes: 1. Pin states during current measurement.
Mode
RES Pin
Internal State
Other Pins
Oscillator Pins
Active (high-speed)
mode (IOPE1)
VCC
Only CPU operates
VCC
System clock
oscillator: Crystal
resonator
Active (medium-speed)
mode (IOPE2)
Sleep mode
VCC
Only on-chip timers
operate
VCC
Subactive mode
VCC
Only CPU operates
VCC
Subsleep mode
VCC
Only on-chip timers
operate, CPU stops
VCC
Watch mode
VCC
Only timer base
VCC
operates, CPU stops
Standby mode
VCC
CPU and timers both VCC
stop, SUBSTP = 1
Subclock oscillator:
Pin X1 = GND
System clock
oscillator: Crystal
resonator
Subclock oscillator:
Crystal resonator
System clock
oscillator: Crystal
resonator
Subclock oscillator:
Pin X1 = Crystal
resonator
2. Excludes current in pull-up MOS transistors and output buffers.
3. When bits IRQ0S1 and IRQ0S0 are set to B'01 or B'10, and bits IRQ1S1 and IRQ1S0
are set to B'01 or B'10, the maximum value is given VCC + 0.3 (V).
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Section 21 Electrical Characteristics
21.4.3
AC Characteristics
Table 21.14 lists the control signal timing, table 21.15 lists the serial interface timing, table 21.16
lists the synchronous serial communication unit timing, and table 21.17 lists the I2C bus interface
timing.
Table 21.14 Control Signal Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable
Values
Reference
Item
Symbol Pins
Test Condition
Min.
Typ.
Max.
Unit Figure
System clock
oscillation
frequency
fOSC
VCC = 2.7 V to 3.6 V
4.0
—
10.0
MHz
2.0
—
4.2
100
—
250
238
—
500
1
—
64
tOSC
—
—
16
µs
—
—
32
OSC1, OSC2
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
OSC clock (φOSC)
cycle time
tOSC
OSC1, OSC2
VCC = 2.7 V to 3.6 V
ns
(10-MHz version)
VCC = 1.8 V to 3.6 V
Figure
21.15
(4-MHz version)
System clock (φ)
cycle time
tcyc
VCC = 2.7 V to 3.6 V
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
On-chip oscillator
oscillation
frequency
tROSC
0.3
—
2.6
MHz Reference
value
On-chip oscillator
clock cycle time
tROSC
0.38
—
3.3
µs
Subclock oscillator fW
oscillation
frequency
X1, X2
—
32.768
or 38.4
—
kHz
Watch clock (φW)
cycle time
X1, X2
—
30.5 or
26.0
—
µs
tW
Reference
value
Figure
21.15
Rev. 3.00 May 15, 2007 Page 425 of 516
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Section 21 Electrical Characteristics
Item
Subclock (φSUB)
cycle time
Applicable
Symbol Pins
Values
Test Condition
Min.
Typ.
Max.
Unit
1
—
8
tW
2
—
—
tcyc
tsubcyc
—
20
45
µs
—
80
—
—
300
800
—
600
1000
Other than above
—
—
50
ms
On-chip
oscillator
At switching on
—
15
25
µs
X1, X2
VCC = 2.2 V to 3.6 V
—
—
2
s
Figures
4.6 and
4.7
Other than above
—
4
—
VCC = 2.7 V to 3.6 V
40
—
—
ns
Figure
21.15
95
—
—
—
15.26 or —
13.02
µs
40
—
—
ns
95
—
—
—
15.26 or —
13.02
tsubcyc
Instruction cycle
time
Oscillation
stabilization time
trc
Reference
Figure
OSC1, OSC2
Ceramic resonator
(VCC = 2.2 V to 3.6 V)
Ceramic resonator
1
*
Figure
21.28
(Other than above)
Crystal resonator
(VCC = 2.7 V to 3.6 V)
Crystal resonator
(VCC = 2.2 V to 3.6 V)
External clock high tCPH
width
OSC1
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
X1
External clock low
width
tCPL
OSC1
VCC = 2.7 V to 3.6 V
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
X1
Rev. 3.00 May 15, 2007 Page 426 of 516
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µs
Figure
21.15
Section 21 Electrical Characteristics
Item
External clock
rising time
Values
Applicable
Symbol Pins
Test Condition
Min.
Typ.
Max.
Unit
tCPr
VCC = 2.7 V to 3.6 V
—
—
10
ns
—
—
24
OSC1
(10-MHz version)
VCC = 1.8 V to 3.6 V
Reference
Figure
Figure
21.15
(4-MHz version)
X1
External clock
falling time
tCPf
OSC1
VCC = 2.7 V to 3.6 V
—
—
55.0
ns
—
—
10
ns
—
—
24
—
—
55.0
ns
trc + 20
× tcyc
—
—
µs
(10-MHz version)
VCC = 1.8 V to 3.6 V
Figure
21.15
(4-MHz version)
X1
RES pin low width
tREL
RES
At switching on or
other than below
Active mode or sleep 20
Figure
2
21.16*
tcyc
mode
Input pin high width tIH
IRQ0, IRQ1,
NMI, IRQAEC,
ADTRG, FTCI,
FTIOA, FTIOB,
FTIOC, FTIOD
AEVL, AEVH
VCC = 2.7 V to 3.6 V
2
—
—
tcyc
Figure
tsubcyc 21.17
50
—
—
ns
110
—
—
2
—
—
tcyc
Figure
tsubcyc 21.17
50
—
—
ns
110
—
—
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
Input pin low width
tIL
IRQ0, IRQ1,
NMI, IRQAEC,
ADTRG, FTCI,
FTIOA, FTIOB,
FTIOC, FTIOD
AEVL, AEVH
VCC = 2.7 V to 3.6 V
(10-MHz version)
VCC = 1.8 V to 3.6 V
(4-MHz version)
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. For details on the power-on reset characteristics, refer to table 21.21 and figure 21.26.
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Section 21 Electrical Characteristics
Table 21.15 Serial Interface Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values
Item
Input clock
cycle
Symbol
Asynchronous
Test Condition
tscyc
Clock
synchronous
Reference
Min.
Typ.
Max.
Unit
Figure
4
—
—
Figure 21.18
6
—
—
tcyc or
tsubcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Figure 21.18
Transmit data delay time
(clock synchronous)
tTXD
—
—
1
tcyc or
tsubcyc
Figure 21.19
Receive data setup time
(clock synchronous)
tRXS
400.0
—
—
ns
Figure 21.19
Receive data hold time
(clock synchronous)
tRXH
400.0
—
—
ns
Figure 21.19
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Section 21 Electrical Characteristics
Table 21.16 Synchronous Serial Communication Unit (SSU) Timing
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, output load = 100 pF, unless otherwise specified.
Values
Item
Symbol
Applicable Test
Pins
Condition
Clock cycle
tsucyc
SSCK
4


tcyc
Clock high pulse width
tHI
SSCK
0.4

0.6
tsucyc
Clock low pulse width
tLO
SSCK
0.4

0.6
tsucyc
tRISE
SSCK


1
tcyc


1.0
µs

1
tcyc
Clock rising
time
Master
Clock falling
time
Master
Slave
Min.
Typ.
Max.
Unit
tFALL
SSCK



1.0
µs
Data input setup time
tSU
SSO
SSI
1


tcyc
Data input hold time
tH
SSO
SSI
1


tcyc
SCS setup
time
Slave
tLEAD
SCS
1tcyc + 
100

ns
SCS hold
time
Slave
tLAG
SCS
1tcyc + 
100

ns
Data output delay time
tOD
SSO
SSI


1
tcyc
Slave access time
tSA
SSI


1tcyc + ns
100
Slave out release time
tOR
SSI


1tcyc +
100
Slave
Reference
Figure
Figures
21.20 to
21.24
ns
Rev. 3.00 May 15, 2007 Page 429 of 516
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Section 21 Electrical Characteristics
Table 21.17 I2C Bus Interface Timing
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified.
Test
Condition
Values
Item
Symbol
SCL input cycle time
tSCL
SCL input high width
tSCLH
SCL input low width
tSCLL
5tcyc + 300
—
—
ns
Falling time for SCL
and SDA inputs
tSf
—
—
300
ns
Pulse width of spike
on SCL and SDA to
be suppressed
tSP
—
—
1tcyc
ns
SDA input bus-free
time
tBUF
5tcyc
—
—
ns
Start condition input
hold time
tSTAH
3tcyc
—
—
ns
Repeated start
condition input setup
time
tSTAS
3tcyc
—
—
ns
Stop condition input
setup time
tSTOS
3tcyc
—
—
ns
Data-input setup time tSDAS
1tcyc + 20
—
—
ns
Data-input hold time
tSDAH
0
—
—
ns
Capacitive load of
SCL and SDA
Cb
0
—
400
pF
Falling time of SCL
and SDA output
tSf
—
—
300
ns
Rev. 3.00 May 15, 2007 Page 430 of 516
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Min.
Typ.
Reference
Max.
Unit
Figure
12tcyc + 600 —
—
ns
3tcyc + 300
—
ns
Figure
21.25
—
Section 21 Electrical Characteristics
21.4.4
A/D Converter Characteristics
Table 21.18 lists the A/D converter characteristics.
Table 21.18 A/D Converter Characteristics
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Item
Applicable
Symbol Pins
Values
Test Condition
Min.
Typ.
Max. Unit
Notes
*
Analog power AVCC
supply voltage
AVCC
1.8
—
3.6
Analog input
voltage
AN0 to AN5
–0.3
—
AVCC V
+ 0.3
—
—
1.0
mA
AVIN
AVCC = 3.0 V
V
1
Analog power AIOPE
supply current
AISTOP1
AVCC
AVCC
—
600
—
µA
*
Reference
value
AISTOP2
AVCC
—
—
5
µA
*
Analog input
capacitance
CAIN
AN0 to AN5
—
—
15.0
pF
Permissible
signal source
impedance
RAIN
—
—
10.0
kΩ
—
—
10
Bits
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
—
—
±3.5
LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
—
±5.5
Subclock operating
—
—
±5.5
Resolution
(data length)
Nonlinearity
error
2
3
Other than
subclock
operation
Subactive or
subsleep mode,
conversion time =
31/φW
Other than above
Quantization
error
—
—
±7.5
—
—
±0.5
4
*
LSB
Rev. 3.00 May 15, 2007 Page 431 of 516
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Section 21 Electrical Characteristics
Values
Applicable
Item
Symbol Pins
Absolute
accuracy
Conversion
time
Test Condition
Min.
Typ.
Max. Unit
Notes
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
—
—
±4.0
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
—
±6.0
Subclock operating
—
—
±6.0
Subactive or
subsleep mode,
conversion time =
31/φW
Other than above
—
—
±8.0
*
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
12.4
—
124
LSB
4
µs
System clock
oscillator is
selected
31
62
124
On-chip oscillator
is selected
Reference value
(fROSC = 1 MHz)
—
807
—
φSUB = 38.4 kHz
—
945
—
φSUB = 32.8 kHz
—
992
—
φSUB = ROSC/32
Reference value
(fROSC = 1 MHz)
Other than
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
29.5
—
124
System clock
oscillator is
selected
31
62
124
On-chip oscillator
is selected
Reference value
(fROSC = 1 MHz)
—
807
—
φSUB = 38.4 kHz
—
945
—
φSUB = 32.8 kHz
—
992
—
φSUB = ROSC/32
Reference value
(fROSC = 1 MHz)
Notes: 1. Connect AVCC to VCC when the A/D converter is not used.
2. AISTOP1 is the current flowing through the ladder resistor while the A/D converter is idle.
3. AISTOP2 is the current flowing at a reset, in standby mode or watch mode, through the
ladder resistor while the A/D converter is idle.
4. Conversion time is 29.5 µs.
Rev. 3.00 May 15, 2007 Page 432 of 516
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Section 21 Electrical Characteristics
21.4.5
Comparator Characteristics
Table 21.19 shows the comparator characteristics.
Table 21.19 Comparator Characteristics
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values
Item
Test Condition
Min.
Typ.
Max.
Unit
Notes
Accuracy
1LSB = VCC/30
—
1/2
—
LSB
Comparing
with internal
resistor
network
—
—
15
µs
0.9
—
0.9 × VCC
V
0.9
—
26/30 × VCC V
—
AVCC + 0.3
V
3
—
MΩ
Conversion time
External input reference
voltage
VCref pin
Internal resistance
compare voltage
Comparator input voltage
COMP0 and COMP1 –0.3
pins
Ladder resistance
21.4.6
—
Reference
value
Watchdog Timer Characteristics
Table 21.20 shows the watchdog timer characteristics.
Table 21.20 Watchdog Timer Characteristics
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values
Applicable
Item
Symbol Pins
On-chip
oscillator
overflow time
tOVF
Note:
*
Test Condition
Min.
Typ.
Max.
Unit
Notes
0.2
0.4
—
s
*
Indicates that the period from when the counter starts with 0 to when the counter
reaches 255 and an internal reset occurs while the on-chip oscillator is selected.
Rev. 3.00 May 15, 2007 Page 433 of 516
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Section 21 Electrical Characteristics
21.4.7
Power-On Reset Circuit Characteristics
Table 21.21 lists the power-on reset circuit characteristics.
Table 21.21 Power-On Reset Circuit Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V,
Ta = −20 to +75°C (general specifications), Ta = −40 to +85°C (wide temperature range
specifications), unless otherwise specified.
Values
Symbol Test Condition
Min.
Reset voltage
V_rst
0.7Vcc 0.8Vcc 0.9Vcc V
Power supply
rising time
t_vtr
The Vcc rising time should be
shorter than half the RES rising
time.
Reset count time
t_out
Count start time
t_cr
Pull-up resistance RP
Rev. 3.00 May 15, 2007 Page 434 of 516
REJ09B0152-0300
Typ.
Max.
Unit
Item
0.8
—
4.0
3.2
—
26.7
µs
On-chip oscillator
is selected
(reference value)
Adjustable by the value of the
external capacitor connected to
the RES pin.
60
100
—
Notes
kΩ
Section 21 Electrical Characteristics
21.5
Operation Timing
Figures 21.15 to 21.26 show operation timings.
tOSC, tW
VIH
OSC1,
X1
VIL
tCPH
tCPL
tCPr
tCPf
Figure 21.15 Clock Input Timing
RES
VIL
tREL
Figure 21.16 RES Low Width Timing
NMI, IRQ0, IRQ1,
ADTRG, IRQAEC,
AEVL, AEVH,
FTCI, FTIOA to FTIOD
VIH
VIL
tIL
tIH
Figure 21.17 Input Timing
tSCKW
SCK3
tScyc
Figure 21.18 SCK3 Input Clock Timing
Rev. 3.00 May 15, 2007 Page 435 of 516
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Section 21 Electrical Characteristics
tscyc
VIH or VOH*
SCK3
VIL or VOL*
tTXD
TXD3
(transmit data)
VOH*
VOL*
tRXS
tRXH
RXD3
(receive data)
Note: * Output timing referenced levels
Output high
VOH = 1/2Vcc + 0.2 V
Output low
VOL = 0.8 V
Load conditions are shown in figure 21.27.
Figure 21.19 SCI3 Input/Output Timing in Clock Synchronous Mode
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 21.20 SSU Input/Output Timing in Clock Synchronous Mode
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Section 21 Electrical Characteristics
SCS (output)
VIH or VOH
VIL or VOL
tFALL
tHI
tRISE
SSCK (output)
CPOS = 1
tLO
tHI
SSCK (output)
CPOS = 0
tSUCYC
tLO
SSO (output)
tOH
tOD
SSI (input)
tSU
tH
Figure 21.21 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 1)
SCS (output)
VIH or VOH
VIL or VOL
tFALL
tHI
tRISE
SSCK (output)
CPOS = 1
tLO
tHI
SSCK (output)
CPOS = 0
tLO
tSUCYC
SSO (output)
tOH
tOD
SSI (input)
tSU
tH
Figure 21.22 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 0)
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Section 21 Electrical Characteristics
VIH or VOH
SCS (input)
VIL or VOL
tFALL
tHI
tLEAD
tRISE
tLAG
SSCK (input)
CPOS = 1
tLO
tHI
SSCK (input)
CPOS = 0
tSUCYC
tLO
SSO (input)
tH
tSU
SSI (output)
tOH
tSA
tOD
tOR
Figure 21.23 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 1)
VIH or VOH
VIL or VOL
SCS (input)
tLEAD
tFALL
tHI
tRISE
tLAG
SSCK (input)
CPOS = 1
tLO
tHI
SSCK (input)
CPOS = 0
tSUCYC
tLO
SSO (input)
tSU
tH
SSI (output)
tSA
tOH
tOD
tOD
Figure 21.24 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 0)
Rev. 3.00 May 15, 2007 Page 438 of 516
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Section 21 Electrical Characteristics
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOS
SCL
P*
S*
tSf
Sr*
tSCLL
P*
tSDAS
tSr
tSCL
tSDAH
Note: * S, P, and Sr represent the following:
S: Start condition
P: Stop condition
Sr: Repeated start condition
Figure 21.25 I2C Bus Interface Input/Output Timing
VCC
t_vtr
v_rst
RES
Internal reset
t_cr
t_out
Figure 21.26 Power-On Reset Circuit Reset Timing
Rev. 3.00 May 15, 2007 Page 439 of 516
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Section 21 Electrical Characteristics
21.6
Output Load Circuit
VCC
2.4 kΩ
LSI output pin
30 pF
12 kΩ
Figure 21.27 Output Load Condition
21.7
Recommended Resonators
(1) Recommended Crystal Resonators
Frequency (MHz)
Manufacturer
4.194304
NIHON DEMPA KOGYO CO., LTD.
Part No.
NR-18
10
NIHON DEMPA KOGYO CO., LTD.
NR-18
(2) Recommended Ceramic Resonators
Frequency (MHz)
Manufacturer
2
Murata Manufacturing Co., Ltd.
Part No.
CSTCC2M00G53-B0
CSTCC2M00G56-B0
4.19
Murata Manufacturing Co., Ltd.
CSTLS4M19G53-B0
CSTLS4M19G56-B0
10
Murata Manufacturing Co., Ltd.
CSTLS10M0G53-B0
CSTLS10M0G56-B0
Figure 21.28 Recommended Resonators
Rev. 3.00 May 15, 2007 Page 440 of 516
REJ09B0152-0300
Section 21 Electrical Characteristics
21.8
Usage Note
The F-ZTAT and masked ROM versions satisfy the electrical characteristics shown in this
manual, however actual electrical characteristic values, operating margins, noise margins, and
other properties may vary due to differences in manufacturing process, on-chip ROM, layout
patterns, and so on.
When system evaluation testing is carried out using the F-ZTAT version, the same evaluation
testing should also be conducted for the masked ROM version when changing over to that version.
Rev. 3.00 May 15, 2007 Page 441 of 516
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Section 21 Electrical Characteristics
Rev. 3.00 May 15, 2007 Page 442 of 516
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Appendix
Appendix
A.
Instruction Set
A.1
Instruction List
Condition Code
Symbol
Description
Rd
Rs
Rn
ERd
ERs
ERn
(EAd)
(EAs)
PC
SP
CCR
N
Z
V
C
disp
→
+
–
×
÷
∧
∨
General destination register
General source register
General register
General destination register (address register or 32-bit register)
General source register (address register or 32-bit register)
General register (32-bit register)
Destination operand
Source operand
Program counter
Stack pointer
Condition-code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Displacement
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
Addition of the operands on both sides
Subtraction of the operand on the right from the operand on the left
Multiplication of the operands on both sides
Division of the operand on the left by the operand on the right
Logical AND of the operands on both sides
Logical OR of the operands on both sides
⊕
¬
( ), < >
Logical exclusive OR of the operands on both sides
NOT (logical complement)
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Rev. 3.00 May 15, 2007 Page 443 of 516
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Appendix
Symbol
Description
↔
Condition Code Notation (cont)
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
1
Set to 1
—
Not affected by execution of the instruction
∆
Varies depending on conditions, described in notes
Rev. 3.00 May 15, 2007 Page 444 of 516
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Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
No. of
States*1
MOV.B @ERs, Rd
B
MOV.B @(d:16, ERs), Rd
B
4
@(d:16, ERs) → Rd8
— —
MOV.B @(d:24, ERs), Rd
B
8
@(d:24, ERs) → Rd8
— —
MOV.B @ERs+, Rd
B
@ERs → Rd8
— —
Advanced
Normal
—
— —
—
2
Rs8 → Rd8
— —
0
—
2
@ERs → Rd8
— —
0
—
4
0
—
6
0
—
10
0
—
6
—
4
0
—
6
0
—
8
0
—
4
0
—
6
0
—
10
0
—
6
—
4
0
—
6
0
—
8
0
—
4
0
—
2
0
—
4
0
—
6
0
—
10
0
—
6
—
6
0
—
8
0
—
4
0
—
6
0
—
10
↔ ↔ ↔ ↔ ↔ ↔
#xx:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔
C
0
↔ ↔ ↔ ↔ ↔ ↔ ↔
V
↔ ↔ ↔ ↔ ↔ ↔ ↔
Z
0
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
@@aa
N
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
H
0
↔ ↔ ↔ ↔ ↔
2
I
↔ ↔ ↔ ↔ ↔
2
@(d, PC)
Operation
@aa
@(d, ERn)
2
B
@ERn
#xx
B
MOV.B Rs, Rd
Rn
Operand Size
Condition Code
MOV.B #xx:8, Rd
Mnemonic
MOV
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
0
ERs32+1 → ERs32
MOV.B @aa:8, Rd
B
2
@aa:8 → Rd8
— —
MOV.B @aa:16, Rd
B
4
@aa:16 → Rd8
— —
MOV.B @aa:24, Rd
B
6
@aa:24 → Rd8
— —
MOV.B Rs, @ERd
B
Rs8 → @ERd
— —
MOV.B Rs, @(d:16, ERd)
B
4
Rs8 → @(d:16, ERd)
— —
MOV.B Rs, @(d:24, ERd)
B
8
Rs8 → @(d:24, ERd)
— —
MOV.B Rs, @–ERd
B
ERd32–1 → ERd32
— —
2
2
Rs8 → @ERd
MOV.B Rs, @aa:8
B
2
Rs8 → @aa:8
— —
MOV.B Rs, @aa:16
B
4
Rs8 → @aa:16
— —
MOV.B Rs, @aa:24
B
6
Rs8 → @aa:24
— —
MOV.W #xx:16, Rd
W
#xx:16 → Rd16
— —
MOV.W Rs, Rd
W
Rs16 → Rd16
— —
MOV.W @ERs, Rd
W
@ERs → Rd16
— —
MOV.W @(d:16, ERs), Rd
W
4
@(d:16, ERs) → Rd16
— —
MOV.W @(d:24, ERs), Rd
W
8
@(d:24, ERs) → Rd16
— —
MOV.W @ERs+, Rd
W
@ERs → Rd16
— —
4
2
2
2
ERs32+2 → @ERd32
MOV.W @aa:16, Rd
W
4
@aa:16 → Rd16
— —
MOV.W @aa:24, Rd
W
6
@aa:24 → Rd16
— —
MOV.W Rs, @ERd
W
Rs16 → @ERd
— —
MOV.W Rs, @(d:16, ERd)
W
4
Rs16 → @(d:16, ERd)
— —
MOV.W Rs, @(d:24, ERd)
W
8
Rs16 → @(d:24, ERd)
— —
2
Rev. 3.00 May 15, 2007 Page 445 of 516
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Appendix
Condition Code
Advanced
2
0
—
8
0
—
10
0
—
14
0
—
10
—
10
0
—
12
0
—
8
0
—
10
0
—
14
0
—
10
—
10
0
—
12
0
—
6
—
10
—
6
—
10
↔
—
↔
6
0
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
—
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
8
0
↔ ↔ ↔ ↔ ↔ ↔
6
—
↔ ↔ ↔ ↔ ↔ ↔
—
0
0
0
0
— —
↔ ↔ ↔
6
↔ ↔ ↔
C
—
0
— —
↔
V
↔
Z
0
— —
↔
N
↔
H
— —
0
— —
↔
I
ERd32–2 → ERd32
2
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
W
#xx
MOV.W Rs, @–ERd
No. of
States*1
↔
MOV
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0
Rs16 → @ERd
MOV.W Rs, @aa:16
W
4
Rs16 → @aa:16
— —
MOV.W Rs, @aa:24
W
6
Rs16 → @aa:24
— —
MOV.L #xx:32, ERd
L
#xx:32 → ERd32
— —
MOV.L ERs, ERd
L
ERs32 → ERd32
— —
MOV.L @ERs, ERd
L
@ERs → ERd32
— —
MOV.L @(d:16, ERs), ERd
L
6
@(d:16, ERs) → ERd32
— —
MOV.L @(d:24, ERs), ERd
L
10
@(d:24, ERs) → ERd32
— —
MOV.L @ERs+, ERd
L
@ERs → ERd32
— —
6
2
4
4
ERs32+4 → ERs32
MOV.L @aa:16, ERd
L
6
@aa:16 → ERd32
— —
MOV.L @aa:24, ERd
L
8
@aa:24 → ERd32
— —
MOV.L ERs, @ERd
L
ERs32 → @ERd
— —
MOV.L ERs, @(d:16, ERd)
L
6
ERs32 → @(d:16, ERd)
— —
MOV.L ERs, @(d:24, ERd)
L
10
ERs32 → @(d:24, ERd)
— —
MOV.L ERs, @–ERd
L
ERd32–4 → ERd32
— —
4
4
ERs32 → @ERd
POP
MOV.L ERs, @aa:16
L
6
ERs32 → @aa:16
— —
MOV.L ERs, @aa:24
L
8
ERs32 → @aa:24
— —
POP.W Rn
W
2 @SP → Rn16
SP+2 → SP
POP.L ERn
4 @SP → ERn32
L
SP+4 → SP
PUSH
PUSH.W Rn
2 SP–2 → SP
W
Rn16 → @SP
PUSH.L ERn
4 SP–4 → SP
L
ERn32 → @SP
MOVFPE MOVFPE @aa:16, Rd
MOVTPE MOVTPE Rs, @aa:16
B
B
Rev. 3.00 May 15, 2007 Page 446 of 516
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4
4
Cannot be used in
Cannot be used in
this LSI
this LSI
Cannot be used in
Cannot be used in
this LSI
this LSI
Appendix
2. Arithmetic Instructions
C
↔ ↔
— (2)
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
— (2)
↔
(3)
↔ ↔
— (1)
ERd32+#xx:32 →
↔ ↔ ↔ ↔ ↔
Rd16+Rs16 → Rd16
↔ ↔ ↔ ↔ ↔
— (1)
↔
Rd16+#xx:16 → Rd16
2
2
Rd8+#xx:8 +C → Rd8
—
2
B
2
Rd8+Rs8 +C → Rd8
—
↔ ↔
—
↔
Rd8+Rs8 → Rd8
Advanced
V
—
Normal
Z
↔
L
N
↔ ↔
ADD.L #xx:32, ERd
H
↔ ↔
W
I
Rd8+#xx:8 → Rd8
ADDS ADDS.L #1, ERd
L
2
ERd32+1 → ERd32
— — — — — —
2
ADDS.L #2, ERd
L
2
ERd32+2 → ERd32
— — — — — —
2
ADDS.L #4, ERd
L
2
ERd32+4 → ERd32
— — — — — —
2
INC.B Rd
B
2
Rd8+1 → Rd8
— —
INC.W #1, Rd
W
2
Rd16+1 → Rd16
— —
INC.W #2, Rd
W
2
Rd16+2 → Rd16
— —
INC.L #1, ERd
L
2
ERd32+1 → ERd32
— —
INC.L #2, ERd
L
2
ERd32+2 → ERd32
— —
DAA Rd
B
2
Rd8 decimal adjust
—
*
Rd8–Rs8 → Rd8
—
↔
ADD.W Rs, Rd
—
W
@@aa
ADD.W #xx:16, Rd
Condition Code
@(d, PC)
B
No. of
States*1
Operation
@aa
ADD.B Rs, Rd
@–ERn/@ERn+
2
@(d, ERn)
B
@ERn
#xx
ADD.B #xx:8, Rd
Rn
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Rd16–#xx:16 → Rd16
— (1)
Rd16–Rs16 → Rd16
— (1)
ERd32–#xx:32 → ERd32
— (2)
ERd32–ERs32 → ERd32
— (2)
Rd8–#xx:8–C → Rd8
—
ADD
2
4
2
6
2
4
2
6
ERd32
ADD.L ERs, ERd
L
2
ERd32+ERs32 →
(3)
2
2
—
2
—
2
—
2
—
2
*
↔
—
2
2
B
2
Rd8–Rs8–C → Rd8
—
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
2
↔ ↔ ↔ ↔ ↔ ↔
INC
B
↔ ↔ ↔ ↔ ↔
ADDX.B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔ ↔
ADDX ADDX.B #xx:8, Rd
↔ ↔ ↔ ↔ ↔ ↔
ERd32
SUBS SUBS.L #1, ERd
L
2
ERd32–1 → ERd32
— — — — — —
2
SUBS.L #2, ERd
L
2
ERd32–2 → ERd32
— — — — — —
2
SUBS.L #4, ERd
L
2
ERd32–4 → ERd32
— — — — — —
2
DEC.B Rd
B
2
Rd8–1 → Rd8
— —
DEC.W #1, Rd
W
2
Rd16–1 → Rd16
— —
DEC.W #2, Rd
W
2
Rd16–2 → Rd16
— —
DAA
SUB.W Rs, Rd
W
SUB.L #xx:32, ERd
L
SUB.L ERs, ERd
L
SUBX SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
DEC
B
2
4
2
6
2
2
(3)
(3)
↔ ↔ ↔
W
↔ ↔ ↔
B
SUB.W #xx:16, Rd
↔ ↔
SUB.B Rs, Rd
↔ ↔ ↔
SUB
↔ ↔ ↔ ↔ ↔ ↔ ↔
→ Rd8
4
2
6
2
2
2
—
2
—
2
—
2
Rev. 3.00 May 15, 2007 Page 447 of 516
REJ09B0152-0300
Appendix
Advanced
I
Normal
H
N
Z
V
C
DEC.L #1, ERd
L
2
ERd32–1 → ERd32
— —
—
2
DEC.L #2, ERd
L
2
ERd32–2 → ERd32
— —
↔ ↔
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Condition Code
Operation
—
2
DAS.Rd
B
2
Rd8 decimal adjust
—
↔ ↔ ↔
DAS
No. of
States*1
↔ ↔ ↔
DEC
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
*
—
2
— — — — — —
14
— — — — — —
22
*
→ Rd8
MULXU MULXU. B Rs, Rd
B
2
Rd8 × Rs8 → Rd16
(unsigned multiplication)
MULXU. W Rs, ERd
W
2
Rd16 × Rs16 → ERd32
Rd8 × Rs8 → Rd16
↔
4
— —
↔
B
— —
16
↔
MULXS MULXS. B Rs, Rd
— —
↔
(unsigned multiplication)
— —
24
— — (6) (7) — —
14
— — (6) (7) — —
22
— — (8) (7) — —
16
— — (8) (7) — —
24
(signed multiplication)
MULXS. W Rs, ERd
W
4
Rd16 × Rs16 → ERd32
(signed multiplication)
DIVXU DIVXU. B Rs, Rd
B
2
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
DIVXU. W Rs, ERd
W
2
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
DIVXS DIVXS. B Rs, Rd
B
4
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
DIVXS. W Rs, ERd
W
4
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
CMP.W #xx:16, Rd
W
CMP.W Rs, Rd
W
CMP.L #xx:32, ERd
L
CMP.L ERs, ERd
L
2
2
4
2
6
2
Rev. 3.00 May 15, 2007 Page 448 of 516
REJ09B0152-0300
Rd8–#xx:8
—
Rd8–Rs8
—
Rd16–#xx:16
— (1)
Rd16–Rs16
— (1)
ERd32–#xx:32
— (2)
ERd32–ERs32
— (2)
↔ ↔ ↔ ↔ ↔ ↔
B
↔ ↔ ↔ ↔ ↔ ↔
B
CMP.B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
CMP.B #xx:8, Rd
↔ ↔
CMP
↔ ↔ ↔ ↔ ↔ ↔
(signed division)
2
2
4
2
4
2
Appendix
NEG.W Rd
W
2
0–Rd16 → Rd16
—
NEG.L ERd
L
2
0–ERd32 → ERd32
—
EXTU.W Rd
W
2
0 → (<bits 15 to 8>
— —
0
— —
0
— —
— —
Advanced
C
Normal
V
↔ ↔ ↔
—
↔ ↔ ↔
Z
↔ ↔ ↔
0–Rd8 → Rd8
↔ ↔ ↔ ↔
2
2
0
—
2
↔
H
B
0
—
2
↔
I
NEG.B Rd
0
—
2
↔
N
↔ ↔ ↔
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Condition Code
Operation
↔
EXTU
No. of
States*1
↔
NEG
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0
—
2
2
2
of Rd16)
EXTU.L ERd
L
2
0 → (<bits 31 to 16>
of ERd32)
EXTS
EXTS.W Rd
W
2
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
EXTS.L ERd
L
2
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
Rev. 3.00 May 15, 2007 Page 449 of 516
REJ09B0152-0300
Appendix
3. Logic Instructions
AND.L #xx:32, ERd
L
AND.L ERs, ERd
L
OR.B #xx:8, Rd
B
OR.B Rs, Rd
B
OR.W #xx:16, Rd
W
OR.W Rs, Rd
W
OR.L #xx:32, ERd
L
OR.L ERs, ERd
L
XOR
XOR.B #xx:8, Rd
B
XOR.B Rs, Rd
B
XOR.W #xx:16, Rd
W
XOR.W Rs, Rd
W
XOR.L #xx:32, ERd
L
XOR.L ERs, ERd
L
NOT
NOT.B Rd
N
Z
V
C
— —
0
—
2
Rd8∧Rs8 → Rd8
— —
0
—
2
Rd16∧#xx:16 → Rd16
— —
0
—
4
Rd16∧Rs16 → Rd16
— —
0
—
2
ERd32∧#xx:32 → ERd32
— —
0
—
6
ERd32∧ERs32 → ERd32
— —
0
—
4
Rd8⁄#xx:8 → Rd8
— —
0
—
2
Rd8⁄Rs8 → Rd8
— —
0
—
2
Rd16∨#xx:16 → Rd16
— —
0
—
4
Rd16∨Rs16 → Rd16
— —
0
—
2
ERd32∨#xx:32 → ERd32
— —
0
—
6
ERd32∨ERs32 → ERd32
— —
0
—
4
Rd8⊕#xx:8 → Rd8
— —
0
—
2
Rd8⊕Rs8 → Rd8
— —
0
—
2
Rd16⊕#xx:16 → Rd16
— —
0
—
4
Rd16⊕Rs16 → Rd16
— —
0
—
2
ERd32⊕#xx:32 → ERd32
— —
0
—
6
4
ERd32⊕ERs32 → ERd32
— —
0
—
4
B
2
¬ Rd8 → Rd8
— —
0
—
2
NOT.W Rd
W
2
¬ Rd16 → Rd16
— —
0
—
2
NOT.L ERd
L
2
¬ Rd32 → Rd32
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
OR
Advanced
W
H
Rd8∧#xx:8 → Rd8
0
—
2
2
4
2
6
4
2
2
4
2
6
4
2
2
4
2
6
Rev. 3.00 May 15, 2007 Page 450 of 516
REJ09B0152-0300
I
Normal
AND.W Rs, Rd
—
W
@@aa
AND.W #xx:16, Rd
@(d, PC)
B
Condition Code
Operation
@aa
AND.B Rs, Rd
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
AND
@–ERn/@ERn+
2
@(d, ERn)
B
@ERn
#xx
AND.B #xx:8, Rd
Mnemonic
Rn
Operand Size
Addressing Mode and
Instruction Length (bytes)
Appendix
4. Shift Instructions
W
2
SHAL.L ERd
L
2
SHAR SHAR.B Rd
B
2
SHAR.W Rd
W
2
SHAR.L ERd
L
2
SHLL.B Rd
B
2
SHLL.W Rd
W
2
SHLL.L ERd
L
2
SHLR SHLR.B Rd
B
2
SHLR.W Rd
W
2
SHLR.L ERd
L
2
ROTXL ROTXL.B Rd
B
2
ROTXL.W Rd
W
2
ROTXL.L ERd
L
2
ROTXR ROTXR.B Rd
B
2
ROTXR.W Rd
W
2
ROTXR.L ERd
L
2
ROTL ROTL.B Rd
B
2
ROTL.W Rd
W
2
ROTL.L ERd
L
2
ROTR ROTR.B Rd
B
2
ROTR.W Rd
W
2
ROTR.L ERd
L
2
SHLL
0
MSB
LSB
V
C
— —
— —
— —
C
— —
LSB
MSB
— —
— —
C
0
LSB
MSB
— —
— —
— —
0
C
MSB
LSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
MSB
LSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
MSB
LSB
— —
— —
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Advanced
Z
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
I
C
N
↔ ↔ ↔
SHAL.W Rd
H
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
Condition Code
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
SHAL SHAL.B Rd
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev. 3.00 May 15, 2007 Page 451 of 516
REJ09B0152-0300
Appendix
5. Bit-Manipulation Instructions
BSET BSET #xx:3, Rd
B
BSET #xx:3, @ERd
B
BSET #xx:3, @aa:8
B
BSET Rn, Rd
B
BSET Rn, @ERd
B
BSET Rn, @aa:8
B
BCLR BCLR #xx:3, Rd
B
BCLR #xx:3, @ERd
B
BCLR #xx:3, @aa:8
B
BCLR Rn, Rd
B
BCLR Rn, @ERd
B
BCLR Rn, @aa:8
B
BNOT BNOT #xx:3, Rd
B
No. of
States*1
Condition Code
2
4
4
2
4
4
2
4
4
2
4
4
2
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
(#xx:3 of Rd8) ← 1
— — — — — —
2
(#xx:3 of @ERd) ← 1
— — — — — —
8
(#xx:3 of @aa:8) ← 1
— — — — — —
8
(Rn8 of Rd8) ← 1
— — — — — —
2
(Rn8 of @ERd) ← 1
— — — — — —
8
(Rn8 of @aa:8) ← 1
— — — — — —
8
(#xx:3 of Rd8) ← 0
— — — — — —
2
(#xx:3 of @ERd) ← 0
— — — — — —
8
(#xx:3 of @aa:8) ← 0
— — — — — —
8
(Rn8 of Rd8) ← 0
— — — — — —
2
(Rn8 of @ERd) ← 0
— — — — — —
8
(Rn8 of @aa:8) ← 0
— — — — — —
8
(#xx:3 of Rd8) ←
— — — — — —
2
— — — — — —
8
— — — — — —
8
— — — — — —
2
— — — — — —
8
— — — — — —
8
¬ (#xx:3 of Rd8)
BNOT #xx:3, @ERd
B
(#xx:3 of @ERd) ←
4
¬ (#xx:3 of @ERd)
BNOT #xx:3, @aa:8
B
4
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
BNOT Rn, Rd
B
(Rn8 of Rd8) ←
2
¬ (Rn8 of Rd8)
BNOT Rn, @ERd
B
(Rn8 of @ERd) ←
4
¬ (Rn8 of @ERd)
BNOT Rn, @aa:8
B
4
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
B
BTST #xx:3, @ERd
B
BTST #xx:3, @aa:8
B
BTST Rn, Rd
B
BTST Rn, @ERd
B
BTST Rn, @aa:8
B
BLD #xx:3, Rd
B
2
4
4
2
4
4
2
Rev. 3.00 May 15, 2007 Page 452 of 516
REJ09B0152-0300
¬ (#xx:3 of Rd8) → Z
— — —
¬ (#xx:3 of @ERd) → Z
— — —
¬ (#xx:3 of @aa:8) → Z
— — —
¬ (Rn8 of @Rd8) → Z
— — —
¬ (Rn8 of @ERd) → Z
— — —
¬ (Rn8 of @aa:8) → Z
— — —
(#xx:3 of Rd8) → C
— — — — —
— —
2
— —
6
— —
6
— —
2
— —
6
— —
6
↔
BLD
BTST #xx:3, Rd
↔ ↔ ↔ ↔ ↔ ↔
BTST
2
Appendix
BST
BIST
B
BLD #xx:3, @aa:8
B
BILD #xx:3, Rd
B
BILD #xx:3, @ERd
B
BILD #xx:3, @aa:8
B
BST #xx:3, Rd
B
BST #xx:3, @ERd
B
BST #xx:3, @aa:8
B
BIST #xx:3, Rd
B
BIST #xx:3, @ERd
B
BIST #xx:3, @aa:8
B
BAND BAND #xx:3, Rd
BAND #xx:3, @ERd
B
BAND #xx:3, @aa:8
B
BIAND BIAND #xx:3, Rd
BOR
BIOR
B
B
BIAND #xx:3, @ERd
B
BIAND #xx:3, @aa:8
B
BOR #xx:3, Rd
B
BOR #xx:3, @ERd
B
BOR #xx:3, @aa:8
B
BIOR #xx:3, Rd
B
BIOR #xx:3, @ERd
B
BIOR #xx:3, @aa:8
B
BXOR BXOR #xx:3, Rd
B
BXOR #xx:3, @ERd
B
BXOR #xx:3, @aa:8
B
BIXOR BIXOR #xx:3, Rd
B
BIXOR #xx:3, @ERd
B
BIXOR #xx:3, @aa:8
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
H
N
Z
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Condition Code
Operation
V
C
(#xx:3 of @ERd) → C
— — — — —
6
(#xx:3 of @aa:8) → C
— — — — —
¬ (#xx:3 of Rd8) → C
— — — — —
¬ (#xx:3 of @ERd) → C
— — — — —
¬ (#xx:3 of @aa:8) → C
— — — — —
↔ ↔ ↔ ↔ ↔
BILD
BLD #xx:3, @ERd
No. of
States*1
C → (#xx:3 of Rd8)
— — — — — —
2
C → (#xx:3 of @ERd24)
— — — — — —
8
C → (#xx:3 of @aa:8)
— — — — — —
8
¬ C → (#xx:3 of Rd8)
— — — — — —
2
¬ C → (#xx:3 of @ERd24)
— — — — — —
8
¬ C → (#xx:3 of @aa:8)
— — — — — —
8
C∧(#xx:3 of Rd8) → C
— — — — —
2
C∧(#xx:3 of @ERd24) → C
— — — — —
C∧(#xx:3 of @aa:8) → C
— — — — —
C∧ ¬ (#xx:3 of Rd8) → C
— — — — —
C∧ ¬ (#xx:3 of @ERd24) → C
— — — — —
C∧ ¬ (#xx:3 of @aa:8) → C
— — — — —
C∨(#xx:3 of Rd8) → C
— — — — —
C∨(#xx:3 of @ERd24) → C
— — — — —
C∨(#xx:3 of @aa:8) → C
— — — — —
C∨ ¬ (#xx:3 of Rd8) → C
— — — — —
C∨ ¬ (#xx:3 of @ERd24) → C
— — — — —
C∨ ¬ (#xx:3 of @aa:8) → C
— — — — —
C⊕(#xx:3 of Rd8) → C
— — — — —
C⊕(#xx:3 of @ERd24) → C
— — — — —
C⊕(#xx:3 of @aa:8) → C
— — — — —
C⊕ ¬ (#xx:3 of Rd8) → C
— — — — —
C⊕ ¬ (#xx:3 of @ERd24) → C
— — — — —
C⊕ ¬ (#xx:3 of @aa:8) → C
— — — — —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BLD
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
6
2
6
6
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Rev. 3.00 May 15, 2007 Page 453 of 516
REJ09B0152-0300
Appendix
6. Branching Instructions
Bcc
No. of
States*1
Condition Code
BRA d:8 (BT d:8)
—
2
If condition
BRA d:16 (BT d:16)
—
4
is true then
BRN d:8 (BF d:8)
—
2
PC ← PC+d
BRN d:16 (BF d:16)
—
4
BHI d:8
—
2
BHI d:16
—
4
BLS d:8
—
2
BLS d:16
—
4
BCC d:8 (BHS d:8)
—
2
BCC d:16 (BHS d:16)
—
4
BCS d:8 (BLO d:8)
—
2
BCS d:16 (BLO d:16)
—
4
BNE d:8
—
2
BNE d:16
—
4
BEQ d:8
—
2
BEQ d:16
—
4
BVC d:8
—
2
BVC d:16
—
4
BVS d:8
—
2
BVS d:16
—
4
BPL d:8
—
2
BPL d:16
—
4
BMI d:8
—
2
BMI d:16
—
4
BGE d:8
—
2
BGE d:16
—
4
BLT d:8
—
2
BLT d:16
—
4
BGT d:8
—
2
BGT d:16
—
4
BLE d:8
—
2
BLE d:16
—
4
Rev. 3.00 May 15, 2007 Page 454 of 516
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Always
Never
else next;
C∨ Z = 0
C∨ Z = 1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V = 0
N⊕V = 1
Z∨ (N⊕V) = 0
Z∨ (N⊕V) = 1
H
N
Z
V
C
Advanced
I
Normal
Branch
Condition
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
Appendix
JMP
BSR
JMP @ERn
—
JMP @aa:24
—
JMP @@aa:8
—
BSR d:8
—
No. of
States*1
Condition Code
2
4
2
2
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
PC ← ERn
— — — — — —
PC ← aa:24
— — — — — —
PC ← @aa:8
— — — — — —
8
10
PC → @–SP
— — — — — —
6
8
— — — — — —
8
10
— — — — — —
6
8
— — — — — —
8
10
— — — — — —
8
12
— — — — — —
8
10
4
6
PC ← PC+d:8
BSR d:16
PC → @–SP
4
—
PC ← PC+d:16
JSR
JSR @ERn
—
PC → @–SP
2
PC ← ERn
JSR @aa:24
—
PC → @–SP
4
PC ← aa:24
JSR @@aa:8
—
2
PC → @–SP
PC ← @aa:8
RTS
RTS
—
2 PC ← @SP+
Rev. 3.00 May 15, 2007 Page 455 of 516
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Appendix
7. System Control Instructions
Condition Code
H
C
Advanced
@@aa
I
Normal
—
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
No. of
States*1
—
TRAPA TRAPA #x:2
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2 PC → @-SP
1
— — — — —
14
16
N
Z
V
CCR → @-SP
↔
↔
↔
↔
↔
CCR ← @SP+
↔
—
10
—
— — — — —
2
↔ ↔ ↔ ↔ ↔
RTE
↔ ↔ ↔ ↔ ↔
<vector> → PC
RTE
2
PC ← @SP+
SLEEP SLEEP
—
Transition to power-
LDC @ERs, CCR
W
LDC @(d:16, ERs), CCR
W
6
@(d:16, ERs) → CCR
LDC @(d:24, ERs), CCR
W
10
@(d:24, ERs) → CCR
LDC @ERs+, CCR
W
2
#xx:8 → CCR
2
Rs8 → CCR
4
@ERs → CCR
4
6
8
12
↔
↔
↔
↔
↔
↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔
8
10
CCR → Rd8
—
— — — — —
2
CCR → @ERd
—
— — — — —
6
6
CCR → @(d:16, ERd)
—
— — — — —
8
10
CCR → @(d:24, ERd)
—
— — — — —
12
ERd32–2 → ERd32
—
— — — — —
8
ERs32+2 → ERs32
STC
2
↔ ↔
@ERs → CCR
↔ ↔ ↔ ↔ ↔
B
↔ ↔ ↔ ↔ ↔
B
LDC Rs, CCR
↔ ↔ ↔ ↔ ↔
LDC #xx:8, CCR
↔ ↔
LDC
↔ ↔ ↔ ↔ ↔
down state
LDC @aa:16, CCR
W
6
LDC @aa:24, CCR
W
8
STC CCR, Rd
B
STC CCR, @ERd
W
STC CCR, @(d:16, ERd)
W
STC CCR, @(d:24, ERd)
W
STC CCR, @–ERd
W
2
4
4
@aa:16 → CCR
@aa:24 → CCR
8
CCR → @aa:16
—
— — — — —
8
8
CCR → @aa:24
—
— — — — —
10
ANDC ANDC #xx:8, CCR
B
2
CCR∧#xx:8 → CCR
2
CCR∨#xx:8 → CCR
B
2
↔ ↔ ↔
↔ ↔ ↔
2
B
—
— — — — —
2
ORC
ORC #xx:8, CCR
XORC XORC #xx:8, CCR
NOP
NOP
—
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REJ09B0152-0300
CCR⊕#xx:8 → CCR
2 PC ← PC+2
↔ ↔ ↔
6
W
↔ ↔ ↔
W
STC CCR, @aa:24
↔ ↔ ↔
STC CCR, @aa:16
↔ ↔ ↔
CCR → @ERd
2
2
Appendix
8. Block Data Transfer Instructions
EEPMOV
No. of
States*1
Condition Code
repeat
H
N
Z
V
C
Advanced
I
4 if R4L ≠ 0 then
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
—
Rn
EEPMOV. B
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
— — — — — —
8+4n*2
— — — — — —
8+4n*2
@R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next
EEPMOV. W
—
4 if R4 ≠ 0 then
repeat
@R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until
R4=0
else next
Notes: 1. The number of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases, see appendix A.3, Number of
Execution States.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
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Rev. 3.00 May 15, 2007 Page 458 of 516
XOR
SUBX
OR
XOR
AND
MOV
B
C
D
E
F
BILD
CMP
BIAND
BIST
BLD
A
BIXOR
BAND
AND
TRAPA
RTE
BST
BEQ
BNE
MOV.B
Table A-2
(2)
LDC
7
ADDX
BIOR
BXOR
OR
BOR
BSR
BCS
RTS
BCC
AND.B
ANDC
6
9
BTST
DIVXU
BLS
XOR.B
XORC
5
ADD
BCLR
MULXU
BHI
OR.B
ORC
4
MOV
BVS
9
Table A-2
(2)
SUB
ADD
Table A-2
(2)
BVC
8
BMI
MOV
Table A-2
(2)
Table A-2
(2)
B
Table A-2
EEPMOV
(2)
JMP
BPL
Table A-2
(2)
Table A-2
(2)
A
C
BSR
BGE
Instruction when most significant bit of BH is 1.
Instruction when most significant bit of BH is 0.
8
7
BNOT
DIVXU
MULXU
5
BSET
BRN
BRA
6
LDC
3
Table A-2 Table A-2 Table A-2 Table A-2
(2)
(2)
(2)
(2)
STC
Table A-2
(2)
NOP
4
3
2
1
0
2
1
0
2nd byte
BH BL
CMP
MOV
E
JSR
BGT
SUBX
ADDX
Table A-2
(3)
BLT
D
BLE
Table A-2
(2)
Table A-2
(2)
F
Table A.2
AL
1st byte
AH AL
A.2
AH
Instruction code:
Appendix
Operation Code Map
Operation Code Map (1)
SUBS
DAS
BRA
MOV
MOV
1B
1F
58
79
7A
1
ADD
ADD
BRN
NOT
17
DEC
ROTXR
13
1A
ROTXL
12
DAA
0F
SHLR
ADDS
0B
11
INC
0A
SHLL
MOV
01
10
0
SUB
SUB
CMP
CMP
BLS
NOT
ROTXR
ROTXL
SHLR
SHLL
3
4
OR
OR
BCC
LDC/STC
2nd byte
BH BL
BHI
2
1st byte
AH AL
XOR
XOR
BCS
DEC
EXTU
INC
5
AND
AND
BNE
6
BEQ
DEC
EXTU
INC
7
BVC
9
BVS
SUBS
NEG
ROTR
ROTL
SHAR
SHAL
ADDS
SLEEP
8
BPL
A
MOV
BMI
CMP
SUB
NEG
ROTR
ROTL
SHAR
C
D
BGE
BLT
DEC
EXTS
INC
Table A-2 Table A-2
(3)
(3)
ADD
SHAL
B
BGT
E
F
BLE
DEC
EXTS
INC
Table A-2
(3)
Table A.2
BH
AH AL
Instruction code:
Appendix
Operation Code Map (2)
Rev. 3.00 May 15, 2007 Page 459 of 516
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Rev. 3.00 May 15, 2007 Page 460 of 516
DIVXS
3
BSET
7Faa7 *2
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
BSET
7Faa6 *2
BTST
BCLR
7Eaa7 *2
BNOT
BTST
BSET
7Dr07 *1
7Eaa6 *2
BSET
7Dr06 *1
BTST
BCLR
MULXS
2
7Cr07 *1
BNOT
DIVXS
1
BTST
MULXS
0
BIOR
BOR
BIOR
BIXOR
BXOR
BIXOR
BXOR
XOR
5
3rd byte
CH CL
OR
4
BOR
2nd byte
BH BL
7Cr06 *1
01F06
01D05
01C05
01406
CL
1st byte
AH AL
BIAND
BAND
BIAND
BAND
AND
6
7
BIST
BILD
BST
BLD
BIST
BILD
BST
BLD
4th byte
DH DL
8
LDC
STC
9
A
LDC
STC
B
C
LDC
STC
D
E
STC
F
LDC
Instruction when most significant bit of DH is 1.
Instruction when most significant bit of DH is 0.
Table A.2
AH
ALBH
BLCH
Instruction code:
Appendix
Operation Code Map (3)
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,
L=M=N=0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev. 3.00 May 15, 2007 Page 461 of 516
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Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location
Execution Status
(Instruction Cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3*
Word data access
SM
—
Internal operation
SN
Note:
*
1
Depends on which on-chip peripheral module is accessed. See section 20.1, Register
Addresses (Address Order).
Rev. 3.00 May 15, 2007 Page 462 of 516
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Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Mnemonic
Instruction
Fetch
I
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W #xx:16, Rd
2
ADD.W Rs, Rd
1
ADD.L #xx:32, ERd
3
ADD.L ERs, ERd
1
ADDS
ADDS #1/2/4, ERd
1
ADDX
ADDX #xx:8, Rd
1
ADDX Rs, Rd
1
AND
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
AND.W #xx:16, Rd
2
AND.W Rs, Rd
1
AND.L #xx:32, ERd
3
AND.L ERs, ERd
2
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
BAND #xx:3, @ERd
2
1
BAND #xx:3, @aa:8
2
1
Bcc
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
Word Data
Access
M
Internal
Operation
N
Rev. 3.00 May 15, 2007 Page 463 of 516
REJ09B0152-0300
Appendix
Instruction Mnemonic
Instruction
Fetch
I
Bcc
BLT d:8
2
BGT d:8
2
BLE d:8
2
BRA d:16(BT d:16)
2
2
BRN d:16(BF d:16)
2
2
BHI d:16
2
2
BLS d:16
2
2
BCC d:16(BHS d:16)
2
2
BCS d:16(BLO d:16)
2
2
BNE d:16
2
2
BEQ d:16
2
2
BVC d:16
2
2
BVS d:16
2
2
BPL d:16
2
2
BMI d:16
2
2
BGE d:16
2
2
BLT d:16
2
2
BGT d:16
2
2
BLE d:16
2
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @ERd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @ERd
2
2
2
BCLR
BIAND
BILD
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
BCLR Rn, @aa:8
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @ERd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD #xx:3, @ERd
2
1
BILD #xx:3, @aa:8
2
1
Rev. 3.00 May 15, 2007 Page 464 of 516
REJ09B0152-0300
Word Data
Access
M
Internal
Operation
N
Appendix
Instruction Mnemonic
Instruction
Fetch
I
BIOR
BIOR #xx:3, Rd
1
BIOR #xx:3, @ERd
2
1
BIOR #xx:3, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @ERd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @ERd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @ERd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @ERd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @ERd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @ERd
2
1
BOR #xx:3, @aa:8
2
1
BIST
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
BSET #xx:3, Rd
1
BSET #xx:3, @ERd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @ERd
2
BSET Rn, @aa:8
2
BSR d:8
2
1
BSR d:16
2
1
Word Data
Access
M
Internal
Operation
N
2
2
2
BST #xx:3, Rd
1
BST #xx:3, @ERd
2
2
BST #xx:3, @aa:8
2
2
Rev. 3.00 May 15, 2007 Page 465 of 516
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Appendix
Instruction Mnemonic
Instruction
Fetch
I
BTST
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BTST #xx:3, Rd
1
BTST #xx:3, @ERd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @ERd
2
1
BTST Rn, @aa:8
2
1
BXOR #xx:3, Rd
1
BXOR #xx:3, @ERd
2
1
BXOR #xx:3, @aa:8
2
1
CMP.B #xx:8, Rd
1
CMP.B Rs, Rd
1
CMP.W #xx:16, Rd
2
CMP.W Rs, Rd
1
CMP.L #xx:32, ERd
3
CMP.L ERs, ERd
1
DAA
DAA Rd
1
DAS
DAS Rd
1
DEC
DEC.B Rd
1
DEC.W #1/2, Rd
1
DEC.L #1/2, ERd
1
DIVXS.B Rs, Rd
2
DIVXS.W Rs, ERd
2
20
DIVXU.B Rs, Rd
1
12
DIVXU.W Rs, ERd
1
BXOR
CMP
DIVXS
DIVXU
EEPMOV
EXTS
EXTU
12
20
1
EEPMOV.B
2
2n+2*
EEPMOV.W
2
2n+2*1
EXTS.W Rd
1
EXTS.L ERd
1
EXTU.W Rd
1
EXTU.L ERd
1
Rev. 3.00 May 15, 2007 Page 466 of 516
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Appendix
Instruction Mnemonic
Instruction
Fetch
I
INC
JMP
JSR
LDC
MOV
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
Word Data
Access
M
INC.B Rd
1
INC.W #1/2, Rd
1
INC.L #1/2, ERd
1
JMP @ERn
2
JMP @aa:24
2
JMP @@aa:8
2
JSR @ERn
2
JSR @aa:24
2
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
LDC@ERs, CCR
2
1
LDC@(d:16, ERs), CCR
3
1
LDC@(d:24,ERs), CCR
5
1
LDC@ERs+, CCR
2
1
LDC@aa:16, CCR
3
1
1
Internal
Operation
N
2
1
2
1
1
1
2
1
LDC@aa:24, CCR
4
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @ERs, Rd
1
1
MOV.B @(d:16, ERs), Rd
2
1
MOV.B @(d:24, ERs), Rd
4
1
MOV.B @ERs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B @aa:24, Rd
3
1
MOV.B Rs, @Erd
1
1
MOV.B Rs, @(d:16, ERd)
2
1
MOV.B Rs, @(d:24, ERd)
4
1
MOV.B Rs, @-ERd
1
1
MOV.B Rs, @aa:8
1
1
2
2
2
Rev. 3.00 May 15, 2007 Page 467 of 516
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Appendix
Instruction Mnemonic
Instruction
Fetch
I
MOV
MOV.B Rs, @aa:16
2
1
MOV.B Rs, @aa:24
3
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @ERs, Rd
1
1
MOV.W @(d:16,ERs), Rd
2
1
MOV.W @(d:24,ERs), Rd
4
1
MOV.W @ERs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W @aa:24, Rd
3
1
MOV.W Rs, @ERd
1
1
MOV.W Rs, @(d:16,ERd)
2
1
MOV.W Rs, @(d:24,ERd)
4
1
MOV.W Rs, @-ERd
1
1
MOV.W Rs, @aa:16
2
1
MOV.W Rs, @aa:24
3
1
MOV.L #xx:32, ERd
3
MOV.L ERs, ERd
1
MOV.L @ERs, ERd
2
2
MOV.L @(d:16,ERs), ERd
3
2
MOV.L @(d:24,ERs), ERd
5
2
MOV.L @ERs+, ERd
2
2
MOV.L @aa:16, ERd
3
2
MOV.L @aa:24, ERd
4
2
MOV.L ERs,@ERd
2
2
MOV.L ERs, @(d:16,ERd)
3
2
MOV.L ERs, @(d:24,ERd)
5
2
MOV.L ERs, @-ERd
2
2
MOV.L ERs, @aa:16
3
2
MOV.L ERs, @aa:24
4
MOVFPE
MOVFPE @aa:16, Rd*2
2
1
MOVTPE
MOVTPE Rs,@aa:16*2
2
1
Rev. 3.00 May 15, 2007 Page 468 of 516
REJ09B0152-0300
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
Word Data
Access
M
2
Internal
Operation
N
2
2
2
2
Appendix
Instruction Mnemonic
Instruction
Fetch
I
MULXS
MULXU
NEG
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MULXS.B Rs, Rd
2
12
MULXS.W Rs, ERd
2
20
MULXU.B Rs, Rd
1
12
MULXU.W Rs, ERd
1
20
NEG.B Rd
1
NEG.W Rd
1
NEG.L ERd
1
NOP
NOP
1
NOT
NOT.B Rd
1
NOT.W Rd
1
NOT.L ERd
1
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
OR.W #xx:16, Rd
2
OR.W Rs, Rd
1
OR.L #xx:32, ERd
3
OR.L ERs, ERd
2
OR
Branch
Stack
Addr. Read Operation
J
K
ORC
ORC #xx:8, CCR
1
POP
POP.W Rn
1
1
2
POP.L ERn
2
2
2
PUSH
ROTL
ROTR
ROTXL
PUSH.W Rn
1
1
2
PUSH.L ERn
2
2
2
ROTL.B Rd
1
ROTL.W Rd
1
ROTL.L ERd
1
ROTR.B Rd
1
ROTR.W Rd
1
ROTR.L ERd
1
ROTXL.B Rd
1
ROTXL.W Rd
1
ROTXL.L ERd
1
Rev. 3.00 May 15, 2007 Page 469 of 516
REJ09B0152-0300
Appendix
Instruction Mnemonic
Instruction
Fetch
I
ROTXR
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ROTXR.B Rd
1
ROTXR.W Rd
1
ROTXR.L ERd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAL.W Rd
1
SHAL.L ERd
1
SHAR.B Rd
1
SHAR.W Rd
1
SHAR.L ERd
1
SHLL.B Rd
1
SHLL.W Rd
1
SHLL.L ERd
1
SHAR
SHLL
SHLR
SHLR.B Rd
1
SHLR.W Rd
1
SHLR.L ERd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
STC CCR, @ERd
2
1
STC CCR, @(d:16,ERd)
3
1
STC CCR, @(d:24,ERd)
5
1
STC CCR,@-ERd
2
1
STC CCR, @aa:16
3
1
1
SUB
SUBS
STC CCR, @aa:24
4
SUB.B Rs, Rd
1
SUB.W #xx:16, Rd
2
SUB.W Rs, Rd
1
SUB.L #xx:32, ERd
3
SUB.L ERs, ERd
1
SUBS #1/2/4, ERd
1
Rev. 3.00 May 15, 2007 Page 470 of 516
REJ09B0152-0300
2
Appendix
Instruction Mnemonic
Instruction
Fetch
I
SUBX
SUBX #xx:8, Rd
1
SUBX. Rs, Rd
1
TRAPA
TRAPA #xx:2
2
XOR
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC #xx:8, CCR
1
XORC
Branch
Stack
Addr. Read Operation
J
K
1
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
2
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed
n+1 times respectively.
2. It cannot be used in this LSI.
Rev. 3.00 May 15, 2007 Page 471 of 516
REJ09B0152-0300
Appendix
A.4
Combinations of Instructions and Addressing Modes
Table A.5
Combinations of Instructions and Addressing Modes
@@aa:8
—
—
—
—
—
—
—
—
—
WL
MOVFPE,
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL BWL
—
—
—
—
—
—
—
—
—
—
—
WL BWL
—
—
—
—
—
—
—
—
—
—
—
B
BWL BWL
@ERn
Rn
#xx
—
@(d:16.PC)
—
—
BWL BWL BWL BWL BWL BWL
@aa:24
—
—
MOV
@aa:16
—
—
Instructions
@aa:8
@(d:8.PC)
@ERn+/@ERn
@(d:24.ERn)
—
POP, PUSH
Functions
Data
transfer
instructions
@(d:16.ERn)
Addressing Mode
MOVTPE
Arithmetic
operations
ADD, CMP
SUB
ADDX, SUBX
B
B
—
—
—
—
—
—
—
—
—
—
—
ADDS, SUBS
—
L
—
—
—
—
—
—
—
—
—
—
—
INC, DEC
—
BWL
—
—
—
—
—
—
—
—
—
—
—
DAA, DAS
—
B
—
—
—
—
—
—
—
—
—
—
—
MULXU,
—
BW
—
—
—
—
—
—
—
—
—
—
—
NEG
—
BWL
—
—
—
—
—
—
—
—
—
—
—
EXTU, EXTS
—
WL
—
—
—
—
—
—
—
—
—
—
—
AND, OR, XOR
—
BWL
—
—
—
—
—
—
—
—
—
—
—
NOT
—
BWL
—
—
—
—
—
—
—
—
—
—
—
Shift operations
—
BWL
—
—
—
—
—
—
—
—
—
—
—
Bit manipulations
—
B
B
—
—
—
B
—
—
—
—
—
—
BCC, BSR
—
—
—
—
—
—
—
—
—
—
—
—
—
JMP, JSR
—
—
—
—
—
—
—
—
—
—
RTS
—
—
—
—
—
—
—
—
TRAPA
—
—
—
—
—
—
—
—
RTE
—
—
—
—
—
—
—
SLEEP
—
—
—
—
—
—
—
LDC
B
B
W
W
W
W
STC
—
B
W
W
W
ANDC, ORC,
B
—
—
—
—
—
—
—
—
—
MULXS,
DIVXU,
DIVXS
Logical
operations
Branching
instructions
System
control
instructions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
W
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XORC
NOP
Block data transfer instructions
Rev. 3.00 May 15, 2007 Page 472 of 516
REJ09B0152-0300
BW
Appendix
B.
I/O Ports
B.1
I/O Port Block Diagrams
SBY
PUCR12
VCC
PMR15
(IRQAEC)
P12
PDR12
Internal data bus
VCC
VSS
PCR12
AEC module
IRQAEC
PDR1: Port data register 1
PCR1: Port control register 1
PMR1: Port mode register 1
PUCR1: Port pull-up control register 1
ECPWM
AECPWM
Figure B.1 (a) Port 1 Block Diagram (P12)
Rev. 3.00 May 15, 2007 Page 473 of 516
REJ09B0152-0300
Appendix
SBY
PUCR11
VCC
VCC
PMR13
(AEVL)
P11
PFCR
(IRQ1S1,
IRQ1S0)
VSS
Internal data bus
PMR14
(FTCI)
PDR11
PCR11
AEC module
AEVL
Timer W module
FTCI
IRQ1
PDR1: Port data register 1
PCR1: Port control register 1
PMR1: Port mode register 1
PUCR1: Port pull-up control register 1
PFCR : Pin function control register
Figure B.1 (b) Port 1 Block Diagram (P11)
Rev. 3.00 May 15, 2007 Page 474 of 516
REJ09B0152-0300
Appendix
Timer W
SBY
Output
control
signal A
PUCR10
VCC
PMR11
(TMOW)
VCC
PMR10
(AEVH)
P12
Internal data bus
PMR12
(CLKOUT)
PDR10
VSS
PCR10
FTIOA
WATCH
AEC module
AEVH
RTC module
TMOW
PDR1:
PCR1:
PMR1:
PUCR1:
WATCH:
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
Watch mode
CLKOUT
φosc, φosc/2,
φosc/4
Figure B.1 (c) Port 1 Block Diagram (P10)
Rev. 3.00 May 15, 2007 Page 475 of 516
REJ09B0152-0300
Appendix
SBY
PUCR32
VCC
SPCR
(SPC3)
VCC
P32
PDR32
VSS
PCR32
PDR3: Port data register 3
PCR3: Port control register 3
PUCR3: Port pull-up control register 3
SPCR: Serial port control register
Figure B.2 (a) Port 3 Block Diagram (P32)
Rev. 3.00 May 15, 2007 Page 476 of 516
REJ09B0152-0300
Internal data bus
SPCR
(SCINV1)
SCI3 module
TXD3/IrTXD
Appendix
SCI3 module
RE3
RXD3/IrRXD
SBY
PUCR31
VCC
P31
PDR31
VSS
PCR31
PDR3: Port data register 3
PCR3: Port control register 3
PUCR3: Port pull-up control register 3
SPCR: Serial port control register
Internal data bus
VCC
SPCR
(SCINV0)
Figure B.2 (b) Port 3 Block Diagram (P31)
Rev. 3.00 May 15, 2007 Page 477 of 516
REJ09B0152-0300
Appendix
SCI3 module
SBY
SCKIE3
SCKOE3
SCKO3
SCKI3
PUCR30
VCC
PFCR
(IRQ0S1,
IRQ0S0)
VCC
P30
Internal data bus
PMR30
(VCref)
PDR30
VSS
PCR30
Comparator
VCref
IRQ0
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure B.2 (c) Port 3 Block Diagram (P30)
Rev. 3.00 May 15, 2007 Page 478 of 516
REJ09B0152-0300
Appendix
SBY
PUCR8n
Timer W
P8n
PDR8n
Internal data bus
VCC
Output
control
signals
B to D
VSS
PCR8n
FTIOB
to
FTIOD
WATCH
PDR8: Port data register 8
PCR8: Port control register 8
PUCR8: Port pull-up control register 8
WATCH: Watch mode
n = 4 to 2
Figure B.3 (a) Port 8 Block Diagram (P84 to P82)
Rev. 3.00 May 15, 2007 Page 479 of 516
REJ09B0152-0300
Appendix
SBY
PUCR93
SSU
SSI output control
SSI input control
SSI NMOS
open-drain
output control
PODR93
PFCR
(IRQ1S1,
IRQ1S0)
P93
Internal data bus
VCC
PDR93
VSS
PCR93
SSI output
SSI input
IRQ1
PDR9: Port data register 9
PCR9: Port control register 9
PODR9: Port open-drain control register 9
PUCR9: Port pull-up control register 9
Note: When the SSUS bit in PFCR is 1, the SSI pin is
switched to the SCS pin.
Figure B.4 (a) Port 9 Block Diagram (P93)
Rev. 3.00 May 15, 2007 Page 480 of 516
REJ09B0152-0300
Appendix
SBY
PUCR92
SSU
SSO output control
PODR92
PFCR
(IRQ0S1,
IRQ0S0)
P92
Internal data bus
VCC
SSO input control
SSO NMOS
open-drain output
control
PDR92
VSS
PCR92
SSO output
SSO input
IRQ0
PDR9: Port data register 9
PCR9: Port control register 9
PODR9: Port open-drain control register 9
PUCR9: Port pull-up control register 9
Note: When the SSUS bit in PFCR is 1, the SSO pin is
switched to the SSCK pin.
Figure B.4 (b) Port 9 Block Diagram (P92)
Rev. 3.00 May 15, 2007 Page 481 of 516
REJ09B0152-0300
Appendix
SBY
PUCR91
SSU
SSCK output control
PODR91
P91
PDR91
Internal data bus
VCC
SSCK input control
SSCK NMOS
open-drain output
control
VSS
PCR91
SSCK output
SSCK input
IIC2 bus module
ICE
SDAO
VSS
SDAI
PDR9: Port data register 9
PCR9: Port control register 9
PODR9: Port open-drain control register 9
PUCR9: Port pull-up control register 9
Note:Priority: SSU pin > IIC2 pin > P91
When the SSUS bit in PFCR is 1, the SSCK pin is
switched to the SSO pin.
Figure B.4 (c) Port 9 Block Diagram (P91)
Rev. 3.00 May 15, 2007 Page 482 of 516
REJ09B0152-0300
Appendix
SBY
PUCR90
SSU
SCS output control
PODR90
P90
PDR90
Internal data bus
VCC
SCS input control
SCS NMOS
open-drain output
control
VSS
PCR90
SCS output
SCS input
IIC2 bus module
ICE
SCLO
VSS
SCLI
PDR9: Port data register 9
PCR9: Port control register 9
PODR9: Port open-drain control register 9
PUCR9: Port pull-up control register 9
Note: Priority: SSU pin > IIC2 pin > P90
When the SSUS bit in PFCR is 1, the SCS pin is
switched to the SSI pin.
Figure B.4 (d) Port 9 Block Diagram (P90)
Rev. 3.00 May 15, 2007 Page 483 of 516
REJ09B0152-0300
Appendix
Comparator
Internal data bus
COMPm
PBn
A/D module
AMR3 to
AMR0
DEC
Vin
n = 5 or 4
m = 1 or 0
Internal data bus
Figure B.5 (a) Port B Block Diagram (PB5 or PB4)
PBn
A/D module
DEC
AMR3 to
AMR0
Vin
n = 3 or 2
Figure B.5 (b) Port B Block Diagram (PB3 or PB2)
Rev. 3.00 May 15, 2007 Page 484 of 516
REJ09B0152-0300
Appendix
IRQn
PFCR
(IRQnS1,
IRQnS0)
PBn
Internal data bus
PMRBn
A/D module
DEC
AMR3 to
AMR0
Vin
PMRB: Port mode register B
PFCR: Pin function control register
n = 1 or 0
Figure B.5 (c) Port B Block Diagram (PB1 or PB0)
Rev. 3.00 May 15, 2007 Page 485 of 516
REJ09B0152-0300
Appendix
B.2
Port
Port States in Each Operating State
Reset
Sleep
(High-Speed/
MediumSpeed)
Subsleep
Standby
Active
(High-Speed/
MediumWatch
Subactive Speed)
P12 to P10 High
Retained
impedance
Retained
High
Functions
1 2
impedance* *
Functions
Retained
P32 to P30 High
Retained
impedance
Retained
High
Functions
1 2
impedance* *
Functions
Retained
P84 to P82 High
Retained
impedance
Retained
High
Functions
1 2
impedance* *
Functions
Retained
P93 to P90 High
Retained
impedance
Retained
High
Functions
1 2
impedance* *
Functions
Retained
PB5 to
PB0
High
High
1
impedance impedance*
High
High
impedance impedance
High
High
impedance impedance
Notes: 1. Registers are retained and output level is high impedance.
2. High-level output when the pull-up MOS is turned on.
Rev. 3.00 May 15, 2007 Page 486 of 516
REJ09B0152-0300
High
impedance
Appendix
B.3
Port 9 Related Register Settings and Pin Functions
Table B.1
Port 9 Related Register Settings and Pin Functions
SSU Setting
PFCR Setting
IIC2
Setting
IRQ1S1,
IRQ0S1,
SSUMS
BIDE
MSS
TE
RE
ICE
SSUS
IRQ1S0
IRQ0S0
0
*
0
0
1
0
0
Other then Other
(Receive)
(IIC2 not
(Clock
(Slave)
synchro-
01
used)
P91
P90
SSI input P92 I/O
P93
SSCK
P90 I/O
SSI input IRQ0N
SSCK
input
01
1
1
0
0
0
(IIC2 not
(Transmit)
used)
1
1
1
0
(Transmit)
(Receive)
(IIC2 not
used)
0
Other then Other
P93 I/O
input
SSCK
P91 I/O
SSI input
P91 I/O
SSI input
P90 I/O
then 01
01
Other
IRQ1N
SSCK
then 01
input
input
P93 I/O
SSO
SSCK
output
input
Other then Other
input
01
then 01
01
Other
IRQ1N
SSO
SSCK
then 01
input
output
input
P93 I/O
SSCK
SSO
input
output
Other then Other
01
then 01
01
Other
IRQ1N
SSCK
SSO
then 01
input
input
output
SSI input SSO
SSCK
Other then Other
then 01
Other then Other
P90 I/O
input
01
01
1
P92
then 01
Other then 01
nous)
Pin Functions
P93 I/O
output
input
SSCK
SSO
input
output
01
then 01
01
Other
IRQ1N
SSCK
SSO
then 01
input
input
output
P90 I/O
P90 I/O
P90 I/O
P90 I/O
SSI input
SSI input
Rev. 3.00 May 15, 2007 Page 487 of 516
REJ09B0152-0300
Appendix
SSU Setting
PFCR Setting
IIC2 Setting
IRQ1S1,
IRQ0S1,
SSUMS
BIDE
MSS
TE
RE
ICE
SSUS
IRQ1S0
IRQ0S0
0
*
1
0
1
0
0
Other then Other
(Receive)
(IIC2 not
(Clock
(Master)
synchro-
01
used)
1
0
0
0
(IIC2 not
(Transmit)
used)
1
1
1
0
(Transmit)
(Receive)
(IIC2 not
used)
Rev. 3.00 May 15, 2007 Page 488 of 516
0
Other then Other
P91
P90
SSCK
P90 I/O
output
P93 I/O
SSCK
output
SSCK
P91 I/O
SSI input
P91 I/O
SSI input
P90 I/O
then 01
01
Other
IRQ1N
SSCK
then 01
input
output
P93 I/O
SSO
SSCK
output
output
Other then Other
output
01
then 01
01
Other
IRQ1N
SSO
SSCK
then 01
input
output
output
P93 I/O
SSCK
SSO
output
output
Other then Other
01
then 01
01
Other
IRQ1N
SSCK
SSO
then 01
input
output
output
Other then Other
SSI input SSO
then 01
Other then Other
P90 I/O
input
01
01
1
P92
SSI input IRQ0N
01
1
REJ09B0152-0300
P93
SSI input P92 I/O
then 01
Other then 01
nous)
Pin Functions
P93 I/O
SSCK
output
output
SSCK
SSO
output
output
01
then 01
01
Other
IRQ1N
SSCK
SSO
then 01
input
output
output
P90 I/O
P90 I/O
P90 I/O
P90 I/O
SSI input
SSI input
Appendix
SSU Setting
PFCR Setting
IIC2
Setting
Pin Functions
IRQ1S1,
IRQ0S1,
SSUMS
BIDE
MSS
TE
RE
ICE
SSUS
IRQ1S0
IRQ0S0
P93
1 (Four-line
0
0
0
1
0
0
Other
Other
P93 I/O SSO
(Receive)
(IIC2 not
bus commu- (One-way)
(Slave)
nication)
used)
1
1
0
0
0
(IIC2 not
(Transmit)
used)
1
1
0
(Transmit)
(Receive)
(IIC2 not
used)
1
0
(Master)
1
0
(Receive)
(IIC2 not
0
1
0
used)
1
0
0
0
(IIC2 not
(Transmit)
used)
1
1
1
0
(Transmit)
(Receive)
(IIC2 not
used)
0
1
P90
SCS
then 01
input
input
input
01
Other
IRQ1N
SSO
SSCK
SCS
then 01
input
input
input
input
Other
Other
SCS
SSCK
SSO
P90 I/O
then 01
then 01
input
input
input
Other
Other
SSI
P92 I/O SSCK
then 01
then 01
output
Other
01
SSI
SCS
input
input
IRQ0N
SSCK
SCS
output
input
input
input
P91 I/O SSI
Other
Other
SCS
SSCK
then 01
then 01
input
input
Other
Other
SSI
SSO
SSCK
SCS
then 01
then 01
output
input
input
input
Other
Other
SCS
SSCK
SSO
SSI
then 01
then 01
input
input
input
output
Other
Other
SSI
P92 I/O SSCK
then 01
then 01
input
Other
01
SSI
then 01
1
P91
SSCK
then 01
then 01
1
P92
output
SCS
output
output
IRQ0N
SSCK
SCS
input
input
output
output
P91 I/O SSI
Other
Other
SCS
SSCK
then 01
then 01
output
output
Other
Other
P93 I/O SSO
then 01
then 01
01
Other
input
SSCK
SCS
output
output
output
IRQ1N
SSO
SSCK
SCS
then 01
input
output
output
output
Other
Other
SCS
SSCK
SSO
P90 I/O
then 01
then 01
output
output
output
Other
Other
SSI
SSO
SSCK
SCS
then 01
then 01
input
output
output
output
Other
Other
SCS
SSCK
SSO
SSI
then 01
then 01
output
output
output
input
Rev. 3.00 May 15, 2007 Page 489 of 516
REJ09B0152-0300
Appendix
SSU Setting
IIC2
PFCR Setting
Setting
ICE
SSUMS
BIDE
MSS
TE
RE
1 (Four-line
1
0
0
1
0
(Receive)
(IIC2 not
bus commu- (Bidirecnication)
(Slave)
tional)
IRQ1S1,
IRQ1S0
IRQ0S0
P93
0
Other
Other
P93 I/O SSO
1
0
0
0
(IIC2 not
(Transmit)
used)
1
1
0
(Master)
1
0
(Receive)
(IIC2 not
0
used)
1
1
0
0
0
(IIC2 not
(Transmit)
used)
1
0
0
0
0
0
1
(SSU not
(IIC2
used)
used)
IRQ0S1,
SSUS
used)
1
Pin Functions
*
then 01
input
input
input
Other
IRQ1N
SSO
SSCK
SCS
then 01
input
input
input
input
Other
Other
SCS
SSCK
SSO
P90 I/O
then 01
then 01
input
input
input
Other
Other
P93 I/O SSO
then 01
then 01
01
Other
SSCK
SCS
output
input
input
IRQ1N
SSO
SSCK
SCS
then 01
input
output
input
input
Other
Other
SCS
SSCK
SSO
P90 I/O
then 01
then 01
input
input
output
Other
Other
P93 I/O SSO
SSCK
SCS
then 01
then 01
input
output
output
01
Other
IRQ1N
SSO
SSCK
SCS
then 01
input
input
output
output
Other
Other
SCS
SSCK
SSO
P90 I/O
then 01
then 01
output
output
input
Other
Other
P93 I/O SSO
then 01
then 01
01
Other
SSCK
SCS
output
output
output
IRQ1N
SSO
SSCK
SCS
then 01
input
output
output
output
Other
Other
SCS
SSCK
SSO
P90 I/O
then 01
then 01
output
output
output
Other
Other
P93 I/O P92 I/O SDA I/O SCL I/O
then 01
then 01
Other
01
01
used)
*
P93 I/O IRQ0N
Other
IRQ1N
then 01
input
01
IRQ1N
IRQ0N
input
input
Other
Other
then 01
then 01
Other
01
01
01
*: Don't care.
Rev. 3.00 May 15, 2007 Page 490 of 516
REJ09B0152-0300
SDA I/O SCL I/O
input
P92 I/O SDA I/O SCL I/O
SDA I/O SCL I/O
P93 I/O P92 I/O P91 I/O P90 I/O
P93 I/O IRQ0N
then 01
[Legend]
P90
SCS
01
01
(IIC2 not
P91
SSCK
then 01
then 01
0
P92
P91 I/O P90 I/O
input
Other
IRQ1N
then 01
input
P92 I/O P91 I/O P90 I/O
01
IRQ1N
IRQ0N
input
input
P91 I/O P90 I/O
Appendix
C.
Product Part No. Lineup
Product Part No.
Package
(Package
Model Marking Code)
Flash memory (10 MHz)
version
(4 MHz)
HD64F38602RFT10
38602R10
HD64F38602RFT4
38602R4
(10 MHz)
HD64F38602RFH10
F38602RFH10
(4 MHz)
HD64F38602RFH4
F38602RFH4
HD64338602RFT
38602R(***)
32-pin QFN
(TNP-32)
HD64338602RFH
38602R(***)
32-pin LQFP
(32P6U-A)
HD64338600RFT
38600R(***)
32-pin QFN
(TNP-32)
HD64338600RFH
38600R(***)
32-pin LQFP
(32P6U-A)
Product Classification
H8/38602R
Group
H8/38602R
Masked ROM version
H8/38600R
Masked ROM version
32-pin QFN
(TNP-32)
32-pin LQFP
(32P6U-A)
[Legend]
(***): ROM code
Rev. 3.00 May 15, 2007 Page 491 of 516
REJ09B0152-0300
Figure D.1 Package Dimensions (TNP-32)
32
26
x4
y
y1
t
D
9 Z
D
17
10
16
TNP-32/TNP-32V
Previous Code
b
b1
×M
MASS[Typ.]
0.06g
Note: Don't connect the exposed part of die-pad-support-leads to the pads on a
printed wiring board (PWB).
1
25
HD
RENESAS Code
PVQN0032KA-A
HE
E
c
c1
ZE
P-VQFN32-5x6-0.50
A
REJ09B0152-0300
A2
Rev. 3.00 May 15, 2007 Page 492 of 516
A1
5.0
0.17
c
0.20
1.0
0.22
ZE
c1
5.2
1.0
HE
ZD
0.25
0.20
t
6.2
y1
HD
0.05
0.20
y
0.05
0.70
0.27
x
0.5
0.60
Lp
0.50
e
0.20
0.22
0.17
b
b1
0.95
0.04
A1
0.02
0.005
A
0.89
E
A2
6.0
D
Reference Dimension in Millimeters
Symbol
Min
Nom
Max
D.
e
Lp
JEITA Package Code
Appendix
Package Dimensions
The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have
priority.
32
25
ZD
1
24
e
D
HD
Index mark
*1
y
8
17
*3
bp
9
16
Previous Code
32P6U-A
x
E
F
*2
ZE
RENESAS Code
PLQP0032GB-A
MASS[Typ.]
0.2g
b1
bp
c1
Detail F
Terminal cross section
A2
A1
JEITA Package Code
P-LQFP32-7x7-0.80
L1
L
e
x
y
ZD
ZE
L
L1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
Reference Dimension in Millimeters
Symbol
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Appendix
Figure D.2 Package Dimensions (32P6U-A)
Rev. 3.00 May 15, 2007 Page 493 of 516
REJ09B0152-0300
c
c
A
HE
Appendix
Rev. 3.00 May 15, 2007 Page 494 of 516
REJ09B0152-0300
Main Revisions and Additions in this Edition
Item
Page Revisions (See Manual for Details)
Section 1 Overview
1
The description on the package, P-LQFP-32, is added.
36
Modified
1.1 Features
•
Compact package
Section 2 CPU
2.8.2 EEPMOV Instruction
Section 3 Exception Handling
EEPMOV is a block-transfer instruction and transfers
the byte size of data indicated by R4 or R4L, which
starts from the address indicated by R5, to the address
indicated by R6. Set R4, R4L, and R6 so that the end
address of the destination address (value of R6 + R4L
or R6 + R4) does not exceed H'FFFF (the value of R6
must not change from H'FFFF to H'0000 during
execution).
44
3.2 Reset
Modified
A reset has the highest exception priority.
There are three sources to generate a reset. Table 3.2
lists the reset sources.
Table 3.2 Reset Sources
44
Added
3.2.1 Reset Exception Handling
44
The description in this section is modified.
3.8.1 Notes on Stack Area Use
58
Modified
……, so the stack pointer (SP: R7) should never
indicate an odd address. To save register values, use
PUSH.W Rn (MOV.W Rn, @–SP) or PUSH.L ERn
(MOV.L ERn, @–SP). To restore register values, use
POP.W Rn (MOV.W @SP+, Rn) or POP.L ERn
(MOV.L @SP+, ERn).
Rev. 3.00 May 15, 2007 Page 495 of 516
REJ09B0152-0300
Item
Page Revisions (See Manual for Details)
Section 4 Clock Pulse Generators 67
Modified
4.2.4 On-Chip Oscillator Selection
Method
…… The input level on the E7_2 pin during a reset is
pulled up or down using a resistor according to the
selected oscillator, and fixed on exit from the reset
state.
When the on-chip oscillator is selected, a resonator no
longer needs to be connected to the OSC1 and OSC2
pins. In such a case, fix the OSC1 pin to GND or leave
it open, and leave the OSC2 pin open.
Note is added.
Notes:
1. ……
2. When the on-chip debugger is connected, the value
of the resistor should be high. When not connected,
it is specified according to the selected oscillator.
Figure 4.5 Typical Connection to
32.768-kHz/38.4-kHz Crystal
Resonator
68
Modified
Frequency
Manufacturer
Products Name Equivalent Series Resistance
38.4 kHz
EPSON TOYOCOM CORPORATION
C-4-TYPE
30 kΩ (max.)
C-001R
35 kΩ (max.)
32.768 kHz EPSON TOYOCOM CORPORATION
C 1 = C 2 = 7 pF (typ.)
Note: Consult with the crystal resonator manufacturer to determine the parameters.
4.3.1 Connecting 32.768kHz/38.4-kHz Crystal Resonator
68
Added
1. When the resonator other than ones listed above is
used, perform matching evaluation with the crystal
resonator manufacture and connect it under the
optimum condition. Even when the resonator listed
above or the equivalent is used, as the oscillation
characteristics depend on the board specification,
perform matching evaluation on the mounting board.
2. Perform matching evaluation in the reset state (the
RES pin is low) and on exit from the reset state (the
RES pin is driven from low to high).
4.4.1 Prescaler S
71
Deleted
The output from prescaler S is shared by the on-chip
peripheral modules. The division ratio can be set
separately for each on-chip peripheral function.
Rev. 3.00 May 15, 2007 Page 496 of 516
REJ09B0152-0300
Item
Page Revisions (See Manual for Details)
4.5.1 Note on Resonators and
Resonator Circuits
72
4.5.3 Definition of Oscillation
Stabilization Wait Time
74
The description in this section is modified.
Figure 4.12 Oscillation
Stabilization Wait Time
75
Modified
Modified
Resonator characteristics are closely related to board
design. Therefore, resonators should be assigned after
being carefully evaluated by the user in the masked
ROM version and flash memory version, with referring
to the examples shown in this section.
Oscillation waveform
(OSC2)
System clock (φ)
Oscillation
start time
Wait time
Operating mode
Standby mode,
watch mode,
or subactive
mode
Oscillation stabilization wait time
Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
4.5.5 Note on the Oscillation
Stabilization of Resonators
76
4.5.6 Note on Using Power-On
Reset
76
Section 5 Power-Down Modes
81
The note is modified.
Notes:
3. … When the watchdog timer stops operating and the
WDON bit is cleared to 0 by software, this bit is valid
and the watchdog timer enters module standby mode.
CKSTPR2
Table 5.3 Internal State in Each
Operating Mode
Modified
The power-on reset circuit in this LSI adjusts the reset
clear time by the capacitor capacitance, which is
externally connected to the RES pin. The external
capacitor capacitance should be adjusted to secure the
oscillation stabilization time before reset clearing. For
details, refer to section 19, Power-On Reset Circuit.
5.1.3 Clock Halt Registers 1 and
2 (CKSTPR1 and CKSTPR2)
•
The title modified
86
The note is modified.
Notes:
6. Functions if the 32.768-kHz RTC is selected as an
internal clock. Halted and retained otherwise.
Rev. 3.00 May 15, 2007 Page 497 of 516
REJ09B0152-0300
Item
Page Revisions (See Manual for Details)
5.2.2 Standby Mode
88
Modified
… However, as long as the rated voltage is supplied,
the contents of CPU registers, on-chip RAM, and some
on-chip peripheral module registers are retained. …
Modified
… or the requested interrupt is disabled by the interrupt
enable bit.
When a reset source is generated in standby mode, the
system clock oscillator starts. If a reset is generated by
the RES pin, it must be kept low until the system clock
oscillator output stabilizes and the tREL period has
elapsed. The CPU starts reset exception handling
when the RES pin is driven high.
5.2.3 Watch Mode
88
Modified
… or the requested interrupt is disabled by the interrupt
enable register.
When a reset source is generated in watch mode, the
system clock oscillator starts. If a reset is generated by
the RES pin, it must be kept low until the system clock
oscillator output stabilizes. The CPU starts reset
exception handling when the RES pin is driven high.
5.2.4 Subsleep Mode
89
Modified
… or the requested interrupt is disabled by the interrupt
enable register.
When a reset source is generated in subsleep mode,
the system clock oscillator starts. If a reset is generated
by the RES pin, it must be kept low until the system
clock oscillator output stabilizes. The CPU starts reset
exception handling when the RES pin is driven high.
5.2.5 Subactive Mode
89
Modified
… on the combination of bits SSBY, LSON, and TMA3
in SYSCR1 and bits MSON and DTON in SYSCR2.
Subactive mode is not cleared if the I bit in CCR is set
to 1 or the requested interrupt is disabled by the
interrupt enable register.
When a reset source is generated in subactive mode,
the system clock oscillator starts. If a reset is generated
by the RES pin, it must be kept low until the system
clock oscillator output stabilizes and the tREL period has
elapsed. The CPU starts reset exception handling
when the RES pin is driven high.
Rev. 3.00 May 15, 2007 Page 498 of 516
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Item
Page Revisions (See Manual for Details)
5.2.6 Active (Medium-Speed)
Mode
90
Modified
In active (medium-speed) mode, the clock set by the
MA1 and MA0 bits in SYSCR1 is used as the system
clock, and the CPU and on-chip peripheral modules
function.
Active (medium-speed) mode is cleared by the SLEEP
instruction. When active (medium-speed) mode is
cleared, a transition to standby mode is made
depending on the combination of bits SSBY, LSON,
and TMA3 in SYSCR1, a transition to watch mode is
made depending on the combination of bits SSBY and
TMA3 in SYSCR1, or a transition to sleep mode is
made depending on the combination of bits SSBY and
LSON in SYSCR1. Moreover, a transition to active
(high-speed) mode or subactive mode is made by a
direct transition. Active (medium-sleep) mode is not
entered if the I bit in CCR is set to 1 or the requested
interrupt is disabled in the interrupt enable register.
When the RES pin goes low, the CPU goes into the
reset state and active (medium-sleep) mode is cleared.
In active (medium-speed) mode, the on-chip peripheral
modules function at the clock set by the MA1 and MA0
bits in SYSCR1.
5.3 Direct Transition
91
5.3.1 Direct Transition from Active 91
(High-Speed) Mode to Active
(Medium-Speed) Mode
The description in this section is modified.
Added
When a SLEEP instruction is executed in active (highspeed) mode while the SSBY and LSON bits in
SYSCR1 are cleared to 0 and the MSON and DTON
bits in SYSCR2 are set to 1, a transition is made to
active (medium-speed) mode via sleep mode.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (1).
Example: When φosc/8 is selected as the CPU
operating clock after the transition
Direct transition time = (2 + 1) × 1tosc + 14 × 8tosc =
115tosc
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 499 of 516
REJ09B0152-0300
Item
Page Revisions (See Manual for Details)
5.3.2 Direct Transition from Active 92
(High-Speed) Mode to Subactive
Mode
Added
When a SLEEP instruction is executed in active (highspeed) mode while the SSBY, TMA3, and LSON bits in
SYSCR1 are set to 1 and the DTON bit in SYSCR2 is
set to 1, a transition is made to subactive mode via
watch mode.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (2).
Example: When φw/8 is selected as the subactive
operating clock after the transition
Direct transition time = (2 + 1) × 1tosc + 14 × 8tw =
3tosc + 112tw
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
5.3.3 Direct Transition from Active 92
(Medium-Speed) Mode to Active
(High-Speed) Mode
Added
When a SLEEP instruction is executed in active
(medium-speed) mode while the SSBY and LSON bits
in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is cleared to 0, and the DTON bit in SYSCR2 is set to
1, a transition is made to active (high-speed) mode via
sleep mode.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (3).
Example: When φosc/8 is selected as the CPU
operating clock before the transition
Direct transition time = (2 + 1) × 8tosc + 14 × 1tosc =
38tosc
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 500 of 516
REJ09B0152-0300
Item
Page Revisions (See Manual for Details)
5.3.4 Direct Transition from Active 93
(Medium-Speed) Mode to
Subactive Mode
Added
When a SLEEP instruction is executed in active
(medium-speed) mode while the SSBY, LSON, and
TMA3 bits in SYSCR1 are set to 1 and the DTON bit in
SYSCR2 is set to 1, a transition is made to subactive
mode via watch mode.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (4).
Example: When φosc/8 and φw/8 are selected as the
CPU operating clock before and after the transition,
respectively
Direct transition time = (2 + 1) × 8tosc + 14 × 8tw =
24tosc + 112tw
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
5.3.5 Direct Transition from
Subactive Mode to Active (HighSpeed) Mode
93
Added and modified
When a SLEEP instruction is executed in subactive
mode while the SSBY and TMA3 bits in SYSCR1 are
set to 1, the LSON bit in SYSCR1 is cleared to 0, the
MSON bit in SYSCR2 is cleared to 0, and the DTON bit
in SYSCR2 is set to 1, a transition is made directly to
active (high-speed) mode via watch mode after the
waiting time set in bits STS2 to STS0 in SYSCR1 has
elapsed.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (5).
Direct transition time = {(Number of SLEEP instruction
execution states) + (Number of internal processing
states)} × (tsubcyc before transition) + (Wait time set in
bits STS2 to STS0) + (Number of interrupt exception
handling execution states) × (tcyc after transition)…..(5)
Example: When φw/8 is selected as the CPU
operating clock after the transition and wait time =
8192 states
Direct transition time = (2 + 1) × 8tw + (8192 + 14)
×1tosc = 24tw + 8206tosc
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 501 of 516
REJ09B0152-0300
Item
Page Revisions (See Manual for Details)
5.3.6 Direct Transition from
Subactive Mode to Active
(Medium-Speed) Mode
94
Added
When a SLEEP instruction is executed in subactive
mode while the SSBY and TMA3 bits in SYSCR1 are
set to 1, the LSON bit in SYSCR1 is cleared to 0, and
the MSON and DTON bits in SYSCR2 are set to 1, a
transition is made directly to active (medium-speed)
mode via watch mode after the waiting time set in bits
STS2 to STS0 in SYSCR1 has elapsed.
The time from the start of SLEEP instruction execution
to the end of interrupt exception handling (the direct
transition time) is calculated by equation (6).
Example: When φw/8 and φosc/8 are selected as the
CPU operating clock before and after the transition,
respectively, and wait time = 8192 states
Direct transition time = (2 + 1) × 8tw + 8192 × 1tosc +
14 × 8tosc = 24tw + 8304tosc
For the legend of symbols used above, refer to
section 21, Electrical Characteristics.
Section 6 ROM
117
Modified
… Then the flash memory should be set to enter the
module standby mode.
6.7 Notes on Setting Module
Standby Mode
If an interrupt is generated in module standby mode,
the vector address cannot be fetched. As a result, the
program may run away.
Section 8 I/O Ports
122
•
P10/AEVH/FTIOA/TMOW/CL
KOUT pin
8.7.2 Input Characteristics
Difference due to Pin Function
124
Rev. 3.00 May 15, 2007 Page 502 of 516
REJ09B0152-0300
Added
Note: * Switching the clock (φOSC, φOSC/2, or φOSC/4) for
CLKOUT output must be performed when
CLKOUT output is halted (CLKOUT = 0).
When making a transition to a power-down
mode wherein the system clock oscillator is
halted, the output level is retained. (In standby
mode, output is the high-impedance state.)
When making a transition from a power-down
mode wherein the system clock oscillator is
halted, to the active mode wherein the system
clock oscillator operates, halt CLKOUT output
(CLKOUT = 0) before the transition.
8.1.5 Pin Functions
This section is newly added.
Item
Page Revisions (See Manual for Details)
Section 9 Timer B1
148
Modified
Figure 9.2 Timer B1 Initial Setting
Flow
Cancel the module standby mode of timer B1
*1
Set counter function with bit TMB17
in TMB1 and counter clock with bits
TMB12 to TMB10 in TMB1
(bit TMB16 must be cleared to 0
when writing to these bits)
Section 11 Realtime Clock (RTC) 193
11.3.7 Clock Source Select
Register (RTCCSR)
Modified
Bit Bit Name Description
3
RCS3
Clock Source Selection
2
RCS2
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1
0
RCS1
RCS0
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1000: φW/4⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ RTC operation
1001 to 1111: Setting prohibited
11.4.1 Initial Settings of Registers 196
after Power-On
11.5 Interrupt Sources
198
Modified
The RTC registers that store second, minute, hour, and
day-of-week data, control registers, and interrupt
registers are not reset by a RES input, or by a reset
source caused by a watchdog timer.
Modified
… When using an interrupt, set the IENRTC (RTC
interrupt request enable) bit in IENR1 to 1 last after
other registers are set.
11.6.2 Note when Using RTC
Interrupts
199
Added
Rev. 3.00 May 15, 2007 Page 503 of 516
REJ09B0152-0300
Item
Page Revisions (See Manual for Details)
Section 12 Watchdog Timer
203
12.2.1 Timer Control/Status
Register WD1 (TCSRWD1)
Added
Bit Bit Name Description
0
WRST
Watchdog Timer Reset
Indicates whether a reset caused by the watchdog
timer is generated. This bit is not cleared by a reset
caused by the watchdog timer.
[Setting condition]
When TCWD overflows and an internal reset signal
is generated
12.3.1 Watchdog Timer Mode
208
Modified
… When a clock pulse is input after the TCWD count
value has reached H'FF, the watchdog timer overflows
and an internal reset signal is generated. The internal
reset signal is output for a period of 512 clock cycles by
the on-chip oscillator (ROSC).
Figure 12.2 Example of Watchdog 208
Timer Operation
Modified
TCWD overflow
H'FF
H'F1
TCWD
count value
H'00
Start
H'F1 written
to TCWD
H'F1 written to TCWD
Reset generated
Internal reset
signal
512 clock cycles by Rosc
Figure 12.3 Interval Timer Mode
Operation
209
Modified
H'FF
TCWD
count value
Time
H'00
WT/IT = 1
12.5.3 Clearing the WT/IT or
IEOVF Bit in TCSRWD2 to 0
210
Added
Table 12.1 Assembly Program for 211
Clearing WT/IT or IEOVF Bit to 0
Added
Rev. 3.00 May 15, 2007 Page 504 of 516
REJ09B0152-0300
Interval timer
Interval timer
Interval timer
Interval timer
Interval timer
interrupt
interrupt
interrupt
interrupt
interrupt
request generated request generated request generated request generated request generated
Item
Page Revisions (See Manual for Details)
Table 12.2 The Value of "xx"
211
Added
Section 13 Asynchronous Event
Counter (AEC)
222
Modified
13.3.6 Event Counter H (ECH)
13.3.7 Event Counter L (ECL)
222
Section 14 Serial Communication 231
Interface 3 (SCI3, IrDA)
14.3.5 Serial Mode Register
(SMR)
235
Bit
Bit Name Description
7
ECH7
Either the external asynchronous event AEVH pin,
6
ECH6
φ/2, φ/4, or φ/8, or the overflow signal from lower 8-
5
ECH5
bit counter ECL can be selected as the input clock
4
ECH4
3
ECH3
2
ECH2
1
ECH1
0
ECH0
source. ECH can be cleared to H'00 when the
CRCH bit in ECCSR is cleared to 0.
Modified
Bit
Bit Name Description
7
ECL7
Either the external asynchronous event AEVL pin,
6
ECL6
φ/2, φ/4, or φ/8 can be selected as the input clock
5
ECL5
source. ECL can be cleared to H'00 when the
4
ECL4
3
ECL3
2
ECL2
1
ECL1
0
ECL0
CRCL bit in ECCSR is cleared to 0.
Deleted
The serial communication interface 3 (SCI3) can handle
both asynchronous and clock synchronous serial
communication. In the asynchronous method, serial
data communication can be carried out using standard
asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an
Asynchronous Communication Interface Adapter
(ACIA). A function is also provided for serial
communication between processors (multiprocessor
communication function).
Modified
Bit
Bit Name Description
2
MP
5-Bit CommunicationWhen this bit is set to 1, the
5-bit communication format is enabled. Make sure
to set bit 5 (PF) to 1 when setting this bit (MP) to 1.
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Item
Page Revisions (See Manual for Details)
14.3.6 Serial Control Register
(SCR)
237
Bit 3 is reserved.
14.3.7 Serial Status Register
(SSR)
240
Deleted
14.3.10 IrDA Control Register
(IrCR)
SSR consists of status flags of the SCI3 and
multiprocessor bits for transfer. 1 cannot be written to
flags TDRE, RDRF, OER, PER, and FER; they can only
be cleared.
240
Bits 1 and 0 are reserved.
252
Modified
Bit
Bit Name Description
7
IrE
IrDA EnableSelects whether the SCI3 I/O pins
function as the SCI3 or IrDA.0: TXD3/IrTXD and
RXD3/IrRXD pins function as TXD3 and RXD31:
TXD3/IrTXD and RXD3/IrRXD pins function as
IrTXD and IrRXD
14.3.11 Serial Extended Mode
Register (SEMR)
253
Added
Bit
Bit Name Description
3
ABCS
Asynchronous Mode Basic Clock Select
Selects the basic clock for the bit period in
asynchronous mode.
This setting is enabled only in asynchronous mode
(COM bit in SMR3 is 0).
0: Operates on a basic clock with a frequency of
16 times the transfer rate
1: Operates on a basic clock with a frequency of
eight times the transfer rate
Clear the ABCS bit to 0, when the IrDA function is
enabled.
Table 14.8 Data Transfer Formats 255
(Asynchronous Mode)
The formats are modified.
Table 14.9 SMR Settings and
Corresponding Data Transfer
Formats
The settings are modified.
256
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Item
Page Revisions (See Manual for Details)
Figure 14.4 Sample SCI3
Initialization Flowchart
258
Modified
Wait
No
[[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR to 1. Setting bits
TE and RE enables the TXD3 and RXD3
pins to be used. Also set the RIE, TIE,
and TEIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
transmission and idled at reception to
wait for the start bit.
1-bit interval elapsed?
Yes
Set SPC3 bit in SPCR to 1
Set TE and RE bits in
SCR to 1, and set RIE, TIE
and TEIE bits.
[4]
<Initialization completion>
Figure 14.6 Sample Serial
Transmission Flowchart
(Asynchronous Mode)
260
Modified
No
[3]
Break output?
Yes
[3]
Clear PDR to 0 and set PCR to 1
Clear SPC3 bit in SPCR and
TE bit in SCR to 0*
<End>
14.5 Operation in Clock
Synchronous Mode
264
14.6 Multiprocessor
Communication Function
270
To output a break in serial transmission,
after setting PCR to 1 and PDR to 0,
clear the SPC3 bit in SPCR and the TE
bit in SCR to 0.
Note: * When the SPC3 bit in SPCR is cleared to 0,
the pin functions as an I/O port.
Deleted
… After 8-bit data is output, the transmission line holds
the MSB state. In clock synchronous mode, no parity or
multiprocessor bit is added.
This section is deleted.
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Item
Page Revisions (See Manual for Details)
14.8.2 Mark State and Break
Sending
277
Section 16 I2C Bus Interface 2
(IIC2)
323
Modified
When the SPC3 bit in SPCR is 0, the TXD3 pin
functions as an I/O port whose direction (input or
output) and level are determined by PCR and PDR,
regardless of the TE setting. This can be used to set the
TXD3 pin to the mark state (high level) or send a break
during data transmission. To maintain the
communication line at the mark state until the SPC3 bit
in SPCR is set to 1, set both PCR and PDR to 1. As the
SPC3 bit in SPCR is cleared to 0 at this point, the TXD3
pin functions as an I/O port, and 1 is output from the
TXD3 pin. To send a break during data transmission,
first set PCR to 1 and PDR to 0, and then clear the
SPC3 and TE bits to 0. When the TE bit is cleared to 0
directly after the SPC3 bit is cleared to 0, the transmitter
is initialized regardless of the current transmission state
after the TE bit is cleared, the TXD3 pin functions as an
I/O port after the SPC3 bit is cleared, and 0 is output
from the TXD3 pin.
16.3.5 I2C Bus Status Register
(ICSR)
Modified
Bit
Bit Name
3
STOP
Description
Stop Condition Detection Flag[Setting
conditions]
•
In master mode, when a stop condition
is detected after the completion of
frame transfer
•
In slave mode, when a stop condition is
detected, after the slave address of the
first byte, following the general call and
the detection of the start condition,
matches the address set in SAR
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Item
Page Revisions (See Manual for Details)
Figure 16.15 Receive Mode
Operation Timing
339
Modified
SCL
7
8
1
2
SDA
(Input)
Bit 6
Bit 7
Bit 0
Bit 1
MST
TRS
RDRF
ICDRS
Data 2
ICDRR
Data 1
User
processing
Section 17 A/D Converter
350
17.3.1 A/D Result Register
(ADRR)
17.7.3 Usage Notes
Data 3
Data 2
[3]Read ICDRR
Modified
ADRR is a 16-bit read-only register that stores the
results of A/D conversion. The data is stored in the
upper 10 bits of ADRR. ADRR can be read by the CPU
at any time, …
360
Deleted
3. When A/D conversion is started after clearing module
standby mode, wait for 10φ clock cycles before
starting A/D conversion.
4. When the LADS bit in ADSR is changed as from
halting to operating, wait for 10φ clock cycles before
starting A/D conversion.
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Item
Page Revisions (See Manual for Details)
Section 18 Comparators
368
4. If the LSI enters the software standby mode or watch
mode when a comparator is operating, the internal
operation of the comparator is maintained. Since the
comparator operates even in software standby mode
or watch mode, it returns to the same mode after the
specified interrupt is canceled, though the current for
the comparator is consumed.
If a comparator is not required to return to the
software standby mode or watch mode when an
interrupt is canceled and the current consumption
needs to be reduced, stop the comparator by clearing
the CME0 and CME1 bits in CMCR0 and CMCR1 to
0 before shifting the mode.
18.5 Usage Notes
Section 19 Power-On Reset
Circuit
370
Modified
The operation timing of the power-on reset circuit is
shown in figure 19.2. As the power supply voltage rises,
the capacitor, which is externally connected to the RES
pin, is gradually charged through the on-chip pull-up
resistor (Rp).
19.2.1 Power-On Reset Circuit
Section 21 Electrical
Characteristics
Modified
411
Modified
Item Symbol Applicable Test Condition
Table 21.3 Control Signal Timing
Pins
Oscill
ation
stabili
zation
trc
Values
Min. Typ. Max.
OSC1,OSC2 Ceramic resonator
—
20
45
—
80
—
—
300
800
—
600
1000
(VCC = 2.2 V to 3.6 V)
Ceramic resonator
(Other than above)
time
Crystal resonator
(VCC = 2.7 V to 3.6 V)
Crystal resonator
(VCC = 2.2 V to 3.6 V)
Rev. 3.00 May 15, 2007 Page 510 of 516
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Item
Page Revisions (See Manual for Details)
Table 21.14 Control Signal Timing 425
Modified
Item Symbol Applicable Test Condition
Pins
Oscill
trc
Values
Min. Typ. Max.
OSC1,OSC2 Ceramic resonator(VCC —
ation
20
45
80
—
300
800
600
1000
= 2.2 V to 3.6 V)
stabili
Ceramic
zation
—
resonator(Other than
time
above)
Crystal resonator(VCC = —
2.7 V to 3.6 V)
Crystal resonator(VCC = —
2.2 V to 3.6 V)
Modified
Condition Code
I
H
N
Z
V
C
—
*
↔
*
↔
Rd8 decimal adjust
↔
—
@@aa
@(d, PC)
2
No. of
States*1
Operation
@aa
2
@–ERn/@ERn+
B
@(d, ERn)
Rn
DAA
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2. Arithmetic Instructions
Advanced
A.1 Instruction List
Normal
447
@ERn
Appendix
2
→ Rd8
C. Product Part No. Lineup
491
The list is modified.
D. Package Dimensions
492
Added
Figure D.2 Package Dimensions
(32P6U-A)
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Rev. 3.00 May 15, 2007 Page 512 of 516
REJ09B0152-0300
Index
A
A/D converter ......................................... 349
Addressing modes..................................... 27
Absolute address................................... 28
Immediate ............................................. 29
Memory indirect ................................... 29
Program-counter relative ...................... 29
Register direct....................................... 28
Register indirect.................................... 28
Register indirect with displacement...... 28
Register indirect with post-increment... 28
Register indirect with pre-decrement.... 28
Asynchronous event counter (AEC) ....... 213
16-bit counter operation...................... 223
8-bit counter operation........................ 224
Event counter PWM operation ........... 225
C
Clock pulse generators.............................. 63
System clock oscillator ......................... 66
Comparators............................................ 361
Hysteresis characteristics.................... 366
Condition field.......................................... 26
Condition-code register (CCR)................. 11
CPU ............................................................ 7
E
Effective address....................................... 30
Effective address extension ...................... 26
Exception handling ................................... 41
F
Flash memory ........................................... 99
Boot mode........................................... 105
Boot program ...................................... 104
Erasing a block.................................... 100
Erasing/erasing-verifying.................... 112
Error protection................................... 114
Hardware protection............................ 114
On-board programming modes ........... 104
Power-down states .............................. 115
Programming units.............................. 100
Programming/erasure in user program
mode.................................................... 108
Programming/programming-verifying 109
Software protection............................. 114
G
General registers ....................................... 10
I
I/O ports .................................................. 119
I2C bus format ......................................... 328
I2C bus interface 2 (IIC2)........................ 311
Acknowledge ...................................... 328
Bit synchronous circuit ....................... 346
Clocked synchronous serial format..... 337
Noise canceler..................................... 340
Slave address....................................... 328
Start condition..................................... 328
Stop condition ..................................... 328
Transfer rate ........................................ 316
Instruction set............................................ 16
Arithmetic operations instructions ........ 18
Bit manipulation instructions ................ 21
Block data transfer instructions............. 25
Branch instructions ............................... 23
Data transfer instructions ...................... 17
Logic operations instructions ................ 20
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Shift instructions................................... 20
System control instructions................... 24
Interrupt mask bit (I)................................. 11
IrDA........................................................ 271
L
Large current port ................................... 119
Large current ports...................................... 1
M
Memory map .............................................. 8
O
Operation field.......................................... 26
P
Package....................................................... 2
Pin assignment............................................ 3
Power-down modes .................................. 77
Power-Down Modes
Module standby function ...................... 96
Sleep mode ........................................... 87
Standby mode ....................................... 88
Subactive mode .................................... 89
Subsleep mode...................................... 89
Power-on reset circuit............................. 369
Program counter (PC)............................... 11
R
Realtime clock (RTC)............................. 185
Data reading procedure....................... 197
Initial setting procedure ...................... 196
Register field ............................................ 26
Registers
Rev. 3.00 May 15, 2007 Page 514 of 516
REJ09B0152-0300
ADRR ......................... 350, 374, 378, 382
ADSR.......................... 352, 374, 378, 382
AEGSR ....................... 218, 374, 378, 381
AMR ........................... 351, 374, 378, 382
BRR ............................ 243, 374, 378, 382
CKSTPR1 ..................... 81, 375, 379, 383
CKSTPR2 ..................... 81, 375, 379, 383
CMCR......................... 362, 373, 377, 381
CMDR......................... 364, 373, 377, 381
EBR1........................... 103, 372, 376, 380
ECCR.......................... 219, 374, 378, 381
ECCSR........................ 220, 374, 378, 381
ECH ............................ 222, 374, 378, 381
ECL............................. 222, 374, 378, 381
ECPWCR.................... 216, 374, 377, 381
ECPWDR.................... 217, 374, 377, 381
FENR .......................... 104, 372, 376, 380
FLMCR1..................... 101, 372, 376, 380
FLMCR2..................... 102, 372, 376, 380
FLPWCR .................... 103, 372, 376, 380
GRA............................ 165, 373, 377, 381
GRB ............................ 165, 373, 377, 381
GRC ............................ 165, 373, 377, 381
GRD............................ 165, 373, 377, 381
ICCR1 ......................... 314, 372, 376, 380
ICCR2 ......................... 317, 372, 376, 380
ICDRR ........................ 327, 372, 376, 380
ICDRS................................................. 327
ICDRT ........................ 326, 372, 376, 380
ICIER.......................... 321, 372, 376, 380
ICMR .......................... 319, 372, 376, 380
ICSR ........................... 323, 372, 376, 380
IEGR ............................. 47, 375, 379, 383
IENR ............................. 48, 375, 379, 383
IrCR ............................ 252, 374, 378, 382
IRR................................ 50, 375, 379, 383
OSCCR ......................... 64, 375, 379, 383
PCR1........................... 120, 375, 379, 382
PCR3........................... 125, 375, 379, 382
PCR8........................... 129, 375, 379, 382
PCR9........................... 133, 375, 379, 382
PDR1 .......................... 120, 375, 378, 382
PDR3 .......................... 125, 375, 378, 382
PDR8 .......................... 129, 375, 378, 382
PDR9 .......................... 133, 375, 378, 382
PDRB.......................... 138, 375, 378, 382
PFCR .......................... 143, 373, 376, 380
PMR1.......................... 121, 375, 378, 382
PMR3.......................... 126, 375, 378, 382
PMRB ......................... 139, 375, 378, 382
PODR9 ....................... 134, 373, 376, 380
PUCR1........................ 121, 375, 378, 382
PUCR3........................ 126, 375, 379, 382
PUCR8........................ 130, 373, 376, 380
PUCR9........................ 134, 373, 376, 380
RDR............................ 234, 374, 378, 382
RHRDR ...................... 189, 372, 376, 380
RMINDR .................... 188, 372, 376, 380
RSECDR..................... 187, 372, 376, 380
RSR..................................................... 234
RTCCR1 ..................... 191, 372, 376, 380
RTCCR2 ..................... 192, 372, 376, 380
RTCCSR..................... 193, 372, 376, 380
RTCFLG..................... 194, 372, 376, 380
RWKDR ..................... 190, 372, 376, 380
SAR ............................ 326, 372, 376, 380
SCR............................. 237, 374, 378, 382
SEMR ......................... 253, 374, 378, 382
SMR............................ 235, 374, 378, 382
SPCR ...................142, 251, 374, 378, 381
SSCRH ....................... 285, 373, 377, 381
SSCRL........................ 287, 373, 377, 381
SSER........................... 290, 373, 377, 381
SSMR ......................... 289, 373, 377, 381
SSR ............................. 240, 374, 378, 382
SSRDR ....................... 293, 373, 377, 381
SSSR........................... 291, 373, 377, 381
SSTDR........................ 293, 373, 377, 381
SSTRSR.............................................. 293
SYSCR1 ....................... 78, 375, 379, 383
SYSCR2........................ 80, 375, 379, 383
TCB1........................... 147, 373, 376, 380
TCNT .......................... 164, 373, 377, 381
TCRW......................... 158, 373, 377, 381
TCSRWD1.................. 203, 374, 378, 382
TCSRWD2.................. 205, 374, 378, 382
TCWD......................... 206, 374, 378, 382
TDR ............................ 234, 374, 378, 382
TIERW........................ 159, 373, 377, 381
TIOR0 ......................... 161, 373, 377, 381
TIOR1 ......................... 163, 373, 377, 381
TLB1................................................... 147
TMB1.......................... 146, 373, 376, 380
TMRW ........................ 157, 373, 377, 381
TMWD........................ 207, 374, 378, 382
TSR ..................................................... 234
TSRW ......................... 160, 373, 377, 381
S
Serial communication interface 3 (SCI3)
Asynchronous mode............................ 253
Bit rate................................................. 243
Break................................................... 277
Clocked synchronous mode ................ 265
Framing error ...................................... 261
Mark state ........................................... 277
Overrun error ...................................... 261
Parity error .......................................... 261
Stack pointer (SP) ..................................... 11
Synchronous serial communication unit
(SSU) ...................................................... 283
Clock polarity...................................... 294
Clocked synchronous communication
mode.................................................... 297
Communication mode ......................... 296
Transfer clock ..................................... 293
Rev. 3.00 May 15, 2007 Page 515 of 516
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T
V
Timer B1................................................. 145
Auto-reload timer operation ............... 150
Interval timer operation ...................... 150
Timer W ................................................. 153
PWM operation .................................. 170
Vector address........................................... 42
Rev. 3.00 May 15, 2007 Page 516 of 516
REJ09B0152-0300
W
Watchdog timer....................................... 201
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/38602R Group
Publication Date: Rev.1.00, May 20, 2004
Rev.3.00, May 15, 2007
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Hardware Manual