CY62128EV30 MoBL® 1 Mbit (128K x 8) Static RAM Functional Description[1] Features • Very high speed: 45 ns • Temperature ranges– The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). — Industrial: –40°C to +85°C — Automotive-A: –40°C to +85°C — Automotive-E: –40°C to +125°C • Wide voltage range: 2.20V – 3.60V • Pin compatible with CY62128DV30 • Ultra low standby power — Typical standby current: 1 µA — Maximum standby current: 4 µA • Ultra low active power To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO pins is then written into the location specified on the Address pin (A0 through A16). — Typical active current: 1.3 mA @ f = 1 MHz • Easy memory expansion with CE1, CE2 and OE features • Automatic power down when deselected To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. • CMOS for optimum speed and power • Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin STSOP packages Logic Block Diagram IO0 INPUT BUFFER SENSE AMPS ROW DECODER IO1 128K x 8 ARRAY IO2 IO3 IO4 IO5 IO6 POWER DOWN IO7 A16 A12 A13 OE A14 COLUMN DECODER WE A15 CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05579 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 07, 2007 [+] Feedback CY62128EV30 MoBL® Pin Configuration[2] A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STSOP Top View (not to scale) A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP I Top View (not to scale) OE A10 CE1 IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3 Top View SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO 0 IO 1 IO 2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 IO 7 IO 6 IO 5 IO 4 IO 3 Product Portfolio Power Dissipation Product Range Speed (ns) VCC Range (V) Min Typ[3] Max CY62128EV30LL Ind’l/Auto-A 2.2 3.0 3.6 CY62128EV30LL 2.2 3.0 3.6 Auto-E Operating ICC (mA) f = 1 MHz Typ[3] 45 55 f = fmax Standby ISB2 (µA) Max Typ[3] Max Typ[3] Max 1.3 2.0 11 16 1 4 1.3 4.0 11 35 1 30 Notes: 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05579 Rev. *C Page 2 of 11 [+] Feedback CY62128EV30 MoBL® Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................... 55°C to +125°C Supply Voltage to Ground Potential ......................................... –0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[4, 5] ......................... –0.3V to VCC(max) + 0.3V Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Operating Range Device Ambient Temperature VCC[6] –40°C to +85°C 2.2V to 3.6V Range CY62128EV30LL Ind’l/Auto-A Auto-E –40°C to +125°C DC Input Voltage[4,5] ...................... –0.3V to VCC(max) + 0.3V Electrical Characteristics (Over the Operating Range) 45 ns (Ind’l/Auto-A) Parameter VOH VOL VIH VIL Description Test Conditions Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Min Typ [3] Max 55 ns (Auto-E) Min Typ[3] Max Unit IOH = –0.1 mA 2.0 2.0 V IOH = –1.0 mA, VCC > 2.70V 2.4 2.4 V IOL = 0.1 mA 0.4 0.4 V IOL = 2.1 mA, VCC > 2.70V 0.4 0.4 V VCC = 2.2V to 2.7V 1.8 VCC + 0.3V 1.8 VCC + 0.3V V VCC= 2.7V to 3.6V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V VCC= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V –1 +1 –4 +4 µA +1 –4 IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current +4 µA 11 16 11 35 mA 1.3 2.0 1.3 4.0 mA –1 f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA f = 1 MHz CMOS levels ISB1 Automatic CE CE1 > VCC−0.2V, CE2 < 0.2V Power down VIN > VCC–0.2V, VIN < 0.2V) Current — CMOS Inputs f = fmax (Address and Data Only), f = 0 (OE and WE), VCC = 3.60V 1 4 1 35 µA ISB2[7] CE1 > VCC – 0.2V, CE2 < 0.2V Automatic CE Power down VIN > VCC – 0.2V or VIN < 0.2V, Current — CMOS Inputs f = 0, VCC = 3.60V 1 4 1 30 µA Capacitance (For all packages)[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Notes: 4. VIL(min) = –2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 7. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05579 Rev. *C Page 3 of 11 [+] Feedback CY62128EV30 MoBL® Thermal Resistance Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) TSOP I SOIC STSOP Unit 33.01 48.67 32.56 °C/W 3.42 25.86 3.59 °C/W Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC 30 pF R2 INCLUDING JIG AND SCOPE 90% 10% 90% 10% GND Rise Time = 1 V/ns Equivalent to: Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT Parameters 2.50V R1 R2 RTH VTH V 3.0V Unit 16667 1103 Ω 15385 1554 Ω 8000 645 Ω 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR[7] Data Retention Current Conditions Min Typ[3] Max 1.5 VCC = 1.5V, CE1 > VCC − 0.2V or CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V tCDR[8] Chip Deselect to Data Retention Time tR[9] Operation Recovery Time Unit V Ind’l/Auto-A 3 µA Auto-E 30 µA 0 ns tRC ns Data Retention Waveform [10] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5V VCC(min) tR CE Notes: 9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 10. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document #: 38-05579 Rev. *C Page 4 of 11 [+] Feedback CY62128EV30 MoBL® Switching Characteristics (Over the Operating Range)[10, 11] 45 ns (Ind’l/Auto-A) Parameter Description Min Max 55 ns (Auto-E) Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 55 ns tDOE OE LOW to Data Valid 22 25 ns 45 [12] tLZOE OE LOW to Low Z 10 CE LOW to Low Z [12] tHZCE CE HIGH to High tPU CE LOW to Power Up tPD 55 10 10 0 CE HIGH to Power Up ns 20 18 ns ns 20 0 45 ns ns 5 18 Z[12, 13] ns 10 5 OE HIGH to High Z tLZCE Write 45 [12,13] tHZOE 55 ns ns 55 ns Cycle[14] tWC Write Cycle Time 45 55 ns tSCE CE LOW to Write End 35 40 ns tAW Address Setup to Write End 35 40 ns tHA Address Hold from Write End 0 0 ns tSA Address Setup to Write Start 0 0 ns tPWE WE Pulse Width 35 40 ns tSD Data Setup to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High Z[12, 13] WE HIGH to Low Z[12] 18 10 20 10 ns ns Notes: 11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 13. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 14. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05579 Rev. *C Page 5 of 11 [+] Feedback CY62128EV30 MoBL® Switching Waveforms Read Cycle 1 (Address transition controlled) [15, 16] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE controlled) [10, 16, 17] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Write Cycle No. 1 (WE controlled) [10, 15, 18, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA IO NOTE 20 tHD DATA VALID tHZOE Notes: 15. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 16. WE is HIGH for read cycle. 17. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 18. Data IO is high impedance if OE = VIH. 19. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 20. During this period, the IOs are in output state. Do not apply input signals. Document #: 38-05579 Rev. *C Page 6 of 11 [+] Feedback CY62128EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Write Cycle No. 3 (WE controlled, OE LOW) [10, 19] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA IO NOTE 20 tHD DATA VALID tLZWE tHZWE Truth Table CE1 CE2 WE OE H X X X High Z Deselect/Power Down Standby (ISB) X L X X High Z Deselect/Power Down Standby (ISB) L H H L Data Out Read Active (ICC) L H H H High Z Output Disabled Active (ICC) L H L X Data in Write Active (ICC) Document #: 38-05579 Rev. *C Inputs/Outputs Mode Power Page 7 of 11 [+] Feedback CY62128EV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code Package Diagram Operating Range Package Type CY62128EV30LL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) CY62128EV30LL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free) Industrial CY62128EV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free) 45 CY62128EV30LL-45ZXA 51-85056 32-pin TSOP Type I (Pb-free) Automotive-A 55 CY62128EV30LL-55ZXE 51-85056 32-pin TSOP Type I (Pb-free) Automotive-E Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 1. 32-Pin (450 Mil) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE Document #: 38-05579 Rev. *C 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 51-85081-*B Page 8 of 11 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 2. 32-Pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056 51-85056-*D Document #: 38-05579 Rev. *C Page 9 of 11 [+] Feedback CY62128EV30 MoBL® Package Diagrams (continued) Figure 3. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094 51-85094-*D MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05579 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62128EV30 MoBL® Document History Page Document Title: CY62128EV30 MoBL® 1 Mbit (128K x 8) Static RAM Document Number: 38-05579 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 285473 See ECN PCI New Data Sheet *A 461631 See ECN NXR Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62128EV30 Removed Reverse TSOP I package from Product offering. Changed ICC (Typ) from 8 mA to 11 mA and ICC (Max) from 12 mA to 16 mA for f = fmax Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz Changed ISB2 (max) from 1 µA to 4 µA Changed ISB2 (Typ) from 0.5 µA to 1 µA Changed ICCDR (max) from 1 µA to 3 µA Changed the AC Test load Capacitance value from 50 pF to 30 pF Changed tLZOE from 3 to 5 ns Changed tLZCE from 6 to 10 ns Changed tHZCE from 22 to 18 ns Changed tPWE from 30 to 35 ns Changed tSD from 22 to 25 ns Changed tLZWE from 6 to 10 ns Updated the Ordering Information table. *B 464721 See ECN NXR Updated the Block Diagram on page # 1 *C 1024520 See ECN VKN Added final Automotive-A and Automotive-E information Added footnote #9 related to ISB2 and ICCDR Updated Ordering Information table Document #: 38-05579 Rev. *C Page 11 of 11 [+] Feedback