TI CSD96370Q5M Synchronous buck nexfetâ ¢ power stage Datasheet

CSD96370Q5M
www.ti.com
SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
Synchronous Buck NexFET™ Power Stage
FEATURES
APPLICATIONS
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1
90% System Efficiency at 25A
High Frequency Operation (Up To 2MHz)
Incorporates Power Block Technology
High Density – SON 5-mm × 6-mm Footprint
Low Power Loss 2.6W at 25A
Ultra Low Inductance Package
System Optimized PCB Footprint
3.3V and 5V PWM Signal Compatible
3-State PWM Input
Integrated Bootstrap Diode
Pre-Bias Start-Up Protection
Shoot Through Protection
RoHS Compliant – Lead Free Terminal Plating
Halogen Free
Synchronous Buck Converters
Multiphase Synchronous Buck Converters
POL DC-DC Converters
Memory and Graphic Cards
Desktop and Server VR11.x and VR12 V-Core
Synchronous Buck Converters
ORDERING INFORMATION
Device
Package
Media
CSD96370Q5M
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Qty
Ship
2500
Tape and
Reel
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DESCRIPTION
The CSD96370Q5M NexFET Power Stage is an optimized design for use in a high power, high density
Synchronous Buck converter. This product integrates an enhanced gate driver IC and Power Block Technology
to complete the power stage switching function. This combination produces a high current, high efficiency, high
speed switching device and delivers an excellent thermal solution in a small 5-mm × 6-mm outline package due
to its large ground based thermal pad. In addition, the PCB footprint has been optimized to help reduce design
time and simplify the completion of the overall system design.
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VIN
CIN
100
5
90
4
VDD = 5V
VIN = 12V
VOUT = 1.2V
LOUT = 0.3µH
fSW = 500kHz
T A = 25°C
LO
VCC
VOUT
VOUT
PWM1
COUT
SS
RT
VOUT
Efficiency (%)
CSD96370Q5M
VDD
80
70
3
2
PWM2
PGND
60
Power Loss (W)
spacer
1
Efficiency
Power Loss
LO
50
Multi Phase
Control IC
0
CSD96370Q5M
5
10
15
Output Current (A)
20
0
25
G029
S0488-01
Figure 1. Application Diagram
Figure 2. Efficiency and Power Loss
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
CSD96370Q5M
SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
TA = 25°C (unless otherwise noted)
VIN to PGND
VDD to PGND
VALUE
UNIT
–0.3 to 16
V
–0.3 to 6
V
ENABLE to PGND (2)
–0.3 to VDD + 0.3
V
PWM to PGND (2)
–0.3 to VDD + 0.3
V
BOOT to BOOT_R
ESD Rating
(2)
Human Body Model (HBM)
Charged Device Model (CDM)
Power Dissipation, PD
–0.3 to VDD + 0.3
V
2
kV
500
V
12
W
Storage Temperature Range, TSTG
–55 to 150
°C
Operating Junction Temperature Range
–55 to 150
°C
(1)
(2)
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
Should not exceed 6V
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Conditions
MIN
MAX
UNIT
Gate Drive Voltage, VDD
4.5
5.5
V
Input Supply Voltage, VIN
3.3
13.2
V
5.5
V
40
A
Output Voltage, VOUT
Continuous Output Current, IOUT
Peak Output Current, IOUT-PK (2)
Switching Frequency, fSW
VIN = 12V, VDD = 5V, VOUT = 1.2V,
fSW = 500kHz, LOUT = 0.3µH (1)
60
CBST = 0.1µF (min)
200
On Time Duty Cycle
kHz
85%
Minimum PWM On Time
40
Operating Temperature
–40
(1)
(2)
A
2000
ns
125
°C
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
System conditions as defined in Note 1. Peak Output Current is applied for tp = 50µs.
THERMAL INFORMATION
TA = 25°C (unless otherwise noted)
PARAMETER
RqJC
RqJB
(1)
(2)
2
MIN
Thermal Resistance, Junction-to-Case (Top of package) (1)
Thermal Resistance, Junction-to-Board
(2)
2
TYP
MAX
UNIT
20
°C/W
2
°C/W
2
RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch, 0.06-inch
(1.52-mm) thick FR4 board.
RqJB value based on hottest board temperature within 1mm of the package.
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CSD96370Q5M
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SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = POR to 5.5V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
Power Loss (1)
VIN = 12V, VDD = 5V, VOUT = 1.2V, IOUT = 25A,
fSW = 500kHz, LOUT = 0.3µH , TJ = 25°C
–
2.6
3.3
W
Power Loss (2)
VIN = 12V, VDD = 5V, VOUT = 1.2V, IOUT = 40A,
fSW = 500kHz, LOUT = 0.3µH , TJ = 125°C
–
8
10
W
ENABLE = 0V, VDD = 5V
–
–
100
µA
Standby Supply Current ( IDD)
ENABLE = 0V, PWM = 0V
–
1
5
µA
Operating Supply Current (IDD)
ENABLE = 5V, PWM = 50% Duty cycle,
fSW = 500kHz
–
16
20
mA
–
3.6
3.9
V
UVLO (VDD Falling)
3.4
3.5
–
Hysteresis
100
–
250
mV
–
600
1000
ns
V
VIN
VIN Quiescent Current (IQ)
VDD
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power on Reset (VDD Rising)
Startup Delay (3)
ENABLE = PWM = 5V
V
ENABLE
Logic Level Low Threshold (VIL)
0.8
1
–
Logic Level High Threshold (VIH)
–
1.6
2.0
Threshold Hysteresis
–
580
–
mV
Weak Pull-down Impedance
Schmitt Trigger Input PWM = 5V (See Figure 5)
V
–
100
–
kΩ
Rising Propagation Delay (tPDH)
–
600
–
ns
Falling Propagation Delay (tPDL)
–
200
–
ns
PWM
IPWMH
PWM = 5V
–
620
800
µA
IPWML
PWM = 0V
–
–260
–340
µA
PWM Logic Level High (VPWMH )
–
–
2.2
V
PWM Logic Level Low (VPWML )
0.8
–
–
V
–
1.5
–
V
–
100
–
ns
3-State Shutdown Hold-off Time (t3HT)
–
100
–
ns
3-State Shutdown Propagation Delay (t3SD)
–
650
–
ns
3-State Recovery Propagation Delay (t3RD)
–
75
–
ns
PWM 3-State open Voltage
PWM to VSW propagation delay
(tPDLH and tPDHL)
VDD = POR to 5.5V, CPWM = 10pF (See Figure 6)
BOOTSTRAP SWITCH
Forward Voltage (VFBOOT)
VDD – VBOOT, IF = 20mA
–
180
360
mV
Reverse Leakage (IRBOOT) (2)
VBOOT – VDD = 20V
–
0.15
1
µA
(1)
(2)
(3)
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
Specified by design
POR to VSW rising
Copyright © 2010–2011, Texas Instruments Incorporated
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SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
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PIN CONFIGURATION
SON 5mm ´ 6mm
22-Pin Package
(Top View)
ENABLE
1
22
PWM
NC
VDD
2
21
NC
3
20
NC
NC
4
19
BOOT
NC
VSW
5
18
BOOT_R
17
VIN
VSW
7
16
VIN
VSW
8
15
VIN
VSW
9
14
VIN
VSW
10
13
VIN
VSW
11
12
VIN
6
PGND
23
P0125-01
PIN DESCRIPTION
PIN
NO.
4
DESCRIPTION
NAME
1
ENABLE
Enables device operation. If ENABLE=logic HIGH, turns on the device. If ENABLE=logic LOW, the device is turned off
and MOSFET gates are actively pulled low. An internal 100kΩ pull down resistor will pull the ENABLE pin LOW if left
floating.
2
NC
Not for electrical connection, connect to floating pad only.
3
VDD
Supply Voltage to Gate Drivers and internal circuitry.
4
NC
Not for electrical connection, connect to floating pad only.
5
NC
Not for electrical connection, connect to floating pad only.
6
VSW
Voltage Switching Node – pin connection to the output inductor.
7
VSW
Voltage Switching Node – pin connection to the output inductor.
8
VSW
Voltage Switching Node – pin connection to the output inductor.
9
VSW
Voltage Switching Node – pin connection to the output inductor.
10
VSW
Voltage Switching Node – pin connection to the output inductor.
11
VSW
Voltage Switching Node – pin connection to the output inductor.
12
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
13
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
14
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
15
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
16
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
17
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
18
BOOT_R
19
BOOT
Bootstrap capacitor connection. Connect a minimum 0.1µF 16V X5R, ceramic cap from BOOT to BOOT_R pins. The
bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.
20
NC
Not for electrical connection, connect to floating pad only.
21
NC
Not for electrical connection, connect to floating pad only.
22
PWM
Pulse Width modulated 3-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate
high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if
greater than the 3-State Shutdown Hold-off Time (t3HT)
23
PGND
Power Ground
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CSD96370Q5M
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SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
VDD
Boot
VIN
Control
FET
PWM
EN
Boot_R
UVLO
and
Control Logic
Shoot
Through
Control
VSW
Sync
FET
PGND
B0433-01
Figure 3. Functional Block Diagram
FUNCTIONAL DESCRIPTION
POWERING CSD96370Q5M AND GATE DRIVERS
An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETS. The gate driver IC is capable of supplying in excess of 4 Amps peak current into the
MOSFET gates to achieve fast switching. A 1uF 10V X5R or higher ceramic capacitor is recommended to
bypass VDD pin to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included.
The bootstrap supply to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor
between BOOT and BOOT_R pins. An optional RBOOT resistor which can be used to slow down the turn on
speed of the Control FET and reduce voltage spikes on the Vsw node. A typical 1Ω to 4.7Ω value is a
compromise between switching loss and VSW spike amplitude.
UVLO (Under Voltage Lock Out)
The VDD supply is monitored for UVLO conditions and both Control FET and Sync FET gates are held low until
adequate supply is available. An internal comparator evaluates the VDD voltage level and if VDD is greater than
the Power On Reset threshold (VPOR) the gate driver becomes active. If VDD is less than the UVLO threshold, the
gate driver is disabled and the internal MOSFET gates are actively driven low. At the rising edge of the VDD
voltage, both Control FET and Sync FET gates will be actively held low during VDD transitions between 1.0V to
VPOR. This region is referred to the Gate Drive Latch Zone (see Figure 4). In addition, at the falling edge of the
VDD voltage, both Control FET and Sync FET gates are actively held low during the UVLO to 1.0V transition.
The Power Stage CSD96370Q5M device must be powered up and Enabled before the PWM signal is applied.
VDD
VPOR
Gate Drive
Latch Zone
1.0V
UVLO
1.0V
T0487-01
Figure 4. POR and UVLO
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ENABLE
The ENABLE pin is TTL compatible. The logic level thresholds are sustained under all VDD operating conditions
between VPOR to VDD. In addition, if this pin is left floating, a weak internal pull down resistor of 100kΩ will pull the
ENABLE pin below the logic level low threshold. The operational functions of this pin should follow the timing
diagram outlined in Figure 5. A logic level low will actively hold both Control FET and Sync FET gates low and
VDD pin should typically draw less than 5µA.
POWER UP SEQUENCING
If the ENABLE signal is used, it is necessary to ensure proper co-ordination with the ENABLE and soft-start
features of the external PWM controller in the system. If the CSD96370Q5M was disabled through ENABLE
without sequencing with the PWM IC controller, the buck converter output will have no voltage or fall below
regulation set point voltage. As a result, the PWM controller IC delivers Max duty cycle on the PWM line. If the
Power Stage CSD96370Q5M is re-enabled by driving the ENABLE pin high, there will be an extremely large
input inrush current when the output voltage builds back up again. The input inrush current might have
undesirable consequences such as inductor saturation, driving the input power supply into current limit or even
catastrophic failure of the CSD96370Q5M device. Disabling the PWM controller is recommended when the
CSD96370Q5M is disabled. The PWM controller should always be re-enabled by going through soft-start routine
to control and minimize the input inrush current and reduce current and voltage stress on all buck converter
components. It is recommended that the external PWM controller be disabled when CSD96370Q5M is disabled
or nonoperational because of UVLO.
PWM
The input PWM pin incorporates a 3-State function. The Control FET and Sync FET gates are forced low if the
PWM pin is left floating for more than the 3-State Hold off time (t3HT), typically 100ns. This requires the source
impedance of the driving PWM signal to be a minimum of 250kΩ when in 3-State mode. Operation in and out of
3-State mode should follow the timing diagram outlined in Figure 6. Both VPWML and VPWMH threshold levels are
set to accommodate both 3.3V and 5V logic controllers. During normal operation, the PWM signal should be
driven to logic levels Low and High with a maximum of 220Ω/320Ω sink/source impedance respectively.
GATE DRIVERS
The CSD96370Q5M has an internal high-performance gate driver IC that ensures minimum MOSFET dead-time
while eliminating potential shoot-through currents. Propagation delays between the Control FET and Sync FET
gates are kept to a minimum to minimize body diode conduction and improve efficiency. The gate driver IC
incorporates an adaptive shoot through protection scheme which ensures that neither MOSFET is turned on
while the other one is still conducting at the same time, preventing cross conduction. See Table 1.
Table 1. Truth Table
ENABLE
PWM
CONTROL FET
GATE
SYNC FET GATE
VSW
L
X
L
L
3-State
H
<Min ON time
L
L
3-State
H
L
L
H
PGND
H
3-State
L
L
3-State
H
H
H
L
VIN
L = Logic Low; H = Logic High; X = Don't care; minimum on time = 40ns
START UP IN PRE-BIASED OUTPUT VOLTAGE
The CSD96370Q5M incorporates a simple pre-bias feature to protect against the discharging of a prebiased
output voltage and inducing large negative inductor currents. After the Power On Reset threshold is crossed and
the ENABLE pin is set to logic level high, both internal MOSFETs are actively held low until the PWM pin
receives a signal that crosses logic level high threshold and meets the minimum on time criteria (see the
Electrical Characteristics Table). This allows the PWM control IC to provide a soft start routine that creates a
monotonic startup of the output voltage. The pre-bias feature is enabled for a single event and subsequent PWM
signals creates normal switching of the internal MOSFETs (see Table 1). To reactivate the pre-bias feature, the
ENABLE pin needs to be pulled below logic level low or the VDD supply voltage needs to cross UVLO.
6
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SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
90%
tPDL
ENABLE
tPDH
10%
90%
VSW
10%
T0488-01
Figure 5. CSD96370Q5M ENABLE Timing Diagram (VDD = PWM = 5V)
spacer
spacer
spacer
spacer
spacer
spacer
PWM 3-State Window
VPWMH
PWM
VPWML
t3RD
t3HT + t3SD
VOUT
VSW
tPDLH
tPDHL
VOUT
t3RD
t3HT + t3SD
T0489-01
Figure 6. CSD96370Q5M PWM Timing Diagram
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TYPICAL CHARACTERISTICS
Test conditions: VIN = 12V, VDD = 5V, fSW= 500kHz, VOUT = 1.2V, LOUT = 0.3mH, DCR = 0.54mΩ, TJ = 125°C
spacer
10
1.2
Typ
Max
9
1.1
Power Loss, Normalized
Power Loss (W)
8
7
6
5
4
3
1
0.9
0.8
0.7
2
0.6
1
0
0
5
10
15
20
25
Output Current (A)
30
35
0.5
-50
40
-25
50
50
45
45
40
40
35
35
30
25
20
15
400LFM
200LFM
100LFM
Nat Conv
5
25
50
75
100
Junction Temperature ( °C)
125
150
G002
Figure 8. Power Loss vs Temperature
Output Current (A)
Output Current (A)
Figure 7. Power Loss vs Output Current
10
0
G001
30
25
20
15
400LFM
200LFM
100LFM
Nat Conv
10
5
0
0
0
10
20
30
40
50
60
Ambient Temperature (°C)
70
80
90
0
10
20
G003
Figure 9. Safe Operating Area – PCB Vertical Mount (1)
30
40
50
60
Ambient Temperature (°C)
70
80
90
G004
Figure 10. Safe Operating Area – PCB Horizontal Mount (1)
50
45
Output Current (A)
40
35
30
25
20
15
10
Typ SOA
Min SOA
5
0
0
20
40
60
80
100
Board Temperature (°C)
120
140
G005
Figure 11. Typical and Min Safe Operating Area (1)
1. The Typical CSD96370Q5M System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application section
for detailed explanation.
8
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SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
TYPICAL CHARACTERISTICS
Test conditions: VIN = 12V, VDD = 5V, fSW= 500kHz, VOUT = 1.2V, LOUT = 0.3mH, DCR = 0.54mΩ, TJ = 125°C
1.6
17.1
14.2
1.5
14.2
1.4
11.4
1.4
11.4
1.3
8.5
1.3
8.5
1.2
5.7
1.2
5.7
1.1
2.8
1.1
2.8
0
1
0.9
-2.8
0.8
-5.7
0.7
-8.5
0.6
200
-11.4
600 800 1000 1200 1400 1600 1800 2000
Switching Frequency (kHz)
400
0
1
0.9
-2.8
0.8
-5.7
0.7
-8.5
0.6
-11.4
3
4
5
6
8
9
10
7
Input Voltage (V)
G006
Figure 12. Normalized Power Loss vs Frequency
11
12
13
14
G007
Figure 13. Normalized Power Loss vs Input Voltage
1.6
17
18.2
1.5
14.1
1.6
15.6
1.4
11.3
1.5
13
1.3
8.5
1.2
5.6
1.1
2.8
1.4
10.4
1.3
7.8
1.2
5.2
1.1
2.6
0
1
0.9
-2.9
0.8
-5.7
-8.5
-2.6
0.7
0.8
-5.2
0.6
0.6
1
1.4
1.8
2.2 2.6 3 3.4
Output Voltage (V)
3.8
4.2
4.6
5
-11.4
0
0.1
0.2
G008
Figure 14. Normalized Power Loss vs Output Voltage
0.3
0.4 0.5 0.6 0.7 0.8
Output Inductance (µH)
0.9
1
1.1
G009
Figure 15. Normalized Power Loss vs Output Inductance
70
20
65
19
60
18
55
Driver Current (mA)
Driver Current (mA)
0
1
0.9
SOA Temperature Adj (°C)
20.8
1.7
Power Loss, Normalized
1.8
SOA Temperature Adj (°C)
Power Loss, Normalized
SOA Temperature Adj (°C)
17.1
Power Loss, Normalized
1.6
1.5
SOA Temperature Adj (°C)
Power Loss, Normalized
spacer
50
45
40
35
30
17
16
15
14
13
25
12
20
15
11
10
200
10
-50
400
600
800 1000 1200 1400 1600 1800 2000
Switching Frequency (kHz)
G030
Figure 16. Driver Current vs Frequency
Copyright © 2010–2011, Texas Instruments Incorporated
-25
0
25
50
75
100
Junction Temperature ( °C)
125
150
G031
Figure 17. Driver Current vs Temperature
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APPLICATION INFORMATION
The Power Stage CSD96370Q5M is a highly optimized design for synchronous buck applications using NexFET
devices with a 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest
power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more
systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the
parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such
as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance
in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss
generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has
provided measured power loss performance curves. Figure 7 plots the power loss of the CSD96370Q5M as a
function of load current. This curve is measured by configuring and running the CSD96370Q5M as it would be in
the final application (see Figure 18). The measured power loss is the CSD96370Q5M device power loss which
consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.
Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT)
(1)
The power loss curve in Figure 7 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD96370Q5M datasheet give engineers guidance on the temperature boundaries within
an operating system by incorporating the thermal resistance and system power loss. Figure 9, Figure 10, and
Figure 11 outline the temperature and airflow conditions required for a given load current. The area under the
curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.
Normalized Curves
The normalized curves in the CSD96370Q5M data sheet give engineers guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
CSD96370Q5M
Gate Drive
Current (IDD)
VDD
A
Gate Drive
V
Voltage (VDD)
Boot
VDD
DRVH
HSgate
Control
FET
VSW
VSW
LSgate
Sync
FET
VIN
A
VIN
BST
CBoot
CIN
V
Input Voltage
(VIN)
Boot_R
ENABLE
LL
PWM
Input Current
(IIN)
DRVL
PWM
LOUT
A
COUT
VOUT
Output Current
(IOUT)
GND
PGND
Averaging
Circuit
V
Averaged Switched
Node Voltage
(VSW_AVG)
S0489-01
Figure 18. Power Loss Test Circuit
10
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Copyright © 2010–2011, Texas Instruments Incorporated
CSD96370Q5M
www.ti.com
SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).
Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the
following procedure will outline the steps engineers should take to predict product performance for any set of
system conditions.
Design Example
Operating Conditions: Output Current (lOUT) = 25A, Input Voltage (VIN ) = 7V, Output Voltage (VOUT) = 1V,
Switching Frequency (fSW) = 800kHz, Output Inductor (LOUT) = 0.2µH
Calculating Power Loss
•
•
•
•
•
•
Power Loss at 25A = 3.3W (Figure 7)
Normalized Power Loss for switching frequency ≈ 1.09 (Figure 12)
Normalized Power Loss for input voltage ≈ 1.07 (Figure 13)
Normalized Power Loss for output voltage ≈ 0.95 (Figure 14)
Normalized Power Loss for output inductor ≈ 1.06 (Figure 15)
Final calculated Power Loss = 3.3W × 1.09 × 1.07 × 0.95 × 1.06 ≈ 3.88W
Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for switching frequency ≈ 2.7°C (Figure 12)
SOA adjustment for input voltage ≈ 0.1°C (Figure 13)
SOA adjustment for output voltage ≈ –1.3°C (Figure 14)
SOA adjustment for output inductor ≈ 1.6°C (Figure 15)
Final calculated SOA adjustment = 2.7 + 0.1 + (–1.3) + 1.6 ≈ 3.1°C
50
45
Output Current (A)
40
35
30
1
25
20
VDD = 5V
VIN = 12V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.3 µH
15
10
5
2
3
0
0
20
40
60
80
100
Board Temperature (°C)
120
140
G028
Figure 19. Power Stage CSD96370Q5M SOA
In the design example above, the estimated power loss of the CSD96370Q5M would increase to 3.88W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.1°C. Figure 19
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 3.1°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Copyright © 2010–2011, Texas Instruments Incorporated
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11
CSD96370Q5M
SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
www.ti.com
RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
Electrical Performance
The CSD96370Q5M has the ability to switch at voltages rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.
• The placement of the input capacitors relative to VIN and PGND pins of CSD96370Q5M device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 20).
The example in Figure 20 uses 6 x 10µF 1206 25V ceramic capacitors (TDK Part # C3216X5R1C106KT or
equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of
vias interconnecting both layers. In terms of priority of placement next to the Power Stage C5, C8 and C7,
C19 should follow in order.
• The bootstrap cap CBOOT 0.1µF 0603 16V ceramic capacitor should be closely connected between BOOT and
BOOT_R pins
• The switching node of the output inductor should be placed relatively close to the Power Stage
CSD96370Q5M VSW pins. Minimizing the VSW node length between these two components will reduce the
PCB conduction losses and actually reduce the switching noise level. (1)
Thermal Performance
The CSD96370Q5M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 20 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 20. Recommended PCB Layout (Top Down View)
(1)
12
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
CSD96370Q5M
www.ti.com
SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
MECHANICAL DATA
h
c2
q
c
A
L
K
E2
c1
E1
12
11
12
11
q
b
E
23
D2
D1
1
1
22
22
e
q
A1
Top View
0.3 x 45
Side View
L
Bottom View
Note: Exposed tie clips may vary
c
E1
M0201-01
DIM
MILLIMETERS
Min
Nom
INCHES
Max
Min
Nom
Max
A
1.400
1.500
1.55
0.057
0.059
0.061
A1
0.000
0.000
0.050
0.000
0.000
0.002
b
0.200
0.250
0.320
0.008
0.010
0.013
c
0.150
0.200
0.250
0.006
0.008
0.010
c1
0.150
0.200
0.250
0.006
0.008
0.010
c2
0.200
0.250
0.300
0.008
0.010
0.012
D1
5.900
6.000
6.100
0.232
0.236
0.240
D2
5.379
5.479
5.579
0.212
0.216
0.220
E
5.900
6.000
6.100
0.232
0.236
0.240
E1
4.900
5.000
5.100
0.193
0.197
0.201
E2
3.140
3.240
3.340
0.124
0.128
0.132
e
h
0.500 TYP
1.150
K
1.250
0.020 TYP
1.350
0.045
0.380 TYP
0.049
0.053
0.015 TYP
L
0.400
0.500
0.600
0.016
0.020
0.024
q
0.00
—
—
0.00
—
—
Copyright © 2010–2011, Texas Instruments Incorporated
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13
CSD96370Q5M
SLPS265A – NOVEMBER 2010 – REVISED JANUARY 2011
www.ti.com
Land Pattern Recommendation
0.331 (0.013)
0.370 (0.015)
1.000 (0.039)
12
11
0.410 (0.016)
6.300
(0.248)
0.300
(0.012)
5.300
(0.209)
5.639
(0.222)
1
22
0.500
(0.020)
3.400
(0.134)
5.900
(0.232)
M0202-01
NOTE: Dimensions are in mm (inches).
spacer
Stencil Recommendation
0.250 (0.010)
0.311
(0.012)
11
0.250 (0.010)
0.300 (0.012)
12
0.850 (0.033)
0.500 (0.020)
1.145 (0.045)
5.250
(0.207)
1
0.250 (0.010)
22
0.300
(0.012)
0.600 (0.024)
0.750 (0.030)
0.300
(0.012)
1.400 (0.055)
5.700 (0.224)
M0204-01
NOTE: Dimensions are in mm (inches).
REVISION HISTORY
Changes from Original (November 2010) to Revision A
•
14
Page
Added the Operating Junction Temperature Range in the Abs Max Table .......................................................................... 2
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Copyright © 2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2011
PACKAGING INFORMATION
Orderable Device
CSD96370Q5M
Status
(1)
ACTIVE
Package Type Package
Drawing
SON
DQP
Pins
Package Qty
22
2500
Eco Plan
(2)
Pb-Free (RoHS
Exempt)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD96370Q5M
Package Package Pins
Type Drawing
SON
DQP
22
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
6.3
1.8
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Feb-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD96370Q5M
SON
DQP
22
2500
346.0
346.0
29.0
Pack Materials-Page 2
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