ICHAUS IC-MU Off-axis nonius encoder with integrated hall sensor Datasheet

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iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
Rev B1, Page 1/59
FEATURES
APPLICATIONS
♦
♦
♦
♦
♦ Rotative absolute encoders
♦ Linear absolute scales
♦ Singleturn and multiturn
encoders
♦ Motor feedback encoders
♦ BLDC motor commutation
♦ Hollow shaft encoder
♦ Multi-axis measurement systems
♦
♦
♦
♦
♦
♦
♦
♦
♦
Integrated Hall sensors for two-track scanning
Hall sensors optimized for 1.28 mm pole width (master track)
Signal conditioning for offset, amplitude, and phase
Sine/digital real-time conversion with 12-bit resolution (14-bit
filtered)
2-track nonius absolute value calculation up to 18 bits
16, 32, or 64 pole pairs per measurement distance
Enlargement of measurement distance with second iC-MU
Synchronization of external multiturn systems
Configuration from an external EEPROM using a multimaster
I2C interface
Microcontroller-compatible serial interface (SPI, BiSS, SSI)
Incremental quadrature signals with an index (ABZ)
FlexCount® : scalable resolution from 1 up to 65536 CPR
Commutation signals for motors from 1 up to 16 pole pairs
(UVW)
PACKAGES
DFN16
5 mm x 5 mm
BLOCK DIAGRAM
VPA
PORT A
VPD
PORT B
MASTER TRACK
PA0
PB0
B
PA1
PB1
12 BIT
NONIUS TRACK
PA2
PB2
B
PA3
PB3
12 BIT
SER INTERFACE
HALL SENSORS
+
PGA
SINUS/DIGITAL
CONFIGURATION
ANA/DIG OUTPUT
iC-MU
128 Byte RAM
AMPLITUDE CONTROL
SCL
MTC
SYNCHRONISATION
CLOCK
INTERFACE HANDLER
SDA
I2C EEPROM
INTERFACE
BIAS
ERROR MANAGEMENT
REFERENCE
ENCODER PROCESSOR
VNA
Copyright © 2013 iC-Haus
MTD
MULTITURN
INTERFACE
VND
http://www.ichaus.com
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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DESCRIPTION
iC-MU is used for magnetic off-axis position definition
with integrated Hall sensors. By scanning two separate channels i.e. the master and nonius track the
device can log an absolute position within one mechanical revolution. The chip conditions the sensor
signals and compensates for typical signal errors.
The internal 12-bit sine/digital converters generate
two position words that supply high-precision position data within one sine-period. The integrated nonius calculation engine calculates the absolute position within one mechanical revolution and synchronizes this with the master track position word. Position data can be transmitted serially, incrementally, or
analog through two ports in various modes of operation. Commutation signals for brushless DC (BLDC)
motors with up to 16 pole pairs are derived from the
absolute position and supplied through a 3-pin interface.
During startup the device loads a CRC-protected
configuration from an external EEPROM.
After the device has been reset an optional external
multiturn is read in an synchronized with the internal
position data. During operation the position is cyclically checked.
The device offered here is a multifunctional iC that contains integrated BiSS C interface components. The BiSS C process is
protected by patent DE 10310622 B4 owned by iC-Haus GmbH.
Users benefit from the open BiSS C protocol with a free license
which is necessary when using the BiSS C protocol in conjunction with this iC.
Download the license at
www.biss-interface.com/bua
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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Rev B1, Page 3/59
CONTENTS
PACKAGING INFORMATION
4
PIN CONFIGURATION . . . . . . . . . . . .
4
PACKAGE DIMENSIONS . . . . . . . . . . .
5
ABSOLUTE MAXIMUM RATINGS
6
THERMAL DATA
6
ELECTRICAL CHARACTERISTICS
7
OPERATING CONDITIONS: Multiturn Interface
9
OPERATING CONDITIONS: I/O Interface
10
PRINCIPLE OF MEASUREMENT
12
Rotative measuring system . . . . . . . . . .
12
Linear measuring system . . . . . . . . . . .
12
CONFIGURATION PARAMETERS
14
REGISTER ASSIGNMENTS (EEPROM)
16
Register assignment (EEPROM) . . . . . . .
16
Special BiSS registers . . . . . . . . . . . . .
18
SIGNAL CONDITIONING FOR MASTER AND
NONIUS CHANNELS: x = M,N
19
Gain settings . . . . . . . . . . . . . . . . . .
19
Offset compensation . . . . . . . . . . . . . .
20
Phase adjustment . . . . . . . . . . . . . . .
20
ANALOG SIGNAL CONDITIONING FLOW: x =
M,N
21
1. Conditioning the BIAS current . . . . . . .
21
2. Positioning of the sensor . . . . . . . . . .
21
3.a Test modes analog master and analog
nonius . . . . . . . . . . . . . . . . . . .
21
3.b Test mode CNV_x . . . . . . . . . . . . .
21
4. Trackoffset SPON . . . . . . . . . . . . . .
21
I2C interface / CRC
22
. . . . . . . . . . . . . .
22
Startup behavior . . . . . . . . . . . . . . . .
23
CONFIGURABLE I/O INTERFACE
Setting the interfaces . . . . . . . . . . . . . .
26
28
29
31
31
32
32
33
33
34
CONVERTER AND NONIUS CALCULATION
Converter principle . . . . . . . . . . . . . . .
Synchronization mode . . . . . . . . . . . . .
35
35
35
MT INTERFACE
Configuration of the Multiturn interface . . . .
Construction of a Multiturn system with two
iC-MU . . . . . . . . . . . . . . . . . . .
Direct Communication To Multiturn Sensor .
38
38
40
41
19
Bias current source . . . . . . . . . . . . . . .
I2C INTERFACE AND STARTUP BEHAVIOR
Serial interface
Configuring the data format and data
length . . . . . . . . . . . . . . . . . . .
BiSS C interface . . . . . . . . . . . . . . . .
SSI interface . . . . . . . . . . . . . . . . . .
SPI interface: general description . . . . . . .
SPI interface: Command ACTIVATE . . . . .
SPI interface: Command SDAD transmission
SPI interface: Command SDAD status . . . .
SPI interface: Command Read REGISTER
(single) . . . . . . . . . . . . . . . . . .
SPI interface: Command Write REGISTER
(single) . . . . . . . . . . . . . . . . . .
SPI interface: Command REGISTER
status/data . . . . . . . . . . . . . . . .
INCREMENTAL OUTPUT ABZ,
STEP/DIRECTION AND CW/CCW
42
UVW COMMUTATION SIGNALS
44
REGISTER ACCESS THROUGH SERIAL
INTERFACE (SPI AND BISS)
Address sections/Registerprotectionlevel . .
45
49
STATUS REGISTER AND ERROR MONITORING 50
Status register . . . . . . . . . . . . . . . . . 50
Error and warning bit configuration . . . . . . 50
COMMAND REGISTER
Implementing internal commands . . . . . . .
Configurable NPRES Pin . . . . . . . . . . .
52
52
54
POSITION OFFSET VALUES AND PRESET
FUNCTION
Preset function . . . . . . . . . . . . . . . . .
56
56
DESIGN REVIEW: Notes On Chip Functions
58
25
25
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WITH INTEGRATED HALL SENSORS
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Rev B1, Page 4/59
PACKAGING INFORMATION
PIN CONFIGURATION
1
Hall Sensors Master Track
PIN FUNCTIONS
No. Name Function
16
2
15
3
14
4
13
12
7
MU
...
yyww...
8
Hall Sensors Nonius Track
9
5
6
11
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCL
SDA
VPA
VNA
PB0
PB1
PB2
PB3
PA3
PA2
PA1
PA0
VND
VPD
MTD
MTC
TP
EEPROM interface, clock
EEPROM interface, data
+4.5 V. . . +5.5 V analog supply voltage
Analog Ground
Port B, Pin 0: Digital I/O, analog output
Port B, Pin 1: Digital I/O, analog output
Port B, Pin 2: Digital I/O, analog output
Port B, Pin 3: Digital I/O, analog output
Port A, Pin 3: Digital I/O
Port A, Pin 2: Digital I/O
Port A, Pin 1: Digital I/O
Port A, Pin 0: Digital I/O
Digital ground
+4.5 V. . . +5.5 V digital supply voltage
Multiturn interface, data input
Multiturn interface, clock output
Thermal Pad
The Thermal Pad on the underside of the package should be appropriately connected to VNA/VND for better
heat dissipation (ground plane).
Analog and digital grounds have to be connected low ohmic on the PCB.
Only the Pin 1 mark on the front or reverse is determinative for package orientation (
subject to change).
MU and code are
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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Rev B1, Page 5/59
PACKAGE DIMENSIONS
All dimensions given in mm.
RECOMMENDED PCB-FOOTPRINT
4
15
R0.
0.50
TOP
0.30
4.80
BOTTOM
4
1.80
0.50
0.25
0.40
5
3.45
5
1.80
0.80
3.40
0.90
0.42
SIDE
dra_mu-dfn16-1_pack_1, 10:1
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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ABSOLUTE MAXIMUM RATINGS
Maximum ratings do not constitute permissible operating conditions; functionality is not guaranteed. Exceeding the maximum ratings can
damage the device
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Voltage at VPA, VPD
-0.3
6
V
G002 I()
Current in VPA
-10
20
mA
G003 I()
Current in VPD
-10
100
mA
G004 V()
G005 I()
Voltage at all pins except VPD
-0.3
VPD+0.3
V
Current in all I/O pins
DC current
Pulse width < 10 µs
-10
-100
10
100
mA
mA
G006 Vd()
ESD Susceptibility at all pins
HBM, 100 pF discharged through 1.5 kΩ
G007 Ptot
Permissible Power Dissipation
G008 Tj
Chip-Temperature
G009 Ts
Storage Temperature Range
2
kV
400
mW
-40
150
°C
-40
150
°C
THERMAL DATA
Operating conditions: VPA = VPD = 5 V ±10%
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
T01
Ta
Operating Ambient Temperature Range
T02
Rthja
Thermal Resistance Chip to Ambient
DFN16
Typ.
-40
Surface mounted, Thermal-Pad soldered to
approx. 2 cm² copper area on the PCB
All voltages are referenced to ground (pin VND = VNA) unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
Max.
110
40
°C
K/W
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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ELECTRICAL CHARACTERISTICS
Operating conditions: VPD, VPA = 5 V ±10%, Tj = -40. . . 125°C, IBP calibrated to 200 µA, reference is VNA = VND,
unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
101
V(VPA)
Permissible Supply Voltage at
VPA
4.5
5
5.5
V
102
V(VPD)
Permissible Supply Voltage at
VPD
4.5
5
5.5
V
103
I(VPA)
Analog Supply Current in VPA
3
8
12
mA
104
I(VPD)
Digital Supply Current in VPD
25
40
65
mA
105
Vc()hi
Clamp Voltage hi at all pins
Vc()hi = V() - V(VPD), I() = +1 mA
0.3
1.6
V
106
Vc()lo
Clamp Voltage lo at all pins
I() = -1 mA
-1.6
-0.3
107
ton()
Power-Up Time
VPD > 4 V, EEPROM Data valid
at surface of chip
20
V
ms
Hall Sensors
201
Hext
Operating Magnetic Field
Strength
202
f()
Operating Magnetic Field Frequency
203
rpm
Permissible rotation of pole wheel 16 pole pairs
32 pole pairs
with FRQ_CNV=lo
64 pole pairs
204
vmax
Permissible movement speed
205
hpac
Sensor-to-Package-Surface Dis- with DFN16-5x5 mm
tance
15
100
kA/m
7
kHz
24000
12000
6000
rpm
rpm
rpm
17
m/s
400
µm
Assembly Tolerances
301
TOLrad
Permissible Radial Displacement
0.5
mm
302
TOLtan
Permissible Tangential Displacement
0.5
mm
303
WOBrad
Permissible Excentricity of Code MPC = 0x4
MPC = 0x5, 0x6
Disc
0.06
0.1
mm
mm
Bias Current Source, Reference Voltage, Power On Reset, Clock Oscillator
401
Vbg
Bandgap Voltage
TEST = 0x1F
1.18
1.25
1.32
V
402
403
Vref
Reference Voltage
TEST = 0x1F
45
50
55
%VPA
IBM
Reference Current
CIBM = 0x0
CIBM = 0xF
IBM calibrated
-100
-370
-220
-200
-180
µA
µA
µA
404
VPDon
Turn-on Threshold VPD
(power on release)
increasing voltage at V(VPD)
3.7
4
4.3
V
405
VPDoff
Turn-off Threshold VPD
(power down reset)
decreasing voltage at V(VPD)
3
3.5
3.8
V
406
VPDhys
Hysteresis
VPDhys = VPDon - VPDoff
407
fosc
Clock Frequency
TEST=0x26, fosc = 64*f(HCLK), IBM aligned
26
30
MHz
0
10
-9
-8.5
%
%
%
70
-70
-65
mV
mV
6.5
-6.5
-6
°
°
Signal Conditioning Master and Noniusspur (x = M, N)
501 GC
Adjustable Gain Range
GC_x = 0x0
GC_x = 0x1
GC_x = 0x2
GC_x = 0x3
502 GF
Adjustable Fine Gain Range
GF_x = 0x00
GF_x = 0x20
GF_x = 0x3F
503 GX
Adjustable Gain(SIN)/Gain(COS) GX_x = 0x00
GX_x = 0x3F
GX_x = 0x7F
504 VOS
Adjustable Offset Calibration
VOS_x = 0x3F
VOS_x = 0x7F
505 PHM
Adjustable Phase Calibration
PH_M = 0x3F
PH_M = 0x7F
Master Track
0.35
22
V
4.4
7.7
12.4
20.6
1
4.4
19
9
65
6
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ELECTRICAL CHARACTERISTICS
Operating conditions: VPD, VPA = 5 V ±10%, Tj = -40. . . 125°C, IBP calibrated to 200 µA, reference is VNA = VND,
unless otherwise stated
Item
No.
506
Symbol
PHN
Parameter
Conditions
Unit
Min.
Typ.
Max.
12.5
-12.5
-12
°
°
4
4.8
Vss
Adjustable Phase Calibration
Nonius Track
PH_N = 0x3F
PH_N = 0x7F
12
507
Vampl
Signal Level Controller
chip internally, Vampl =
Vpp(PSINx)+Vpp(NSINx), ENAC =
1
3.2
508
Vae()lo
Signal Monitoring Threshold lo
Vae()lo = Vpp(PSINx)+Vpp(NSINx)
1.2
2.8
Vpp
509
Vae()hi
Signal Monitoring Threshold hi
Vae()hi = Vpp(PSINx)+VPP(NSINx)
5
6.3
Vpp
Sine-To-Digital Conversion
601
Aabs
Absolute Angular Accuracy
ideal input signals, reference to 12 Bit of sine
period
2
LSB
602
Arel
Relative Angular Accuracy
FILT = 0x2
FILT = 0x7
ideal input signals, reference to 12 Bit of sine
period, f = 1 KHz
2
1/4
LSB
LSB
16 periods, MPC = 0x4
32 periods, MPC = 0x5
64 periods, MPC = 0x6
referenced to 360° of Master sine period
10
5
2.5
DEG
DEG
DEG
0.4
V
Nonius Calculation
701 Pnon
Permissible Track deviation
Master vers. Nonius
Digital Output Port PA1..3, MTC, SCL, SDA
801
Vs()hi
Saturation Voltage hi Pins PA1..3, Vs()hi = V(VPD) - V(), I() = -4 mA
MTC
802
Vs()lo
Saturation Voltage lo
I() = 4 mA versus VND
803
Isc()hi
Short-Circuit Current hi Pins
PA1..3, MTC
V() = V(VND), 25 °C
804
Isc()lo
Short-Circuit Current lo
V() = V(VPD), 25 °C
90
mA
805
tr()
Rise Time
CL = 50 pF
60
ns
806
tf()
Fall Time
CL = 50 pF
60
ns
807
808
Ilk(PA3)
Leakage Current at PA3
MODEA=0, PA0 = hi
5
uA
f(SCL)
Frequency at SCL
normal mode
during start-up
0.4
-90
-50
50
-5
V
mA
80
60
kHz
kHz
Digital Input Port PA0..2, MTD, SCL, SDA
901
Vt()hi
Threshold Voltage hi
2
V
902
Vt()lo
Threshold Voltage lo
0.8
V
903
Vt()hys
Hysteresis
Vt()hys = Vt()hi - Vt()lo
150
mV
904
Ipu()
Pull-Up Current Pins PA0..2,
MTD
V() = 0 V . . . V(VPD)-1 V
-60
-30
-6
905
Ipu()
Pull-Up Current Pins SCL, SDA
V() = 0 V . . . V(VPD)-1 V
-750
-300
-75
µA
906
f()
Permissible Input Frequency
10
MHz
1
mA
µA
Analog/Digital Output Port PB0..3
A01
I()buf
Analog Driver Current
-1
A02
fg()ana
Analog Bandwidth
A03
Isc()hi,ana Analoge Short-Circuit Current hi
V() = V(VND)
A04
Isc()lo,ana Analoge Short-Circuit Current lo
V() = V(VPD)
A05
Rout(),ana Output Resistor, Analog Mode
I() = 1 mA
500
Ω
A06
Vs()hi,dig
Digital Saturation Voltage hi
Vs() = V(VPD) - V(), I() = -4 mA
0.5
V
A07
Vs()lo,dig
Digital Saturation Voltage lo
I() = 4 mA
0.5
A08
Isc()hi,dig
Short-Circuit Current hi
V() = V(VPD)
A09
Isc()lo,dig
Short-Circuit Current lo
V() = V(VND)
70
mA
A10
tr()
Rise Time
CL = 50 pF
50
ns
A11
tf()
Fall Time
CL = 50 pF
50
ns
A12
Ipu(PB3)
Pull-Up Current
V() = 0 V...V(VPD) - 1 V, MODEB = 0x0..0x3
-60
-6
uA
A13
Ilk()
Leakage Current
MODEB = 0x7
-5
5
uA
100
kHz
-1.5
1.5
-60
mA
mA
-35
45
-30
V
mA
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OPERATING CONDITIONS: Multiturn Interface
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
Multiturn Interface (Figure 1)
I001 tMTC
Clock Period
I002 ts MD
Setup Time:
Data valid before MTC hi→lo
50
6.4
ns
I003 th MD
Hold Time:
Data stable after MTC hi→lo
50
ns
I004 ttos
Timeout
I005 tcycle
Cycle Time
20
CHK_MT=1
1
ttos
tMTC
MTC
MTD
us
MSB
tsMD
MSB-1
MSB-2
LSB+1
LSB
thMD
tcycle
Figure 1: Timing muliturn interface, MODE_MT/=0
us
5
ms
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OPERATING CONDITIONS: I/O Interface
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
SPI-Interface (Figure 2)
I101 TSCK
Permissible Clock Period
I102 tNCS
Setup Time:
NCS lo before SCK hi → lo
see Elec. Char. No.: 906
1/f()
ns
I103 tp1
Propagation Delay:
MISO hi after NCS lo → hi
I104 tIS
Setup Time:
MOSI stable before SCK lo → hi
30
ns
I105 tSI
Hold Time:
MOSI stable after SCK lo → hi
30
ns
I106 tp2
Propagation Delay:
MISO stable after SCK hi → lo
I107 tCC
Wait Time:
between NCS lo → hi and NCS hi → lo
50
ns
30
ns
30
ns
500
ns
BiSS-Interface (Figure 3)
I108 ttos
Timeout
80
20000
ns
I109 tMAS
Permissible Clock Period
100
2 x ttos
ns
I110 tMASh
Clock Signal Hi Level Duration
50
ttos
ns
I111 tMASl
Clock Signal Lo Level Duration
50
ns
SSI-Interface (Figure 4)
I112 ttos
Timeout
I113 tMAS
Permissible Clock Period
250
2 x ttos
ns
I114 tMASh
Clock Signal Hi Level Duration
125
ttos
ns
I115 tMASl
Clock Signal Lo Level Duration
125
PA0: NCS
tNCS
20000
tIS
tSI
TSCK
tCC
PA1: SCK
PA2: MOSI
tp2
tp1
PA3: MISO
Figure 2: Timing SPI interface
tMAS
PA1:MA
PA3:SLO
START
tMASh tMASl
DATA
DATA
ttos
ttos
Figure 3: Timing BiSS interface
ns
ns
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tMAS
PA1:MA
PA3:SLO
DATA
DATA
DATA
DATA
ttos
tMASh tMASl
Figure 4: Timing SSI interface
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PRINCIPLE OF MEASUREMENT
MASTER
16
2
15
3
14
4
13
5
12
6
11
7
10
8
NONIUS
TOLrad
9
TOLtang
CHIP CENTER
POLEDISK CENTER
AXIS CENTER
DIAMETER MASTER
1
DIAMETER NONIUS
An absolute position measuring system consists of a
magnetized code carrier and an iC-MU which integrates Hall sensors for signal scanning, signal conditioning, and interpolation in one single device. iC-MU
can be used in rotative and linear measurement systems.
WOBrad
Figure 5: Rotative position measurement system
Figure 6: Linear position measurement system
Rotative measuring system
The magnetic code carrier consists of two magnetic
encoder tracks. The outer track comprises an even
number of alternately magnetized poles and is used
for high-precision position definition. This is thus called
the master track. The second inside track has one pole
pair less than the outer track and is thus referred to as
the nonius track. This track is used to calculate an absolute position within one revolution of the pole disc.
To this end, the difference in angle between the two
tracks is calculated.
Number of pole pairs
Master track diameter
[mm]
Chip center to axis center
[mm]
Nonius track diameter
[mm]
Master track pole width
[mm]
Nonius track pole width
[mm]
16
32
64
13,04 26,08 52,15
4,72 11,24 24,28
5,84 18,88 44,95
1,28 1,28 1,28
0,61 0,96 1,12
Table 6: Pole disc dimensions in mm for rotative systems
Figure 7: Definition of system measurements
The Hall sensors of iC-MU span one pole pair of the
code carrier. The pole width of the master track is
defined by the distance of the Hall sensors and is
1.28 mm. The position of the sensors on the upper
chip edge has been optimized for 32 pole pairs. Accordingly, the Hall sensors generate a periodic sine
and cosine signal with a cycle length of 2.56 mm. The
scan diameter can be computed from the number of
pole pairs. The diameter of the pole disc although depends on other mechanical requirements and should
be approx. 3 mm greater than the scan diameter. A
specific diameter for the master and nonius tracks is
derived depending on the number of configured pole
pairs.
The distance between the hall sensors of the nonius track and the master track is stipulated as being
3.6 mm by the evaluation device. The scan diameters
of the nonius track can be seen in Table 6.
Linear measuring system
With a linear nonius system the pole width of the master track is also 1.28 mm. The pole width of the nonius
track is defined by the number of pole pairs with
pnonius = 1.28 mm ∗
number of polesmaster
number of polesnonius
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Number of pole pairs
16
32
64
Master track pole width [mm] 1,28 1,28 1,28
Nonius track pole width [mm] 1,365 1,321 1,300
Table 7: Linear scales, pole widths in mm
iC-MU OFF-AXIS NONIUS ENCODER
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CONFIGURATION PARAMETERS
Analog parameters (valid for all channels)
CIBM:
Bias current settings (p. 19)
ENAC:
Amplitude control unit activation (p. 20)
Signal conditioning
GC_M:
Master gain range selection (p. 19)
GF_M:
Master gain (p. 19)
GX_M:
Master cosine signal gain adjustment
(p. 19)
VOSS_M:
Master sine offset adjustment (p. 20)
VOSC_M:
Master cosine offset adjustment (p. 20)
PH_M:
Master phase adjustment (p. 20)
GC_N:
Nonius gain range selection (p. 19)
GF_N:
Nonius gain (p. 19)
GX_N:
Nonius cosine signal gain adjustment
(p. 19)
VOSS_N:
Nonius sine offset adjustment (p. 20)
VOSC_N:
Nonius cosine offset adjustment (p. 20)
PH_N:
Nonius phase adjustment (p. 20)
Digital parameters
TEST:
Adjustment modes/iC-Haus test modes
(p. 21)
CRC16:
EEPROM configuration data checksum
(p. 22)
CRC8:
EEPROM offset and preset data
checksum (p. 22)
NCHK_CRC: Cyclic check of CRC16 and CRC8
(p. 22)
BANKSEL: Serial Access: Bankregister (p. 45)
RPL:
Register Access Control (p. 49)
RPL_RESET: Serial Access: Register for reset
register access restriction (p. 49)
EVENT_COUNT: Serial Access: Eventcounter (p. 53)
HARD_REV: serial address: revision code (p. 48)
Configurable I/O interface
MODEA:
I/O port A configuration (p. 25)
MODEB:
I/O port B configuration (p. 25)
PA0_CONF:
Configurable commands to pin PA0 A
(p. 54)
ROT:
Direction of rotation (p. 44)
OUT_MSB: Output shift register configuration: MSB
used bits (p. 27)
OUT_LSB: Output shift register configuration: LSB
used bits (p. 27)
OUT_ZERO: Output shift register configuration:
number of zeros inserted after the used
bits and before an error/warning (p. 27)
MODE_ST: Data output (p. 26)
GSSI:
Gray/binary data format (p. 30)
RSSI:
Ring operation (p. 30)
Multiturn interface
MODE_MT: Multiturn mode (p. 38)
SBL_MT:
Multiturn synchronization bit length
(p. 38)
CHK_MT:
Cyclic check of the multiturn value
(p. 39)
GET_MT:
Access Multiturn-Sensor via MT-Sensor
via I/O-Interface (S. 41)
ROT_MT:
Direction of rotation external multiturn
(p. 39)
ESSI_MT:
Error Bit external multiturn (p. 39)
SPO_MT:
Offset external multiturn (p. 39)
Converter and nonius calculation
FILT:
Digital filter settings (p. 35)
MPC:
Master period count (p. 35)
LIN:
Linear scanning (p. 36)
SPO_x:
Offset of nonius to master
(x=BASE,0-14) (p. 36)
NCHK_NON: Cyclic check of the nonius value (low
active) (p. 37)
Incremental output ABZ, STEP/DIR and CW/CCW
RESABZ:
Incremental interface resolution
ABZ,STEP-DIR,CW/CCW (p. 42)
LENZ:
Index pulse length (p. 43)
INV_A:
A/STEP/CW signal inversion (p. 42)
INV_B:
B/DIR/CCW signal inversion (p. 42)
INV_Z:
Z/NCLR signal inversion (p. 42)
SS_AB:
System AB step size (p. 43)
FRQAB:
AB output frequency (p. 43)
CHYS_AB: Converter hysteresis (p. 43)
ENIF_AUTO: Incremental interface enable (p. 43)
UVW commutation signals
PPUVW:
Number of commutation signal pole
pairs (p. 44)
PP60UVW: Commutation signal phase position
(p. 44)
OFF_UVW: Commutation signal start angle (p. 44)
OFF_COM: serial address: absolute position offset
for UVW calculation engine changed by
nonius (S. 44)
Status/command registers and error monitoring
CMD_MU:
serial address: command register
(p. 52)
STATUS0:
serial address: status register 0 (p. 50)
STATUS1:
serial address: status register 1 (p. 50)
CFGEW:
Error and warning bit configuration
(p. 50)
EMTD:
Minimum error message duration
(p. 51)
ACC_STAT: Outputconfiguration status register
(S. 50)
ACRM_RES: Automatic reset with master track
amplitude errors (p. 37)
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BiSS-ID/Profile-ID
REVISION: BiSS revision ID (p. 18)
MANUFACTURER: BiSS manufacturer ID (p. 18)
EDSBANK:
BiSS-EDSBANK (p. 18)
PROFILE_ID: BiSS profile ID (p. 18)
SERIAL:
BiSS serial number (p. 18)
Preset function
OFF_ABZ: Offset Absolute position offset for ABZ
calculation engine (p. 56)
OFF_POS: serial address: absolute position offset
for ABZ calculation engine changed by
nonius/multiturn (p. 56)
PRES_POS: Preset position for ABZ section (p. 56)
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Rev B1, Page 16/59
REGISTER ASSIGNMENTS (EEPROM)
scope of eeprom register view
access
via
EEPROM
N.B.:
ADDR is used in register tables to
indicate the address of the
corresponding parameter. If the
addressing scheme differs
between the EEPROM and the
serial interface ADDR. SER is
used to indicate the addressing
through the serial interface.
ADDR
iC-MU
SPI
BiSS
SSI
Figure 8: Scope of register mapping EEPROM
Register assignment (EEPROM)
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Signal Conditioning
0x00
GC_M(1:0)
GF_M(5:0)
GX_M(6:0)
VOSS_M(6:0)
VOSC_M(6:0)
PH_M(6:0)
0x01
0x02
0x03
0x04
0x05
0x06
CIBM(3:0)
ENAC
GC_N(1:0)
GF_N(5:0)
GX_N(6:0)
VOSS_N(6:0)
VOSC_N(6:0)
PH_N(6:0)
0x07
0x08
0x09
0x0A
Digital Parameters
MODEB(2:0)
0x0B
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
MODEA(2:0)
CFGEW(7:0)
0x0C
NCHK_CRC NCHK_NON
ACRM_RES
EMTD(2:0)
ESSI_MT(1:0)
ROT_MT
LIN
FILT(2:0)
SPO_MT(3:0)
MPC(3:0)
GET_MT
CHK_MT
SBL_MT(1:0)
MODE_MT(3:0)
OUT_ZERO(2:0)
OUT_MSB(4:0)
GSSI
RSSI
MODE_ST(1:0)
OUT_LSB(3:0)
RESABZ(7:0)
RESABZ(15:8)
ROT
SS_AB(1:0)
ENIF_AUTO
FRQAB(2:0)
LENZ(1:0)
CHYS_AB(1:0)
PP60UVW
INV_A
INV_B
RPL(1:0)
PPUVW(5:0)
ACC_STAT
TEST
TEST(7:0)
0x18
TRACK-OFFSET
0x19
0x1A
SPO_0(3:0)
SPO_2(3:0)
SPO_BASE(3:0)
SPO_1(3:0)
INV_Z
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Rev B1, Page 17/59
OVERVIEW
Addr
Bit 7
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
Bit 6
Bit 5
SPO_4(3:0)
SPO_6(3:0)
SPO_8(3:0)
SPO_10(3:0)
SPO_12(3:0)
SPO_14(3:0)
Bit 4
Bit 3
CRC16
CRC16(15:8)
CRC16(7:0)
0x21
0x22
OFFSET/PRESET
OFF_ABZ(3:0)
0x23
OFF_ABZ(11:4)
OFF_ABZ(19:12)
OFF_ABZ(27:20)
OFF_ABZ(35:28)
0x24
0x25
0x26
0x27
OFF_UVW(3:0)
0x28
OFF_UVW(11:4)
0x29
PRES_POS(3:0)
0x2A
PRES_POS(11:4)
PRES_POS(19:12)
PRES_POS(27:20)
PRES_POS(35:28)
0x2B
0x2C
0x2D
0x2E
CRC8
CRC8(7:0)
0x2F
PA0_CONF
PA0_CONF(7:0)
0x30
BiSS Profile and Serial number
EDSBANK(7:0) = 0x01
PROFILE_ID(7:0)
PROFILE_ID(15:8)
SERIAL(7:0)
SERIAL(15:8)
SERIAL(23:16)
SERIAL(31:24)
0x31
0x32
0x33
0x34
0x35
0x36
0x37
Device Identification
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Notes:
REVISION(7:0)
REVISION(15:8)
REVISION(23:16)
REVISION(31:24)
REVISION(39:32)
REVISION(47:40)
MANUFACTURER(7:0)
MANUFACTURER(15:8)
Register assignment for serial access through SPI/BiSS s.p. 45
Table 8: Register assignment (EEPROM)
Bit 2
Bit 1
SPO_3(3:0)
SPO_5(3:0)
SPO_7(3:0)
SPO_9(3:0)
SPO_11(3:0)
SPO_13(3:0)
Bit 0
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iC-MU OFF-AXIS NONIUS ENCODER
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Rev B1, Page 18/59
Special BiSS registers
For further information on parameters, see
BiSS Interface Protocol Description (C Mode)
www.ichaus.de/product/iC-MU.
EDSBANK(7:0)
Addr. 0x31; bit 7:0
EDSBANK(7:0)
Addr. SER:0x41; bit 7:0
Code
Description
0x00
...
0xFF
EDSBANK: has to be set to 0x01 for iC-MU
Table 11: EDSBANK: Start of EDS-part
REVISION(7:0)
Addr. 0x38; bit 7:0
REVISION(15:8)
Addr.
Addr.
Addr.
Addr.
Addr.
0x39;
0x3A;
0x3B;
0x3C;
0x3D;
Addr.
Addr.
Addr.
Addr.
SER:0x78; bit 7:0
Code
Description
SER:0x79; bit 7:0
0x0000
...
0xFFFF
Profile ID
REVISION(23:16)
REVISION(31:24)
REVISION(39:32)
REVISION(47:40)
REVISION(7:0)
REVISION(15:8)
REVISION(23:16)
REVISION(31:24)
REVISION(39:32)
REVISION(47:40)
Code
bit 7:0
bit 7:0
bit 7:0
bit 7:0
bit 7:0
SER:0x7A; bit 7:0
SER:0x7B; bit 7:0
Addr. 0x32; bit 7:0
Addr. 0x33; bit 7:0
PROFILE_ID(7:0)
Addr. SER:0x42; bit 7:0
PROFILE_ID(15:8)
Addr. SER:0x43; bit 7:0
Addr. SER:0x7C; bit 7:0
Addr. SER:0x7D; bit 7:0
Table 12: PROFILE_ID: Profile ID
Description
0x000000000000
...
PROFILE_ID(15:8)
PROFILE_ID(7:0)
Device ID
0xFFFFFFFFFFFF
Table 9: REVISION: Device ID
MANUFACTURER(7:0)
MANUFACTURER(15:8)
MANUFACTURER(7:0)
MANUFACTURER(15:8)
Addr. 0x3E; bit 7:0
Addr. 0x3F; bit 7:0
Addr. SER:0x7E; bit 7:0
Addr. SER:0x7F; bit 7:0
Code
Description
0x0000
...
Manufacturer ID
SERIAL(7:0)
SERIAL(15:8)
Addr. 0x34; bit 7:0
Addr. 0x35; bit 7:0
SERIAL(23:16)
SERIAL(31:24)
Addr. 0x36; bit 7:0
Addr. 0x37; bit 7:0
SERIAL(7:0)
Addr. SER:0x44; bit 7:0
SERIAL(15:8)
SERIAL(23:16)
SERIAL(31:24)
Addr. SER:0x45; bit 7:0
Addr. SER:0x46; bit 7:0
Addr. SER:0x47; bit 7:0
Code
Description
0x00000000
...
Serial number
0xFFFFFFFF
0xFFFF
Table 10: MANUFACTURER: Manufacturer ID
Table 13: SERIAL: Serial number
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SIGNAL CONDITIONING FOR MASTER AND NONIUS CHANNELS: x = M,N
Bias current source
The calibration of the bias current source in test mode
TEST=0x1F is prerequisite for adherence to the given
electrical characteristics and also instrumental in the
determination of the chip timing (e.g. SCL clock frequency). For the calibration the current out of pin PB2
into VNA must be measured, and register bits CIBM
changed until the current is calibrated to 200 µA.
GF_M(5:0)
GF_N(5:0)
Addr. 0x00; bit 5:0
Addr. 0x06; bit 5:0
Code
Fine gain
0x00
0x01
1,000
1,048
...
0x3F
· GF _x)
exp( ln(20)
64
19,08
Table 16: Hall signal amplification
VOSS_x
CIBM(3:0)
Addr. 0x05; bit 3:0
Code
Description
0x0
-40 %
...
0x8
0x9
...
0xF
...
0%
+5 %
...
+35 %
X
X
GC_x
GF_x
HALL
ENAC
X
HALL
GC_M(1:0)
GC_N(1:0)
Addr. 0x00; bit 7:6
Addr. 0x06; bit 7:6
Code
Coarse gain
0x0
0x1
0x2
0x3
4.4
7.8
12.4
20.7
GX_x
PSIN_x
PH_x
+
X
X
+
Table 14: Calibrating the bias current
Gain settings
iC-MU has signal conditioning features that can compensate for signal and adjustment errors. The Hall signals are amplified in two stages. The gain of both amplification stages is automatically controlled when the
bit ENAC is set to ’1’. The register bits GC_x and GF_x
have no effect. In the case of a deactivated automatic
gain control (ENAC=’0’) the gain must be set manually.
First, the approximate field strength range must be selected in which the Hall sensor is to be operated. The
first amplifier stage can be programmed in the following ranges:
+
PCOS_x
VOSC_x
Figure 9: Conditioning of hall voltages
Register GX_x enables the sensitivity of the sine channel in relation to the cosine channel to be corrected.
The amplitude of the cosine channel is adapted to the
amplitude of the sine channel. The cosine amplitude
can be corrected within a range of approx. ±10 %.
GX_M(6:0)
GX_N(6:0)
Addr. 0x01; bit 6:0
Addr. 0x07; bit 6:0
Code
Description
0x00
1,000
0x01
...
0x3F
0x40
...
0x7F
1,0015
exp( ln(20)
· GX _x)
2048
1,0965
0,9106
exp(− ln(20)
· (128 − GX _x))
2048
0,9985
Table 17: Cosine gain adjustment
Table 15: Selection of the Hall signal amplification
range
The second amplifier stage can be varied within a wide
range.
The integrated amplitude control unit can be activated
using bit ENAC. In this case the differential signal amplitude is regulated to 2 Vpp; the values of GF_x have
no effect here.
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Rev B1, Page 20/59
ENAC
Addr. 0x05; bit 7
Code
Description
0
Amplitude control not active (constant)
VOSS_M(6:0)
VOSS_N(6:0)
VOSC_M(6:0)
1
Amplitude control active (sin2 + cos2 )
VOSC_N(6:0)
Addr. 0x02; bit 6:0
Addr. 0x08; bit 6:0
Addr. 0x03; bit 6:0
Addr. 0x09; bit 6:0
Code
Description
Table 18: Amplitude control unit activation
0x00
0x01
...
0x3F
0 mV
1 mV
...
63 mV
After startup the gain is increased until the set amplitude is obtained. If the input amplitude is altered by the
distance between the magnet and sensor being varied,
or if there is a change in the supply voltage or temperature, the gain is automatically adjusted. The conversion of the sine signals into high-resolution quadrature
signals thus always takes place at optimum amplitude.
0x40
0x41
...
0x7F
0 mV
-1 mV
...
-63 mV
PSIN_x
PSx
SIN
DIG
PCOS_x
PSIN 500mV/DIV
PCOS 500mV/DIV
PCx
100µs/DIV
2Vss
PSM 200mV/DIV
PCM 200mV/DIV
100µs/DIV
0.5Vss
Table 19: Sine and cosine offset adjustment
Phase adjustment
The phase between sine and cosine is adjusted by
PH_x (6:0). The compensation range for the master
track is approx. ±6°. The compensation range for the
nonius track is nearly twice as large and is approx.
±11.25°.
PH_M(6:0)
Code
Addr. 0x04; bit 6:0
Function
0x00
...
0x3F
0°
+ 6°*PH_M/63
+ 6°
0x40
...
0x7F
0°
- 6 °*(PH_M-64)/63
-6°
Table 20: Master track phase adjustment
Figure 10: Definition of differential amplitude
PH_N(6:0)
Code
Offset compensation
If there is an offset in the sine or cosine signal, possibly
caused by a magnet not being precisely adjusted, for
instance, this can be corrected by registers VOSS_x
and VOSC_x. The output voltage can be shifted in
each case by ±63 mV in order to compensate for the
offset.
Addr. 0x0A; bit 6:0
Function
0x00
0°
...
0x3F
0x40
...
0x7F
+ 11,25°*PH_N/63
+ 11,25°
0°
- 11,25 °*(PH_N-64)/63
- 11,25 °
Table 21: Nonius track phase adjustment
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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ANALOG SIGNAL CONDITIONING FLOW: x = M,N
For the purpose of signal conditioning iC-MU has several settings that make internal reference values and
the amplified Hall voltages of the individual sensors accessible at the outer pins of PORT B for measurement.
This allows the settings of the amplifier (GC_x, GF_x),
the amplitude ratio of cosine to sine signal (GX_x), and
the offset (VOSS_x , VOSC_x) and phase (PH_x) of
the master (x = M) and nonius tracks (x = N) to be directly observed on the oscilloscope.
Test mode can be programmed using register TEST
(address 0x18). The individual test modes are listed in
Table 22 and 23.
N.B.:
MODEB must be set to 0x0 before selecting a test
mode.
Test Mode output signals
Modus
TEST Pin PB0
Normal
0x00
Analog REF 0x1F VREF
Digital CLK
0x26 -
Pin PB1
Pin PB2
Pin MTC
VBG
-
IBM
-
CLK
The output signals of the signal path are available as
differential signals with a mean voltage of half the supply voltage and can be selected for output according to
Table 23.
2. Positioning of the sensor
Next, the sensor should be adjusted in relation to the
magnetic code carrier. The value of MPC (Table 48)
has to be selected according to the magnetic code carrier. The register values for VOSS_x, VOSC_x, GX_x
and PH_x are set to 0. The chip position will now be
displaced radially to the magnetic code carrier until the
phase shift between the sine and cosine is 90°.
Depending on the mounting of the system it may be
necessary to displace iC-MU tangentially to the magnetic code carrier to adjust the amplitude between the
sine and cosine signals.
A fine adjustment of the analog signals is made with
the registers described in the chapter SIGNAL CONDITIONING FOR MASTER AND NONIUS CHANNELS
page 19.
Table 22: Test modes for signal conditioning
The adjustment should be made in the order:
1. Conditioning the BIAS current
First of all, the internal bias is set. The BIAS current is adjustable in the range of -40 % to +35% to
compensate variations of this current and thus differences in characteristics between different iC-MU (e.g.
due to manufacturing variations). The nominal value
of 200 µA is measured as a short-circuit current at pin
PB2 referenced to VNA in test mode 0x1F.
Additionally various internal reference voltages are
available for measuring in this test mode. VREF corresponds to half the supply voltage (typically 2.5 V) and
is used as a reference voltage for the hall sensor signals. VBG is the internal bandgap reference (1.25 V)
Alternatively the frequency at Pin MTC can be adjusted
to 380 kHz using register value CIBM in test mode
0x26, if an analog measuring of the current is not possible.
Test mode output signals
Modus
TEST Pin PB0
Normal
0x00
Analog Master
0x01 PSM
Analog CNV_M 0x03 PSIN_M
Analog Nonius
0x11 PSN
Analog CNV_N
0x13 PSIN_N
Pin PB1
Pin PB2
Pin PB3
NSM
NSIN_M
NSN
NSIN_N
PCM
PCOS_M
PCN
PCOS_N
NCM
NCOS_M
NCN
NCOS_N
Table 23: Testmodes and available output signals
1. phase
2. amplitude
3. offset
3.a Test modes analog master and analog nonius
In these test modes the amplified, conditioned signals
are presented to port B. These signals can be charged
with a maximum of 1 mA and should not exceed a differential voltage of 0.5 Vpp.
3.b Test mode CNV_x
In this test mode the sensor signals are present at port
B as they are internally for further processing on the
interpolator. The achievable interpolation accuracy is
determined by the quality of signals PSIN_x/NSIN_x
and PCOS_x/NCOS_x and can be influenced in this
test mode by adjustment of the gain, amplitude ratio,
offset, and phase. The signals must be tapped at high
impedance.
4. Trackoffset SPON
After the analog adjustment of the master and nonius track the absolute system must be electrically calibrated for maximum adjustment tolerance. See page
36 ff.
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I2C INTERFACE AND STARTUP BEHAVIOR
I2C interface / CRC
The multimaster-I2C interface enables read and write
access to a serial EEPROM which uses an addressing scheme equal to an 24C01 EEPROM (e.g. 24C02,
256 bytes, 5V type with a 3.3V function).
The configuration data in the EEPROM in address
range 0x00 to 0x20 and 0x30 to 0x3F is checked with
a 16 bit CRC (CRC16). The start value for the CRC16
calculation is 1.
CRC16(7:0)
CRC16(15:8)
CRC16(15:0)
Addr. 0x21; bit 7:0
Addr. 0x22; bit 7:0
Addr. SER: no access;
Code
Meaning
...
CRC formed with CRC polynomial 0x11021*)
Notes:
*) x16 + x12 + x5 + 1, start value 0x1
This is equivalent to CRC-CCITT/CRC-16
Table 24: EEPROM data checksum
The offset and preset position for iC-MU’s preset sequence is not part of the configuration data area. The
data is located in address range 0x23 to 0x2E of the
EEPROM and is checked separately with a 8-bit CRC
(CRC8). The start value for the CRC8 calculation is 1.
CRC8(7:0)
CRC8(7:0)
Addr. 0x2F; bit 7:0
Addr. SER: no access;
Code
Meaning
...
CRC formed with CRC polynomial 0x197*)
Notes:
*) x8 + x7 + x4 + x2 + x1 + 1, start value 0x1
Table 25: Offset/preset data checksum
iC-MU calculates CRC8 and CRC16 automatically
when writing the configuration to the EEPROM. The
serial interface does not allow to access the CRC8
and CRC16 values. CRC16 and CRC8 are checked on
startup. A cyclic check during operation can be configured with NCHK_CRC. With the command CRC_VER
(s. Tab. 97) a CRC check can be explicitly requested.
An error is signaled by status bit CRC_ERR.
NCHK_CRC
Addr. 0x0D; bit 6
Code
Meaning
0
1
cyclical CRC check of CRC16 and CRC8
no cyclical CRC check
Table 26: Zyclic CRC check
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Startup behavior
After switching on the power (power-on reset) iC-MU
reads the configuration data out from the EEPROM. If
an error occurs during the EEPROM data readout (a
CRC error or communication fault with the EEPROM),
the current read-in is aborted and restarted. Following
a third faulty attempt the read-in process is terminated
and the internal iC-MU configuration register initialized
as in Tab. 27. The addresses are referenced to the
register allocation for an register access through the
serial interface s. p. 45.
N.B.: After the third faulty attempt to read-in the configuration data from the EEPROM the default value of
MODEA is set to BiSS or SPI depending on the logic
level at pin PA0 (PA0=0 → BiSS, PA0=1 → SPI).
The amplitude control is started after the read-in of the
EEPROM. To determine the absolute position a nonius
calculation is started. An external multiturn is read-in if
configured. If there is an error the multiturn read-in is
repeated until no multiturn error occurs. The Statusbit
MT_ERR is set in this case, register communication
is possible. The ABZ/UVW-converter is only started
if there was no CRC_ERR, EPR_ERR, MT_ERR or
MT_CTR error during startup. The startup behaviour
is described in picture 11.
Default values
Bank
Addr.
(serial
access)
value
Meaning
0
0x05
0x88
Amplitude control active
(ENAC=1), CIBM = 0%
0
0x0B
0x02
PA0=0 → BiSS interface
(MODEA=0x2),
ABZ Incremental
(MODEB=0x0)
PA0=1 → SPI interface
(MODEA=0x0),
ABZ Incremental
(MODEB=0x0)
0
0x00
0
0x0E
0x06
FILTER activated
0
0x0F
0x05
32 pole pairs master
track
0
0x10
0x00
no Multiturn,
Noniuscheck active
0
0x11
0xA5
5 bit Noniusinformation,
5 Zeros added
0
0x12
0x00
output with max.
resolution
0
0
0x13
0x14
0xFF
0x0F
resolution 16384 edges
0
0x15
0x13
up to 12000 rpm
(SS_AB=0x1),
266ns minimum edge
distance
0
0x16
0x10
90° Index, 0.08°
Hysteresis
0
0x17
0x02
1 pole pair Polpaar
commutation
-
0x78
0x4D
'M
-
0x79
0x55
'U
-
0x7A
HARD_REV
s. Tab. 87
-
0x7E
0x69
'i
-
0x7F
0x43
'C
Notes:
all other registers are preset with 0
Register assignment for register access through
serial interface s. S. 45
Table 27: Default configuration without the EEPROM
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startup
read EEPROM
(max 3 times on error)
no
after last try
EEPROM ok?
yes
set EEPROM Error:
CRC_ERR or EPR_ERR
no
yes
PA0 == 0?
set MODEA=0x00 (SPITRI)
set MODEA=0x02 (BiSS)
startup amplitude control
startup amplitude control
startup absolute interface
startup absolute interface
N.B.:
to startup incremental interface
after CRC_ERR or EPR_ERR
use command ABS_RESET
registercommunication
possible
startup multiturn interface
yes startup multiturn
ok?
startup incremental interface
normal operation
Figure 11: Startup behavior
no
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CONFIGURABLE I/O INTERFACE
Setting the interfaces
iC-MU has several configurable output modes which
can be set using parameters MODEA and MODEB.
The pins at port A are set with MODEA. The choice
of a serial interface at port A has also effect on the output of error and warning bits in the serial protocol see
Table 31.
N.B.:
With an empty EEPROM or after the third faulty attempt to read-in the configuration data from the EEPROM the default value of MODEA is set to BiSS or
SPI depending on the logic level at pin PA0 (PA0=0
→ BiSS, PA0=1 → SPI).
MODEA(2:0)
Addr. 0x0B; bit 2:0
Code
PA0
PA1
PA2
PA3
Function
0x0
0x1
0x2
0x3
0x4
NCS
NCS
SCLK
SCLK
MA
A
MA
MOSI
MOSI
SLI
B
SLI
MISO
MISO
SLO
Z
SLO
SPITRI
SPI
BiSS
ABZ *)
SSI
0x5
0x6
0x7
NPRES
MA
MA
MA
SLI
SLI
SLI
SLO
SLO
SLO
SSI+ERRL
SSI+ERRH
ExtSSI
NPRES
NPRES
NPRES
NPRES
NPRES
Note: *) to save this configuration in the EEPROM see command
SWITCH page 52 ff.
Table 28: Port A configuration
The pins at port B are set with MODEB.
MODEB(2:0)
Addr. 0x0B; bit 6:4
Code
PB0
PB1
PB2
PB3
Function
0x0
0x1
0x2
A
U
STEP
B
V
DIR
Z
W
NCLR
NER
NER
NER
ABZ
UVW
Step/Direction
0x3
CW
CCW
NCLR
NER
0x4
NSN
PSN
PCN
NCN
0x5
NSM
PSM
PCM
NCM
CW/CCW
Incremental
SIN/COS
Nonius
SIN/COS
Master
0x6
0x7
-
-
-
-
reserved
tristate
Table 29: Port B configuration
N.B.:
It is not possible to select ABZ at port A and ABZ,
Step/Direction or CW/CCW at port B simultaneously.
In operating modes ABZ, UVW, step/direction, and
CW/CCW the position is output incrementally. In setting SIN/COS Master the master track analog signal is
switched directly to the analog drivers. The signals of
the nonius track are available on the drivers with setting SIN/COS Nonius.
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MODE_ST selects data
of Output Shift Register
MODE_ST=0x0
Internal Absolute Data
MSB
MT
LSB MSB
MT MPC
37 37..29
26..18 25..17
MODE_ST=0x1
Internal FlexCount ® Data
37
MODE_ST=0x2
Internal Raw Data
by
B
O it s
U el
T_ ec
LS ted
B
B
O it s
U el
T_ ec
M ted
SB b
y
Serial interface
Configuring the data format and data length
LSB MSB
MPC MAS
14
13
0
MSB
ABZ
LSB
ABZ
17
0
MSB
NON
37
LSB
MAS
LSB MSB
NON MAS
27
16
15
14
LSB
MAS
13
0
OUT_LSB
OUT_MSB
OUT_ZERO
MODEA
Output Shift Register
PA3
MSB
LSB
0
0
ERR WRN
PA2
shift direction
Figure 12: Determining the output data length
The structure of the output shift register is shown in
Figure 12. The abbreviation MT stands for the multiturn data, MPC is short for the number of master periods in bit, ABZ for the data whose resolution is specified by the parameter RESABZ (Table 67), NON for the
data of the nonius track and MAS for the data of the
master track. The numbering of the user data starts
at the LSB with zero. OUT_MSB and OUT_LSB determine which part of the user data is output by the output
shift register.
MODE_ST selects the type of user data to be output
through the output shift register.
Data length = 13 + OUT_MSB - OUT_LSB + OUT_ZERO +
optional ERR/WRN (depending on MODEA)
There is an exception for the calculation of the output
data length. If parameter MPC=12 and OUT_LSB = 0,
the number of output bits is given by:
data_length_2 = OUT_MSB + OUT_ZERO + ERR/WRN (depending on MODEA) - 2
MODEA(2:0)
Function
MODE_ST(1:0)
Addr. 0x12; bit 5:4
Code
Description
0x0
0x1
0x2
0x3
output absolute position
output position in user resolution*) (Flexcount®)
output raw-data of Master- and Noniustrack
reserved
Note:
*) resolution defined by RESABZ (Table 67)
Table 30: Selection of output data
The number of output bits is determined by parameters OUT_MSB, OUT_LSB, OUT_ZERO and the error/warning bits (see Figure 12 and Table 31):
SPI
BiSS
SSI
SSI+ERRL
SSI+ERRH
ExtSSI
Addr. 0x0B; bit 2:0
Error
low active
high active
Warning
low active
high active
x
x
-
x
-
-
x
x
-
x
-
Table 31: MODEA: error/warning-bit within serial protocols
OUT_MSB configures the bit of the user data which is
output as MSB at pin PA3.
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OUT_MSB(4:0)
Addr. 0x11; bit 4:0
Code
Description
0x00
MSB = Bit 13
0x01
...
0x18
MSB = Bit 14
...
MSB = Bit 37
configured. Parameter OUT_ZERO can be used to
achieve multiples of 8 bits when sensor data is output
through the SPI interface.
OUT_ZERO(2:0)
Table 32: Selection of shift register MSB
OUT_LSB determines the LSB of the user data being
output through the output shift register.
Addr. 0x11; bit 7:5
Code
Description
0x0
0x1
...
no additional ’0’ Bit
1 additional ’0’ Bit
...
0x7
7 additional ’0’-Bits
Table 34: Selection of additional ZEROs
OUT_LSB(3:0)
Addr. 0x12; bit 3:0
Code
Condition
Description
0x0
MPC = 12,
OUT_MSB > 0x02
MPC 6= 12
LSB = Bit 16
LSB = Bit 0
0x1
0x2
...
0xD
-
LSB = Bit 1
LSB = Bit 2
...
LSB = Bit 13
0xE
0xF
OUT_MSB > 0x00
OUT_MSB > 0x01
LSB = Bit 14
LSB = Bit 15
Table 33: Selection of shift register LSB
With OUT_ZERO additional zeros to be inserted between the user data and the error/warning bit can be
The direction of rotation can be inverted with parameter ROT. The parameter affects the output of the data
word through the serial interface in MODE_ST=0x0
and 0x1, the ABZ-interface and the UVW-interface.
ROT
Addr. 0x15; bit 7
Code
Description
0
1
no inversion of direction of rotation
inversion of rotation
Note:
no effect in MODE_ST = 2 (raw-data) for the data
output through the serial interface
Table 35: Inversion of the direction of rotation (for MT
and ST data)
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BiSS C interface
0
0
ERR WRN
Zero bits
busy
OUT
cycle
Figure 13: Example of BiSS line signals
MODEA
Code
Description
0x2
BiSS-C
Table 36: MODEA: BiSS
The BiSS C interface has an adaptive sensor data
timeout. Data is output in binary form. The error and
warning bit is low active. Transmission of sensor and
register data is implemented. iC-MU needs no processing time therefore tbusy is one master clock cycle.
For further information regarding the BiSS-C-protocol
visit www.biss-interface.com.
In BiSS protocol iC-MU uses fixed CRC polynomials, see Table 37. The singlecycle data (SCD), i.e.
the primary data which is newly generated and completely transmitted in each cycle, contains the position
data (optional multiturn + singleturn) and the error and
warning bit. The CRC value is output inverted.
datachannel*)
CRC
HEX Code
Polynomial
SCD
(sensor)
CDM, CDS
(register)
0x43
x6 +x1 +x0
0x13
x4 +x1 +x0
Note:
*) explanation s. BiSS-C specification
Table 37: BiSS CRC polynomials
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SSI interface
ERR
out
cyle
Figure 14: Example of SSI line signals (MODEA=0x5/0x6) with optional unidirectional register communication
LSB
ERR WRN MSB
Zero bits
LSB
CRC
out
cycle
Figure 15: Example of extended SSI line signals (MODEA=0x7, ExtSSI)
MODEA
Code
Description
0x4
0x5
Standard SSI, no error-bit
Standard SSI, error-bit low active
0x6
0x7
Standard SSI, error-bit high active
extended SSI, data-package like BiSS-C
In standard SSI mode singleturn data and, optionally,
multiturn data, an error, and a stop zero can be transmitted. In extended SSI mode (ExtSSI) the multiturn
data (optional), singleturn data, error, warning, and
CRC can be read out. All data is sent with the MSB
first and is equivalent to the data package that is output through BiSS.
Table 38: MODEA: SSI
The SSI interface of iC-MU can handle sensor data
communication and unidirectional register communication (Advanced SSI protocoll see Figure 14).
In SSI mode the sensor data can be output in binary
or Gray code.
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GSSI
Addr. 0x12; bit 7
RSSI
Addr. 0x12; bit 6
Code
Data format
Code
Ring operation
0
binary coded
0
normal output
1
Gray coded
1
Ring operation
Table 39: Data format (for MT and ST data)
SSI interface ring operation can either be achieved by
externally short-circuiting SLO and SLI or by using parameter RSSI.
Table 40: Ring operation
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SPI interface: general description
NCS
SCLK: MODE 0
SCLK: MODE 3
MOSI
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
MISO
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Figure 16: SPI transmission SPI-Mode 0 and 3, using opcode Read REGISTER(single) as an example
MODEA
Code
Description
0x0
0x1
SPITRI
SPI
Table 41: MODEA: SPI
In mode SPITRI MISO (Pin PA3) is set to tristate if the
slave is not selected by the master, i.e. NCS=1.
SPI modes 0 and 3 are supported, i.e. idle level of
SCLK 0 or 1, acceptance of data on a rising edge.
Data is sent in packages of 8 bits and with the MSB
first (see Figure 16). Each data transmission starts
with the master sending an opcode (Table 42) to the
slave.
The following describes the typical sequence of an SPI
data transmission, taking the command Read REGISTER (single) as an example (see Figure 16):
1. The master initializes a transmission with a falling
edge at NCS.
OPCODE
Code
Description
0xB0
0xA6
0xF5
0x97
0xD2
0xAD
ACTIVATE
SDAD-transmission (sensor data)
SDAD Status (no latch)
Read REGISTER(single)
Write REGISTER (single)
REGISTER status/data
Table 42: SPI OPCODEs
For the setup to be compatible with SPI protocol, when
setting the sensor data length for the command "SDAD
transmission" with parameters OUT_MSB, OUT_LSB,
and OUT_ZERO, it must be ensured that the output
data length is a multiple of 8 bits.
SPI interface: Command ACTIVATE
Each iC-MU has one RACTIVE and one PACTIVE register. These registers are used pairwise to configure
the register data channel and the sensor/actuator data
channel of a slave.
2. iC-MU passes the level on from MOSI to MISO.
4. The master terminates the command with a rising edge at NCS.
Using the ACTIVATE command, the register and sensor data channels of the connected slaves can be
switched on and off. The command causes all slaves
to switch their RACTIVE and PACTIVE registers between MOSI and MISO and set them to 0 (slaves in
chain connection). The register and sensor/actuator
data channels can be switched on and off with data
bytes following the OPCODE.
5. iC-MU switches its MISO output to
(MODEA=0x1) or tristate (MODEA=0x0).
After startup of iC-MU RACTIVE and PACTIVE is set
to 1.
3. The master transmits the opcode OP and address ADR via MOSI; iC-MU immediately outputs
OP and ADR via MISO.
1
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NCS
NCS
SCLK
MISO
OP
RAPA 0-3
RAPA 4-7
...
8 cycles
Figure 17: Set ACTIVATE: RACTIVE/PACTIVE
(several slaves)
The ACTIVATE command resets the bits FAIL, VALID,
BUSY, and DISMISS in the SPI-STATUS byte (see Table 46).
1 Slave
OP
MOSI
2 Slaves
SCLK
MOSI
MOSI
OP
1
0
0
0
MISO
OP
0
0
0
0
OP
1
0
0
0
0
0
MISO
OP
0
0
1
0
0
0
RA0 PA0
0
0
RA0 PA0 RA1 PA1
1
0
0
0
RACTIVE/PACTIVE-vector
8 cycles
Figure 18: Set ACTIVATE: RACTIVE/PACTIVE
(Example with one and two slaves)
MISO
SCLK
Register communication deactivated
Register communication activated*)
Note
*) default after startup
Table 43: RACTIVE
If RACTIVE is not set, on commands Read REGISTER (single), Write REGISTER (single), REGISTER
status/data the ERROR bit is set in the SPI-STATUS
byte (see Table 46) to indicate that the command has
not been executed. At MISO the slave immediately
outputs the data transmitted by the master via MOSI.
PACTIVE
Code
Description
0
1
Sensor data channel deactivated
Sensor data channel activated*)
Note
*) default after startup
NCS
0
1
SPI
Master
iC-MU
MOSI
MOSI
MISO
SCLK
Description
NCS
RACTIVE
Code
SCLK
NCS
iC-MU
MOSI
(1)
MISO
(0)
Figure 19: Example configuration with 2 Slaves
(daisy chained)
SPI interface: Command SDAD transmission
iC-MU samples the actual converter values on the first
rising edge at SCLK, when NCS is at zero (REQ). Because iC-MU can output the sensor data (SD) immediately, the master can transmit the SDAD transmission
command directly. The sensor data shift register (the
size of which is 8 to 40 bits in multiples of 8 using iCMU) is switched and clocked out between MOSI and
MISO.
If invalid data is sampled in the shift register, the ERROR bit is set in the SPI-STATUS byte (see Table 46)
and the output data bytes are set to zero.
Table 44: PACTIVE
NCS
REQ
SCLK
If PACTIVE is not set, on commands SDAD status and
SDAD transmission the ERROR bit is set in the SPISTATUS byte (see Table 46) to indicate that the command has not been executed. At MISO the slave immediately outputs the data transmitted by the master
via MOSI.
If only one slave is connected up with one register and
one sensor data channel, it must be ensured that the
RACTIVE and PACTIVE bits come last in the data byte.
MOSI
OP
MISO
OP
SD1
SD2
...
8 cycles
Figure 20: SDAD transmission: read SD
SPI interface: Command SDAD status
If the master does not know the processing time of the
connected slaves, it can request sensor data using the
command SDAD status. The command causes:
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1. All slaves activated via PACTIVE to switch their
SVALID register between MOSI and MISO.
N.B.: iC-MU does not need additional
processing time to generate valid sensor
data. Therefore "SDAD-transmission" can
be issued directly.
2. The next request for sensor data started with the
first rising edge at SCLK of the next SPI communication is ignored by the slave.
no
SV == 1?
The end of conversion is signaled by SVALID (SV). Using this command, the master can poll to the end of
conversion. The sensor data is read out via the command SDAD transmission.
SVALID
Code
Description
0
1
Sensor data invalid
Sensor data valid
yes
SDAD-transmission
2
REGISTER
status/data
(ERROR == 1)?
yes
Table 45: SVALID
NCS
1
SDAD status
error
handling
REQ
SCLK
MOSI
OP
MISO
OP
SV 0-7 SV 8-15
Figure 23: Example sequence of the commands
SDAD Status/SDAD-transmission
...
8 cycles
SPI interface: Command Read REGISTER (single)
This command enables register data to be read out
from the slave byte by byte.
Figure 21: SDAD status
If only one slave is connected, the corresponding
SVALID bit (SV0) is placed at bit position 7 in the
SVALID byte.
NCS
REQ
The master first transmits the Read REGISTER (single) command and then address ADR. The slave immediately outputs the command and address at MISO.
SCLK
1 Slave
OP
0
0
0
0
0
0
0
0
NCS
MISO
OP
SV 0
0
0
0
0
0
0
0
SCLK
2 Slaves
1
MOSI
MOSI
OP
0
0
0
0
0
0
0
0
MISO
OP
0
0
0
0
0
0
SV 0 SV 1
2
MOSI
OP
ADR
MISO
OP
ADR
+
OP
OP
STATUS DATA
8 cycles
8 cycles
SVALID-vector
Figure 22: SDAD status (Example with one and
two slaves)
Picture 23 shows the interaction of the two commands
SDAD Status and SDAD transmission. It is not necessary to start each sensor data communication with
the command SDAD Status (1). iC-MU has no processing time and can therefore directly output valid
sensor data. Because of that the command sequence
can start with SDAD-transmission (2). Following this,
the command REGISTER status/data should be executed to detect an unsuccessful SPI communication.
Figure 24: Read REGISTER (single): set the read
address (1) + command REGISTER
status/data to read-out data (2)
Following this, using the REGISTER status/data command (see page 34) the master can poll until the validity of the DATA following the SPI-STATUS byte is signaled via SPI-STATUS.
SPI interface: Command Write REGISTER (single)
This command enables data to be written to the slave
byte by byte.
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The master first transmits the Write REGISTER (single) command and then address ADR and the data
(DATA). The slave immediately outputs the command,
address, and data at MISO.
The master transmits the REGISTER status/data opcode. The slave immediately passes the opcode on to
MISO. The slave then transmits the SPI-STATUS byte
and a DATA byte.
NCS
Following the commands Read REGISTER (single)
and Write REGISTER (single), the validity of the DATA
byte is signaled with the VALID status bit.
SCLK
MOSI
OP
ADR
DATA
MISO
OP
ADR
DATA
8 cycles
Figure 25: Write REGISTER (single); set
WriteAddress and Data
The requested data byte is returned via DATA following
the Read REGISTER (single) command. Following
the Write REGISTER (single) command, the data to
be written is repeated in the DATA byte. With all other
opcodes, the DATA byte is not defined.
NCS
Using the REGISTER status/data command, the
master can poll to the end of communication (signaled
via the SPI-STATUS byte ).
SPI interface: Command REGISTER status/data
SCLK
MOSI
OP
MISO
OP
STATUS DATA
8 cylces
Figure 26: REGISTER status/data
The REGISTER status/data command can be used to
request the status of the last register communication
and/or the last data transmission. The SPI-STATUS
byte contains the information summarized in Table 46.
SPI-STATUS
Bit
Name
7
6..4
ERROR
-
Figure 27 shows the interaction of the commands
REGISTER read/write and REGISTER status/data.
REGISTER
read/write
(single)
Description of the status
report
Opcode not
implemented, Sensor
data was invalid on
readout
Reserved
REGISTER
status/data
yes
Statusbits of the register communication
3
DISMISS
Address refused
2
1
FAIL
BUSY
0
VALID
Data request has failed
Slave is busy with a
request
DATA is valid
Note
Display logic: 1 = true, 0 = false
Table 46: Communication status byte
All SPI status bits are updated with each register access. The exception to the rule is the ERROR bit; this
bit indicates whether an error occurred during the last
SPI-communication with the slave.
yes
DATA valid
or written
(BUSY == 1)?
(VALID == 1)?
(FAIL == 1)?
(DISMISS == 1)?
(ERROR == 1)?
yes
yes
error
handling
Figure 27: Example sequence of commands REGISTER read/write and REGISTER status/data
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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CONVERTER AND NONIUS CALCULATION
10 ms
FILT6
1 ms
FILT5
FILT4
100 us
latency
Converter principle
The system consist of two real-time tracking converters, each with a resolution of 12 bits for the master
track and nonius track. Above the maximal permissible input frequency the status bits FRQ_CNV is set.
The tracking converter can’t follow the input signal any
more. With a filter setting of type FILT1 and bigger an
increased resolution of 14 bits is available.
FILT3
10 us
FILT2
1 us
FILT1
FILT0
0.1 us
0.1 Hz
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
frequency
A digital filter can be configured with FILT to reduce the
noise of the digital output signals. Using this the digital
angle values of the tracking converter can be filtered.
Figure 29: Filter latencies
Synchronization mode
FILT
Addr. 0x0E; bit 2:0
Code
Typ
noise suppression
latency
0x0
0x1
0x2
0x3
0x4
FILT0
FILT1
FILT2
FILT3
FILT4
0 dB
15 dB
21 dB
27 dB
39 dB
0x5
FILT5
45 dB
< 1 µs
< 1 µs
2.5 µs
10 µs
164 µs fsin < 50 Hz
25 µs fsin < 1 kHz
650 µs fsin < 12 Hz
33 µs fsin < 1 kHz
0x6
FILT6
51 dB
Table 48 lists the configurable master period counts
and the resulting bit lengths for nonius synchronization, and the synchronization bit length used. The
paramter MPC defines thus the nonius system and
has to be chosen according to the magnetic code carrier. If MPC is switched during operation, command
ABS_RESET must be executed and the track offset
values must be calibrated again.
2.6 ms fsin < 3 Hz 41 µs
fsin < 1 kHz
MPC(3:0)
Addr. 0x0F; bit 3:0
Code
Master
period
count
Nonius
period
count
bitlength
synchronisation
bitlength
0x4
16
15
4
8
0x5
0x6
32
64
31
63
5
6
7
6
Table 47: Digital filter features
for MU as Nonius-Multiturn *)
30
phase elec. [deg]
10
3
1
FILT6
FILT5
FILT2
FILT1
FILT0
0
127
255
511
7
8
9
5
4
3
0xA
0xB
0xC
1024
2048
4096
1023
2047
4095
10
11
12
2
1
0
Note
*) see page 40
Table 48: Master period count and the resulting bit
lengths
FILT3
10
128
256
512
FILT4
0.3
0.1 −1
10
0x7
0x8
0x9
1
2
10
10
sine frequency [Hz]
3
10
Figure 28: Phase relationship of the filters
4
10
LIN selects the hall sensors for linear or rotative systems.
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WITH INTEGRATED HALL SENSORS
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LIN
Addr. 0x0E; bit 4
Code
Description
SPO_BASE(3:0)
SPO_BASE(3:0)
0
Rotative
Code
Starting point referred to 1 revolution
1
Linear
0x0
...
0x7
0x8
0x9
...
0 * (22.5°/2MPC )
...
7 * (22.5°/2MPC )
-8 * (22.5°/2MPC )
-7 * (22.5°/2MPC )
...
0xF
-1 * (22.5°/2MPC )
Table 49: Selection of linear/rotative hall sensors
An offset between the nonius track and the master track within one revolution can be adjusted with
SPO_BASE and SPO_x (x=0-14) .
The following formula describes how the error curve
based on the raw data from the master and nonius
track can be calculated. MPC is the number of sine
periods of the measuring distance.
TOLSPON = RAWMASTER − RAWNONIUS ∗
2MPC
2MPC − 1
The maximum tolerable phase deviation for a 2-track
nonius system is shown in Table 50. For the tolerable phase deviation of a 3-track nonius system please
reffer to Table 64 page 40.
Permissible Max. Phase Deviation
Periods/revolution
Master Nonius
16
15
32
31
64
63
[given in degree per signalperiod of 360°]
Master ↔ Nonius
+/- 9.84°
+/- 4.92°
+/- 2.46°
Table 50: Tolerable phase deviation for the master versus the nonius track of a 2 track nonius system (with reference to 360°, electrical)
Table 51: Nonius track offset start value
SPO_0(3:0)
SPO_1(3:0)
SPO_2(3:0)
Addr. 0x19; bit 7:4
Addr. 0x1A; bit 3:0
Addr. 0x1A; bit 7:4
Addr. SER: 0x52
Addr. SER: 0x53
Addr. SER: 0x53
SPO_3(3:0)
SPO_4(3:0)
SPO_5(3:0)
SPO_6(3:0)
SPO_7(3:0)
SPO_8(3:0)
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
0x1B;
0x1B;
0x1C;
0x1C;
0x1D;
0x1D;
bit 3:0
bit 7:4
bit 3:0
bit 7:4
bit 3:0
bit 7:4
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
SER: 0x54
SER: 0x54
SER: 0x55
SER: 0x55
SER: 0x56
SER: 0x56
SPO_9(3:0)
SPO_10(3:0)
SPO_11(3:0)
SPO_12(3:0)
SPO_13(3:0)
SPO_14(3:0)
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
0x1E;
0x1E;
0x1F;
0x1F;
0x20;
0x20;
bit 3:0
bit 7:4
bit 3:0
bit 7:4
bit 3:0
bit 7:4
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
SER: 0x57
SER: 0x57
SER: 0x58
SER: 0x58
SER: 0x59
SER: 0x59
Code
Slope referred to 1 revolution
0x0
...
0 * (22.5°/2MPC )
...
0x7
0x8
0x9
...
0xF
7 * (22.5°/2MPC )
-8 * (22.5°/2MPC )
-7 * (22.5°/2MPC )
...
-1 * (22.5°/2MPC )
P14
MPC )
x=0 SPO_x = {−7 ... 7} ∗ (22.5°/2
Note
An offset correction curve can be specified with
SPO_BASE and SPO_x (x = 0-14). SPO_BASE is
the start-value. SPO_0 to SPO_14 can be interpreted
as slope-values. A change in the slope of the offset
function can be made each 22.5°. The slope value
SPO_15 is computed automatically by iC-MU. To do
this the following condition must be met:
14
X
SPO_x = {−7 ... 7}
x=0
The offset value between to slopes (e.g. SPO_0 and
SPO_1) is interpolated. The computed offset is added
to the converted result of the nonius track prior to synchronization and is used to calibrate the nonius to the
master track. An offset value is chosen by the absolute position given by the nonius difference (masternonius).
Addr. 0x19; bit 3:0
Addr. SER:0x52; bit 3:0
Table 52: Nonius track offset slopes
SPO_15(3:0)
Addr. SER:0x5A; bit 3:0
Code
Slope
0x0
...
0xF
P
is automatically computed: − 14
x=0 SPO_x
-
Note
internal register, not readable via serial interface
Table 53: Nonius track offset slope (is automatically
computed)
The principle is shown in Figure 30. The red curve corresponds to the error curve of the nonius difference absolute within 360°. By taking the blue marked SPO_x
curve it is shown, that the nonius difference can be
changed in a way that the resulting green curve is in
the valid synchronisation range. It can be seen that
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Description
0
automatic period verification
1
no automatic period verification
SPO_15
SPO_14
SPO_13
SPO_12
SPO_11
SPO_10
SPO_9
SPO_8
SPO_7
SPO_6
SPO_5
SPO_4
SPO_3
SPO_2
SPO_1
Table 54: Automatic nonius period verification
slope used
in range
+ 1 period
tolerable
offset
error
degree
- 1 period
error curve
resulting curve
spo_x curve
spo_x correction
range
SPO_BASE
Addr. 0x0D; bit 5
Code
relative to
M-N
SPO_0
0°
NCHK_NON
22
.5
°
45
°
67
.5
°
90
°
11
2.
5
14 °
5°
16
7.
5
18 °
0°
20
2.
5
22 °
5°
24
7.
5
27 °
0°
29
2.
5
31 °
5°
33
7.
5
36 °
0°
an error within 22.5° (in the Figure between 67.5° and
90°) can not be corrected. For SPO_0 the range of a
possible slope change is exemplary shown.
SPO_0
SPO_1
The nonius data and incremental interface can be automatically reset with ACRM_RES if the master amplitude is too low. The incremental section is reset as
soon as the amplitude control unit indicates that the
master amplitude is too low (AM_MIN occurs, see Table 91). The ABZ-interface shows position 0 as default.
When the master amplitude is again in its set range, a
new nonius calculation is carried out and the incremental section is restarted.
ACRM_RES
Addr. 0x0D; bit 4
Code
Description
0
1
no automatic reset
automatic reset active
Table 55: Automatic Reset triggered by AM_MIN
Figure 30: Nonius track offset calibration
Following the first nonius synchronization the number of excessed periods is counted and output. Using NCHK_NON the system can be configured to
check the internal period counter against the period
given by the code disc at regular intervals. Command
NON_VER explicitly requests nonius verification. If
an error is found during verification of the nonius, bit
NON_CTR is set in status register STATUS1.
normal operation
ACRM_RES?
no
yes
no
no
AM_MIN
error set?
incr. part
in reset state?
yes
yes
wait
20 ms
reset incr. part
Figure 31 describes the principle of nonius synchronization with verification, with ϕ representing the respective digitized angle of the relevant track.
nonius reset
multiturn reset
initial nonius calculation
MPC
ϕm - ϕn
SYNC BITS
yes startup multiturn
ok?
no
12 Bit
ϕm
ϕabsolut
INIT_PERIOD
ϕm
restart incr. part
CORRECTION
Figure 32: Automatic reset ACRM_RES
CNT_PERIOD
+
MSB
LSB
INTERNAL
WORD
Figure 31: Principle of nonius synchronization
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WITH INTEGRATED HALL SENSORS
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MT INTERFACE
MTC
MODE_MT(3:0)
MTD
MSB
LSB
MODE_MT + SBL_MT + ESSI_MT
tout
Figure 33: Example of multiturn SSI line signals
Configuration of the Multiturn interface
iC-MU can read in and synchronize binary data from
an external SSI sensor through the serial multiturn interface. On startup the first data value read in determines the start value of the internal period counter. After startup the multiturn periods are counted internally
and output. If there is an error reading the multiturn
during startup, the read-in will be repeated.
Addr. 0x10; bit 3:0
Code
Function
Code
Function
0x0
0x1
0x2
no external data
1 *) bit
2 *) bit
0x8
0x9
0xA
4 *) + 12 bit
5 *) + 12 bit
6 *) + 12 bit
0x3
0x4
0x5
0x6
0x7
3 *) bit
4 *) bit
5 *) bit
6 *) bit
3 *) + 12 bit
0xB
0xC
0xD
0xE
0xE
4 bit
8 bit
12 bit
16 bit
18 bit
Notes:
*) data interpreted as ST
If MPC ≥ 0x07 than MODE_MT has to be set to
0x0 or 0xD
Table 56: MT interface operating mode
For synchronization a synchronization bit length must
be set by SBL_MT. Synchronization takes place between the read external multiturn word and the internal
counted cycle data. Synchronization can take place
automatically within the relevant phase tolerances.
SBL_MT(1:0)
multiturnstartup
read external
multiturn
serial-communication error?
yes
Addr. 0x10; bit 5:4
Code
MT synchronisation
bitlength
synchronisation
tolerance (ST-resolution)
0x0
1 bit
± 90°
0x1
0x2
0x3
2 bit
3 bit
4 bit
± 90°
± 135°
± 157,5°
set MT_ERR
Table 57: MT synchronization bit length
no
sync to master track
°
90
0°
°
°
0°
27
18
0
90
0°
°
18
0
0°
Figure 34: Error handling during startup
27
proceed with
startup-sequence
Figure 35 shows the principle of a 2 bit MT synchronization for ideal signals (without indication of synchronization tolerance limits).
ST MSB -1
MT LSB -2
SBL_MT=0x2
For exclusive multiturn systems a 4, 8, 12, 16 or 18-bit
multiturn data value can be read in (MODE_MT=0xB0xE). There is also the possibility to interpret a part
of the external multiturn data value as singleturn. For
further information see Construction of a Multiturn
system with two iC-MU S. 40.
ideal 2 bit
synchronisation
ST MSB
If the MT interface is not used (MODE_MT=0x0), the
internal 24-bit period counter can extend the singleturn
data output to include the counted multiturn cycles.
MT LSB -1
MT LSB
multiturn
data output
°/ST
Figure 35: Principle of 2 bit MT synchronization
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Rev B1, Page 39/59
The direction of rotation of the read multiturn data can
be inverted using parameter ROT_MT.
1-18 bit
1-4 bit
SYNC BITS
MODE_MT
SBL_MT
read-in multiturn
ROT_MT
ROT_MT
invert bits according
to ROT_MT
Addr. 0x0E; bit 5
Code
Function
0
1
no inversion of direction of rotation
inversion of direction of rotation
SPO_MT
+
Table 58: Inverted direction of rotation of external multiturn
SYNC BITS
multiturn to be
synchronized to
internal singleturn
synchronisation unit
The parameter ESSI_MT configures the evaluation of
an optional error-bit send by the external multiturn device.
multiturn
singleturn value
Figure 36: Parameters to configure external multiturn
ESSI_MT
Addr. 0x0E; bit 7:6
Code
Function
0x0
0x1
0x2
no error bit
1 error-bit low active
reserved
0x3
1 error-bit high active
Table 59: Evaluation of an error-bit of the external multiturn
CHK_MT can be used to verify the counted multiturn
at regular intervals. Verification can also be requested
using command MT_VER. A multiturn verification error
(comparison of the internal counted multiturn cycles
with the external multiturn data) is signaled through the
status bit MT_CTR.
CHK_MT
The total data length of the external read multiturn data
word is determined by:
Addr. 0x10; bit 6
Code
Function
0
1
no verification
periodical verification
Table 61: Multiturn verification
data_length_ext_mt = Bits(MODE_MT) + Bits(SBL_MT) + Bits(ESSI_MT)
normal operation
CHK_MT?
The parameter SPO_MT allows to balance an existing
static offset between the singleturn and the multiturn.
The offset is added before the synchronization of the
read multiturn data (see Figure 36).
yes
read external
multiturn
serial comm. error
no
sync to master track
and compare to counted
multiturn-value
reset
MT_ERR
yes
SPO_MT
Addr. 0x0F; bit 7:4
Code
Function
0x0
...
multiturn offset
set MT_ERR
reset
MT_CTR
no
compare error
yes
set MT_CTR
0xF
Table 60: Offset of external multiturn
Figure 37: Error handling in normal operation with
cyclic verification of the period counter
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Rev B1, Page 40/59
Construction of a Multiturn system with two iC-MU
A 3 Track nonius system can be build using two iC-MU.
The singleturn iC-MU (1) can be configured to interpret
3, 4, 5, or 6 bits of the read multiturn data as singleturn
data (ST) (see Table 56). The output through the incremental interface of iC-MU (1) is then absolute with
this additional information.
The construction of such a system is shown as an example in Figure 38 and the configuration in Table 62.
iC-MU
nonius
1023
master
1024
segment
992
iC-MU
PA3 / SLO
PA1 / MA
MTC
(1)
MTD
PA3 / SLO
PA1 / MA
(2)
Master
SL
MA
Figure 38: 3-track nonius with 2 iC-MU
MPC
(2)
0x7
0x8
0x9
0xA
0xB
0xC
(1)
0x4
0x4
0x5
0x5
0x6
0x6
Periods/revolution
Master Segm. Nonius
128
120
127
256
240
255
512
496
511
1024
992
1023
2048
2016
2047
4096
4032
4095
ST Periods [Bit]
from MT(2) from ST(1)
3
4
4
4
4
5
5
5
5
6
6
6
Table 63: Settings for a 3-track nonius system using 2
iC-MU
Permissible Max. phase deviation
Periods/revolution
Master Segm. Nonius
128
256
512
1024
2048
4096
Note
[given in degree per signalperiod of 360°]
Master ↔ Segm. Master ↔ Non.*)
(1)
(2)
120
127
+/-9.84°
240
255
+/-9.84°
496
511
+/-4.92°
992
1023
+/-4.92°
2016
2047
+/-2.46°
4032
4095
+/-2.46°
*) with SBL_MT=0x3
+/-19.68°
+/-9.84°
+/-9.84°
+/-4.92°
+/-4.92°
+/-2.46°
Table 64: Tolerable phase deviation for the master versus the nonius or segment track of a 3-track
nonius system (with reference to 360°, electrical)
Figure 39 shows the principle of the synchronisation of
the data from iC-MU (2) to iC-MU (1).
Bits of Multiturn MU (2)
iC-MU (1): singleturn
ϕm - ϕn
Parameter
Value
Description
MPC
MODE_MT
0x5
0x5
5 Bit ST periods
5 Bit ST periods via multiturn
SBL_MT
0x3
4 Bit synchronisation of read multiturn
data
ϕm
ϕm
MPC (2)
SYNC BITS
MPC (1)
ϕm - ϕs
CORRECTION
SYNC BITS
12 Bit
CORRECTION
Parameter
Value
Description
MPC
MODE_ST
0xA
0x0
0x0
10 Bit periods
no additional multiturn data
output of internal absolute data
OUT_MSB
0xA
OUT_LSB
0xF
MSB output configuration
9 Bit output data while having 10 Bit
periods
LSB output configuration
9 Bit output data while having 10 Bit
periods
MODE_MT
Table 62: Configuration example for the 3-track nonius
system of Fig.38
Table 63 shows the possible settings for a 3-track nonius systems with 2 iC-MU and the resulting periods/revolution of the tracks. The maximum phase deviation of the tracks is summarized in Table 64.
ϕabsolut
INIT_PERIOD
iC-MU (2): multiturn
CNT_PERIOD
+
MSB
LSB
INTERNAL
WORD
Figure 39: Principle of the synchronisation of a 3track nonius system using 2 iC-MU without further multiturn data
To facilitate the initial configuration of an iC-MU as a
SSI multiturn device the command SWITCH can be
used (see page 52). The singleturn iC-MU (1) in
Figure 38 has to enable the direct communication to
the multiturn sensor by setting GET_MT to 1. The
configuration of iC-MU (2) can take place using the
BiSS protocol. After the configuration of the external multiturn MODEA_NEW and RPL_NEW are used
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to set the target configuration of MODEA and RPL.
After that the command SWITCH is executed. By
reading STATUS1 it is possible to control if there was
an error while executing the command. After the
next startup or after the execution of the command
SOFT_RESET iC-MU starts with the interface configurated with MODEA_NEW and RPL_NEW.
Direct Communication To Multiturn Sensor
Making use of the BiSS Interface bus capabilities, iCMU can connect in modes MODEA = 0x02 and 0x040x07 (BiSS and SSI) the external multiturn sensor to
the BiSS master controller when GET_MT is enabled.
To this end pin MA (PA1) receiving the BiSS master’s
clock signal is fed through to pin MTC and the MTD
pin is activated in place of the SLI (PA2) pin. Upon enabling this mode the single cycle timeout must have
elapsed and an additional init command carried out
by the BiSS master, before it can run the first register
communication.
Example: external multiturn sensor built with iC-MU is
connected to the MT interface of a first iC-MU, preparing the singleturn data. With GET_MT enabled, the
external multiturn can then be addressed via BiSS ID
0 and the singleturn via BiSS ID 1. This temporal chain
operation simplifies device parametrization during encoder manufacturing.
GET_MT
Addr. 0x10; bit 7
Code
Function
0
1
Disabled
MT sensor communication enabled
Table 65: Direct BiSS communication enable for MT
sensor via I/O Interface
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Rev B1, Page 42/59
INCREMENTAL OUTPUT ABZ, STEP/DIRECTION AND CW/CCW
MODEA
Code
Description
0x3
ABZ
CW
CCW
MODEB
Code
Description
0x0
0x2
0x3
ABZ
Step/Direction
CW/CCW Incremental
Notes:
It is not possible to select an incremental interface
on MODEA and MODEB simultaneously
STEP
DIR
Table 66: MODEA/MODEB: ABZ, step/direction and
CW/CCW
NCLR
The resolution of incremental signals ABZ can be programmed for each singleturn cycle within a range of 4
to 262,144 edges using the internal FlexCount®. The
number of master periods which is equivalent to a singleturn cycle is defined by the settings in register MPC
(Table 48).
A
RESABZ(7:0)
RESABZ(15:0)
φ360AB
B
Z
Resolution
Interpolation factor
0x0000
0x0001
...
0xFFFF
4
8
...
262144
1
2
...
65536
Notes:
For non-binary resolutions above 32,768 (0x2000)
the relative error increases
φhys
φz90
clockwise rotation
Addr. 0x13; bit 7:0
Addr. 0x14; bit 7:0
Code
tmtd
counterclockwise rotation
time
Figure 40: Definition of the ABZ, STEP/DIR, and
CW/CCW signals
The phase position of the incremental output signals
can be inverted using the relevant configuration bit
INV_x (x = A,B,Z).
Table 67: FlexCount®- Resolution
INV_A
Figure 40 shows the ABZ, step/direction, and
CW/CCW signals. The length of a signal A or B cycle
is defined by ϕ360AB as a range between two rising
edges of an A or B signal.
Addr. 0x16; bit 2
Code
A/STEP/CW-Signal
0
1
normal
inversion
Table 68: Inversion A-Signal
INV_B
ϕhys represents the hysteresis which must be exceeded before further edges are generated at the incremental interface.
Addr. 0x16; bit 1
Code
B/DIR/CCW-Signal
0
1
normal
inversion
Table 69: Inversion B-Signal
Minimum edge distance t mtd is the minimum time which
must have elapsed before another event can be output
at the incremental interface.
The length of the Z pulse with setting ZLEN = 0x00 is
defined by ϕz90 .
INV_Z
Addr. 0x16; bit 0
Code
Z/NCLR-Signal
0
normal
1
inversion
Table 70: Inversion Z-Signal
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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Index pulse Z can be programmed in four lengths. The
position of the index pulse in relation to the A/B signals
is shown in Figure 41.
LENZ(1:0)
Addr. 0x16; bit 7:6
Code
Z-pulse length
0x0
90°
0x1
0x2
0x3
180°
270°
360°
FRQAB(2:0)
Table 71: Index pulse length
A
B
Z 360°
Z 270°
Z 180°
Z 90°
-2
The minimum edge distance t mtd of the ABZ,
STEP/DIR or CW/CCW interface can be limited by setting the maximum output frequency with FRQAB. It can
be used to adjust the output frequency to a frequency
limit given by an external ABZ, STEP/DIR or CW/CCW
counter device.
Addr. 0x15; bit 2:0
Code
Output frequency AB
Edge distance t mtd
0x0
0x1
0x2
0x3
0x4
6.25 MHz
3.13 MHz
1.56 MHz
781.25 kHz
390.63 kHz
40 ns
80 ns
160 ns
320 ns
640 ns
0x5
0x6
0x7
195.31 kHz
48.83 kHz
12.2 kHz
1.28 µs
5.12 µs
20.48 µs
Table 74: AB output frequency
0
-1
1
2
3
4
Figure 41: Index pulse length settings
The direction of rotation can be inverted with parameter ROT. The parameter affects the output of the data
word through the serial interface in MODE_ST=0x0
and 0x1, the ABZ-interface and the UVW-interface.
ROT
Addr. 0x15; bit 7
Code
Description
0
1
no inversion of direction of rotation
inversion of rotation
The incremental counter has an integrated hysteresis
which prevents multiple switching of the incremental
signals at the reversing point. Hysteresis ϕhys must
first be exceeded before edges can again be generated at A or B. This hysteresis can be set within a range
of 0° to 0.35° according to Table 75 and is referenced
to 360° of a singleturn cycle.
CHYS_AB(1:0)
Addr. 0x16; bit 5:4
Code
Hysteresis
0x0
0x1
no hysteresis
0.175°
0x2
0x3
0.35°
0.7°
Table 75: Hysteresis with an inverted direction of rotation
Table 72: Inverted direction of rotation
Parameter SS_AB must be configured depending on
the maximum speed. With a filter setting of FILT =
0x00 (Table 47), correspondingly higher SS_AB step
size values must be programmed. The maximum possible resolution of the incremental count signal is reduced according to the set step size. The FRQ_ABZ
status bit is set in the case of an unacceptable high
speed.
SS_AB(1:0)
Addr. 0x15; bit 5:4
Code
max. resolution
max. rpm
0x0
0x1
0x2
0x3
218
217
216
215
6000 rpm
12000 rpm
6000 rpm mit FILT=0x0
12000 rpm mit FILT=0x0
Table 73: System AB step size
The parameter ENIF_AUTO selects whether at startup
the incremental interface is enabled after the converter
has found its operating point or if the counting to the
absolute angle can be seen at the incremental interface.
ENIF_AUTO
Addr. 0x15; bit 4
Code
Description
0
1
counting to operating point visible
counting to operating point not visible
Table 76: Incremental interface enable
See the chapter on the preset function (p. 56) to set
the offset for ABZ output.
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WITH INTEGRATED HALL SENSORS
Rev B1, Page 44/59
UVW COMMUTATION SIGNALS
MODEB
PP60UVW
Addr. 0x16; bit 3
Code
Description
Code
Phase UVW Signale
0x1
UVW
0
1
120° phase shift
60° phase shift
Table 77: MODEB: UVW
Table 79: Commutation signal phase length
iC-MU can generate commutation signals for BLDC
motors from 1 up to 16 pole pairs. The hysteresis is
set fixed to 0.0879° referenced to a mechanical revolution.
Register OFF_UVW is used to set the start angle and
compensate for the offset between the winding of the
BLDC and the Hall sensor signals. This angle can be
set with 12 bits.
Figure 42 shows the commutation sequence for a motor with 6 pole pairs. Here, a commutation sequence
spanning an angle of ϕ360UVW repeats itself 6 times
within one mechanical revolution of the motor. The
phaseshift between the commutation signals is 120°.
N.B.:
After startup or the commands SOFT_RESET and
ABS_RESET the OFF_UVW values are amended
to include the nonius data, with a configured multiturn updated with the multiturn data, and stored as
OFF_COM in the internal RAM.
U
V
W
φmech
φ120uvw
0°
60°
φ360uvw
120°
300°
360°
Figure 42: commutation signals UVW
OFF_UVW(3:0)
OFF_UVW(11:4)
Addr. 0x28; bit 7:4
Addr. 0x29; bit 7:0
OFF_UVW(3:0)
OFF_UVW(11:4)
Addr. SER:0x4B; bit 7:4
Addr. SER:0x4C; bit 7:0
Code
Offset UVW signals
0x000
0x001
...
0xFFF
0.00° mech
0.09° mech
360.0° mech
· OFF _UVW
4096
359.9° mech
Table 80: Commutation signal start angle
Using parameter PPUVW the number of commutation
sequences per mechanical revolution can be set.
OFF_COM(3:0)
OFF_COM(11:4)
Code
PPUVW(5:0)
Addr. 0x17; bit 5:0
Code
number of pole
pairs
Code
number of pole
pairs
0x02
0x05
1 pole pair
2 pole pairs
0x1A
0x1D
9 pole pairs
10 pole pairs
0x08
0x0B
0x0E
0x11
0x14
0x17
3 pole pairs
4 pole pairs
5 pole pairs
6 pole pairs
7 pole pairs
8 pole pairs
0x20
0x23
0x26
0x29
0x2C
0x2F
11 pole pairs
12 pole pairs
13 pole pairs
14 pole pairs
15 pole pairs
16 pole pairs
Table 78: Number of commutation signal pole pairs
0x000
...
R
R
Description
start angle commation signal (automatically
computed)
0xFFF
Table 81: Commutation signal start angle amended by
the nonius/MT
The direction of rotation can be inverted with parameter ROT. The parameter affects the output of the data
word through the serial interface in MODE_ST=0x0
and 0x1, the ABZ-interface and the UVW-interface.
ROT
The sequence of the commutation signals can be selected by ϕ120UVW as in Figure 42 or with a distance of
60° between two neighboring rising edges referenced
to one UVW cycle using parameter PP60UVW.
Addr. SER:0x23; bit 7:4
Addr. SER:0x24; bit 7:0
Addr. 0x15; bit 7
Code
Description
0
1
no inversion of direction of rotation
inversion of rotation
Table 82: Inverted direction of rotation
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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REGISTER ACCESS THROUGH SERIAL INTERFACE (SPI AND BISS)
scope of serial interface register view
N.B.:
ADDR is used in register
tables to indicate the address
of the corresponding
parameter. If the addressing
scheme differs between the
EEPROM and the serial
interface ADDR. SER is used
to indicate the addressing
through the serial interface.
EEPROM
iC-MU
access
via
SPI
BiSS
SSI
ADDR/
ADDR. SER
Figure 43: Scope of register mapping serial interface
The distribution of addresses in iC-MU corresponds to
the document BiSS C Protocol Description which can
be downloaded at www.biss-interface.com.
iC-MU supports an addressing scheme using banks.
Therefore the internal address space is divided into
banks of 64 bytes each. The address sections visible via the I/O interface recognizes a ”dynamic” section
(addresses 0x00 to 0x3F) and a ”static” section which
is permanently visible (addresses 0x40 to 0x7F). The
static address section is always visible independent of
the bank currently selected. Figure 44 illustrates how
the banks selected by BANKSEL are addressed.
The address translation for the addressable memory
areas via the bank register to the EEPROM addresses
is shown in Table 84.
Code
Description
Memory location
during operation
Mode
CONF
0
internal register
iC-MU
configuration
data
EDS
1
E2P:
0x040-0x07F
Electronic-DataSheet
...
4
...
E2P:
0x100-0x13F
5
E2P:
0x140-0x17F
...
31
...
E2P:
0x7C0-0x7FF
USER
BANKSEL(4:0)
Addr. SER:0x40; bit 4:0
Code
Description
0x0
...
0x1F
Selection of the memory bank
OEM data, free
user area
Table 84: Address translation Addr Ser: 0x00-0x3F
Table 83: Register to select a memory bank
After startup the BANKSEL register ist set to 0.
The abbreviation Addr. SER used in the register tables of the specification of the iC-MU stands for the
addressing of this register through the serial interface.
CONF: Bank 0, Addresses 0x00-0x3F
Addr.
SER
0x00
Bit 7
Bit 6
GC_M(1:0)
0x01
0x02
0x03
0x04
0x05
0x06
Bit 5
Bit 4
Bit 3
Bit 2
GF_M(5:0)
GX_M(6:0)
VOSS_M(6:0)
VOSC_M(6:0)
PH_M(6:0)
CIBM(3:0)
ENAC
GC_N(1:0)
Bit 1
GF_N(5:0)
Bit 0
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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CONF: Bank 0, Addresses 0x00-0x3F
Addr.
SER
Bit 7
Bit 6
Bit 5
Bit 4
0x08
0x09
0x0A
MODEB(2:0)
0x0B
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Bit 1
Bit 0
MODEA(2:0)
CFGEW(7:0)
0x0C
0x0E
Bit 2
GX_N(6:0)
VOSS_N(6:0)
VOSC_N(6:0)
PH_N(6:0)
0x07
0x0D
Bit 3
NCHK_CRC NCHK_NON
ACRM_RES
EMTD(2:0)
ESSI_MT(1:0)
ROT_MT
LIN
FILT(2:0)
SPO_MT(3:0)
MPC(3:0)
GET_MT
CHK_MT
SBL_MT(1:0)
MODE_MT(3:0)
OUT_ZERO(2:0)
OUT_MSB(4:0)
GSSI
RSSI
MODE_ST(1:0)
OUT_LSB(3:0)
RESABZ(7:0)
RESABZ(15:8)
ROT
SS_AB(1:0)
ENIF_AUTO
FRQAB(2:0)
LENZ(1:0)
CHYS_AB(1:0)
PP60UVW
INV_A
INV_B
RPL(1:0)
PPUVW(5:0)
TEST(7:0)
ACC_STAT
INV_Z
0x19
RESERVED
...
0x1D
0x1E
OFF_ABZ(3:0)
OFF_ABZ(11:4)
OFF_POS*(19:12)
OFF_POS*(27:20)
OFF_POS*(35:28)
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
RESERVED
OFF_COM**(3:0)
RESERVED
OFF_COM**(11:4)
PA0_CONF(7:0)
0x26
...
RESERVED
0x3F
Hinweis:
* OFF_ABZ value amended to include nonius/multiturn information
** OFF_UVW value amended to include nonius information
Table 85: Register mapping bank 0, addresses 0x00-0x3F (access via serial interface)
OFF_POS* are the offset values (OFF_ABZ) altered
by the nonius calculation or by an external multiturn
which are used as a start value for the counted internal cycle data.
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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Rev B1, Page 47/59
Static part: Addresses 0x40-0xBF
Addr.
SER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EDSBANK(7:0)
PROFILE_ID(7:0)
PROFILE_ID(15:8)
SERIAL(7:0)
SERIAL(15:8)
SERIAL(23:16)
SERIAL(31:24)
OFF_ABZ(19:12)
OFF_ABZ(27:20)
OFF_ABZ(35:28)
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
OFF_UVW(3:0)
RESERVED
OFF_UVW(11:4)
0x4C
0x4D
PRES_POS(3:0)
0x4F
0x50
0x51
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
RESERVED
PRES_POS(11:4)
PRES_POS(19:12)
PRES_POS(27:20)
PRES_POS(35:28)
0x4E
0x52
SPO_0(3:0)
SPO_2(3:0)
SPO_4(3:0)
SPO_6(3:0)
SPO_8(3:0)
SPO_10(3:0)
SPO_12(3:0)
SPO_14(3:0)
SPO_BASE(3:0)
SPO_1(3:0)
SPO_3(3:0)
SPO_5(3:0)
SPO_7(3:0)
SPO_9(3:0)
SPO_11(3:0)
SPO_13(3:0)
RPL_RESET(7:0)
I2C_E2P_START(7:0)
I2C_RAM_START(7:0)
I2C_RAM_END(7:0)
I2C_DEVID(7:0)
I2C_RETRY(7:0)
0x60
...
USER_EXCHANGE_REGISTERS
0x6F
0x70
0x71
RESERVED
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
Bit 1
BANKSEL(4:0)
0x40
0x4B
Bit 2
EVENT_COUNT(7:0)
HARD_REV(7:0)
CMD_MU(7:0)
STATUS0(7:0)
STATUS1(7:0)
REVISION(7:0)
REVISION(15:8)
REVISION(23:16)
REVISION(31:24)
Bit 0
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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Static part: Addresses 0x40-0xBF
Addr.
SER
0x7C
0x7D
0x7E
0x7F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION(39:32)
REVISION(47:40)
MANUFACTURER(7:0)
MANUFACTURER(15:8)
0x80
...
RESERVED
0xBF
Table 86: Register mapping bank 0-31, addresses 0x40-0xBF (access via serial interface)
The current iC-MU hardware version can be read out
through HARD_REV.
HARD_REV(7:0)
Addr. SER: 0x74; bit 7:0
Code
Chip version
Addressing scheme
using banks
0x02
0x03
0x04
iC-MU 0
iC-MU 1
iC-MU Z
-
0x05
0x06
iC-MU Y
iC-MU Y1
x
x
Table 87: HARD_REV
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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Address sections/Registerprotectionlevel
address-space visible via serial interface with
register protection level RP1
Register access can be restricted via RPL (see Table
88). RPL = 0x2/0x3 selects a shipping mode with limited access which can be set back to RPL = 0x0. To
set back RPL the content of Bank: 0, Addr. SER: 0x17
has to be written to RPL_RESET.
ADR.
SER
RPL(1:0)
Code
0x0
0x1
0x2
0x3
Mode
Addr. 0x17; bit 7:6
Access restriction
0x40
0x41
Configuration mode, no
restrictions
Shipping mode, without
command E2P_COM,
reset is not possible
RP0
RP1
0x47
0x48
Shipping mode, with
command E2P_COM,
reset to RP0 possible
Shipping mode, without
command E2P_COM,
reset to RP0 possible
RP1
0x4C
0x4D
.
..
..
n/a
bank 5-31
r
r/w
BANKSEL
.
bank 1-4
..
bank 0
.
0x3F
USER
..
0x00
EDS
.
CONF
r/w
selects
EDSBANK
profile ID
serial number
r
OFF_x
n/a
PRES_x
r/w
0x51
0x52
RP1
SPO_x
n/a
0x59
0x5A
SPECIAL REGISTERS
Table 88: Register access control
r/w
0x6F
0x70
RESERVED
RPL_RESET(7:0)
Addr. SER:0x5A; bit 7:0
Code
Description
0x00
...
0xFF
Set back value for RPL
0x72
0x73
0x74
0x75
n/a
EVENT_CNT
HARD_REV
CMD/STATUS
r/w
0x77
0x78
Table 89: Set back value for RPL
BiSS ID
r
0x7F
0x80
Sections CONF, EDS and USER are protected at different levels in shipping mode for read and write access (see Figure 44).
RPL(1:0)
r
n/a
n/a :not available
r
:readable
w :writeable
Figure 44: Principle of bank-wise memory addressing and access restrictions with register
protection level RP1
RPL*
Addr. 0x17; bit 7:6
Section
CONF
EDS
USER
RP0
RP1
r/w
n/a
r/w
r/w
Note
*) RPL: Register Protection Level
r/w
r
RESERVED
0xBF
n/a: iC-MU refuses access to those register
addresses
r: Registers are readable
w: Registers are writeable
Table 90: Register Read/Write Protection Levels
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iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
Rev B1, Page 50/59
STATUS REGISTER AND ERROR MONITORING
Status register
Various Status-information can be read out via status
bytes STATUS0 and STATUS1.
STATUS0(7:0)
Addr. SER: 0x76; bit 7:0
Bit
Name
Description of status message
4
STUP
Startup iC-MU
3
2
1
0
AN_MAX
AN_MIN
AM_MAX
AM_MIN
Signal error:
Signal error:
Signal error:
Signal error:
Notes
Error indication logic: 1 = true, 0 = false
R
N.B.:
A read access to the reserved addresses SER: 0x3D
and 0x3E also clears the accumulated status information STATUS0 and STATUS1 if ACC_STAT is set
to 1.
Error and warning bit configuration
clipping (nonius track)
poor level (nonius track)
clipping (master track)
poor level (master track)
The output and the polarity of the error and warning
bit within the different serial protocols (MODEA Table
28) can be found in Table 94. Messages are allocated
to the error and warning bit by parameter CFGEW according to Table 95.
Table 91: Statusregister 0
STATUS1(7:0)
Addr. SER: 0x77; bit 7:0
Bit
Name
Description of status message
R
MODEA(2:0)
7
6
5
4
CRC_ERR
EPR_ERR
MT_ERR
MT_CTR
Function
3
NON_CTR
2
FRQ_ABZ
1
FRQ_CNV
0
CMD_EXE
Invalid check sum internal RAM
Configuration error on startup: No EEPROM
Multiturn communication error
Multiturn data consistency error:
counted multiturn ↔ external MT data
Period counter consistency error:
counted period ↔ calculated Nonius position
Excessive signal frequency for
ABZ-converter
Excessive signal frequency for internal 12 Bit
converter
Command execution in progress
Notes
Error indication logic: 1 = true, 0 = false
Table 92: Statusregister 1
ACC_STAT configures, if the status registers show the
actual or the accumulated status information.
If the accumulated status is configured, the status bits
are maintained until the status register is read out or
the command ABS_RESET bzw. SOFT_RESET are
executed. This is valid except for EPR_ERR, STUP
and CMD_EXE. These bits are set in the status register independent of the ACC_STAT configuration while
the status information is active. The status register can
be accessed independently of the internal operating
state.
ACC_STAT
Addr. 0x0B; bit 2:0
Error
low active
high active
Warning
low active
high active
SPI
-
-
-
-
BiSS
SSI
x
x
x
x
-
x
x
-
SSI+ERRL
SSI+ERRH
ExtSSI
Table 94: MODEA: error/warning-bit within serial protocols
CFGEW(7:0)
Addr. 0x0C; bit 7:0
Bit
Visibility for error bit
7
6
MT_ERR/MT_CTR
NON_CTR
5
4
3
2
Ax_MAX und Ax_MIN
EPR_ERR
CRC_ERR
CMD_EXE
Bit
Visibility for warning bit
1
FRQ_CNV/FRQ_ABZ
0
Ax_MAX und Ax_MIN
Notes
x = M, N
Encoding:
0 = message enabled, 1 = message disabled
Table 95: Error and warning bit configuration
Addr. 0x0D; bit 7
Code
Description
0
Output of actual status information
1
Output of accumulated status information
Table 93: Output configuration of status register
If an error pin is configured using MODEB (Table 29),
an internal error (see status register, ACC_STAT configuration and error bit configuration with CFGEW) is
signaled by the NER pin (PB3). The minimum message time for I/O pin NER can be set by EMTD.
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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EMTD(2:0)
Addr. 0x0D; bit 2:0
Code
min. disp. time
Code
min. disp. time
0x0
0x1
0x2
0x3
0 ms
12.5 ms
25 ms
37.5 ms
0x4
0x5
0x6
0x7
50 ms
62.5 ms
75 ms
87.5 ms
Table 96: Minimum error display time
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
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COMMAND REGISTER
Implementing internal commands
An implemented command is executed depending on
the written data value.
CMD_MU(7:0)
Addr. SER: 0x75; bit 7:0
W
Code
Command
Explanation
0x01
WRITE_ALL
0x02
WRITE_OFF
0x03
ABS_RESET
0x04
NON_VER
0x05
MT_RESET
0x06
MT_VER
0x07
SOFT_RESET
0x08
0x09
SOFT_PRES
SOFT_E2P_PRES
0x0A
E2P_COM
0x0B
EVENT_COUNT
0x0C
SWITCH
Write internal
configuration and Offset
values to EEPROM
Write internal Offset
values to EEPROM
Reset of Absolute value
(including ABZ-part)
Verification of actual
position by doing a
nonius calculation
New read in and
synchronisation of
multiturn value
Read in of multiturn and
verification of counted
multiturn value
startup with read in of
EEPROM
Set output to preset
Set output to preset and
save offset values to
EEPROM
start EEPROM
communication
increment event counter
by 1
A variant of WRITE_ALL
to write configurations of
MODEA and RPL which
inhibit register
communications
Verification of CRC16
and CRC8
0x0D
CRC_VER
0x0E
CRC_CALC
0x0F
0x10
...0xFF
SET_MTC
RES_MTC
no function
Note:
*) MODE_MT=0x00
Recalculate internal
CRC16 and CRC8
values
Set MTC-Pin *)
Reset MTC-Pin *)
Table 97: Implemented commands
WRITE_ALL stores the internal configuration and offset/preset values to the EEPROM. CRC16 and CRC8
are automatically updated.
WRITE_OFF only stores the offset/preset data area to
the EEPROM. CRC8 is automatically updated.
If a multiturn is configured, this is read in and synchronized. Offset values OFF_ABZ/OFF_UVW are
amended to include the cycle data and stored as
OFF_POS and OFF_COM. The ABZ/UVW converter
is restarted.
Command NON_VER initiates a nonius calculation
and the computed value is compared to the current
counted period. If there is a discrepancy, error bit
NON_CTR is set in status register STATUS1.
With command MT_RESET an external multiturn is
read in anew and synchronized.
Offset values
OFF_ABZ and OFF_UVW are amended to include
the multiturn data and stored as OFF_POS and
OFF_COM. Attention: The ABZ/UVW converter is not
restarted. If part of the multiturn data is used for the
singleturn information, ABS_RESET has to be executed instead.
With command MT_VER an external multiturn is read
in and the counted multiturn value is verified. If there
is a discrepancy, error bit MT_CTR is set in status register STATUS1.
With command SOFT_RESET internal finite state machines and counters are reset. The EEPROM is read
in anew. A redefinition of the absolute value is initiated
(see ABS_RESET)
Command SOFT_PRES initiates a preset sequence
(cf. page 56) with preset values PRES_POS. The internal offset values OFF_ABZ are changed to set the
output value to the value given by PRES_POS. The
internal CRC8 is automatically updated.
Command SOFT_E2P_PRES initiates a preset sequence (cf. page 56) with preset values PRES_POS.
The altered offset values OFF_ABZ are stored in the
EEPROM. CRC8 is automatically updated.
Command E2P_COM initiates communication with the
EEPROM (RPL=0x00 and 0x02). Prior to this the following parameters must be configured:
• I2C_DEVID
• I2C_RAM_START
• I2C_RAM_END
Command ABS_RESET initiates a redefinition of the
absolute value. A new nonius calculation is started.
• I2C_E2P_START
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The device ID is written to I2C_DEVID (see Table 98).
If an error occurs while communicating with an external EEPROM up to 3 new communication attempts are
started by iC-MU.
I2C_E2P_START Addr. SER: 0x5D; bit 7:0
Code
Description
0x00
...
0xFF
I2C_RAM_START defines the start address in the internal RAM which in case of a
• write access: marks the begin of the data area
that holds the data to be written
• read access: marks the begin of the data area
where the data read from the EEPROM is written to
I2C-EEPROM start address
Table 101: I2C_E2P_START
With command EVENT_COUNT the value of register
EVENT_COUNT is incremented by 1.
EVENT_COUNT(7:0)
Addr. SER:0x73; bit 7:0
Code
Description
0x0
...
Event counter
0x1F
According to this I2C_RAM_END defines the end address of the data area in the internal RAM. The number of bytes NUM_BYTES to be read/written are determined by the difference between I2C_RAM_END and
I2C_RAM_START.
I2C_E2P_START defines the start address of the EEPROM from which NUM_BYTES bytes should be read/written.
The USER_EXCHANGE_REGISTERS (see Table 86)
can be used for the data-exchange with the EEPROM.
I2C_DEVID(7:0)
Addr. SER:0x60; bit 7:0
Code
Meaning
0xA0
0xA1
write EEPROM
read EEPROM
Table 98: I2C_DEVID
Addr. SER: 0x5E; bit 7:0
Description
I2C_RAM_START
Code
0x00
...
0xFF
Table 102: Event counter
The command SWITCH is a variant of the WRITE_ALL
command which makes it possible to write configurations of MODEA und RPL into the EEPROM
which inhibit further register communications (e.g.
MODEA=ABZ).
N.B.: RPL must be set to 0x0 before starting the
command.
MODEA_NEW and RPL_NEW are used to set the target configuration of MODEA and RPL (e.g. ABZ, no
RPL). On executing the command SWITCH MODEA
and RPL are set to the target values and the configuration is written to the EEPROM. Finally MODEA and
RPL are set back to the original values. This makes it
possible to control the success of the EEPROM write
process by reading STATUS1 (EPR_ERR should not
be set).
I2C-RAM start address
Table 99: I2C_RAM_START
I2C_RAM_END
Addr. SER: 0x5F; bit 7:0
Code
Description
0x00
...
I2C-RAM end address
0xFF
Table 100: I2C_RAM_END
N.B.: CRC_ERR is set after command execution
if there is the cyclic CRC check configured by
NCHK_CRC=0 and the target values of MODEA and
RPL differ from the originals values.
iC-MU starts with the interface and register protection
level configured with MODEA_NEW und RPL_NEW
after the next startup or after the execution of command SOFT_RESET.
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normal
operation
CMD_MU: SWITCH
requested
MTD_STATUS before it sets or resets pin MTC. To use
these commands MODE_MT has to be set to 0x0, i.e.
no external multiturn is configured.
RPL == 0?
no
yes
MTD_STATUS
Addr. SER: 0x60; bit 0
Code
Description
- backup MODEA
- set MODEA_NEW
- set RPL_NEW
0
1
save CONFIG
to EEPROM
MTD Pin was 0, before setting/resetting MTC
MTD Pin was 1, before setting/resetting MTC
Table 105: Status of pin MTD before command execution SET_MTC and RES_MTC
- restore old MODEA
- set RPL to 0
Figure 45: Event sequence of command SWITCH
MODEA_NEW
Code
PA0
Addr. SER: 0x60; bit 2:0
PA1
PA2
PA3
Function
0x0
0x1
0x2
0x3
0x4
0x5
NCS
NCS
SCLK
SCLK
MA
A
MA
MA
MOSI
MOSI
SLI
B
SLI
SLI
MISO
MISO
SLO
Z
SLO
SLO
SPITRI
SPI
BiSS
ABZ
SSI
SSI+ERRL
0x6
0x7
NPRES
MA
MA
SLI
SLI
SLO
SLO
SSI+ERRH
ExtSSI
NPRES
NPRES
NPRES
NPRES
NPRES
Table 103: Target value of MODEA for the command
SWITCH
RPL_NEW
Code
Addr. SER: 0x60; bit 7:6
RegisterproCommand
tection
E2P_COM
Reset to RP0
possible
0x0
RP0
x
x
0x1
0x2
0x3
RP1
RP1
RP1
x
-
x
x
Table 104: Target value for RPL for the command
SWITCH
Command CRC_VER starts a verification of CRC16
and CRC8. In case of an crc error, the CRC_ERR status bit is set.
Command CRC_CALC starts a recalculation of
CRC16 and CRC8. CRC16 and CRC8 are saved internally in iC-MU and are used for later CRC verifications.
The command SET_MTC sets pin MTC to logic level
1.
RES_MTC resets pin MTC to logic level 0.
iC-MU saves the actual logic level of pin MTD to
Configurable NPRES Pin
A configurable NPRES pin can be used at pin PA0 if
MODEA is set to 0x2-0x7. This pin can be used to
execute a command configured by PA0_CONF on a
falling edge of NPRES.
PA0_CONF(7:0)
Addr. 0x30; bit 7:0
PA0_CONF(7:0)
Addr. SER: 0x25; bit 7:0
Code
Command
0x00
0x01
0x02
0x03
0x04
0x05
NO_FUNCTION
WRITE_ALL
WRITE_OFF
ABS_RESET
NON_VER
MT_RESET
0x06
0x07
0x08
0x09
0x0A
0x0B
MT_VER
SOFT_RESET
SOFT_PRES
SOFT_E2P_PRES
E2P_COM
EVENT_COUNT
0x0C
0x0D
0x0E
0x0F
0x10
...0xFF
SWITCH
CRC_VER
CRC_CALC
SET_MTC
RES_MTC
no function
Bank 0
Table 106: Command to be executed on falling edge of
NPRES
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VPD
47k
VPD
PA0
VND
NPRES
VND
Figure 46: External circuitry for NPRES functionality
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POSITION OFFSET VALUES AND PRESET FUNCTION
MODE_MT
MSB
MT
MSB
MPC
LSB
MPC
MSB
MAS
LSB+2
MAS
ADR 0x27
bit 7
ADR 0x25
bit 0
ADR 0x24
bit 7
ADR 0x23
bit 4
PRES_POS ADR 0x2E
bit 7
ADR 0x2C
bit 0
ADR 0x2B
bit 7
ADR 0x2A
bit 4
OFF_ABZ
LSB
MT
upper 12 bit of master track
MPC
Figure 47: Position of the parameters OFF_ABZ and PRES_POS with respect to configured multiturn
(MODE_MT), periods (MPC) and converter resolution
OFF_ABZ holds the position offset values stored
in the EEPROM. After startup or the commands
SOFT_RESET and ABS_RESET the OFF_ABZ values are amended to include the nonius data and the
multiturn data (in case an external multiturn is configured) and stored as OFF_POS in the internal RAM.
For output the OFF_POS value is subtracted with each
conversion from the internally synchronized result.
OFF_ABZ(3:0)
Addr. 0x23; bit 7:4
OFF_ABZ(11:4)
OFF_ABZ(19:12)
OFF_ABZ(27:20)
OFF_ABZ(35:28)
Addr.
Addr.
Addr.
Addr.
0x24;
0x25;
0x26;
0x27;
OFF_ABZ(3:0)
OFF_ABZ(11:4)
OFF_ABZ(19:12)
OFF_ABZ(27:20)
OFF_ABZ(35:28)
Addr.
Addr.
Addr.
Addr.
Addr.
SER:0x1E; bit 7:4
Code
bit 7:0
bit 7:0
bit 7:0
bit 7:0
Bank0
Bank0
SER:0x1F; bit 7:0
SER:0x48; bit 7:0
SER:0x49; bit 7:0
SER:0x4A; bit 7:0
Description
Preset function
The preset function corrects the output position value
of the ABZ, SPI, or BiSS interface to the setpoint given
by PRES_POS. Correction is initiated by writing command SOFT_PRES or SOFT_E2P_PRES to the command register (see page 52), or, if one of these commands is configured with PA0_CONF as NPRES command at PA0 pin, by a falling edge at NPRES. See
Table 28 for configuration of NPRES and Table 106 for
PA0_CONF.
When the preset function is started, the ABZ converter
is stopped. The current position is then determined.
The correction factor for output (OFF_POS) is calculated taking PRES_POS into account and stored in
the internal RAM. Offset values OFF_ABZ are computed and if the command SOFT_E2P_PRES is used
written to the external EEPROM. The ABZ converter is
then restarted.
0x000000000
...
Offset position relative to absolute position
0xFFFFFFFFF
PRES_POS(27:20)
Addr.
Addr.
Addr.
Addr.
PRES_POS(35:28)
Addr. 0x2E; bit 7:0
PRES_POS(3:0)
Addr. SER:0x4D; bit 7:4
Addr. SER:0x4E; bit 7:0
PRES_POS(3:0)
Table 107: Output offset position, relative to absolute
position
PRES_POS(11:4)
PRES_POS(19:12)
OFF_POS(19:12)
Addr. SER:0x20; bit 7:0
Bank0, R
PRES_POS(11:4)
OFF_POS(27:20)
OFF_POS(35:28)
Addr. SER:0x21; bit 7:0
Addr. SER:0x22; bit 7:0
Bank0, R
Bank0, R
PRES_POS(19:12)
Code
Description
PRES_POS(35:28)
Code
0x000000000
...
PRES_POS(27:20)
Offset (is automatically computed)
0xFFFFFFFFF
0x2A;
0x2B;
0x2C;
0x2D;
bit 7:4
bit 7:0
bit 7:0
bit 7:0
Addr. SER:0x4F; bit 7:0
Addr. SER:0x50; bit 7:0
Addr. SER:0x51; bit 7:0
Description
0x000000000
...
Preset position
0xFFFFFFFFF
Table 108: Output position offset amended by the nonius/MT
Table 109: Output position preset
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normal
operation
preset requested
stop ABZ engine
calculate offset-values
store offset values in EEPROM
restart ABZ engine
Figure 48: Preset sequence
SOFT_E2P_PRES
using
command
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DESIGN REVIEW: Notes On Chip Functions
iC-MU Z
No.
Function, Parameter/Code
Description and Application Notes
Please refer to datasheet release A3.
Table 110: Notes on chip functions regarding iC-MU chip release Z.
iC-MU Y1
No.
1
Function, Parameter/Code
Description and Application Notes
CRC of output data iC-MU(2):
IC operating mode BiSS or extended
SSI (MODEA = 0x2, 0x7) and 3-track
nonius with 4096 CPR (MPC = 12,
OUT_LSB = 0x0)
Effects the construction of a multiturn system with two iC-MU (Page 40):
3-track nonius configuration with 2 iC-MU and 4096 periods, sensor data output
using BiSS or extended SSI protocol (SSI with CRC) shows an invalid CRC.
Data output according to the SSI or SPI protocol is not affected.
Table 111: Notes on chip functions regarding iC-MU chip release Y1
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iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
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The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
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iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
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ORDERING INFORMATION
Type
Package
Order Designation
iC-MU
16-pin DFN 5 x 5 mm
iC-MU DFN16-5x5
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners