TI1 CDCLVP2102RGTR Four-lvpecl output, high-performance clock buffer Datasheet

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CDCLVP2102
SCAS881C – AUGUST 2009 – REVISED JANUARY 2016
CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer
1 Features
3 Description
•
•
•
The CDCLVP2102 is a highly versatile, low additive
jitter buffer that can generate four copies of LVPECL
clock outputs from two LVPECL, LVDS, or LVCMOS
inputs for a variety of communication applications. It
has a maximum clock frequency up to 2 GHz. Each
buffer block consists of one input that feeds two
LVPECL outputs. The overall additive jitter
performance is less than 0.1 ps, RMS from 10 kHz to
20 MHz, and overall output skew is as low as 10 ps,
making the device a perfect choice for use in
demanding applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
Dual 1:2 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
Four LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 48 mA
Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 450 ps
Maximum Within Bank Output Skew: 10 ps
LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to +85°C
Supports 105°C PCB Temperature (Measured
with a Thermal Pad)
Available in 3-mm × 3-mm, 16-Pin VQFN (RGT)
Package
ESD Protection Exceeds 2000 V (HBM)
The CDCLVP2102 clock buffer distributes two clock
inputs (IN0, IN1) to four pairs of differential LVPECL
clock outputs (OUT0, OUT3) with minimum skew for
clock distribution. Each buffer block consists of one
input that feeds two LVPECL clock outputs. The
inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2102 is specifically designed for driving
50-Ω transmission lines. When driving the inputs in
single-ended mode, the LVPECL bias voltage
(VAC_REF) should be applied to the unused negative
input pin. However, for high-speed performance up to
2 GHz, differential mode is strongly recommended.
The CDCLVP2102 is characterized for operation from
–40°C to +85°C and is available in a 3-mm × 3-mm,
VQFN-16 package.
2 Applications
•
•
•
•
Wireless Communications
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
Device Information(1)
PART NUMBER
CDCLVP2102
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCC
INP0
LVPECL
INN0
2
INP1
LVPECL
INN1
VAC_REF
2
2
2
OUTP[1,0]
OUTN[1,0]
OUTP[3,2]
OUTN[3,2]
Reference
Generator
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCLVP2102
SCAS881C – AUGUST 2009 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: LVCMOS Input, at VCC =
2.375 V to 3.6 V ........................................................ 6
6.6 Electrical Characteristics: Differential Input, at VCC =
2.375 V to 3.6 V ........................................................ 6
6.7 Electrical Characteristics: LVPECL Output, at VCC =
2.375 V to 2.625 V .................................................... 6
6.8 Electrical Characteristics: LVPECL Output, at VCC =
3 V to 3.6 V ............................................................... 6
6.9 Timing Requirements, at VCC = 2.375 V to 2.625 V . 7
6.10 Timing Requirements, at VCC = 3 V to 3.6 V ......... 8
6.11 Typical Characteristics .......................................... 10
7
Parameter Measurement Information ................ 11
7.1 Test Configurations ................................................. 11
8
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram ......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
13
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
11.3 Thermal Considerations ........................................ 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2011) to Revision C
Page
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes
section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................. 1
•
Added support for 105°C thermal pad temperature .............................................................................................................. 1
•
Deleted Device Comparison table; information in POA ......................................................................................................... 1
•
Changed order of Pin Functions table to alphabetical by pin name ...................................................................................... 4
•
Added PCB temperature to Recommended Operating Conditions ....................................................................................... 5
•
Added VOH specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V ....... 6
•
Added VOL specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V ........ 6
•
Added IEE specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V ......... 6
•
Added ICC specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V ......... 6
•
Added VOH specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V .................. 6
•
Added VOL specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V ................... 7
•
Added IEE specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V .................... 7
•
Added ICC specification for TPCB≤ 105ºC in Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V .................... 7
•
Added tRJIT for f
•
Added tRJIT for fOUT = 122.88 MHz, Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz ................................................... 8
•
Added tRJIT for fOUT = 156.25 MHz, Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz ................................................... 8
•
Added tRJIT for fOUT = 312.5 MHz, Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz ..................................................... 8
•
Added 100 MHz Wenzel oscillator, Input slew rate = 0.9 V/ns (single-ended) footnote ....................................................... 8
2
OUT
= 100 MHz, Input AC coupled, VICM = VAC_REF, 12 kHz to 20 MHz ....................................................... 8
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Changes from Revision A (October 2009) to Revision B
Page
•
Revised description of pin 8 in .............................................................................................................................................. 4
•
Corrected VIL parameter description in Electrical Characteristics table for LVCMOS input ................................................... 6
•
Added footnote (2) to Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V ........................................... 6
•
Changed recommended resistor values in Figure 12(a) ...................................................................................................... 14
•
Changed recommended resistor values in Figure 16........................................................................................................... 16
•
Changed recommended resistor values in Figure 17........................................................................................................... 16
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5 Pin Configuration and Functions
8
VAC_REF
7
INN0
6
INP0
5
VCC
OUTP1
OUTN0
OUTP0
11
10
9
4
INN1
(1)
3
16
Thermal Pad
INP1
15
2
OUTP3
NC
14
CDCLVP2102
1
OUTN2
OUTN3
OUTN1
13
GND
OUTP2
12
RGT Package
16-Pin VQFN
Top View
Thermal pad must be soldered to ground.
Pin Functions
PIN
NAME
NO.
GND
TYPE
DESCRIPTION
1
Ground
INP0, INN0
6, 7
Input
Differential input pair or single-ended input no. 0
INP1, INN1
3, 4
Input
Differential input pair or single-ended input no. 1
OUTP0 OUTN0
9, 10
Output
Differential LVPECL output pair no. 0
OUTP1, OUTN1
11, 12
Output
Differential LVPECL output pair no. 1
OUTP2, OUTN2
13, 14
Output
Differential LVPECL output pair no. 2
OUTP3, OUTN3
15, 16
Output
Differential LVPECL output pair no. 3
VAC_REF
8
Output
Bias voltage output for capacitive-coupled input pair no. 0. Do not use VAC_REF at VCC < 3
V. If used, TI recommends using a 0.1-μF capacitor to GND on this pin. The output
current is limited to 2 mA.
VCC
5
Power
2.5-V or 3.3-V supply for the device
NC
2
—
4
Device ground
Do not connect
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage (2)
VCC
(3)
VIN
Input voltage
VOUT
Output voltage (3)
IIN
Input current
IOUT
Output current
TA
Specified free-air temperature (no airflow)
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
MIN
MAX
UNIT
–0.5
4.6
V
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
V
20
mA
50
mA
85
°C
125
°C
150
°C
–40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All supply voltages must be supplied simultaneously.
The input and output negative voltage ratings may be exceeded if the input clamp-current and output clamp-current ratings are
observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
TA
Ambient temperature
TPCB
PCB temperature (measured at thermal pad)
MIN
NOM
MAX
UNIT
2.375
2.5/3.3
3.60
V
85
°C
–40
105
°C
6.4 Thermal Information
CDCLVP2102
THERMAL METRIC (1) (2) (3)
RGT (VQFN)
UNIT
16 PINS
51.8 (4)
°C/W
79
°C/W
6.12 (4)
°C/W
Junction-to-top characterization parameter
1.4
°C/W
Junction-to-board characterization parameter
19
°C/W
Junction-to-case (bottom) thermal resistance
6.12
°C/W
RθJA
Junction-to-ambient thermal resistance (0 LFM)
RθJC(top)
Junction-to-case (top) thermal resistance
RθJP (5)
Junction-to-pad thermal resistance
ψJT
ψJB
RθJC(bot)
(1)
(2)
(3)
(4)
(5)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).
Connected to GND with four thermal vias (0.3-mm diameter).
2 × 2 vias on pad
RθJP (junction-to-pad) is used for the VQFN package, because the primary heat flow is from the junction to the GND pad of the VQFN
package.
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6.5 Electrical Characteristics: LVCMOS Input, at VCC = 2.375 V to 3.6 V
at TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted)
PARAMETER
fIN
(1)
TEST CONDITIONS
MAX
UNIT
200
MHz
1.8
V
Vth + 0.1
VCC
V
0
Vth – 0.1
V
40
μA
External threshold voltage applied to
complementary input
Vth
Input threshold voltage
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
VCC = 3.6 V, VIH = 3.6 V
IIL
Input low current
VCC = 3.6 V, VIL = 0 V
ΔV/ΔT
Input edge rate
20% to 80%
ICAP
Input capacitance
(1)
MIN
TYP
Input frequency
1.1
–40
1.5
μA
V/ns
5
pF
Figure 5 and Figure 6 show DC test setup.
6.6 Electrical Characteristics: Differential Input, at VCC = 2.375 V to 3.6 V
at TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted)
PARAMETER
fIN
Input frequency
(1)
TEST CONDITIONS
TYP
MAX
UNIT
2000
MHz
fIN ≤ 1.5 GHz
0.1
1.5
V
1.5 GHz ≤ fIN ≤ 2 GHz
0.2
1.5
V
1
VCC – 0.3
V
40
μA
VIN, DIFF, PP
Differential input peak-peak voltage
VICM
Input common-mode level
IIH
Input high current
VCC = 3.6 V, VIH = 3.6 V
IIL
Input low current
VCC = 3.6 V, VIL = 0 V
ΔV/ΔT
Input edge rate
20% to 80%
ICAP
Input capacitance
(1)
MIN
Clock input
–40
1.5
μA
V/ns
5
pF
Figure 7 and Figure 8 show DC test setup. Figure 9 shows AC test setup.
6.7 Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V
at TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC – 1.26
TPCB ≤ 105°C
VCC – 1.26
Output high voltage
VOL
Output low voltage
VOUT, DIFF, PP
Differential output peak-peak voltage
fIN ≤ 2 GHz
VAC_REF
Input bias voltage (2)
IAC_REF = 2 mA
ICC
(1)
(2)
Supply internal current
Output and internal supply current
MIN
TA = –40°C to 85°C
VOH
IEE
(1)
TYP
MAX
VCC – 0.9
=
VCC – 0.83
TA = –40°C to 85°C
VCC – 1.7
VCC – 1.3
TPCB ≤ 105°C
VCC – 1.7
VCC – 1.25
UNIT
V
V
0.5
1.35
V
VCC – 1.6
VCC – 1.1
V
Outputs unterminated,
TA ≤ 85°C
48
Outputs unterminated,
TPCB ≤ 105°C
49
mA
All outputs terminated, 50 Ω to VCC – 2
TA ≤ 85°C
173
All outputs terminated, 50 Ω to VCC – 2
TPCB ≤ 105°C
189
mA
Figure 10 and Figure 11 show DC and AC test setup.
Internally generated bias voltage (VAC_REF) is for 3.3-V operation only. TI recommends applying externally generated bias voltage for
VCC < 3 V.
6.8 Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V
at TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted) (1)
PARAMETER
VOH
(1)
6
Output high voltage
TEST CONDITIONS
MIN
TYP
MAX
TA ≤ 85°C
VCC – 1.26
VCC – 0.9
TPCB ≤ 105°C
VCC – 1.26
VCC – 0.85
UNIT
V
Figure 10 and Figure 11 show DC and AC test setup.
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Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V (continued)
at TA = –40°C to +85°C and TPCB ≤ 105°C (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
TPCB ≤ 105°C
VCC – 1.7
VCC – 1.3
VOUT, DIFF, PP
Differential output peak-peak voltage
fIN ≤ 2 GHz
VAC_REF
Input bias voltage
IAC_REF = 2 mA
ICC
Output and internal supply current
MAX
VCC – 1.3
Output low voltage
Supply internal current
TYP
VCC – 1.7
VOL
IEE
MIN
TA ≤ 85°C
UNIT
V
0.65
1.35
V
VCC – 1.6
VCC – 1.1
V
Outputs unterminated,
TA ≤ 85°C
48
Outputs unterminated,
TPCB ≤ 105°C
49
mA
All outputs terminated, 50 Ω to VCC – 2
TA ≤ 85°C
173
All outputs terminated, 50 Ω to VCC – 2
TPCB ≤ 105°C
189
mA
6.9 Timing Requirements, at VCC = 2.375 V to 2.625 V
Refer to Figure 1 and Figure 2.
MIN
VIN, DIFF, PP = 0.3 V
450
Propagation delay
tSK,PP
Part-to-part skew
tSK,O_WB
Within bank output skew
tSK,O_BB
Bank-to-bank output skew
Both inputs have equal skew
Pulse skew (with 50% duty cycle input)
Crossing-point-to-crossing-point
distortion, fOUT = 100 MHz
tRJIT
PSPUR
tR/tF
Output rise/fall time
–50
UNIT
ps
100
ps
10
ps
15
ps
50
ps
fOUT = 100 MHz, VIN,SE = VCC,
Vth = 1.25 V, 10 kHz to 20 MHz
0.089
ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
0.093
ps, RMS
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
0.037
ps, RMS
0.094
ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
0.091
ps, RMS
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15
V,
VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz,
VIN,SE,1 = VCC, Vth, 1 = VCC/2
–52.5
dBc
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15
V,
VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz,
VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V
–66.8
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15
V,
VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz,
VIN,SE,1 = VCC, Vth, 1 = VCC/2
–52
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15
V,
VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz,
VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V
–66.4
Random additive jitter (with 50% duty cycle fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
input)
VICM = 1 V, 10 kHz to 20 MHz
Coupling on differential OUT8 from OUT7
in the frequency spectrum
of fOUT, 8 ±(fOUT, 8/2) with
synchronous inputs
MAX
450
tPD
tSK,P
NOM
VIN, DIFF, PP = 0.1 V
20% to 80%
dBc
200
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6.10 Timing Requirements, at VCC = 3 V to 3.6 V
Refer to Figure 1 and Figure 2.
MIN
MAX
VIN, DIFF, PP = 0.1 V
450
VIN, DIFF, PP = 0.3 V
450
tPD
Propagation delay
tSK,PP
Part-to-part skew
tSK,O_WB
Within bank output skew
tSK,O_BB
Bank-to-bank output skew
Both inputs have equal skew
Pulse skew (with 50% duty cycle input)
Crossing-point-to-crossing-point
distortion, fOUT = 100 MHz
tSK,P
NOM
–50
fOUT = 100 MHz, (1) VIN,SE = VCC,
Vth = 1.65 V, 10 kHz to 20 MHz
UNIT
ps
100
ps
10
ps
15
ps
50
ps
0.081
ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
0.097
ps, RMS
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
0.05
ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP =
0.15 V,
VICM = 1 V, 10 kHz to 20 MHz
0.098
ps, RMS
fOUT = 100 MHz, (1) VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
0.095
ps, RMS
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 =
0.15 V,
VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz,
VIN,SE,1 = VCC, Vth, 1 = VCC/2
–55.3
dBc
fOUT = 100 MHz (2), Input ACcoupled,
VICM = VAC_REF, 12 kHz to 20 MHz
0.068
ps, RMS
fOUT = 122.88 MHz (3), Input ACcoupled,
VICM = VAC_REF, 12 kHz to 20 MHz
0.056
ps, RMS
fOUT = 156.25 MHz (4), Input ACcoupled,
VICM = VAC_REF, 12 kHz to 20 MHz
0.047
ps, RMS
fOUT = 312.5 MHz (5), Input ACcoupled,
VICM = VAC_REF, 12 kHz to 20 MHz
0.026
ps, RMS
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 =
0.15 V,
VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz,
VIN,SIFF,PP,1 = 1 V, VICM, 1 = 1 V
–65.1
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 =
0.15 V,
VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz,
VIN,SE,1 = VCC, Vth, 1 = VCC/2
–54.7
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 =
0.15 V,
VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz,
VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V
–66.7
(1)
(1)
Random additive jitter (with 50% duty cycle
input)
tRJIT
PSPUR
tR/tF
(1)
(2)
(3)
(4)
(5)
8
Coupling on differential OUT8 from OUT7 in
the frequency spectrum
of fOUT, 8 ±(fOUT, 8/2) with
synchronous inputs
Output rise/fall time
20% to 80%
dBc
200
ps
100-MHz Wenzel oscillator, Input slew rate = 0.9 V/ns (single-ended)
100-MHz Wenzel oscillator, Input slew rate = 3.4 V/ns (differential)
122.88-MHz Rohde & Schwarz SMA100A, Input slew rate = 3.7 V/ns (differential)
156.25-MHz Crystek CPRO33 oscillator, Input slew rate = 2.9 V/ns (differential)
312.5-MHz Rohde & Schwarz SMA100A, Input slew rate = 4 V/ns (differential)
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Figure 1 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 2.
VOH
OUTNx
VOD
VOL
OUTPx
80%
VOUT,DIFF,PP (= 2 ´ VOD)
20%
0V
tR
tF
Figure 1. Output Voltage and Rise/Fall Time
INNx
INPx
tPLH0
tPLH0
tPLH1
tPLH1
OUTN0
OUTP0
OUTN1
OUTP1
tPLH2
tPLH2
OUTN2
OUTP2
tPLH3
tPLH3
OUTN3
OUTP3
(1)
Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn
(n = 0, 1, 2, 3), or as the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, 3).
(2)
Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn (n = 0, 1, 2, 3) across multiple devices, or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2,
3) across multiple devices.
Figure 2. Output and Part-to-Part Skew
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6.11 Typical Characteristics
1.0
VCC = 2.375 V
TA = -40°C to +85°C
VICM = 1 V
VIN,DIFF,PP = Min
0.9
0.8
0.7
0.6
0.5
0.4
0
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Differential Output Peak-to-Peak Voltage (V)
Differential Output Peak-toPeak Voltage (V)
at TA = –40°C to +85°C (unless otherwise noted)
1.1
1.2
1.3
1.0
0.9
0.8
0.7
VCC = 3.0 V
TA = -40°C to +85°C
VICM = 1 V
VIN,DIFF,PP = Min
0.6
0.5
0.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Frequency (GHz)
Frequency (GHz)
Figure 3. Differential Output Peak-to-Peak Voltage vs
Frequency
Figure 4. Differential Output Peak-to-Peak Voltage vs
Frequency
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7 Parameter Measurement Information
7.1 Test Configurations
Figure 5 through Figure 11 show how the device should be set up for a variety of test configurations.
IN
VIH
Vth
VIL
IN
Vth
Figure 5. DC-Coupled LVCMOS Input During Device Test
VCC
VIHmax
Vthmax
VILmax
VIH
Vth
Vth
VIL
VIHmin
Vthmin
VILmin
GND
Figure 6. Vth Variation over LVCMOS Levels
VCC
VCC
130 W
130 W
CDCLVP2102
LVPECL
82 W
82 W
Figure 7. DC-Coupled LVPECL Input During Device Test
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Test Configurations (continued)
100 W
LVDS
CDCLVP2102
Figure 8. DC-Coupled LVDS Input During Device Test
VCC
VCC
82 W
82 W
CDCLVP2102
Differential
130 W
130 W
Figure 9. AC-Coupled Differential Input to Device
Oscilloscope
LVPECL
50 W
50 W
VCC - 2 V
Figure 10. LVPECL Output DC Configuration During Device Test
Phase Noise
Analyzer
LVPECL
150 W
150 W
50 W
Figure 11. LVPECL Output AC Configuration During Device Test
12
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8 Detailed Description
8.1 Overview
The CDCLVP2102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are
required to ensure correct operation of the device and to minimize signal integrity. The proper termination for
LVPECL outputs is a 50 Ω to (VCC – 2) V, but this direct-coupled (DC) voltage is not readily available on PCB.
Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both DC- and AC-coupled
configurations. These configurations are shown in Figure 12 (a and b) for VCC = 2.5 V and Figure 13 (a and b) for
VCC = 3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the
receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.
8.2 Functional Block Diagram
VCC
INP0
LVPECL
INN0
2
INP1
LVPECL
INN1
VAC_REF
2
2
2
OUTP[1,0]
OUTN[1,0]
OUTP[3,2]
OUTN[3,2]
Reference
Generator
GND
8.3 Feature Description
The CDCLVP2102 is a low-additive jitter universal to LVPECL fan-out buffer with two independent inputs. The
small package, low output skew, and low-additive jitter make for a flexible device in demanding applications.
8.4 Device Functional Modes
The two independent inputs of the CDCLVP2102 distribute the input clock to two outputs each. Unused inputs
and outputs can be left floating to reduce overall component cost. Both AC- and DC coupling schemes can be
used with the CDCLVP1204 to provide greater system flexibility.
8.4.1 LVPECL Output Termination
The CDCLVP2102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are
required to ensure correct operation of the device and to minimize signal integrity. The proper termination for
LVPECL outputs is a 50 Ω to (VCC –2) V, but this DC voltage is not readily available on PCB. Therefore, a
Thevenin equivalent circuit is worked out for the LVPECL termination in both DC- and AC-coupled configurations.
These configurations are shown in Figure 12 a and b for VCC = 2.5 V and Figure 13 a and b for VCC = 3.3 V,
respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If
the supply voltage for the driver and receiver is different, AC coupling is required.
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Device Functional Modes (continued)
VCC
VCC
250 W
250 W
CDCLVP2102
LVPECL
62.5 W
62.5 W
(a) Output DC Termination
VBB
CDCLVP2102
LVPECL
86 W
86 W
50 W
50 W
(b) Output AC Termination
Figure 12. LVPECL Output DC and AC Termination for VCC = 2.5 V
14
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Device Functional Modes (continued)
VCC
VCC
130 W
130 W
CDCLVP2102
LVPECL
82 W
82 W
(a) Output DC Termination
VBB
CDCLVP2102
150 W
LVPECL
150 W
50 W
50 W
(b) Output AC Termination
Figure 13. LVPECL Output DC and AC Termination for VCC = 3.3 V
8.4.2 Input Termination
The CDCLVP2102 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 14 shows how to
DC-couple an LVCMOS input to the CDCLVP2102. The series resistance (RS) must be placed close to the
LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver
output impedance.
VIH
Vth
VIL
RS
LVCMOS
CDCLVP2102
Vth =
VIH + VIL
2
Figure 14. DC-Coupled LVCMOS Input to CDCLVP2102
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Device Functional Modes (continued)
Figure 15 shows how to DC-couple LVDS inputs to the CDCLVP2102. Figure 16 and Figure 17 describe the
method of DC coupling LVPECL inputs to the CDCLVP2102 for VCC = 2.5 V and VCC = 3.3 V, respectively.
100 W
LVDS
CDCLVP2102
Figure 15. DC-Coupled LVDS Inputs to CDCLVP2102
VCC
VCC
250 W
250 W
CDCLVP2102
LVPECL
62.5 W
62.5 W
Figure 16. DC-Coupled LVPECL Inputs to CDCLVP2102 (VCC = 2.5 V)
VCC
VCC
130 W
130 W
CDCLVP2102
LVPECL
82 W
82 W
Figure 17. DC-Coupled LVPECL Inputs to CDCLVP2102 (VCC = 3.3 V)
16
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Device Functional Modes (continued)
Figure 18 and Figure 19 show the technique of AC coupling differential inputs to the CDCLVP2102 for
VCC = 2.5 V and VCC = 3.3 V, respectively. TI recommends placing all resistive components close to either the
driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is
required.
VCC
VCC
96 W
96 W
CDCLVP2102
Differential
105 W
105 W
Figure 18. AC-Coupled LVPECL Inputs to CDCLVP2102 (VCC = 2.5 V)
VCC
VCC
82 W
82 W
CDCLVP2102
Differential
130 W
130 W
Figure 19. AC-Coupled LVPECL Inputs to CDCLVP2102 (VCC = 3.3 V)
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCLVP2102 is a low additive jitter LVPECL fan-out buffer that can generate two copies each of two
independent LVPECL, LVDS, or LVCMOS inputs. The CDCLVP2102 can accept reference clock frequencies up
to 2 GHz while providing low output skew.
9.2 Typical Application
Figure 20 shows a fan-out buffer for line-card application.
2.5 V
2.5 V
96
PHY
PRIREF_P
156.25 MHz LVPECL
from backplane
100
PRIREF_N
105
86
86
2.5 V ASIC
250
CDCLVP21xx
62.5
156.25 MHz LVCMOS
Oscillator
SECREF_P
FPGA
100
2.5 V
1k
86
86
SECREF_N
1k
CPU
100
86
86
Figure 20. CDCLVP2102 Typical Application
9.2.1 Design Requirements
The CDCLVP2102 shown in Figure 20 is configured to be able to select two inputs: a 156.25-MHz LVPECL clock
from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out
to desired devices, as shown.
The configuration example is driving 4 LVPECL receivers in a line-card application with the following properties:
• The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP2102 must
be provided with 86-Ω emitter resistors near the driver for proper operation.
• The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP2102. This ASIC
features internal termination so no additional components are needed.
18
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Typical Application (continued)
•
The FPGA requires external AC coupling but has internal termination. Again, 86-Ω emitter resistors are
placed near the CDCLVP2102, and 0.1 μF are placed to provide AC coupling. Similarly, the CPU is internally
terminated and requires external AC coupling capacitors.
9.2.2 Detailed Design Procedure
Refer to Input Termination for proper input terminations, dependent on single ended or differential inputs.
Refer to LVPECL Output Termination for output termination schemes depending on the receiver application.
Unused outputs can be left floating.
In Figure 20, the PHY, ASIC, and FPGA/CPU require different schemes. Power supply filtering and bypassing is
critical for low-noise applications.
See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided on
the CDCLVP2102 Evaluation Module, Low Additive Phase Noise Clock Buffer Evaluation Board User's Guide
(SCAU033).
9.2.3 Application Curves
Reference signal is low-noise Crystek XO CPRO33.156.25
32 fs, RMS
10 kHz to 20 MHz
Figure 21. CDCLVP21xx Reference Phase Noise
57 fs, RMS
10 kHz to 20 MHz
Figure 22. CDCLVP21xx Output Phase Noise
The low additive noise of the CDCLVP2102 can be shown in this line-card application. The low noise 156.25
MHz XO with 32-fs, RMS jitter drives the CDCLVP2102, resulting in 57 fs, RMS when integrated from 10 kHz to
20 MHz. The resultant additive jitter is a low 47 fs, RMS for this configuration.
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10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is very critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. TI
recommends adding as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply pins in
the package. TI recommends, but does not require, inserting a ferrite bead between the board power supply and
the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low DC resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
Figure 23 shows this recommended power-supply decoupling method.
Board
Supply
VCC
Chip
Supply
Ferrite Bead
C
10 mF
C
1 mF
C
0.1 mF
Figure 23. Power-Supply Decoupling
20
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11 Layout
11.1 Layout Guidelines
Power consumption of the CDCLVP2102 can be high enough to require attention to thermal management. For
reliability and performance reasons, the die temperature must be limited to a maximum of 125°C. That is, as an
estimate, ambient temperature (TA) plus device power consumption times RθJA must not exceed 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be
soldered down to ensure adequate heat conduction out of the package. Figure 24 shows a recommended land
and via pattern.
11.2 Layout Example
1,6 mm (min)
0,33 mm (typ)
0,5 mm (typ)
Figure 24. Recommended PCB Layout
11.3 Thermal Considerations
The CDCLVP2102 supports high temperatures on the printed circuit board (PCB) measured at the thermal pad.
The system designer must ensure that the maximum junction temperature is not exceeded. ΨJB can allow the
system designer to measure the board temperature with a fine gauge thermocouple and back calculate the
junction temperature using Equation 1. Note that Ψjb is close to RθJB because 75 to 95% of the heat of a device
is dissipated by the PCB. Further information can be found at SPRA953 and SLUA566.
Tjunction = TPCB + (ΨJB × Power)
(1)
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TPCB = 105°C
ΨJB = 19°C/W
PowerinclTerm = Imax × Vmax = 189 mA × 3.6 V = 680 mW (maximum power consumption including
termination resistors)
PowerexclTerm = 529 mW (maximum power consumption excluding termination resistors, see SLYT127 for
further details)
ΔTjunction = ΨJB × PowerexclTerm = 19°C/W × 529 mW = 10.06°C
Tjunction = ΔTjunction + TChassis = 10.06°C + 105°C = 115°C (the maximum junction temperature of 125°C is
not violated)
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• CDCLVP2102 Evaluation Module, Low Additive Phase Noise Clock Buffer Evaluation Board User's Guide
(SCAU033)
• Using Thermal Calculation Tools for Analog Components (SLUA566)
• Power Consumption of LVPECL and LVDS (SLYT127)
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDCLVP2102RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2102
CDCLVP2102RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2102
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCLVP2102RGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
CDCLVP2102RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCLVP2102RGTR
QFN
RGT
16
3000
338.1
338.1
20.6
CDCLVP2102RGTT
QFN
RGT
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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