ICST ICS94236 Programmable system clock chip for amd - k7â ¢ processor Datasheet

ICS94236
Integrated
Circuit
Systems, Inc.
Programmable System Clock Chip for AMD - K7™ processor
Recommended Application:
VIA KX/KT133 style chipset
Output Features:
•
1 - Differential pair open drain CPU clocks
•
1 - CPU clock @ 3.3V
•
13 - SDRAM @ 3.3V
•
6 - PCI @3.3V,
•
1 - 48MHz, @3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
2 - REF @3.3V, 14.318MHz.
Pin Configuration
Features:
•
Programmable ouput frequency.
•
Programmable ouput rise/fall time.
•
Programmable PCI_F and PCICLK skew.
•
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Uses external 14.318MHz crystal.
•
FS pins for frequency select
Block Diagram
48MHz
/2
XTAL
OSC
24_48MHz
REF (1:0)
CPUCLK
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLKC0
CPUCLKT0
SEL24_48#
Control
SDATA
SCLK
Logic
FS (4:0)
Config.
PD#
Reg.
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
BUFFER IN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1/FS2**
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDCPU
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24/48MHz/FS1**
48-Pin 300mil SSOP
*
**
1
Internal Pull-up Resistor of 120K to VDD.
Internal Pull-down Resistor of 120K to GND.
Internal Pull-down Resistor of 60K to GND.
Functionality
PLL2
X1
X2
VDDREF
REF0
GND
X1
X2
VDDPCI
1
FS4/PCICLK_F
**FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDATA
SCLK
FS 3
FS 2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
( M H z)
95.00
100.00
102.00
105.00
110.00
113.00
115.00
120.00
1 3 3 . 33
135.00
137.00
139.00
141.00
143.00
145.00
150.00
P C IC L K
(MHz)
31.67
33.33
34.00
35.00
36.67
37.67
38.33
40.00
33.33
33.75
34.25
34.75
35.25
35.75
36.25
37.50
* 16 additional frequency selectables via FS4, refer to page5
for frequency table.
0451A—01/10/03
ICS94236
General Description
The ICS94236 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The ICS94236 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Pin Descriptions
P I N N U MB E R
1
PIN NAME
V DDR E F
2
R E F0
3,9,16,22,
33,39,45, 47
GND
TY P E
DE SCRIPT ION
P WR R EF, XTA L p ow er su pp ly, no minal 3.3 V
1 4.3 1 8 Mh z r ef er en ce clo ck.Th is REF ou tpu t is th e STRONGER
O UT
bu f f e r f o r I S A B U S l oa d s
P WR
4
X1
IN
5
X2
OUT
V DDPC I
P WR
PCICLK_F
O UT
6,14
7
FS4 2
2
8
10
11, 12, 13
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
19,30,36
23
24
25
26
IN
Gro u nd
Cr ys tal in pu t, h as in tern al lo ad cap (3 6 pF) an d f eedb ack
r e s i s t o r f ro m X 2
Cr ys tal o utp ut, no minally 1 4.3 1 8MH z. Has in ter n al load
c a p ( 3 6 pF )
S up ply f o r PC IC LK_F an d PC IC LK, no min al 3 .3V
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock output
Logic input to select 24 or 48MHz for pin 25 output
PCI clock output.
PCI clock outputs.
Input to Fanout Buffers for SDRAM outputs.
FS3
PCICLK0
SEL24_48#1, 2
PCICLK1
PCICLK(2:4)
BUFFER IN
IN
O UT
IN
O UT
O UT
IN
SDRAM (11:0)
O UT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
VDDSDR
SDATA
SCLK
PWR
IN
IN
Supply for SDRAM nominal 3.3V.
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24_48MHz
O UT
FS1 2
48MHz
FS0 2
IN
O UT
IN
24MHz/48MHz clock output
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
27
VDD48
PWR
40
SDRAM_OUT
O UT
Reference clock for SDRAM zero delay buffer
41
42
PD#1, 2
VDDCPU
IN
PWR
43
CPUCLKT0
O UT
44
CPUCLKC0
O UT
46
CPUCLK
REF1
FS22
O UT
OUT
IN
Powers down chip, active low
Supply for CPU clock 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
3.3V CPU clock output powered by VDDCPU
14.318 MHz reference clock.
Frequency select pin. Latched Input
48
Power for 24 & 48MHz output buffers and fixed PLL core.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0451A—01/10/03
2
ICS94236
General I2C serial interface information for the ICS94236
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
Address D2(H)
Controller (Host)
Start Bit
Address D3 (H )
ICS (Slave/Receiver)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
If 7H has been written to B8
ACK
Byte 6
Byte 18
If 12H has been written to B8
ACK
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
Byte 19
Byte 20
Stop Bit
*See notes on the following page.
0451A—01/10/03
3
ICS (Slave /Receive r)
ICS94236
Brief I2C registers description for ICS94236
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
2
Functionality & Frequency
Select Register
0
Output frequency, hardware / I C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00 H to this byte.
08H
Watchdog Timer
Count Register
9
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
10H
Watchdog Control Registers 10 Bit [6:0]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
10 Bit [7]
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
Registers
15-16
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1.
2.
3.
4.
5.
6.
7.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0451A—01/10/03
4
ICS94236
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
P WD
Description
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK PCICLK
Spread %
FS4 FS3 FS2 FS1 FS0
MH z
MHz
0
0
0
0
0
95.00
31.67
0.45% Center Spread
0
0
0
0
1
100.00
33.33
0.45% Center Spread
0
0
0
1
0
102.00
34.00
0.45% Center Spread
0
0
0
1
1
105.00
35.00
0.45% Center Spread
0
0
1
0
0
110.00
36.67
0.45% Center Spread
0
0
1
0
1
113.00
37.67
0.45% Center Spread
0
0
1
1
0
115.00
38.33
0.45% Center Spread
0
0
1
1
1
120.00
40.00
0.45% Center Spread
0
1
0
0
0
133.33
33.33
0.45% Center Spread
0
1
0
0
1
135.00
33.75
0.45% Center Spread
0
1
0
1
0
137.00
34.25
0.45% Center Spread
0
1
0
1
1
139.00
34.75
0.45% Center Spread
0
1
1
0
0
141.00
35.25
0.45% Center Spread
0
1
1
0
1
143.00
35.75
0.45% Center Spread
0
1
1
1
0
145.00
36.25
0.45% Center Spread
0
1
1
1
1
150.00
37.50
0.45% Center Spread
1
0
0
0
0
100.90
33.63
0.45% Center Spread
1
0
0
0
1
100.00
33.33
0 to - 0.7% spread
1
0
0
1
0
103.00
34.33
0.45% Center Spread
1
0
0
1
1
107.00
35.67
0.45% Center Spread
1
0
1
0
0
117.00
39.00
0.45% Center Spread
1
0
1
0
1
120.00
30.00
0.45% Center Spread
1
0
1
1
0
123.00
30.75
0.45% Center Spread
1
0
1
1
1
125.00
31.25
0.45% Center Spread
1
1
0
0
0
133.33
33.33
0 to - 0.7% spread
1
1
0
0
1
133.90
33.48
0.45% Center Spread
1
1
0
1
0
147.00
36.75
0.45% Center Spread
1
1
0
1
1
151.00
37.75
0.45% Center Spread
1
1
1
0
0
153.00
38.25
0.45% Center Spread
1
1
1
0
1
155.00
38.75
0.45% Center Spread
1
1
1
1
0
160.00
40.00
0.45% Center Spread
1
1
1
1
1
200.00
50.00
0.45% Center Spread
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable
0- Running
1- Tristate all outputs
Note 1
0
1
0
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0451A—01/10/03
5
ICS94236
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PI N #
PWD
Bit 7
-
X
Bit 6
46
1
CPUCLK
Bit 5
-
1
(Reserved)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
DE S CR I P TI ON
FS2#
BI T
PI N#
P WD
Bi t 7
-
X
DE S C RI P T IO N
Bit 6
7
1
PCICLK_F
Bit 5
-
1
(Reserved)
FS0#
Bit 4
-
X
FS3#
Bit 3
40
1
SDRAM_OUT
Bit 4
13
1
PCICLK4
(SEL24_48#)#
CPUCLK0 enable (both
differential pair. "True" and
Complimentary")
(Reserved)*
Bit 3
12
1
PCICLK3
Bit 2
11
1
PCICLK2
Bi t 1
10
1
PCICLK1
Bit 0
8
1
PCICLK0
Bit 2
-
X
Bit 1
43,44
1
Bit 0
-
1
Note:
* It is recommended to drive this bit to 0.
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
B IT
P IN#
P WD
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
B IT
DE S CR IP T I O N
PI N# PW D
Bit 7
-
1
(Reserved)
Bi t 6
-
1
(Reserved)
Bi t 6
29
1
S DRAM 6
Bit 5
26
1
48MHz
Bit 5
31
1
S DRAM 5
Bi t 4
25
1
24_48MHz
Bi t 4
32
1
S DRAM 4
1
SD R A M 1 1
Bi t 3
34
1
S DRAM 3
Bit 3
17
28
DE SCRI PTI ON
Bit 7
1
S DRAM 7
Bi t 2
18
1
SD R A M 1 0
Bi t 2
35
1
S DRAM 2
Bit 1
20
1
SD R A M 9
Bit 1
37
1
S DRAM 1
Bi t 0
21
1
SD R A M 8
Bi t 0
38
1
S DRAM 0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BI T
PI N# PW D
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
B IT
B it7
B i t6
B it 5
B i t4
B it 3
B i t2
B it1
B i t0
DE S CR IP T I ON
Bi t 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
X
Mode
Bit 3
-
X
FS1#
Bit 2
-
1
(Reserved)
Bi t 1
48
1
REF 1
Bit 0
2
1
REF0
P IN#
-
PWD
0
0
0
0
0
1
1
0
D ESCRI PTI ON
Res erved (Not e)
Res erved (Not e)
Res erved (Not e)
Res erved (Not e)
Res erved (Not e)
Res erved (Not e)
Res erved (Not e)
Res erved (Not e)
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0451A—01/10/03
6
ICS94236
Byte 7: Vendor ID and Revision ID Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
1
X
X
X
X
X
Byte 8: Byte Count and Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
PWD
0
0
0
0
0
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
1
0
0
0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 290ms.
PWD
0
0
0
1
0
0
0
0
Description
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
VCO Divider Bit0
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
0451A—01/10/03
7
ICS94236
Byte 13: Spread Sectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Byte 14:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Spread Spectrum Bit7
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Sectrum Control Register
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0
0
PCI_F Skew Control
0
0
0
0
PCICLK [0:4] Skew Control
0
0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
1
X
0
1
0
1
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 18: Output Rise/Fall Time Select Register
Byte 17: Output Rise/Fall Time Select Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLKT0
CPUCLKC0
Reserved
CPUCLK
SDRAM_OUT: Slew Rate Control
SDRAM [0:11] Slew Rate Control
PWD
1
0
1
0
1
0
1
0
Description
PCI [0:4]: Slew Rate Control
PCI_F Slew Rate Control
48MHz: Slew Rate Control
24MHz: Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting.
Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first
pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
0451A—01/10/03
8
ICS94236
Byte 19: Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Byte 20: Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
are unused registers writing to these registers
will not affect device performance or
functinality.
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO
frequency.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount
desired. See Application note for software support.
0451A—01/10/03
9
ICS94236
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
VIN = VDD
Input High Current
VIN=0 V; Inputs with no pull-up
IIL1
Input Low Current
resistors
Input Low Current
IIL2
VIN=0 V; Inputs with pull-up resistors
Operating
Supply Current
IDD3.3OP66
IDD3.3OP100
IDD3.3OP133
PD
Fi
CIN
CINX
TSTAB
tCPU-PCI
CL=0 pF; Select@ 66MHz
CL=0 pF; Select@ 100MHz
CL=0 pF; Select@ 133MHz
Power Down
Input frequency
Input Capacitance1
1
1
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
From VDD= 3.3 V to 1% target Freq.
VT = 50% to 1.5V
Clk Stabilization
1
Skew
Guaranteed by design, not 100% tested in production.
0451A—01/10/03
10
MIN
2
VSS - 0.3
TYP
MAX
VDD + 0.3
0.8
5
UNITS
V
V
A
-5
uA
-200
uA
12
87
91
104
3.25
14.318
27
1
2.8
180
mA
5
16
5
45
3
4
mA
MHz
pF
pF
ms
ns
ICS94236
Electrical Characteristics - REF(0:1)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VOH5
IOH = -12 mA
Output High Voltage
VOL5
IOL = 9 mA
Output Low Voltage
IOH5
VOH = 2.0 V
Output High Current
IOL5
VOL = 0.8 V
Output Low Current
1
tr5
VOL = 0.4 V, VOH = 2.4 V
Rise Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V
Fall Time
1
dt5
VT = 1.5V
Duty Cycle
1
tjcyc-cyc2B
VT = 1.5V
Jitter, Cycle-to-cycle
1
MIN
2.4
TYP
MAX
1.2
1.5
54.1
1007
4
4
55
1100
UNITS
V
V
mA
mA
ns
ns
%
ps
TYP
MAX
UNITS
1.2
0.4
V
V
mA
ns
ns
0.4
-22
16
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Z0
VO = VX
Output Impedance
VOH2B
Termination to Vpull-up(external)
Output High Voltage
VOL2B
Termination to Vpull-up(external)
Output Low Voltage
IOL2B
VOL = 0.3 V
Output Low Current
1
tr2B
VOL = 0.3 V, VOH = 1.2 V
Rise Time
1
tf2B
VOH = 1.2 V, VOL = 0.3 V
Fall Time
MIN
1
18
0.9
0.9
1
VDIF
Note 2
0.4
1
VDIF
Note 2
0.2
Differential voltage-AC
Differential voltage-DC
Vpu
+0.6
Vpu
+0.6
V
V
VX
Note 3
550
1100
mV
Differential Crossover
1
d
VT = 50%
45
51
55
%
Duty Cycle
t2B
1
tsk2B
VT = 50%
163
200
ps
Skew
1
tjcyc-cyc2B
VT = VX
201
250
ps
Jitter, Cycle-to-cycle
1
tjabs2B
VT = 50%
-250
250
ps
Jitter, Absolute
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltage (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level
3 - Vpullup(external)=1.5V, Min=Vpullup(External)/2-150mV, Max=Vpullup(external)/2+150mV
0451A—01/10/03
11
ICS94236
Electrical Characteristics - CPUCLK (Push-Pull)
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
1
RDSP2B
VO = VDD*0.5
Output Impedance
1
RDSN2B
VO = VDD*0.5
Output Impedance
VOH2B
IOH = -12mA
Output High Voltage
VOL2B
IOL = 12mA
Output Low Voltage
IOH2B
VOH = 1.7 V
Output High Current
IOL2B
VOL = 0.7 V
Output Low Current
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
Rise Time
1
VOH = 2.0 V, VOL = 0.4 V
Fall Time
tf2B
1
dt2B
VT = 1.25V
Duty Cycle
tsk2B
VT = 1.25V
Skew Window
tjcyc-cyc2B
VT = 1.25V
Jitter, Cycle-to-cycle1
1 - Guaranteed by design, not 100% tested in production.
MIN
10
10
2
TYP
MAX
20
20
0.4
-19
19
0.4
0.4
45
1.2
1.1
46.9
142
177
1.6
1.6
55
375
250
TYP
MAX
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
Electrical Characteristics - PCICLK_F, PCICLK(0:4)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VOH5
IOH = -11 mA
Output High Voltage
VOL5
IOL = 9.4 mA
Output Low Voltage
IOH5
VOH = 2.0 V
Output High Current
IOL5
VOL = 0.8 V
Output Low Current
1
tr5
VOL = 0.4 V, VOH = 2.4 V
Rise Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V
Fall Time
1
dt5
VT = 1.5V
Duty Cycle
1
1
VT = 1.5V
Tsk
Skew (window)
1
tjcyc-cyc2B
VT = 1.5V
Jitter, Cycle-to-cycle
1
Guaranteed by design, not 100% tested in production.
0451A—01/10/03
12
MIN
2.6
0.4
-16
19
45
1.8
2
51.7
108
223
2.3
2.3
55
500
500
UNITS
V
V
mA
mA
ns
ns
%
ps
ps
ICS94236
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
1
RDSP3B
VO = VDD*0.5
Output Impedance
VOH3
IOH = -18mA
Output High Voltage
VOL3
IOL = 9.4mA
Output Low Voltage
IOH3
VOH = 2.0 V
Output High Current
IOL3
VOL = 0.8 V
Output Low Current
1
tr3
VOL = 0.4 V, VOH = 2.4 V
Rise Time
1
tf3
VOH = 2.4 V, VOL = 0.4 V
Fall Time
1
dt3
VT = 1.5V
Duty Cycle
(0:11)
tsk3
VT = 1.5V
Skew Window
(0:12)
tsk3
VT = 1.5V
Skew Window
1
tjcyc-cyc3
VT = 1.5V
Jitter, Cycle-to-cycle
1 - Guaranteed by design, not 100% tested in production.
MIN
10
2.4
TYP
MAX
24
0.4
-46
19
45
0.8
0.8
48.5
192
290
173
1.6
1.6
55
250
500
250
TYP
MAX
UNITS
V
V
mA
mA
ns
ns
%
pS
pS
pS
Electrical Characteristics - 24MHz,48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VOH5
IOH = -16 mA
Output High Voltage
VOL5
IOL = 9 mA
Output Low Voltage
IOH5
VOH = 2.0 V
Output High Current
IOL5
VOL = 0.8 V
Output Low Current
1
tr5
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tf5
VOH = 2.4 V, VOL = 0.4 V
Fall Time1
1
dt5
VT = 1.5V
Duty Cycle
1
VT = 1.5V
tj1s5
Jitter, One Sigma
tjcyc_cyc2B
VT = 1.5V
Jitter, Cycle to cycle
1
Guaranteed by design, not 100% tested in production.
0451A—01/10/03
13
MIN
2.4
0.4
-22
16
45
1.1
1.28
52
177
4
4
55
0.5
500
UNITS
V
V
mA
mA
ns
ns
%
ns
ps
ICS94236
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the ICS94236
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K
Via to Gnd
Device
Pad
8.2K
Clock trace to load
Series Term. Res.
Fig. 1
0451A—01/10/03
14
ICS94236
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
CPU_STOP# is considered to be a don't care during the power down operations. The REF and 48MHz clocks are
expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94236 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0451A—01/10/03
15
ICS94236
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94236. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94236.
3. All other clocks continue to run undisturbed.
0451A—01/10/03
16
ICS94236
SYMBOL
In Millimeters
COMMON DIMENSIONS
MIN
MAX
In Inches
COMMON DIMENSIONS
MIN
MAX
A
2.413
2.794
.095
.110
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
.005
.010
SEE VARIATIONS
0.635
0°
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
15.748
16.002
VARIATIONS
N
48
D mm.
D (inch)
.620
.630
JEDEC MO-118
6/ 1/ 00
DOC# 10-0034
REV B
Ordering Information
ICS94236yF-T
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0451A—01/10/03
17