Cypress CY7B9910-5SIT Low skew clock buffer Datasheet

CY7B9910
CY7B9920
Low Skew Clock Buffer
Features
■
All outputs skew <100 ps typical (250 max.)
■
15 to 80 MHz output operation
■
Zero input to output delay
The completely integrated PLL enables “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
■
50% duty cycle outputs
Block Diagram Description
■
Outputs drive 50Ω terminated lines
Phase Frequency Detector and Filter
■
Low operating current
■
24-pin SOIC package
■
Jitter:<200 ps peak to peak, <25 ps RMS
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
Functional Description
VCO
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50Ω. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
Logic Block Diagram
TEST
PHASE
FREQ
DET
FB
REF
VOLTAGE
FILTER
CONTROLLED
OSCILLATOR
FS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 07, 2007
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CY7B9910
CY7B9920
Pin Configuration
SOIC
Top View
REF
VCCQ
FS
NC
VCCQ
VCCN
Q0
Q1
GND
Q2
Q3
VCCN
1
24
2
23
3
22
4
21
20
5
6
7
7B9910
7B9920
19
18
8
17
9
16
10
15
11
14
12
13
GND
TEST
NC
GND
VCCN
Q7
Q6
GND
Q5
Q4
VCCN
FB
Pin Definitions
Signal Name
IO
Description
REF
I
Reference frequency input.This input supplies the frequency and timing against which all functional
variations are measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
FS[1,2,3]
I
Three level frequency range select.
TEST
I
Three level select. See TEST MODE.
Q[0..7]
O
Clock outputs.
VCCN
PWR
Power supply for output drivers.
VCCQ
PWR
Power supply for internal circuitry.
GND
PWR
Ground.
Test Mode
The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and
CY7B9920 to operate as described in Block Diagram Description. For testing purposes, any of the three level inputs can have a
removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input
levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appearing at the REF
and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a
frequency multiplication by using external division in the feedback path of value X.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V.
Document Number: 38-07135 Rev. *B
Page 2 of 11
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CY7B9910
CY7B9920
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Latch Up Current ..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Range
Ambient
Temperature
VCC
Supply Voltage to Ground Potential................–0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
DC Input Voltage ............................................–0.5V to +7.0V
Industrial
–40°C to +85°C
5V ± 10%
Output Current into Outputs (LOW) ............................. 64 mA
Document Number: 38-07135 Rev. *B
Page 3 of 11
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CY7B9910
CY7B9920
Electrical Characteristics Over the Operating Range
CY7B9910
Parameter
VOH
Description
Test Conditions
Min
Output HIGH Voltage
VCC = Min, IOH = –16 mA
2.4
Max
Output LOW Voltage
Max
Unit
V
VCC = Min, IOH =–40 mA
VOL
CY7B9920
Min
VCC –0.75
VCC = Min, IOL = 46 mA
0.45
V
VCC = Min, IOL = 46 mA
0.45
VIH
Input HIGH Voltage
(REF and FB inputs only)
2.0
VCC
VCC –
1.35
VCC
V
VIL
Input LOW Voltage
(REF and FB inputs only)
–0.5
0.8
–0.5
1.35
V
VIHH
Three Level Input HIGH
Voltage (Test, FS)[4]
Min ≤ VCC ≤ Max
VCC – 1V
VCC
VCC – 1V
VCC
V
VIMM
Three Level Input MID
Voltage (Test, FS)[4]
Min ≤ VCC ≤ Max
VCC/2 –
500 mV
VCC/2 +
500 mV
VCC/2 –
500 mV
VCC/2 +
500 mV
V
VILL
Three Level Input LOW
Voltage (Test, FS)[4]
Min ≤ VCC ≤ Max
0.0
1.0
0.0
1.0
V
IIH
Input HIGH Leakage Current
(REF and FB inputs only)
VCC = Max, VIN = Max
10
μA
IIL
Input LOW Leakage Current
(REF and FB inputs only)
VCC = Max, VIN = 0.4V
IIHH
Input HIGH Current
(Test, FS)
VIN = VCC
IIMM
Input MID Current
(Test, FS)
VIN = VCC/2
IILL
Input LOW Current
(Test, FS)
VIN = GND
IOS
Output Short Circuit
Current[5]
VCC = Max, VOUT
= GND (25°C only)
ICCQ
Operating Current Used by
Internal Circuitry
VCCN = VCCQ = Max All
Input
Selects Open
ICCN
Output Buffer Current per
Output Pair[6]
PD
Power Dissipation per
Output Pair[7]
10
–500
μA
–500
200
μA
50
μA
–200
–200
μA
–250
N/A
mA
Com’l
85
85
mA
Mil/Ind
90
90
VCCN = VCCQ = Max
IOUT = 0 mA
Input Selects Open, fMAX
14
19
mA
VCCN = VCCQ = Max
IOUT = 0 mA
Input Selects Open, fMAX
78
104[5]
mW
200
–50
50
–50
Notes
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit
protected.
6. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
ICCN = [(3.5+.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C.
7. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1.See note 3 for variable definition.
Document Number: 38-07135 Rev. *B
Page 4 of 11
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CY7B9910
CY7B9920
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
CIN
Max
Unit
10
pF
TA = 25°C, f = 1 MHz, VCC = 5.0V
Input Capacitance
AC Test Loads and Waveforms
5V
R1
CL
R2
3.0V
2.0V
Vth =1.5V
0.8V
0.0V
R1=130
R2=91
CL = 50 pF (CL = 30pF for –5 and – 2 devices)
(Includes fixture and probe capacitance)
2.0V
Vth =1.5V
0.8V
≤1ns
≤1ns
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (Cy7B9910)
VCC
R1
CL
VCC
R1=100
R2=100
CL = 50 pF (CL =30 pF for –5 and – 2devices)
(Includes fixture and probe capacitance)
80%
Vth = VCC/2
20%
0.0V
R2
80%
Vth = VCC/2
20%
≤ 3ns
≤ 3ns
7B9910–5
7B9910–6
CMOS Input Test Waveform (CY7B9920)
CMOS AC Test Load (CY7B9920)
Switching Characteristics
Over the Operating Range [11]
CY7B9910–2[8]
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
FS =
Min
LOW[1, 2]
Typ
Max
CY7B9920–2[8]
Min
Typ
Max
15
30
15
30
FS = MID[1, 2]
25
50
25
50
FS = HIGH[1, 2, 3]
40
80
40
80[12]
tRPWH
REF Pulse Width HIGH
5.0
tRPWL
REF Pulse Width LOW
5.0
tSKEW
Zero Output Skew (All Outputs)[13, 14]
5.0
[14, 15]
0.25
MHz
ns
5.0
0.1
Unit
ns
0.1
0.75
0.25
ns
0.75
ns
tDEV
Device-to-Device Skew
tPD
Propagation Delay, REF Rise to FB Rise
–0.25
0.0
+0.25
–0.25
0.0
+0.25
ns
tODCV
Output Duty Cycle Variation[16]
–0.65
0.0
+0.65
–0.65
0.0
+0.65
ns
0.15
1.0
1.2
0.5
2.0
2.5
ns
0.15
1.0
1.2
0.5
2.0
2.5
ns
[17, 18]
tORISE
Output Rise Time
tOFALL
Output Fall Time[17, 18]
[19]
tLOCK
PLL Lock Time
0.5
0.5
ms
tJR
Cycle-to-Cycle Output Jitter Peak to Peak
200
200
ps
25
25
ps
RMS
Document Number: 38-07135 Rev. *B
Page 5 of 11
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CY7B9910
CY7B9920
CY7B9910–5
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
FS = LOW
Min
[1, 2]
Min
Typ
Max
15
30
15
30
25
50
25
50
FS = HIGH[1, 2, 3]
40
80
40
80[12]
REF Pulse Width HIGH
5.0
tRPWL
REF Pulse Width LOW
5.0
tSKEW
Zero Output Skew (All Outputs)[13, 14]
5.0
tDEV
Device-to-Device
tPD
Propagation Delay, REF Rise to FB Rise
0.5
MHz
ns
0.25
1.0
Variation[16]
Unit
ns
5.0
0.25
Skew[8, 15]
Output Duty Cycle
CY7B9920–5
Max
FS = MID[1, 2]
tRPWH
tODCV
Typ
0.5
ns
1.0
ns
–0.5
0.0
+0.5
–0.5
0.0
+0.5
ns
–1.0
0.0
+1.0
–1.0
0.0
+1.0
ns
tORISE
Output Rise Time
[17, 18
0.15
1.0
1.5
0.5
2.0
3.0
ns
tOFALL
Output Fall Time[17, 18]
0.15
1.0
1.5
0.5
2.0
3.0
ns
0.5
0.5
ms
200
200
ps
25
25
ps
Time[19]
tLOCK
PLL Lock
tJR
Cycle-to-Cycle Output Jitter Peak to Peak[8]
RMS[8]
Notes
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
10. Applies to REF and FB inputs only.
11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
14. tSKEW is defined as the skew between outputs.
15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, and
so on).
16. tODCV is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920.
19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07135 Rev. *B
Page 6 of 11
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CY7B9910
CY7B9920
Switching Characteristics
Over the Operating Range[11] (continued)
CY7B9910–7
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
Min
Typ
CY7B9920–7
Max
Min
FS = LOW[1, 2]
15
30
15
Typ
Max
Unit
30
MHz
FS = MID[1, 2]
25
50
25
50
FS = HIGH1, 2, 3]
40
80
40
80[12]
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
Outputs)[13, 14]
tSKEW
Zero Output Skew (All
tDEV
Device-to-Device Skew[8, 15]
tPD
Propagation Delay, REF Rise to FB Rise
tODCV
Output Duty Cycle
Time[17, 18]
Output Rise
tOFALL
Output Fall Time17, 18]
tLOCK
tJR
tJR
PLL Lock
Time[19]
Cycle-to-Cycle Output
Jitter
Document Number: 38-07135 Rev. *B
Peak to
RMS[8]
0.75
0.3
1.5
Variation[16]
tORISE
0.3
Peak[8]
0.75
ns
1.5
ns
–0.7
0.0
+0.7
–0.7
0.0
+0.7
ns
–1.2
0.0
+1.2
–1.2
0.0
+1.2
ns
0.15
1.5
2.5
0.5
3.0
5.0
ns
0.15
1.5
2.5
0.5
3.0
5.0
ns
0.5
0.5
ms
200
200
ps
25
25
ps
Page 7 of 11
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CY7B9910
CY7B9920
AC Timing Diagrams
Figure 1. AC Timing Diagrams
tREF
tRPWL
tRPWH
REF
tPD
tODCV
tODCV
FB
Q
tJR
tSKEW
tSKEW
OTHER Q
Figure 2. Zero Skew and Zero Delay Clock Driver
REF
LOAD
Z0
SYSTEM
CLOCK
FB
REF
FS
LOAD
Q0
Q1
Z0
Q2
Q3
Q4
Q5
LOAD
Z0
Q6
Q7
LOAD
TEST
Z0
Document Number: 38-07135 Rev. *B
Page 8 of 11
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CY7B9910
CY7B9920
Operational Mode Descriptions
Figure 2 shows the device configured as a zero skew clock
buffer. In this mode the 7B9910/9920 is used as the basis for a
low skew clock distribution tree. The outputs are aligned and may
each drive a terminated transmission line to an independent
load. The FB input is tied to any output and the operating
frequency range is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission
lines (with impedances as low as 50 ohms), enables efficient
printed circuit board design.
Figure 1 shows the CY7B9910/9920 connected in series to
construct a zero skew clock distribution tree between boards.
Cascaded clock buffers accumulates low frequency jitter
because of the non-ideal filtering characteristics of the PLL filter.
Do not connect more than two clock buffers in series.
Figure 3. Board-to-Board Clock Distribution
LOAD
REF
Z0
FB
SYSTEM
CLOCK
LOAD
REF
FS
Z0
Q0
Q1
Q2
Q3
LOAD
Q4
Q5
Z0
Q6
Q7
FB
REF
FS
TEST
Z0
TEST
Document Number: 38-07135 Rev. *B
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LOAD
LOAD
Page 9 of 11
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CY7B9910
CY7B9920
Ordering Information
Accuracy
(ps)
250
500
750
Pb-Free
250
500
750
CY7B9910–2SC
CY7B9910–2SCT
CY7B9920–2SC[20]
CY7B9910–5SC
CY7B9910–5SCT
CY7B9910–5SI
CY7B9910–5SIT
CY7B9920–5SC
CY7B9920–5SCT
CY7B9920–5SI
CY7B9910–7SC
CY7B9910–7SI[20]
CY7B9920–7SC[20]
CY7B9920–7SI[20]
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC
24-Pb Small Outline IC
24-Pb Small Outline IC
24-Pb Small Outline IC
Operating
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY7B9910–2SXC
CY7B9910–2SXCT
CY7B9910–5SXC
CY7B9910–5SXCT
CY7B9910–5SXI
CY7B9910–5SXIT
CY7B9910–7SXC
CY7B9910–7SXCT
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Ordering Code
Package Type
Package Diagram
Figure 4. 24-Pin (300 Mil) Molded SOIC S13
51-85025-*C
Note
20. Not recommended for new design.
Document Number: 38-07135 Rev. *B
Page 10 of 11
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CY7B9910
CY7B9920
Document History
Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer
Document Number: 38-07135
REV.
ECN NO.
Issue Date Orig. of
Change
Description of Change
**
110244
10/28/01
SZV
Change from Specification number: 38-00437 to 38-07135
*A
1199925
See ECN
DPF/AESA Added Pb-free parts in Ordering Information
Added Note 20: Not recommended for the new design
*B
1353343
See ECN
AESA
Change status to final
© Cypress Semiconductor Corporation, 2001-2007.The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07135 Rev. *B
Revised August 07, 2007
Page 11 of 11
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