CALMIRCO CM88L70TS Cmos integrated dtmf receiver, 3 volt version Datasheet

CM88L70/70C
CALIFORNIA MICRO DEVICES
CMOS INTEGRATED DTMF RECEIVER, 3 VOLT VERSION
Features
• 2.7 to 3.6 volt operating range
• Full DTMF receiver
• Less than 18mW power consumption
• Industrial temperature range
• Uses quartz crystal or ceramic resonators
• Adjustable acquisition and release times
• 18-pin DIP, 20-pin QSOP, 18-pin SOIC,
20-pin PLCC, 20-pin TSSOP
• CM88L70
- Power down mode
- Inhibit mode
- Buffered oscillator output (OSC 3) to
drive other devices
Applications
• PCMCIA
• Portable TAD
• Mobile radio
• Remote control
• Remote data entry
• Call limiting
• Telephone answering systems
• Paging systems
Product Description
The CAMD CM88L70/70C provides full DTMF receiver capability by integrating both the bandsplit filter and digital decoder
functions into a single 18-pin DIP, SOIC, or 20-pin PLCC, TSSOP, or QSOP package. The CM88L70/70C is manufactured using
state-of-the-art CMOS process technology for low power consumption (35mW, max.) and precise data handling. The filter
section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The CM88L70/70C
decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code. This
DTMF receiver minimizes external component count by providing an on-chip differential input amplifier, clock generator, and
a latched three-state interface bus. The on-chip clock generator requires only a low cost TV crystal or ceramic resonator as
an external component.
Block Diagram
C0451098
© 2000 California Micro Devices Corp. All rights reserved.
6/16/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CM88L70/70C
CALIFORNIA MICRO DEVICES
Absolute Maximum Ratings: (Note 1)
This device contains input protection against
damage due to high static voltages or
electric fields; however, precautions should
be taken to avoid application of voltages
higher than the maximum rating.
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage (VDDV SS)
Symbol
Value
VDD
6.0V Max
Voltage on any Pin
Vt
VSS-0.3V to VDD+0.3V
Current on any Pin
It
10mA Max
Storage Temperature
TS
-65°C to +150°C
Note:
1. Exceeding these ratings may cause
permanent damage, functional
operation under these conditions is not
implied.
DC Characteristics: All voltages referenced to VSS, VDD = 3.0V + 20% / -10%, TA = -40°C to +85°C unless otherwise noted.
Parameter
Symbol
DC CHARACTE RISTICS
Min
Typ
Max
Units
Test Conditions
Operating Supply Voltage
V DD
3.0
3.6
V
Operating Supply Current
I DD
3.0
5.0
mA
Standby Supply Current
I DDS
5.0
10
µA
PD =VDD
Low Level Input Voltage
V IL
1.0
V
VDD=3.0V
High Level Input Voltage
V IH
V
VDD=3.0V
0.1
µA
VIN = VSS or VDD (Note 11)
-2.0
µA
TOE = 0V
Input Leakage Current
2.7
2.0
I I H/ L I L
Pull Up (Source) Current on TOE
I so
-12
V
Pull down (sink) Current PD
I PD
1.0
45
µA
PD = 3.0V
Pull down (sink) Current INH
I I NH
1.0
45
µA
IHN = 3.0V
Input Impedance, (IN+, IN-)
R IN
10
MΩ
@ 1K H z
Steering Threshold Voltage
V Tst
1.5
Low Level Output Voltage
V OL
0.1
High Level Output Voltage
V OH
2.4
Output High (Source) Current
I OH
1.0
Output Voltage
Output Resistance
VREF
V
0.4
V
2.6
IOL = 1.0mA
V
IOH = 400µA
mA
VOUT = 2.5V @ VDD = 2.7V
N o L o ad
V R EF
1.5
V
R OR
10
ΚΩ
Operating Characteristics: All voltages referenced to VSS, VDD = 3.0V + 20% / -10%, TA = -40°C to +85°C unless otherwise noted.
Gain Setting Amplifier
OPERATING CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
VSS < VIN < VDD
Input Leakage Current
I IN
10 0
nA
Input Resistance
R IN
10
MΩ
Input Offset Voltage
V OS
15
25
mV
Power Supply Rejection
PSRR
50
60
dB
1KHz (Note 12)
Common Mode Rejection
CMR R
40
60
dB
-3.0V < VIN < 3.0V
D C Open Loop Voltage Gain
A VOL
32
65
dB
Open Loop Unity Gain Bandwidth
fc
0.3
1.0
MH z
Output Voltage Swing
VO
2.2
V P-P
Tolerable Capacitive Load (GS)
CL
Tolerable Resistive Load (GS)
RL
Common Mode Range (No Load)
Vcm
10 0
RL ≥ 100KΩ to VSS
pF
KΩ
5.0
1.5
V P-P
N o L o ad
©2000 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
8/16/2000
CM88L70/70C
CALIFORNIA MICRO DEVICES
AC Characteristics: All voltages referenced to VSS, VDD=3.0V + 20% / -10%, TA=-40°C to +85°C, fCLK=3.579545 MHz
using test circuit (Fig. 1) unless otherwise noted.
AC CHARACTERISTICS
Parameter
Symbol
Max
Units
-36
-6.4
dBm
12.3
370
mVRMS
Positive Twist Accept
6
dB
Negative Twist Accept
6
dB
1.5%±2Hz
Nom.
2,3,5,8,10
Nom.
2,3,5
Valid Input Signal Levels
(each tone of composite signal)
Min
Typ
Freq. D eviation Accept Limit
Freq. D eviation Reject Limit
±3.5%
Notes
1,2,3,4,5,8
Third Tone Tolerance
-16
dB
2,3,4,5,8,9,13,14
Noise Tolerance
-12
dB
2,3,4,5,6,8,9
D ial Tone Tolerance
+22
dB
2,3,4,5,7,8,9
Refer to
Timing D iagram
Tone Present D etection Time
t DP
5
8
14
mS
Tone Absent D etection Time
t DA
0.5
3
8.5
mS
Min Tone D uration Accept
t R EC
40
mS
Max Tone D uration Reject
t R EC
20
mS
Min. Interdigit Pause Accept
t ID
Max. Interdigit Pause Reject
t DO
Propagation D elay (St to Q)
t PQ
13
µS
Propagation D elay (St to StD )
t PSt D
8
µS
Output D ata Set Up (Q to StD )
t QSt D
3.4
µS
Enable
t PTE
200
nS
D isable
t PTD
50 0
nS
Propagation D elay (TOE to Q)
Crystal/Clock Frequency
Clock Output (OSC 2)
f CL K
Capacitive
L o ad
40
20
3.5759
µS
3.5795
C LO
Notes:
1. dBm = decibels above or below a reference power
of 1 mW into a 600 ohm load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40mS. Tone pause = 40 mS.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have
an equal amplitude.
6. Bandwidth limited (0 to 3 KHz) Gaussian Noise.
7. The precise dial tone frequencies are
(350 Hz and 440 Hz) ±2%.
8. For an error rate of better than 1 in 10,000
9.
10.
11.
12.
13.
14.
mS
3.5831
MHz
30
pF
(User Adjustable)
Times shown are
obtained with
circuit in Fig. 1)
TOE = VDD
R L = 10 K Ω
CL = 50pF
Referenced to lowest level frequency component
in DTMF signal.
Minimum signal acceptance level is measured with
specified maximum frequency deviation.
Input pins defined as IN+, IN-, and TOE.
External voltage source used to bias VREF.
This parameter also applies to a third tone injected onto
the power supply.
Referenced to Figure 1. Input DTMF tone level
at -28 dBm.
© 2000 California Micro Devices Corp. All rights reserved.
6/16/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
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CM88L70/70C
CALIFORNIA MICRO DEVICES
Explanation of Events
Explanation of Symbols
A)
VIN
ESt
B)
C)
D)
E)
F)
G)
Tone bursts detected, tone duration invalid, outputs not
updated.
Tone #n detected, tone duration valid, tone decoded and
latched in outputs.
End of tone #n detected, tone absent duration valid,
outputs remain latched until next valid tone.
Outputs switched to high impedance state.
Tone #n + 1 detected, tone duration valid, tone decoded
and latched in outputs (currently high impedance).
Acceptable dropout of tone #n + 1, tone absent duration
invalid, outputs remain latched.
End of tone #n + 1 detected, tone absent duration valid,
outputs remain latched until next valid tone.
St/GT
Q1-Q4
StD
TOE
tREC
tREC
tID
tDO
tDP
tDA
tGTP
tGTA
DTMF composite input signal.
Early Steering Output. Indicates detection
of valid tone frequencies.
Steering input/guard time output. Drives
external RC timing circuit.
4-bit decoded tone output.
Delayed Steering Output. Indicates that
valid frequencies have been present/absent
for the required guard time, thus constituting
a valid signal.
Tone Output Enable (input). A low level
shifts Q1-Q4 to its high impedance state.
Maximum DTMF signal duration not
detected as valid.
Minimum DTMF signal duration required
for valid recognition.
Minimum time between valid DTMF signals.
Maximum allowable drop-out during valid
DTMF signal.
Time to detect the presence of valid
DTMF signals.
Time to detect the absence of valid
DTMF signals.
Guard time, tone present.
Guard time, tone absent.
©2000 California Micro Devices Corp. All rights reserved.
4
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
8/16/2000
CM88L70/70C
CALIFORNIA MICRO DEVICES
Functional Description
The CAMD CM88L70/70C DTMF Integrated Receiver provides the
design engineer with not only low power consumption, but high
performance in a small 18-pin DIP, SOIC, or 20-pin PLCC, TSSOP, or
QSOP package configuration. The CM88L70/70C’s internal
architecture consists of a bandsplit filter section which separates the
high and low tones of the received pair, followed by a digital decode
(counting) section which verifies both the frequency and duration of
the received tones before passing the resultant 4-bit code to the output
bus.
Filter Section
Separation of the low-group and high-group tones is achieved by
applying the dual-tone signal to the inputs of two 9th-order switched
capacitor bandpass filters. The bandwidths of these filters correspond
to the bands enclosing the low-group and high-group tones (See
Figure 3). The filter section also incorporates notches at 350 Hz and
440 Hz which provides excellent dial tone rejection. Each filter output
is followed by a single order switched capacitor section which smooths
the signals prior to limiting. Signal limiting is performed by high-gain
comparators. These comparators are provided with a hysteresis to
prevent detection of unwanted low-level signals and noise. The
outputs of the comparators provide full-rail logic swings at the
frequencies of the incoming tones.
Decoder Section
The CM88L70/70C decoder uses a digital counting technique to
determine the frequencies of the limited tones and to verify that these
tones correspond to standard DTMF frequencies. A complex averaging
algorithm is used to protect against tone simulation by extraneous
signals (such as voice) while providing tolerance to small frequency
variations. The averaging algorithm has been developed to ensure
an optimum combination of immunity to “talk-off” and tolerance to
the presence of interfering signals (third tones) and noise. When the
detector recognizes the simultaneous presence of two valid tones
(known as “signal condition”), it raises the “Early Steering” flag (ESt).
Any subsequent loss of signal condition will cause ESt to fall.
Steering Circuit
Before the registration of a decoded tone pair, the receiver checks for
a valid signal duration (referred to as “character-recognitioncondition”). This check is performed by an external RC time constant
driven by ESt. A logic high on ESt causes VC (See Figure 4) to rise as
the capacitor discharges. Providing signal condition is maintained
(ESt remains high) for the validation period (tGTP), VC reaches the
threshold (VTSt) of the steering logic to register the tone pair, thus
latching its corresponding 4-bit code (See Figure 2) into the output
latch. At this point, the GT output is activated and drives VC to VDD.
GT continues to drive high as long as ESt remains high, signaling that
a received tone pair has been registered. The contents of the output
latch are made available on the 4-bit output bus by raising the threestate control input (TOE) to a logic high. The steering circuit works in
reverse to validate the interdigit pause between signals. Thus, as well
as rejecting signals too short to be considered valid, the receiver will
tolerate signal interruptions (drop outs) too short to be considered a
valid pause. This capability together with the capability of selecting
the steering time constants externally, allows the designer to tailor
performance to meet a wide variety of system requirements.
Component values are chosen according to the following formula:
tREC = tDP + tGTP
tGTP » 0.67 RC
The value of tDP is a parameter of the device and tREC is the minimum
signal duration to be recognized by the receiver. A value for C of 0.1
uF is recommended for most applications, leaving R to be selected by
the designer. For example, a suitable value of R for a tREC of 40
milliseconds would be 300K. A typical circuit using this steering
configuration is shown in Figure 1. The timing requirements for most
telecommunication applications are satisfied with this circuit. Different
steering arrangements may be used to select independently the
guardtimes for tone-present (tGTP) and tone absent (tGTA). This may
be necessary to meet system specifications which place both accept
and reject limits on both tone duration and interdigit pause.
Guard time adjustment also allows the designer to tailor system
parameters such as talk-off and noise immunity. Increasing tREC
improves talk-off performance, since it reduces the probability that
tones simulated by speech will maintain signal condition for long
enough to be registered. On the other hand, a relatively short tREC
with a long tDO would be appropriate for extremely noisy environments
where fast acquisition time and immunity to drop-outs would be
requirements. Design information for guard time adjustment is shown
in Figure 5.
Input Configuration
The input arrangement of the CM88L70/70C provides a differential
input operational amplifier as well as a bias source (VREF) which is
used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor to the opamp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are connected as shown
in Figure 1, with the op-amp connected for unity gain and VREF biasing
the input at ½ VDD. Figure 6 shows the differential configuration,
which permits the adjustment of gain with the feedback resistor R5.
Clock Circuit
The internal clock circuit is completed with the addition of a standard
television color burst crystal or ceramic resonator having a resonant
frequency of 3.579545 MHz. The CM8870C in a PLCC package has
a buffered oscillator output (OSC3) that can be used to drive clock
inputs of other devices such as a microprocessor or other CM887X’s
as shown in Figure 7. Multiple CM88L70/70Cs can be connected as
shown in figure 8 such that only one crystal or resonator is required.
Power Down and Inhibit Mode
A logic high applied to pin 6 (PD) will power down the device to
minimize the power consumption in a standby mode. It stops the
oscillator and functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It
inhibits the detection of tones representing characters A, B, C and
D. The output code will remain the same as the previous detected
code (see Figure 2).
Guard Time Adjustment
In situations which do not require independent selection of receive
and pause, the simple steering circuit of Figure 4 is applicable.
© 2000 California Micro Devices Corp. All rights reserved.
6/16/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
5
CM88L70/70C
CALIFORNIA MICRO DEVICES
Pin Function Table
N am e
IN+
INGS
D e scription
Non-inverting input
Connection to the front-end differential amplifier
Inverting input
Gain Select. Gives access to output of front-end differential amplifier for connection
of feedback resistor.
VR E F
Reference voltage output (nominally VD D /2). May be used to bias the inputs at mid-rail.
INH
Inhibits detection of tones represents keys A,B,C,D.
OSC 3
Digital buffered oscillator output.
PD
Power down
OSC1
Clock input
OSC2
Clock output
Logic high powers down the device and inhibits the oscillator.
3.579545 MHz crystal connected between these pins completes internal oscillator.
VS S
Negative power supply (normally connected to 0V).
TOE
Three-state output enable (input). Logic high enables the outputs Q1 -Q4 . Internal pull-up.
Q1
Q2
Q3
Q4
Three-state outputs. When enabled by TOE, provides the code corresponding to the last
valid tone pair received. (See Fig. 2).
StD
Delayed steering output. Presents a logic high when a received tone pair has been registered and the
output latch is updated. Returns to logic low when the voltage on St/GT falls below VT S t .
ESt
Early steering output. Presents a logic high immediately when the digital algorithm
detects a recognizable tone pair (signal condition). Any momentary loss of signal condition
will cause ESt to return to a logic low.
St/Gt
Steering input/guard time output (bidirectional). A voltage greater than VT S t detected at St causes the
device to register the detected tone pair and update the output latch. A voltage less than VT S t frees the
device to accept a new tone pair. The GT output acts to reset the external steering time constant, and its
state is a function of ESt and the voltage on St. (See Fig. 2)
VD D
Positive power supply.
IC
Internal connection. Must be tied to VS S (for 8870 configuration only)
CM88L70
CM88L70C
All resistors are ± 1%tolerance.
All capacitors are ± 5% tolerance.
FLOW
FHI GH
KEY
TOW
Q4
Q3
Q2
697
1209
1
H
0
0
0
697
1336
2
H
0
0
1
697
1477
3
H
0
0
1
770
1209
4
H
0
1
0
770
1336
5
H
0
1
0
770
1477
6
H
0
1
1
852
1209
7
H
0
1
1
852
1336
8
H
1
0
0
852
1477
9
H
1
0
0
941
1209
0
H
1
0
1
●
H
1
0
1
941
1336
941
1477
#
H
1
1
0
697
1633
A
H
1
1
0
770
1633
B
H
1
1
1
852
1633
C
H
1
1
1
941
1633
D
H
0
0
0
ANY
L
Z
Z
Z
L = Logic Low, H = Logic High, Z = High Impedance
Figure 1. Single Ended Input Configuration
Q1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
Figure 2. Functional Diode Table
©2000 California Micro Devices Corp. All rights reserved.
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215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
8/16/2000
CM88L70/70C
CALIFORNIA MICRO DEVICES
Figure 3. Typical Filter Characteristic
Figure 4. Basic Steering Circuit
Figure 6. Differential Input Configuration
Figure 5. Guard Time Adjustment
© 2000 California Micro Devices Corp. All rights reserved.
6/16/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
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CM88L70/70C
CALIFORNIA MICRO DEVICES
OSC1
OSC2
OSC1
OSC3
OSC2
OSC1
OSC2
OSC1
OSC2
OSC1 of other CM887X’s
Clock input of other devices
3.58 Mhz
30pF
30pF
30pF
Figure 8. CM88L70/70C Crystal Connection
Figure 7. CM88L70C Crystal Connection
(PLCC Package Only)
Pin Assignments
CM88L70C
CM88L70/C
'
%
$
#
"
!
P — Plastic DIP (18)
S — SOIC (18)
&
IN+
IN-
TS — TSSOP (20)
Q — QSOP (20)
CM8870CM88L70C
PE — PLCC (20)
Ordering Information
Example:
CM88L70
CM88L70C
P
I
Product Identification Number
Package
P — Plastic DIP (18)
PE — PLCC (20)
S — SOIC (18)
TS — TSSOP (20)
Q — QSOP (20)
Temperature/Processing
None — 0OC to +70OC, ±5% P.S. Tol.
I — -40OC to +85OC, ±5% P.S. Tol.
©2000 California Micro Devices Corp. All rights reserved.
8
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
8/16/2000