Ordering number : ENA0744 LC875CC8A LC875CB2A CMOS IC ROM 128K/112K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller Overview The SANYO LC875CC8A/B2A are 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrate on a single chip a number of hardware features such as 128K/112K-byte ROM, 4K-byte RAM, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 15-channel AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt feature. Features ROM • 131072 × 8 bits (LC875CC8A) • 114688 × 8 bits (LC875CB2A) RAM • 4096 × 9 bits Minimum Bus Cycle Time • 83.3ns (12MHz) Note: Bus cycle time indicates the speed to read ROM. Minimum Instruction Cycle Time (tCYC) • 250ns (12MHz) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.03 80608HKIM 20070314-S00003 No.A0744-1/29 LC875CC8A/B2A Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units: 64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn, S2Pn, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 2 bit units: 16 (PEn, PFn) Ports whose I/O direction can be designated in 4 bit units: 8 (P0n) • Normal withstand voltage input ports: 1 (XT1) • Dedicated oscillator ports: 2 (CF1, CF2) • Reset pin: 1 (RES) • Power pins: 8 (VSS1 to VSS4, VDD1 to VDD4) Timers - Timer 0: 16-bit timer/counter with capture registers Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with 2 16-bit capture registers) - Timer 1: 16-bit timer/counter that support PWM/ toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) - Timer 4: 8-bit timer with a 6-bit prescaler - Timer 5: 8-bit timer with a 6-bit prescaler - Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) - Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) - Base timer 1) The clock is selectable from the subclock (32.768 kHz crystal oscillator), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes. High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real time. SIO • SIO 0: 8 bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits) • SIO 1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) • SIO2: 8 bit synchronous serial interface 1) LSB first mode 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 Tcyc) 3) Automatic continuous data transmission (1 to 32 bytes) UART: 2 channels 1) Full duplex 2) 7/8/9 bit data bits selectable 3) 1 stop bit (2 bits in continuous transmission mode) 4) Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC) No.A0744-2/29 LC875CC8A/B2A AD Converter: 8 bits × 15 channels • Analog reference voltage can selected from VDD1 or VDD3. PWM: Multifrequency 12-bit PWM × 4 channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) 1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) 2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. Watchdog Timer 1) External RC watchdog timer 2) Interrupt and reset signals selectable Interrupts • 29 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Selectable Level 1 00003H X or L INT0 Interrupt Signal 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/Base timer 5 00023H H or L T0H/INT6 6 0002BH H or L T1L/T1H/INT7 7 00033H H or L SIO0/UART1 receive/UART2 receive 8 0003BH H or L SIO1/SIO2/UART1 transmit/UART2 transmit 9 00043H H or L ADC/T6/T7/PWM4, PWM5 10 0004BH H or L Port 0/T4/T5/PWM0, PWM1 • Priority Level: X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 2048 levels maximum (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • RC oscillator circuit (internal): For system clock • CF oscillator circuit: For system clock with internal Rf • Crystal oscillator circuit: For low-speed system clock • Multifrequency RC oscillator circuit (internal): For system clock System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (at a main clock rate of 10MHz). No.A0744-3/29 LC875CC8A/B2A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by system reset or occurrence of interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the Reset pin to the lower level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the Reset pin to the low level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port 0. (4) Having an interrupt source established in the base timer circuit. Package Form • QIP100E(14×20): “Lead-free type” • TQFP100(14×14): “Lead-free type” Development Tools • Evaluation (EVA) chip : LC87EV690 • Emulator : EVA62S + ECB876600D + SUB875C00 + POD100QFP or POD100SQFP Type B : ICE-B877300 + SUB875C00 + POD100QFP or POD100SQFP Type B • Flash version : LC87F5CC8A No.A0744-4/29 LC875CC8A/B2A Package Dimensions unit : mm (typ) 3151A 23.2 0.8 20.0 51 50 100 31 14.0 81 1 17.2 80 30 0.65 0.15 0.3 0.1 3.0max (2.7) (0.58) SANYO : QIP100E(14X20) Package Dimensions unit : mm (typ) 3274 75 0.5 16.0 14.0 51 50 100 26 14.0 16.0 76 1 0.5 0.2 25 0.125 1.2max 0.1 (1.0) (1.0) SANYO : TQFP100(14X14) No.A0744-5/29 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PA3/AN12 PA4/AN13 PA5/AN14 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PB7 P36 P35/URX2 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1 P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P21/INT4/T1IN/T0LCP/T0HCP P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1 P07/T7O P06/T6O P05/CKO P04 P03 P02 P01 P00 VSS2 VDD2 PWM0 PWM1 SI2P3/SCK20 SI2P2/SCK2 LC875CC8A/B2A Pin Assignments 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LC875CC8A LC875CB2A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SI2P1/SI2/SB2 SI2P0/SO2 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 VDD4 VSS4 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Top view SANYO: QIP100E(14×20) “Lead-free Type” No.A0744-6/29 P35/URX1 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/ T0LCP/T0HCP P26/INT5/T1IN/ T0LCP/T0HCP P25/INT5/T1IN/ T0LCP/T0HCP P24/INT5/T1IN/ T0LCP/T0HCP/INT7/T0HCP1 P23/INT4/T1IN/ T0LCP/T0HCP P22/INT4/T1IN/ T0LCP/T0HCP P21/INT4/T1IN/ T0LCP/T0HCP P20/INT4/T1IN/ T0LCP/T0HCP/INT6/T0LCP1 P07/T7O P06/T6O P05/CKO P04 P03 P02 P01 P00 VSS2 VDD2 PWM0 LC875CC8A/B2A 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 LC875CC8A LC875CB2A PWM1 SI2P3/SCK20 SI2P2/SCK2 SI2P1/SI2/SB2 SI2P0/SO2 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 VDD4 VSS4 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 P17/T1PWMH/BUZ P16/T1PWML 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P36 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VSS3 VDD3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA0 PA1 PA2 PA3/AN12 PA4/AN13 PA5/AN14 Top view SANYO: TQIP100(14×14) “Lead-free Type” No.A0744-7/29 LC875CC8A/B2A QIP NAME TQFP QIP NAME TQFP 1 PA3/AN12 98 51 SI2P2/SCK2 48 2 PA4/AN13 99 52 SI2P3/SCK20 49 3 PA5/AN14 100 53 PWM1 50 4 P70/INT0/T0LCP/AN8 1 54 PWM0 51 5 P71/INT1/T0HCP/AN9 2 55 VDD2 52 6 P72/INT2/T0IN/T0LCP 3 56 VSS2 53 7 P73/INT3/T0IN/T0HCP 4 57 P00 54 8 RES 5 58 P01 55 9 XT1/AN10 6 59 P02 56 10 XT2/AN11 7 60 P03 57 11 VSS1 8 61 P04 58 12 CF1 9 62 P05/CKO 59 13 CF2 10 63 P06/T6O 60 14 VDD1 11 64 P07/T7O 61 15 P80/AN0 12 65 P20/INT4/T1IN/T0LCP/T0HCP/ 62 16 P81/AN1 13 66 P21/INT4/T1IN/T0LCP/T0HCP 63 17 P82/AN2 14 67 P22/INT4/T1IN/T0LCP/T0HCP 64 18 P83/AN3 15 68 P23/INT4/T1IN/T0LCP/T0HCP 65 19 P84/AN4 16 69 P24/INT5/T1IN/T0LCP/T0HCP/ 66 INT6/T0LCP1 INT7/T0HCP1 20 P85/AN5 17 70 P25/INT5/T1IN/T0LCP/T0HCP 67 21 P86/AN6 18 71 P26/INT5/T1IN/T0LCP/T0HCP 68 22 P87/AN7 19 72 P27/INT5/T1IN/T0LCP/T0HCP 69 23 P10/SO0 20 73 P30/PWM4 70 24 P11/SI0/SB0 21 74 P31/PWM5 71 25 P12/SCK0 22 75 P32/UTX1 72 26 P13/SO1 23 76 P33/URX1 73 27 P14/SI1/SB1 24 77 P34/UTX2 74 28 P15/SCK1 25 78 P35/URX2 75 29 P16/T1PWML 26 79 P36 76 30 P17/T1PWMH/BUZ 27 80 PB7 77 31 PE0 28 81 PB6 78 32 PE1 29 82 PB5 79 33 PE2 30 83 PB4 80 34 PE3 31 84 PB3 81 35 PE4 32 85 PB2 82 36 PE5 33 86 PB1 83 37 PE6 34 87 PB0 84 38 PE7 35 88 VSS3 85 39 VSS4 36 89 VDD3 86 40 VDD4 37 90 PC7 87 41 PF0 38 91 PC6 88 42 PF1 39 92 PC5 89 43 PF2 40 93 PC4 90 44 PF3 41 94 PC3 91 45 PF4 42 95 PC2 92 46 PF5 43 96 PC1 93 47 PF6 44 97 PC0 94 48 PF7 45 98 PA0 95 49 SI2P0/SO2 46 99 PA1 96 50 SI2P1/SI2/SB2 47 100 PA2 97 No.A0744-8/29 LC875CC8A/B2A System Block Diagram IR Interrupt control PLA ROM Standby control RC X’tal Clock generator CF PC MRC SIO0 Bus interface ACC SIO1 Port 0 B register SIO2 Port 1 C register Timer 0 Port 3 ALU Timer 1 Port 7 Timer 4 Port 8 Timer 5 ADC PSW RAR PWM0 PWM1 INT0 to 3 Noise rejection filter RAM Port 2 INT4, 5, 6, 7 Stack pointer Base timer Port A Watchdog timer Timer 6 Port B Timer 7 Port C UART1 Port E UART2 Port F PWM5 PWM4 No.A0744-9/29 LC875CC8A/B2A Pin Description Pin Name I/O Function description Option VSS1, VSS2 VSS3, VSS4 - Power supply pin (-) No VDD1, VDD2 VDD3, VDD4 - Power supply pin (+) No • 8-bit I/O port Yes Port 0 I/O • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistor can be turned on and off in 4-bit units • HOLD release input • Port 0 interrupt input • Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output Port 1 I/O Yes •8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11: SIO0 data input, bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input, bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output, Beeper output Port 2 I/O Yes • 8-bit I/O port • I/O specifiable in 1-bit units P20 to P27 • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT6 input/timer 0L capture 1 input P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input INT7 input/timer 0H capture 1 input P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input • Interrupt acknowledge type Port 3 P30 to P36 I/O Rising Falling INT4 enable enable INT5 enable enable INT6 enable INT7 enable Rising/ H level L level enable disable disable enable disable disable enable enable disable disable enable enable disable disable Falling • 7-bit I/O port Yes • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P30: PWM4 output P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit P35: UART2 receive Continued on next page. No.A0744-10/29 LC875CC8A/B2A Continued from preceding page. Pin Name Port 7 I/O I/O Function description Option No • 4-bit I/O port • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistor can be turned on and off in 1-bit units • Other functions P70: INT0 input/HOLD release input/timer 0L capture input/output for watchdog timer P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input P73: INT3 input with noise filter/timer 0 event input/timer 0H capture input • Interrupt acknowledge type Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising/ H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling • AD converter input port: AN8 (P70), AN9 (P71) Port 8 I/O • 8-bit I/O port No • I/O specifiable in 1-bit units P80 to P87 • Other functions P80 to P87: AD converter input port Port A I/O • 6-bit I/O port Yes • I/O specifiable in 1-bit units PA0 to PA5 • Pull-up resistor can be turned on and off in 1-bit units • Shared functions PA3 to PA5: AD converter input port Port B I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PB0 to PB7 • Pull-up resistor can be turned on and off in 1-bit units Port C I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PC0 to PC7 • Pull-up resistor can be turned on and off in 1-bit units Port E I/O • 8-bit I/O port No • I/O specifiable in 2-bit units PE0 to PE7 • Pull-up resistor can be turned on and off in 1-bit units Port F I/O • 8-bit I/O port No • I/O specifiable in 2-bit units PF0 to PF7 • Pull-up resistor can be turned on and off in 1-bit units SIO2 Port I/O • 4-bit I/O port No • I/O specifiable in 1-bit units SI2P0 to SI2P3 • Shared functions: SI2P0: SIO2 data output SI2P1: SIO2 data input, bus I/O SI2P2: SIO2 clock I/O SI2P3: SIO2 clock output PWM0 I/O • PWM0 output port No • General-purpose I/O available PWM1 I/O • PWM1 output port No • General-purpose I/O available RES I Reset pin No XT1 I • Input terminal for 32.768kHz X'tal oscillation No • Shared functions: AN10: AD converter input port General-purpose input port Must be connected to VDD1 if not to be used. XT2 I/O • Output terminal for 32.768kHz X'tal oscillation No • Shared functions: AN11: AD converter input port General-purpose I/O port Must be set for oscillation and kept open if not to be used. CF1 I Ceramic resonator input pin No CF2 O Ceramic resonator output pin No No.A0744-11/29 LC875CC8A/B2A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Options Selected in Units of Option Ttype P00 to P07 1 bit 1 P10 to P17 1 bit P20 to P27 Output Type Pull-up Resistor CMOS Programmable (Note 1) 2 N-channel open drain No 1 CMOS Programmable 2 N-channel open drain Programmable 1 CMOS Programmable 2 N-channel open drain Programmable P30 to P36 PA0 to PA5 1 bit PB0 to PB7 PC0 to PC7 PE0 to PE7 - No CMOS Programmable P70 - No N-channel open drain Programmable P71 to P73 - No CMOS Programmable P80 to P87 - No N-channel open drain No SI2P0, SI2P2 - No CMOS No - No CMOS (when selected as ordinary port) No PF0 to PF7 SI2P3 PWM0, PWM1 SI2P1 N-channel open drain (When SIO2 data is selected) XT1 - No Input only No XT2 - No Output for 32.768kHz quartz oscillator No N-channel open drain (when in general-purpose output mode) Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to P03, P04 to P07). No.A0744-12/29 LC875CC8A/B2A *1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, VSS3, and VSS4 pins. (Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the backup capacitors. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 (Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 No.A0744-13/29 LC875CC8A/B2A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] Maximum supply VDD max VDD1, VDD2, VDD3, VDD4 Input voltage VI(1) XT1, CF1 Input/Output VIO(1) Ports 0, 1, 2 voltage voltage VDD1=VDD2=VDD3=VDD4 min typ max -0.3 +6.5 -0.3 VDD+0.3 unit V Ports 3, 7, 8 Ports A, B, C, E, F -0.3 VDD+0.3 SI2P0 to SI2P3 PWM0, PWM1, XT2 Peak output IOPH(1) current Ports 0, 1, 2, 3 CMOS output select per 1 Ports A, B, C, E, F application pin -10 SI2P0 to SI2P3 High level output current Average IOPH(2) PWM0, PWM1 Per 1 application pin. -20 IOPH(3) P71 to P73 Per 1 application pin. -5 Ports 0, 1, 2, 3 CMOS output select per 1 output current IOM(1) Ports A, B, C, E, F application pin -7.5 (Note 1-1) SI2P0 to SI2P3 IOM(2) PWM0, PWM1 Per 1 application pin. -15 IOM(3) P71 to P73 Per 1 application pin. -3 Total output ΣIOAH(1) P71 to P73 Total of all applicable pins current ΣIOAH(2) PWM0, PWM1 Total of all applicable pins SI2P0 to SI2P3 ΣIOAH(3) Port 0 Total of all applicable pins ΣIOAH(4) Port 0 Total of all applicable pins PWM0, PWM1 -10 -25 mA -25 -45 SI2P0 to SI2P3 ΣIOAH(5) Ports 2, 3, B Total of all applicable pins -25 ΣIOAH(6) Ports A, C Total of all applicable pins -25 ΣIOAH(7) Ports 2, 3, A, B, C Total of all applicable pins -45 ΣIOAH(8) Ports F Total of all applicable pins -25 ΣIOAH(9) Ports 1, E Total of all applicable pins -25 ΣIOAH(10) Ports 1, E, F Total of all applicable pins -45 Note 1-1: Average output current is average of current in 100ms interval. Continued on next page. No.A0744-14/29 LC875CC8A/B2A Continued from preceding page. Parameter Peak output Symbol Pins/Remarks Specification Conditions VDD[V] IOPL(1) current P02 to P07 min typ max unit Per 1 application pin. Ports 1, 2, 3 Ports A, B, C, E, F 20 SI2P0 to SI2P3 PWM0, PWM1 Average IOPL(2) P00, P01 Per 1 application pin. 30 IOPL(3) Ports 7, 8, XT2 Per 1 application pin. 10 IOML(1) P02 to P07 Per 1 application pin. output current Ports 1, 2, 3 (Note 1-1) Ports A, B, C, E, F 15 SI2P0 to SI2P3 Low level output current PWM0, PWM1 IOML(2) P00, P01 Per 1 application pin. 20 IOML(3) Ports 7, 8, XT2 Per 1 application pin. 7.5 Total output ΣIOAL(1) Port 7, XT2 Total of all applicable pins 15 current ΣIOAL(2) Port 8 Total of all applicable pins 15 20 ΣIOAL(3) Ports 7, 8, XT2 Total of all applicable pins ΣIOAL(4) PWM0, PWM1 Total of all applicable pins 45 SI2P0 to SI2P3 ΣIOAL(5) Port 0 Total of all applicable pins ΣIOAL(6) Port 0 Total of all applicable pins mA 45 PWM0, PWM1 80 SI2P0 to SI2P3 Maximum power ΣIOAL(7) Ports 2, 3, B Total of all applicable pins 45 ΣIOAL(8) Ports A, C Total of all applicable pins 45 ΣIOAL(9) Ports 2, 3, A, B, C Total of all applicable pins 80 ΣIOAL(10) Port F Total of all applicable pins 45 ΣIOAL(11) Ports 1, E Total of all applicable pins 45 ΣIOAL(12) Ports 1, E, F Total of all applicable pins 80 Pd max QIP100E(14×20) Ta=-30 to +70°C dissipation Operating ambient Topr temperature Storage ambient 444 TQFP100(14×14) Tstg temperature mW 345 -30 70 -55 125 °C Note 1-1: Average output current is average of current in 100ms interval. No.A0744-15/29 LC875CC8A/B2A Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Specification Parameter Symbol Pins/Remarks Conditions VDD[V] Operating VDD(1) supply voltage Memory VHD sustaining VDD1=VDD2 =VDD3=VDD4 0.245μs ≤ tCYC ≤ 200μs min typ max 2.8 unit 5.5 0.367μs ≤ tCYC ≤ 200μs 2.5 5.5 1.47μs ≤ tCYC ≤ 200μs 2.2 5.5 2.0 5.5 VDD1=VDD2 RAM and register contents in =VDD3=VDD4 HOLD mode. supply voltage High level VIH(1) input voltage Ports 1, 2, 3 SI2P0 to SI2P3 2.2 to 5.5 P71 to P73 P70 port input / 0.3VDD VDD +0.7 interrupt side VIH(2) Ports 0, 8 2.2 to 5.5 Ports A, B, C, E, F PWM0, PWM1 VIH(3) P70 Watchdog VIH(4) XT1, XT2, CF1, RES VIL(1) Ports 1, 2, 3 input voltage V 0.9VDD VDD 2.2 to 5.5 0.75VDD 4.0 to 5.5 VSS VDD 0.1VDD 2.2 to 4.0 VSS 4.0 to 5.5 VSS 2.2 to 4.0 VSS 2.2 to 5.5 VSS 2.2 to 5.5 VSS 0.25VDD 2.8 to 5.5 0.245 200 2.5 to 5.5 0.367 200 2.2 to 5.5 1.470 200 • CF2 pin open 2.8 to 5.5 0.1 12 • System clock frequency 2.5 to 5.5 0.1 8 2.2 to 5.5 0.1 2 SI2P0 to SI2P3 VIL(2) VDD +0.7 2.2 to 5.5 timer side Low level 0.3VDD +0.4 P71 to P73 P70 port input/ 0.2VDD interrupt side VIL(3) Ports 0, 8 Ports A, B, C, E, F VIL(4) PWM0, PWM1 VIL(5) Port 70 Watchdog timer side VIL(6) Instruction XT1, XT2, CF1, RES tCYC cycle time (Note 2-1) External FEXCF(1) CF1 system clock frequency 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 μs division rate=1/1 • External system clock duty =50±5% • CF2 pin open 2.8 to 5.5 0.2 24.4 • System clock frequency 2.5 to 5.5 0.2 16 2.2 to 5.5 0.2 4 division rate=1/2 Oscillation FmCF(1) CF1, CF2 frequency range 12MHz ceramic oscillation See Fig. 1. FmCF(2) CF1, CF2 (Note 2-2) 8MHz ceramic oscillation See Fig. 1. FmCF(3) CF1, CF2 4MHz ceramic oscillation See Fig. 1. FmRC Internal RC oscillation FmMRC Frequency variable RC oscillation source oscillation FsX’tal XT1, XT2 32.768kHz crystal oscillation. See Fig. 2. MHz 2.8 to 5.5 12 2.5 to 5.5 8 2.2 to 5.5 4 2.2 to 5.5 0.3 1.0 2.2 to 5.5 16 2.2 to 5.5 32.768 2.0 kHz Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See tables 1 and 2 for the oscillation constants. No.A0744-16/29 LC875CC8A/B2A Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] High level input IIH(1) current Ports 0, 1, 2 Output disable Ports 3, 7, 8 Pull-up resistor OFF Ports A, B, C,E,F VIN=VDD (including the off-leak current of SI2P0 to SI2P3 RES min typ max unit 2.2 to 5.5 1 2.2 to 5.5 1 2.2 to 5.5 15 the output Tr.) PWM0, PWM1 IIH(2) XT1, XT2 Using as an input port VIN=VDD Low level input IIH(3) CF1 VIN=VDD IIL(1) Ports 0, 1, 2 Output disable Ports 3, 7, 8 Pull-up resistor OFF Ports A, B, C, E, F VIN=VSS (including the off-leak current of current SI2P0 to SI2P3 RES μA 2.2 to 5.5 -1 2.2 to 5.5 -1 2.2 to 5.5 -15 the output Tr.) PWM0, PWM1 IIL(2) XT1, XT2 Using as an input port VIN=VSS IIL(3) CF1 VIN=VSS High level output VOH(1) Ports 0, 1, 2, 3 IOH=-1.0mA 4.5 to 5.5 VDD-1 voltage VOH(2) Ports A, B, C, E, F IOH=-0.4mA 3.0 to 5.5 VDD-0.4 VOH(3) VOH(4) SI2P0 to SI2P3 Ports 71, 72, 73 VOH(5) VOH(6) PWM0, PWM1 VOH(7) P30, P31 VOH(8) (PWM4, 5 output mode) Low level output VOL(1) Ports 0, 1, 2, 3 voltage VOL(2) Ports A, B, C, E, F 2.2 to 5.5 VDD-0.4 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 IOH=-10mA 4.5 to 5.5 VDD-1.5 IOH=-1.6mA 3.0 to 5.5 VDD-0.4 IOH=-1.0mA 2.2 to 5.5 VDD-0.4 IOL=10mA 4.5 to 5.5 1.5 IOL=1.6mA 3.0 to 5.5 0.4 2.2 to 5.5 0.4 IOL=30mA 4.5 to 5.5 1.5 VOL(5) IOL=5.0mA 3.0 to 5.5 0.4 VOL(6) IOL=2.5mA 2.2 to 5.5 0.4 VOL(4) VOL(7) SI2P0 to SI2P3 PWM0, PWM1 P00, P01 Ports 7, 8, XT2 VOL(8) Rpu(1) Ports 0, 1, 2, 3 Rpu(2) Port 7 IOL=1.6mA 3.0 to 5.5 0.4 IOL=1.0mA 2.2 to 5.5 0.4 VOH=0.9VDD 4.5 to 5.5 15 35 80 2.2 to 5.5 15 35 150 kΩ Ports A, B, C, E, F Hysteresis voltage V IOL=1.0mA VOL(3) Pull-up resistation IOH=-0.2mA VHYS RES Ports 1, 2, 7 2.2 to 5.5 0.1VDD V 2.2 to 5.5 10 pF SI2P0 to SI2P3 Pin capacitance CP All pins • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C No.A0744-17/29 LC875CC8A/B2A Serial I/O Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Frequency tSCK(1) Low level tSCKL(1) Pins/ Remarks SCK0(P12) Specification Conditions VDD[V] • See Fig. 6. max unit 1 tSCKH(1) 1 pulse width tSCKHA(1a) Input clock typ 2 pulse width High level min • Continuous data transmission/ reception mode • SIO2 is not in use simultaneous. 2.2 to 5.5 4 tCYC • See Fig. 6. • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/ reception mode • SIO2 is in use simultaneous. 6 Serial clock • See Fig. 6. • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected. 4/3 • See Fig. 6. Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 1/2 Output clock pulse width tSCKHA(2a) • Continuous data transmission/ reception mode • SIO2 is not in use simultaneous. 2.2 to 5.5 • CMOS output selected. tSCKH(2) tSCKH(2) +2tCYC +(10/3)tCYC • See Fig. 6. tSCKHA(2b) tCYC • Continuous data transmission/ reception mode • SIO2 is in use simultaneous. • CMOS output selected. tSCKH(2) tSCKH(2) +2tCYC +(16/3)tCYC • See Fig. 6. Serial input Data setup time SI0(P11), SB0(P11) Data hold • Must be specified with respect • See fig. 6. thDI(1) Input clock 2.2 to 5.5 0.03 tdD0(1) time SO0(P10), SB0(P11), • Continuous data transmission/ (1/3)tCYC reception mode +0.05 • (Note 4-1-3) tdD0(2) μs • Synchronous 8-bit mode. 1tCYC • (Note 4-1-3) tdD0(3) Output clock 0.03 to rising edge of SIOCLK Time Output delay Serial output tsDI(1) • (Note 4-1-3) +0.05 2.2 to 5.5 (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. No.A0744-18/29 LC875CC8A/B2A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Input clock Symbol Frequency tSCK(3) Low level tSCKL(3) Pins/ SCK1(P15) VDD[V] • See Fig. 6. Frequency SCK1(P15) • CMOS output selected. tSCKL(4) 2 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time SI1(P14), SB1(P14) • Must be specified with respect to rising edge of SIOCLK • See fig. 6. Data hold time thDI(2) 0.03 2.2 to 5.5 0.03 Output delay time Serial output tsDI(2) unit 1 2.2 to 5.5 pulse width High level max 1 • See Fig. 6. Low level typ tCYC tSCKH(3) tSCK(4) min 2 2.2 to 5.5 pulse width High level Specification Conditions Remarks pulse width Output clock Serial clock Parameter tdD0(4) SO1(P13), SB1(P14) μs • Must be specified with respect to falling edge of SIOCLK • Must be specified as the time to the beginning of output state 2.2 to 5.5 change in open drain output (1/3)tCYC +0.05 mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. No.A0744-19/29 LC875CC8A/B2A 3. SIO2 Serial I/O Characteristics (Note 4-3-1) Parameter Frequency Symbol tSCK(5) Pins/ SCK2 Specification Conditions Remarks VDD[V] • See Fig. 6. tSCKL(5) tSCKH(5) unit 1 pulse width tSCKHA(5a) Input clock max 1 pulse width High level typ 2 (SI2P2) Low level min • Continuous data transmission/ reception mode of SIO0 is not in use simultaneous. 2.2 to 5.5 4 tCYC • See Fig. 6. • (Note 4-3-2) tSCKHA(5b) • Continuous data transmission/ reception mode of SIO0 is in use simultaneous. 7 Serial clock • See Fig. 6. • (Note 4-3-2) Frequency Low level tSCK(6) tSCKL(6) • CMOS output selected. (SI2P2), • See Fig. 6. 4/3 SCK2O 1/2 (SI2P3) pulse width High level SCK2 tSCK tSCKH(6) 1/2 Output clock pulse width tSCKHA(6a) • Continuous data transmission/ reception mode of SIO0 is not in use simultaneous. 2.2 to 5.5 • CMOS output selected. tSCKH(6) tSCKH(6) +(5/3)tCYC + (10/3)tCYC • See Fig. 6. tCYC • Continuous data transmission/ tSCKHA(6b) reception mode of SIO0 is in use simultaneous. • CMOS output selected. tSCKH(6) tSCKH(6) +(5/3)tCYC + (19/3)tCYC • See Fig. 6. Serial input Data setup time SI2(SI2P1), SB2(SI2P1) • Must be specified with respect Data hold time 0.03 to rising edge of SIOCLK • See fig. 6. thDI(3) 2.2 to 5.5 0.03 Output delay time Serial output tsDI(3) tdD0(5) SO2(SI2P0), SB2(SI2P1) μs • Must be specified with respect to falling edge of SIOCLK • Must be specified as the time to the beginning of output state change in open drain output 2.2 to 5.5 (1/3)tCYC +0.05 mode. • See Fig. 6. Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. No.A0744-20/29 LC875CC8A/B2A Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 are INT2(P72) min typ max unit enabled. INT4(P20 to P23), 2.2 to 5.5 1 2.2 to 5.5 2 2.2 to 5.5 64 2.2 to 5.5 256 2.2 to 5.5 200 INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) INT3(P73) • Interrupt source flag can be set. tPIL(2) (The noise rejection • Event inputs for timer 0 are clock is selected to enabled. tCYC 1/32.) tPIH(3) INT3(P73) • Interrupt source flag can be set. tPIL(3) (The noise rejection • Event inputs for timer 0 are clock is selected to enabled. 1/32.) tPIH(4) INT3(P73) • Interrupt source flag can be set. tPIL(4) (The noise rejection • Event inputs for timer 0 are clock is selected to enabled. 1/128.) tPIL(5) RES Reset acceptable μs AD Converter Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] Resolution N AN0(P80) Absolute ET to AN7(P87), Conversion (Note 6-1) TCAD time AN9(P71), AD conversion time=32×tCYC AN10(XT1), (when ADCR2=0) max unit 8 bit ±1.5 11.74 97.92 (tCYC= (tCYC= AN11(XT2), 0.367μs) 3.06μs) AN12(PA3), 31.36 97.92 (tCYC= (tCYC= 0.980μs) 3.06μs) 15.68 97.92 (Note 6-2) AN13(PA4), 4.5 to 5.5 3.0 to 5.5 AN14(PA5) AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 3.0 to 5.5 Analog input typ 3.0 to 5.5 AN8(P70), precision min 3.0 to 5.5 VAIN 3.0 to 5.5 voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 (tCYC= (tCYC= 0.245μs) 1.53μs) 31.36 97.92 (tCYC= (tCYC= 0.490μs) 1.53μs) VSS VDD 1 -1 LSB μs V μA Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register. No.A0744-21/29 LC875CC8A/B2A Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Normal mode Symbol IDDOP(1) consumption current (Note 7-1) IDDOP(2) Pins/ VDD1 =VDD2 =VDD3 =VDD4 Specification Conditions Remarks VDD[V] min typ max unit • FmCF=12MHz ceramic oscillation mode • FmX’tal=32.768kHz by crystal oscillation 4.5 to 5.5 9.6 14 2.8 to 4.5 4.8 8.5 4.5 to 5.5 6.2 10 2.5 to 4.5 3.2 6.5 4.5 to 5.5 2.5 3 mode • System clock set to 12MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDOP(3) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode IDDOP(4) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDOP(5) • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode IDDOP(6) mA • System clock set to 4MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped 2.2 to 4.5 1.2 2.5 4.5 to 5.5 0.7 2 2.2 to 4.5 0.3 1.5 4.5 to 5.5 1.25 3 2.2 to 4.5 0.75 2 4.5 to 5.5 27 65 • 1/2 frequency division ratio. IDDOP(7) • FmCF=0Hz(oscillation stopped) • FmX’tal=32.768kHz by crystal oscillation mode IDDOP(8) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped •1/2 frequency division ratio. IDDOP(9) • FmCF=0Hz(oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. IDDOP(10) • System clock set to 1MHz with frequency variable RC oscillation • Internal RC oscillation stopped • 1/2 frequency division ratio. IDDOP(11) • FmCF=0Hz(oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. IDDOP(12) μA • System clock set to 32.768kHz side. • Internal RC oscillation stopped • Frequency variable RC oscillation stopped 2.2 to 4.5 12 45 • 1/2 frequency division ratio. Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A0744-22/29 LC875CC8A/B2A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) consumption current (Note 7-1) Pins/ Specification Conditions Remarks VDD[V] VDD1 =VDD2 • HALT mode =VDD3 =VDD4 • FmX’tal=32.768kHz by crystal oscillation • FmCF=12MHz ceramic oscillation mode min typ max unit 4.5 to 5.5 3.3 6 2.8 to 5.5 1.6 3.5 4.5 to 5.5 2.3 4.5 2.5 to 5.5 0.98 2.5 4.5 to 5.5 1.2 2.0 mode • System clock set to 12MHz side IDDHALT(2) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDHALT(3) • HALT mode • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode • System clock set to 8MHz side IDDHALT(4) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDHALT(5) • HALT mode • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz by crystal oscillation mA mode • System clock set to 4MHz side IDDHALT(6) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped 2.2 to 4.5 0.6 1.5 4.5 to 5.5 0.3 1 2.2 to 4.5 0.14 0.5 4.5 to 5.5 1.0 2.5 2.2 to 4.5 0.5 1.8 4.5 to 5.5 17 55 2.2 to 4.5 5 30 4.5 to 5.5 0.02 10 2.2 to 4.5 0.008 8 4.5 to 5.5 14 40 2.2 to 4.5 3.2 2.5 • 1/2 frequency division ratio. • HALT mode IDDHALT(7) • FmCF=0Hz(oscillation stopped) • FmX’tal=32.768kHz by crystal oscillation mode IDDHALT(8) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped •1/2 frequency division ratio. • HALT mode IDDHALT(9) • FmCF=0Hz(oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • System clock set to 1MHz with frequency IDDHALT(10) variable RC oscillation • Internal RC oscillation stopped • 1/2 frequency division ratio. • HALT mode IDDHALT(11) • FmCF=0Hz(oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • System clock set to 32.768kHz side. IDDHALT(12) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped μA • 1/2 frequency division ratio. Current drain during HOLD mode Current drain IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) during timebase clock HOLD mode VDD1 • HOLD mode • CF1=VDD or open (External clock mode) • Timer HOLD mode • CF1=VDD or open(External clock mode) IDDHOLD(4) • FmX'tal=32.768kHz by crystal oscillation mode Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.A0744-23/29 LC875CC8A/B2A UART(Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] Clock rate UBR, UBR2 min typ max unit 8192/3 tCYC UTX1(P32), RTX1(P33), 2.2 to 5.5 UTX2(P33), 16/3 RTX2(P34) Data length: 7,8,and 9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: Non Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR, UBR2 Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H) Stop bit Start bit Start of reception Received data (LSB first) End of reception UBR, UBR2 No.A0744-24/29 LC875CC8A/B2A VDD1, VSS1 Terminal Condition It is necessary to place capacitors between VDD1 and VSS1 as described below. • Place capacitors as close to VDD1 and VSS1 as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’). • Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel. • Capacitance of C2 must be more than 0.1μF. • Use thicker pattern for VDD1 and VSS1. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ VDD3, VSS3 Terminal Condition It is necessary to place capacitors between VDD3 and VSS3 as described below. • Place capacitors as close to VDD3 and VSS3 as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L3 = L3’). • Capacitance of C3 must be more than 0.1μF. • Use thicker pattern for VDD3 and VSS3. L3 VSS3 C3 VDD3 L3’ No.A0744-25/29 LC875CC8A/B2A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1. Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Vendor Frequency Name 12MHz 8MHz MURATA 4MHz Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time Remarks C1 C2 Rf1 Rd1 Range [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE12M0G52-R0 (10) (10) OPEN 470 2.8 to 5.5 0.05 0.15 Internal C1, C2 CSTCE8M00G52-R0 (10) (10) OPEN 2.2k 2.7 to 5.5 0.05 0.15 Internal C1, C2 CSTLS8M00G53-B0 (15) (15) OPEN 680 2.5 to 5.5 0.05 0.15 Internal C1, C2 typ max CSTCR4M00G53-R0 (15) (15) OPEN 3.3k 2.2 to 5.5 0.05 0.15 Internal C1, C2 CSTLS4M00G53-R0 (15) (15) OPEN 3.3k 2.2 to 5.5 0.05 0.15 Internal C1, C2 The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Fig 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2. Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency 32.768kHz Vendor Name SEIKO EPSON Circuit Constant Oscillator Name MC-306 Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 18 18 OPEN 560k 2.2 to 5.5 1.3 3.0 Remarks Applicatable CL Value=12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Fig 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 Rf1 XT1 Rd1 C2 C1 XT2 Rf2 C3 Rd2 C4 CF X’tal Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing point No.A0744-26/29 LC875CC8A/B2A VDD VDD limit Power Supply GND Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilization Time HOLD release signal HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operation mode HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time No.A0744-27/29 LC875CC8A/B2A VDD Note : Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. RRES RES CRES Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission period (only SIO0,2) tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transmission period (only SIO0,2) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Condition No.A0744-28/29 LC875CC8A/B2A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. PS No.A0744-29/29