STMicroelectronics M30L0R8000B0ZAQ 256 mbit (16mb x16, multiple bank, multi-level, burst) 1.8v supply flash memory Datasheet

M30L0R8000T0
M30L0R8000B0
256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst)
1.8V Supply Flash Memory
FEATURES SUMMARY
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SUPPLY VOLTAGE
– VDD = 1.7V to 2.0V for program, erase and
read
– VDDQ = 1.7V to 2.0V for I/O Buffers
– VPP = 9V for fast program (12V tolerant)
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode:
54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
MEMORY ORGANIZATION
– Multiple Bank Memory Array: 16 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
May 2005
Figure 1. Package
FBGA
TFBGA88 (ZAQ) 8 x 10mm
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ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code,
M30L0R8000T0: 880Dh.
– Bottom Device Code,
M30L0R8000B0: 880Eh.
PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
1/83
M30L0R8000T0, M30L0R8000B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2.
Table 1.
Figure 3.
Table 2.
Figure 4.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TFBGA88 Package Connections (Top view through package) . . . .
Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2/83
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M30L0R8000T0, M30L0R8000B0
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Buffer Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Buffer Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Protection Register Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. X-Latency Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Burst length Bits (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/83
M30L0R8000T0, M30L0R8000B0
READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Synchronous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. Dual Operation Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Program/Erase Times and Endurance Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10.Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 11.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13.Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14.Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 15.Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 24. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 25. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 18.Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4/83
M30L0R8000T0, M30L0R8000B0
Table 27. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 19.TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline . . . . 55
Table 28. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data . . . . . . . 55
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 30. M30L0R8000T0 - Parameter Bank Block Addresses . . . .
Table 31. M30L0R8000T0 - Main Bank Base Addresses . . . . . . . . .
Table 32. M30L0R8000T0 - Block Addresses in Main Banks . . . . . .
Table 33. M30L0R8000B0 - Parameter Bank Block Addresses . . . .
Table 34. M30L0R8000B0 - Main Bank Base Addresses . . . . . . . . .
Table 35. M30L0R8000B0 - Block Addresses in Main Banks . . . . . .
.......
.......
.......
.......
.......
.......
......
......
......
......
......
......
......
......
......
......
......
......
. . . . 58
. . . . 58
. . . . 58
. . . . 59
. . . . 59
. . . . 59
APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 36. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 37. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 40. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 41. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 42. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 43. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 44. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 45. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 20.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 21.Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 25.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 26.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 75
Figure 27.Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . 76
APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 46. Command Interface States - Modify Table, Next State . . .
Table 47. Command Interface States - Modify Table, Next Output . .
Table 48. Command Interface States - Lock Table, Next State . . . .
Table 49. Command Interface States - Lock Table, Next Output . . .
.......
.......
.......
.......
......
......
......
......
......
......
......
......
. . . . 77
. . . . 79
. . . . 80
. . . . 81
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5/83
M30L0R8000T0, M30L0R8000B0
Table 50. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6/83
M30L0R8000T0, M30L0R8000B0
SUMMARY DESCRIPTION
The M30L0R8000T0 and M30L0R8000B0 are 256
Mbit (16 Mbit x16) non-volatile Flash memories
that may be erased electrically at block level and
programmed in-system on a Word-by-Word basis
using a 1.7V to 2.0V VDD supply for the circuitry
and a 1.7V to 2.0V VDDQ supply for the Input/Output pins. An optional 9V VPP power supply is provided to speed up factory programming.
The device features an asymmetrical block architecture and is based on a multi-level cell technology.
The M30L0R8000x0 has an array of 259 blocks,
and is divided into 16 Mbit banks. There are 15
banks each containing 16 main blocks of 64
KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 15 main blocks
of 64 KWords.
The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank,
read operations are possible in other banks. Only
one bank at a time is allowed to be in program or
erase mode. It is possible to perform burst reads
that cross bank boundaries. The bank architecture
is summarized in Table 2., and the memory maps
are shown in Figure 4. The Parameter Blocks are
located at the top of the memory address space for
the M30L0R8000T0, and at the bottom for the
M30L0R8000B0.
Each block can be erased separately. Erase can
be suspended, in order to perform a program or
read operation in any other block, and then resumed. Program can be suspended to read data
at any memory location except for the one being
programmed, and then resumed. Each block can
be programmed and erased over 100,000 cycles
using the supply voltage VDD. There is a Buffer
Enhanced Factory programming command available to speed up programming.
Program and erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC standards.
The device supports Synchronous Burst Read and
Asynchronous Read from all blocks of the memory
array; at power-up the device is configured for
Asynchronous Read. In Synchronous Burst Read
mode, data is output on each clock cycle at frequencies of up to 54MHz. The Synchronous Burst
Read operation can be suspended and resumed.
The device features an Automatic Standby mode.
When the bus is inactive during Asynchronous
Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the
standby value and the outputs are still driven.
The M30L0R8000x0 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase.
When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at powerup.
The device includes 17 Protection Registers and 2
Protection Register locks, one for the first Protection Register and the other for the 16 One-TimeProgrammable (OTP) Protection Registers of 128
bits each. The first Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 64 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected. Figure 5., shows the Protection Register Memory Map.
The M30L0R8000x0 is offered in a Stacked
TFBGA88 8x10mm - 8x10 active ball array,
0.8mm pitch package.
In addition to the standard version, the packages
are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free soldering processes.
The devices are supplied with all the bits erased
(set to ’1’).
7/83
M30L0R8000T0, M30L0R8000B0
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A23
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command
Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset
WP
Write Protect
K
Clock
RP
L
Latch Enable
WP
WAIT
Wait
L
VDD
Supply Voltage
K
VDDQ
Supply Voltage for Input/Output
Buffers
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS
Ground
VSSQ
Ground Input/Output Supply
NC
Not Connected Internally
DU
Do Not Use
VDD VDDQ VPP
24
16
A0-A23
DQ0-DQ15
W
E
G
WAIT
M30L0R8000T0
M30L0R8000B0
VSS
VSSQ
AI08496
8/83
M30L0R8000T0, M30L0R8000B0
Figure 3. TFBGA88 Package Connections (Top view through package)
1
2
3
4
5
A
DU
DU
B
A4
A18
A19
VSS
VDD
C
A5
NC
A23
VSS
D
A3
A17
NC
E
A2
A7
F
A1
G
6
7
8
DU
DU
NC
A21
A11
NC
K
A22
A12
VPP
NC
NC
A9
A13
NC
WP
L
A20
A10
A15
A6
NC
RP
W
A8
A14
A16
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
NC
H
NC
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
NC
G
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
E
NC
NC
NC
NC
NC
VDDQ
NC
L
VSS
VSS
VDDQ
VDD
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI08497
9/83
M30L0R8000T0, M30L0R8000B0
Table 2. Bank Architecture
Parameter Bank
16 Mbits
4 blocks of 16 KWords
15 blocks of 64 KWords
Bank 1
16 Mbits
-
16 blocks of 64 KWords
Bank 2
16 Mbits
-
16 blocks of 64 KWords
Bank 3
16 Mbits
-
16 blocks of 64 KWords
----
Main Blocks
----
Parameter Blocks
----
Bank Size
----
Number
Bank 14
16 Mbits
-
16 blocks of 64 KWords
Bank 15
16 Mbits
-
16 blocks of 64 KWords
Figure 4. Memory Map
M30L0R8000B0 - Bottom Boot Block
Address lines A23-A0
M30L0R8000T0 - Top Boot Block
Address lines A23-A0
000000h
00FFFFh
64 KWord
0F0000h
0FFFFFh
64 KWord
Bank 15
C00000h
C0FFFFh
16 Main
Blocks
Parameter
Bank
FE0000h
FEFFFFh
FF0000h
FF3FFFh
FFC000h
FFFFFFh
4 Parameter
Blocks
16 KWord
64 KWord
15 Main
Blocks
64 KWord
64 KWord
16 Main
Blocks
64 KWord
64 KWord
16 Main
Blocks
Bank 2
2F0000h
2FFFFFh
300000h
30FFFFh
64 KWord
Bank 1
EF0000h
EFFFFFh
F00000h
F0FFFFh
1F0000h
1FFFFFh
200000h
20FFFFh
64 KWord
16 Main
Blocks
16 KWord
Bank 1
64 KWord
16 Main
Blocks
00C000h
00FFFFh
010000h
01FFFFh
0F0000h
0FFFFFh
100000h
10FFFFh
64 KWord
Bank 2
DF0000h
DFFFFFh
E00000h
E0FFFFh
Parameter
Bank
64 KWord
Bank 3
CF0000h
CFFFFFh
D00000h
D0FFFFh
000000h
003FFFh
16 Main
Blocks
64 KWord
64 KWord
16 Main
Blocks
Bank 3
64 KWord
3F0000h
3FFFFFh
64 KWord
F00000h
F0FFFFh
64 KWord
FF0000h
FFFFFFh
64 KWord
64 KWord
15 Main
Blocks
64 KWord
16 KWord
4 Parameter
Blocks
16 KWord
16 Main
Blocks
Bank 15
AI08498
10/83
M30L0R8000T0, M30L0R8000B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A23). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address during a Bus Read operation or input a command or
the data to be programmed during a Bus Write operation.
Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable input
controls data outputs during the Bus Read operation of the memory.
Write Enable (W). The Write Enable input controls the Bus Write operation of the memory’s
Command Interface. The data and address inputs
are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the LockDown is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to Table 16., Lock Status).
Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to
Table 21., DC Characteristics - Currents, for the
value of IDD2. After Reset all blocks are in the
Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal
operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH
(refer to Table 22., DC Characteristics - Voltages).
Latch Enable (L). Latch Enable latches the address bits on its rising edge. The address
latch is transparent when Latch Enable is at
V IL and it is inhibited when Latch Enable is at
V IH . Latch Enable can be kept Low (also at
board level) when the Latch Enable function
is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is
ignored during asynchronous read and in write operations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is
at VIH, or Reset is at VIL. It can be configured to be
active during the wait cycle or one data cycle in advance.
VDD Supply Voltage . VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently of VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a
control input and a power supply pin. The two
functions are selected by the voltage range applied to the pin.
If VPP is kept in a low voltage range (0V to VDDQ)
VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection
against program or erase, while if VPP is within the
VPP1 range these functions are enabled (see Tables 21 and 22, DC Characteristics for the relevant
values). VPP is only sampled at the beginning of a
program or erase; a change in its value after the
operation has started does not have any effect and
program or erase operations continue.
If VPP is in the range of VPPH it acts as a power
supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.
11/83
M30L0R8000T0, M30L0R8000B0
VSS Ground. VSS ground is the reference for the
core supply. It must be connected to the system
ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VDDQ. VSSQ
must be connected to VSS
12/83
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors
should be as close as possible to the package). See Figure 9., AC Measurement Load Circuit. The PCB track widths should be sufficient
to carry the required VPP program and erase
currents.
M30L0R8000T0, M30L0R8000B0
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset.
See Table 3., Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
See Figures 10, 11, 12 and 13 Read AC Waveforms, and Tables 23 and 24 Read AC Characteristics, for details of when the output becomes
valid.
Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at VIL with
Output Enable at VIH. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the
bus write operation.
See Figures 16 and 17, Write AC Waveforms, and
Tables 25 and 26, Write AC Characteristics, for
details of the timing requirements.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high impedance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the current consumption. The memory is in standby when
Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and
the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a
program or erase operation, the device enters
Standby mode when finished.
Reset. During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL.
The power consumption is reduced to the Reset
level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to
VSS during a Program or Erase, this operation is
aborted and the memory content is no longer valid.
Table 3. Bus Operations
Operation
WAIT(4)
E
G
W
L
RP
Bus Read
VIL
VIL
VIH
VIL(2)
VIH
Data Output
Bus Write
VIL
VIH
VIL
VIL(2)
VIH
Data Input
Address Latch
VIL
X
VIH
VIL
VIH
Data Output or Hi-Z (3)
Output Disable
VIL
VIH
VIH
X
VIH
Hi-Z
Hi-Z
Standby
VIH
X
X
X
VIH
Hi-Z
Hi-Z
X
X
X
X
VIL
Hi-Z
Hi-Z
Reset
Note: 1.
2.
3.
4.
DQ15-DQ0
X = Don't care.
L can be tied to VIH if the valid address has been previously latched.
Depends on G.
WAIT signal polarity is configured using the Set Configuration Register command.
13/83
M30L0R8000T0, M30L0R8000B0
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution
of the program and erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
The Command Interface is reset to read mode
when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any
invalid combination of commands will be ignored.
Refer to Table 4., Command Codes, Table
5., Standard Commands, Table 6., Factory Program Command, and APPENDIX D., COMMAND
INTERFACE STATE TABLES, for a summary of
the Command Interface.
Read Array Command
The Read Array command returns the addressed
bank to Read Array mode.
One Bus Write cycle is required to issue the Read
Array command. Once a bank is in Read Array
mode, subsequent read operations will output the
data from the memory array.
A Read Array command can be issued to any
banks while programming or erasing in another
bank.
If the Read Array command is issued to a bank
currently executing a program or erase operation,
the bank will return to Read Array mode but the
program or erase operation will continue, however
the data output from the bank is not guaranteed
until the program or erase operation has finished.
The read modes of other banks are not affected.
Read Status Register Command
Table 4. Command Codes
Hex Code
Command
01h
Block Lock Confirm
03h
Set Configuration Register Confirm
10h
Alternative Program Setup
20h
Block Erase Setup
2Fh
Block Lock-Down Confirm
40h
Program Setup
50h
Clear Status Register
60h
Block Lock Setup, Block Unlock Setup,
Block Lock Down Setup and Set
Configuration Register Setup
70h
Read Status Register
80h
Buffer Enhanced Factory Program
90h
Read Electronic Signature
98h
Read CFI Query
B0h
Program/Erase Suspend
C0h
Protection Register Program
D0h
Program/Erase Resume, Block Erase
Confirm, Block Unlock Confirm or Buffer
Program Confirm
E8h
Buffer Program
FFh
Read Array
14/83
The device contains a Status Register that is used
to monitor program or erase operations.
The Read Status Register command is used to
read the contents of the Status Register for the addressed bank.
One Bus Write cycle is required to issue the Read
Status Register command. Once a bank is in Read
Status Register mode, subsequent read operations will output the contents of the Status Register.
The Status Register data is latched on the falling
edge of the Chip Enable or Output Enable signals.
Either Chip Enable or Output Enable must be toggled to update the Status Register data
The Read Status Register command can be issued at any time, even during program or erase
operations. The Read Status Register command
will only change the read mode of the addressed
bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read
the Status Register. A Read Array command is required to return the bank to Read Array mode.
See Table 9. for the description of the Status Register Bits.
M30L0R8000T0, M30L0R8000B0
Read Electronic Signature Command
The Read Electronic Signature command is used
to read the Manufacturer and Device Codes, the
Lock Status of the addressed bank, the Protection
Register, and the Configuration Register.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once a bank is in
Read Electronic Signature mode, subsequent
read operations in the same bank will output the
Manufacturer Code, the Device Code, the Lock
Status of the addressed bank, the Protection Register, or the Configuration Register (see Table 7.).
The Read Electronic Signature command can be
issued at any time, even during program or erase
operations, except during Protection Register Program operations. Dual operations between the Parameter bank and the Electronic Signature
locations are not allowed (see Table 15., Dual Operation Limitations for details).
If a Read Electronic Signature command is issued
to a bank that is executing a program or erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read cycles will
output the Electronic Signature data and the Program/Erase controller will continue to program or
erase in the background.
The Read Electronic Signature command will only
change the read mode of the addressed bank. The
read modes of other banks are not affected. Only
Asynchronous Read and Single Synchronous
Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode.
Read CFI Query Command
The Read CFI Query command is used to read
data from the Common Flash Interface (CFI).
One Bus Write cycle is required to issue the Read
CFI Query command. Once a bank is in Read CFI
Query mode, subsequent Bus Read operations in
the same bank will output the contents of the Common Flash Interface.
The Read CFI Query command can be issued at
any time, even during program or erase operations.
If a Read CFI Query command is issued to a bank
that is executing a program or erase operation the
bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output the CFI data
and the Program/Erase controller will continue to
program or erase in the background.
The Read CFI Query command will only change
the read mode of the addressed bank. The read
modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A
Read Array command is required to return the
bank to Read Array mode.
Dual operations between the Parameter Bank and
the CFI memory space are not allowed (see Table
15., Dual Operation Limitations for details).
See APPENDIX B., COMMON FLASH INTERFACE, Tables 36, 37, 38, 39, 40, 42, 43, 44 and 45
for details on the information contained in the
Common Flash Interface memory area.
Clear Status Register Command
The Clear Status Register command can be used
to reset (set to ‘0’) all error bits (SR1, 3, 4 and 5) in
the Status Register.
One Bus Write cycle is required to issue the Clear
Status Register command. The Clear Status Register command does not affect the read mode of
the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should
be cleared before attempting a new program or
erase command.
Block Erase Command
The Block Erase command is used to erase a
block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost.
If the block is protected then the erase operation
will abort, the data in the block will not be changed
and the Status Register will output the error.
Two Bus Write cycles are required to issue the
command.
■
The first bus cycle sets up the Block Erase
command.
■
The second latches the block address and
starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are
set and the command is aborted.
Once the command is issued the bank enters
Read Status Register mode and any read operation within the addressed bank will output the contents of the Status Register. A Read Array
command is required to return the bank to Read
Array mode.
During Block Erase operations the bank containing the block being erased will only accept the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/
Erase Suspend command, all other commands
will be ignored.
The Block Erase operation aborts if Reset, RP,
goes to VIL. As data integrity cannot be guaran-
15/83
M30L0R8000T0, M30L0R8000B0
teed when the Block Erase operation is aborted,
the block must be erased again.
Refer to Dual Operations section for detailed information about simultaneous operations allowed in
banks not being erased.
Typical Erase times are given in Table
17., Program/Erase Times and Endurance Cycles.
See APPENDIX C., Figure 23., Block Erase Flowchart and Pseudo Code, for a suggested flowchart
for using the Block Erase command.
Program Command
The program command is used to program a single Word to the memory array.
If the block is protected, the program operation will
abort, the data in the block will not be changed and
the Status Register will output the error.
Two Bus Write cycles are required to issue the
Program Command.
■
The first bus cycle sets up the Program
command.
■
The second latches the address and data to
be programmed and starts the Program/Erase
Controller.
Once the programming has started, read operations in the bank being programmed output the
Status Register content.
During a Program operation, the bank containing
the Word being programmed will only accept the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/
Erase Suspend command, all other commands
will be ignored. A Read Array command is required to return the bank to Read Array mode.
Refer to Dual Operations section for detailed information about simultaneous operations allowed in
banks not being programmed.
Typical Program times are given in Table
17., Program/Erase Times and Endurance Cycles.
The Program operation aborts if Reset, RP, goes
to VIL. As data integrity cannot be guaranteed
when the Program operation is aborted, the Word
must be reprogrammed.
See APPENDIX C., Figure 20., Program Flowchart and Pseudo Code, for the flowchart for using
the Program command.
Buffer Program Command
The Buffer Program Command makes use of the
device’s 32-Word Write Buffer to speed up programming. Up to 32 Words can be loaded into the
Write Buffer. The Buffer Program command dra-
16/83
matically reduces in-system programming time
compared to the standard non-buffered Program
command.
If the block is protected, the Buffer Program operation will abort, the data in the block will not be
changed and the Status Register will output the error.
Four successive steps are required to issue the
Buffer Program command.
1. The first Bus Write cycle sets up the Buffer
Program command. The setup code can be
addressed to any location within the targeted
block.
After the first Bus Write cycle, read operations in
the bank will output the contents of the Status
Register. Status Register bit SR7 should be read
to check that the buffer is available (SR7 = 1). If
the buffer is not available (SR7 = 0), re-issue the
Buffer Program command to update the Status
Register contents.
2. The second Bus Write cycle sets up the
number of Words to be programmed. Value n
is written to the same block address, where
n+1 is the number of Words to be
programmed.
3. Use n+1 Bus Write cycles to load the address
and data for each Word into the Write Buffer.
Addresses must lie within the range from the
start address to the start address + n.
Optimum performance is obtained when the
start address corresponds to a 32 Word
boundary. If the start address is not aligned to
a 32 word boundary, the total programming
time is doubled
4. The final Bus Write cycle confirms the Buffer
Program command and starts the program
operation.
All the addresses used in the Buffer Program operation must lie within the same block.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the operation without affecting the data in the memory array.
If the Status Register bits SR4 and SR5 are set to
'1', the Buffer Program Command is not accepted.
Clear the Status Register before re-issuing the
command.
During Buffer Program operations the bank being
programmed will only accept the Read Array,
Read Status Register, Read Electronic Signature,
Read CFI Query and the Program/Erase Suspend
command, all other commands will be ignored.
Refer to Dual Operations section for detailed information about simultaneous operations allowed in
banks not being programmed.
M30L0R8000T0, M30L0R8000B0
See APPENDIX C., Figure 21., Buffer Program
Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Program command.
Buffer Enhanced Factory Program Command
The Buffer Enhanced Factory Program command
has been specially developed to speed up programming in manufacturing environments where
the programming time is critical.
It is used to program one or more Write Buffer(s)
of 32 Words to a block. Once the device enters
Buffer Enhanced Factory Program mode, the
Write Buffer can be reloaded any number of times
as long as the address remains within the same
block. Only one block can be programmed at a
time.
The use of the Buffer Enhanced Factory Program
command requires certain operating conditions:
■
VPP must be set to VPPH
■
VDD must be within operating range
■
Ambient temperature TA must be 30°C ± 10°C
■
The targeted block must be unlocked
■
The start address must be aligned with the
start of a 32 Word buffer boundary
■
The address must remain the Start Address
throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation and the
command cannot be suspended.
If the block is protected, the Buffer Enhanced Factory Program operation will abort, the data in the
block will not be changed and the Status Register
will output the error.
The Buffer Enhanced Factory Program Command
consists of three phases: the Setup Phase, the
Program and Verify Phase, and the Exit Phase,
Please refer to Table 6., Factory Program Command for detail information.
Setup Phase. The Buffer Enhanced Factory Program command requires two Bus Write cycles to
initiate the command.
■
The first Bus Write cycle sets up the Buffer
Enhanced Factory Program command.
■
The second Bus Write cycle confirms the
command.
After the confirm command is issued, read operations output the contents of the Status Register.
The read Status Register command must not be
issued as it will be interpreted as data to program.
The Status Register P/E.C. Bit SR7 should be
read to check that the P/E.C. is ready to proceed
to the next phase.
If an error is detected, SR4 goes high (set to ‘1’)
and the Buffer Enhanced Factory Program operation is terminated. See Status Register section for
details on the error.
Program and Verify Phase. The Program and
Verify Phase requires 32 cycles to program the 32
Words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write
Buffer, until the Write Buffer is full (32 Words). To
program less than 32 Words, the remaining Words
should be programmed with FFFFh.
Three successive steps are required to issue and
execute the Program and Verify Phase of the command.
1. Use one Bus Write operation to latch the Start
Address and the first Word to be programmed.
The Status Register Bank Write Status bit SR0
should be read to check that the P/E.C. is
ready for the next Word.
2. Each subsequent Word to be programmed is
latched with a new Bus Write operation. The
address must remain the Start Address as the
P/E.C. increments the address location.If any
address that is not in the same block as the
Start Address is given, the Program and Verify
Phase terminates. Status Register bit SR0
should be read between each Bus Write cycle
to check that the P/E.C. is ready for the next
Word.
3. Once the Write Buffer is full, the data is programmed sequentially to the memory array.
After the program operation the device automatically verifies the data and reprograms if
necessary.
The Program and Verify phase can be repeated,
without re-issuing the command, to program additional 32 Word locations as long as the address remains in the same block.
4. Finally, after all Words, or the entire block
have been programmed, write one Bus Write
operation to any address outside the block
containing the Start Address, to terminate
Program and Verify Phase.
Status Register bit SR0 must be checked to determine whether the program operation is finished.
The Status Register may be checked for errors at
any time but it must be checked after the entire
block has been programmed.
Exit Phase. Status Register P/E.C. bit SR7 set to
‘1’ indicates that the device has exited the Buffer
Enhanced Factory Program operation and returned to Read Status Register mode. A full Status
Register check should be done to ensure that the
block has been successfully programmed. See the
section on the Status Register for more details.
17/83
M30L0R8000T0, M30L0R8000B0
For optimum performance the Buffer Enhanced
Factory Program command should be limited to a
maximum of 100 program/erase cycles per block.
If this limit is exceeded the internal algorithm will
continue to work properly but some degradation in
performance is possible. Typical program times
are given in Table 17.
See APPENDIX C., Figure 27., Buffer Enhanced
Factory Program Flowchart and Pseudo Code, for
a suggested flowchart on using the Buffer Enhanced Factory Program command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Block Erase operation. The
command can be addressed to any bank.
The Program/Erase Resume command is required to restart the suspended operation.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6
and/ or SR2 of the Status Register will be set to ‘1’.
The following commands are accepted during Program/Erase Suspend:
– Program/Erase Resume
– Read Array (data from erase-suspended
block or program-suspended Word is not
valid)
– Read Status Register
– Read Electronic Signature
– Read CFI Query.
Additionally, if the suspended operation was a
Block Erase then the following commands are also
accepted:
– Clear Status Register
– Program (except in erase-suspended
block)
– Buffer Program (except in erase
suspended blocks)
– Block Lock
– Block Lock-Down
– Block Unlock.
During an erase suspend the block being erased
can be protected by issuing the Block Lock or
Block Lock-Down commands. When the Program/
Erase Resume command is issued the operation
will complete.
It is possible to accumulate multiple suspend operations. For example: suspend an erase operation,
start a program operation, suspend the program
operation, then read the array.
18/83
If a Program command is issued during a Block
Erase Suspend, the erase operation cannot be resumed until the program operation has completed.
The Program/Erase Suspend command does not
change the read mode of the banks. If the suspended bank was in Read Status Register, Read
Electronic signature or Read CFI Query mode the
bank remains in that mode and outputs the corresponding data.
Refer to Dual Operations section for detailed information about simultaneous operations allowed
during Program/Erase Suspend.
During a Program/Erase Suspend, the device can
be placed in standby mode by taking Chip Enable
to VIH. Program/erase is aborted if Reset, RP,
goes to VIL.
See APPENDIX C., Figure 22., Program Suspend
& Resume Flowchart and Pseudo Code, and Figure 24., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Program/Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command is used to
restart the program or erase operation suspended
by the Program/Erase Suspend command. One
Bus Write cycle is required to issue the command.
The command can be issued to any address.
The Program/Erase Resume command does not
change the read mode of the banks. If the suspended bank was in Read Status Register, Read
Electronic signature or Read CFI Query mode the
bank remains in that mode and outputs the corresponding data.
If a Program command is issued during a Block
Erase Suspend, then the erase cannot be resumed until the program operation has completed.
See APPENDIX C., Figure 22., Program Suspend
& Resume Flowchart and Pseudo Code, and Figure 24., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Program/Erase Resume command.
Protection Register Program Command
The Protection Register Program command is
used to program the user One-Time-Programmable (OTP) segments of the Protection Register and
the two Protection Register Locks.
The device features 16 OTP segments of 128 bits
and one OTP segment of 64 bits, as shown in Figure 5., Protection Register Memory Map.
The segments are programmed one Word at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
M30L0R8000T0, M30L0R8000B0
Two Bus Write cycles are required to issue the
Protection Register Program command.
■
The first bus cycle sets up the Protection
Register Program command.
■
The second latches the address and data to
be programmed to the Protection Register and
starts the Program/Erase Controller.
Read operations to the bank being programmed
output the Status Register content after the program operation has started.
Attempting to program a previously protected Protection Register will result in a Status Register error.
The Protection Register Program cannot be suspended. Dual operations between the Parameter
Bank and the Protection Register memory space
are not allowed (see Table 15., Dual Operation
Limitations for details).
The two Protection Register Locks are used to
protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 5., Protection Register
Memory Map, and Figure 5., Protection Register
Memory Map, for details on the Lock bits.
See APPENDIX C., Figure 26., Protection Register Program Flowchart and Pseudo Code, for a
flowchart for using the Protection Register Program command.
Set Configuration Register Command
The Set Configuration Register command is used
to write a new value to the Configuration Register.
Two Bus Write cycles are required to issue the Set
Configuration Register command.
■
The first cycle sets up the Set Configuration
Register command and the address
corresponding to the Configuration Register
content.
■
The second cycle writes the Configuration
Register data and the confirm command.
The Configuration Register data must be written
as an address during the bus write cycles, that is
A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses
A16- A23 are ignored.
Read operations output the array content after the
Set Configuration Register command is issued.
The Read Electronic Signature command is required to read the updated contents of the Configuration Register.
Block Lock Command
The Block Lock command is used to lock a block
and prevent program or erase operations from
changing the data in it. All blocks are locked after
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
■
The first bus cycle sets up the Block Lock
command.
■
The second Bus Write cycle latches the block
address and locks the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 16. shows the Lock Status after issuing a
Block Lock command.
Once set, the Block Lock bits remain set even after
a hardware reset or power-down/power-up. They
are cleared by a Block Unlock command.
Refer to the section, Block Locking, for a detailed
explanation. See APPENDIX C., Figure
25., Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Lock command.
Block Unlock Command
The Block Unlock command is used to unlock a
block, allowing the block to be programmed or
erased.
Two Bus Write cycles are required to issue the
Block Unlock command.
■
The first bus cycle sets up the Block Unlock
command.
■
The second Bus Write cycle latches the block
address and unlocks the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 16. shows the protection status after issuing
a Block Unlock command.
Refer to the section, Block Locking, for a detailed
explanation
and
APPENDIX
C.,
Figure
25., Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Block Unlock
command.
Block Lock-Down Command
The Block Lock-Down command is used to lockdown a locked or unlocked block.
A locked-down block cannot be programmed or
erased. The lock status of a locked-down block
cannot be changed when WP is low, VIL. When
WP is high, VIH, the lock-down function is disabled
and the locked blocks can be individually unlocked
by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
■
The first bus cycle sets up the Block LockDown command.
19/83
M30L0R8000T0, M30L0R8000B0
The second Bus Write cycle latches the block
address and locks-down the block.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table 16. shows the Lock Status after issuing a Block Lock-Down command.
Refer to the section, BLOCK LOCKING, for a detailed explanation and APPENDIX C., Figure
25., Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Lock-Down
command.
■
Commands
Cycles
Table 5. Standard Commands
Bus Operations
1st Cycle
2nd Cycle
Op.
Add
Data
Op.
Add
Data
Read Array
1+
Write
BKA
FFh
Read
WA
RD
Read Status Register
1+
Write
BKA
70h
Read
BKA(2)
SRD
Read Electronic Signature
1+
Write
BKA
90h
Read
BKA(2)
ESD
Read CFI Query
1+
Write
BKA
98h
Read
BKA(2)
QD
Clear Status Register
1
Write
BKA
50h
Block Erase
2
Write
BKA or
BA(3)
20h
Write
BA
D0h
Program
2
Write
BKA or
WA(3)
40h or 10h
Write
WA
PD
Write
BA
E8h
Write
BA
n
Write
PA1
PD1
Write
PA2
PD2
Write
PAn+1
PDn+1
Write
X
D0h
Buffer Program
n+4
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Protection Register Program
2
Write
PRA
C0h
Write
PRA
PRD
Set Configuration Register
2
Write
CRD
60h
Write
CRD
03h
Block Lock
2
Write
BKA or
BA(3)
60h
Write
BA
01h
Block Unlock
2
Write
BKA or
BA(3)
60h
Write
BA
D0h
Block Lock-Down
2
Write
BKA or
BA(3)
60h
Write
BA
2Fh
Note: 1. X = Don't Care, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature
Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address,
PRD = Protection Register Data, CRD = Configuration Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.
3. Any address within the bank can be used.
4. n+1 is the number of Words to be programmed.
20/83
M30L0R8000T0, M30L0R8000B0
Table 6. Factory Program Command
Phase
Setup
Buffer
Enhanced Program/
Factory
Verify(3))
Program
Exit
Note: 1.
2.
3.
4.
Cycles
Command
Bus Write Operations
1st
2nd
3rd
Add
Data
Add
Data Add
2
BKA or
WA(4)
80h
WA1
D0h
≥32
WA1
PD1
WA1
PD2
1
NOT
BA1(2)
X
WA1
Final -1
Final
Data
Add
Data
Add
Data
PD3
WA1
PD31
WA1
PD32
WA = Word Address in targeted bank, BKA= Bank Address, PD = Program Data, BA = Block Address, X = Don’t Care.
WA1 is the Start Address, NOT BA1 = Not Block Address of WA1.
The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block.
Any address within the bank can be used.
Table 7. Electronic Signature Codes
Code
Manufacturer Code
Address (h)
Data (h)
Bank Address + 00
0020
Top
Bank Address + 01
880D
Bottom
Bank Address + 01
880E
Device Code
Locked
0001
Unlocked
Block Protection
Locked and Locked-Down
0003
Unlocked and Locked-Down
0002
Configuration Register
Protection Register PR0
Lock
0000
Block Address + 02
Bank Address + 05
ST Factory Default
CR
0002
Bank Address + 80
OTP Area Permanently Locked
0000
Bank Address + 81
Bank Address + 84
Unique Device
Number
Bank Address + 85
Bank Address + 88
OTP Area
Protection Register PR1 through PR16 Lock
Bank Address + 89
PRLD
Protection Registers PR1-PR16
Bank Address + 8A
Bank Address + 109
OTP Area
Protection Register PR0
Note: CR = Configuration Register, PRLD = Protection Register Lock Data.
21/83
M30L0R8000T0, M30L0R8000B0
Figure 5. Protection Register Memory Map
PROTECTION REGISTERS
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah
Protection Register Lock 89h
88h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR0
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
1 0
AI07563
22/83
M30L0R8000T0, M30L0R8000B0
Table 8. Protection Register Locks
Lock
Description
Lock 1
Address
80h
Bits
Bit 0
preprogrammed to protect Unique Device Number, address 81h to
84h in PR0
Bit 1
protects 64bits of OTP segment, address 85h to 88h in PR0
Bits 2 to 15
89h
Bit 0
protects 128bits of OTP segment PR1
Bit 1
protects 128bits of OTP segment PR2
Bit 2
protects 128bits of OTP segment PR3
----
Lock 2
reserved
----
Number
Bit 13
protects 128bits of OTP segment PR14
Bit 14
protects 128bits of OTP segment PR15
Bit 15
protects 128bits of OTP segment PR16
23/83
M30L0R8000T0, M30L0R8000B0
STATUS REGISTER
The Status Register provides information on the
current or previous program or erase operations.
Issue a Read Status Register command to read
the contents of the Status Register, refer to Read
Status Register Command section for more details. To output the contents, the Status Register is
latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be
read until Chip Enable or Output Enable returns to
VIH. The Status Register can only be read using
single Asynchronous or Single Synchronous
reads. Bus Read operations from any address
within the bank, always read the Status Register
during program and erase operations.
The various bits convey information about the status and any errors of the operation. Bits SR7, SR6,
SR2 and SR0 give information on the status of the
device and are set and reset by the device. Bits
SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset
by issuing a Clear Status Register command or a
hardware reset. If an error bit is set to ‘1’ the Status
Register should be reset before issuing another
command.
The bits in the Status Register are summarized in
Table 9., Status Register Bits. Refer to Table 9. in
conjunction with the following text descriptions.
plete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.
Erase Status Bit (SR5). The Erase Status bit is
used to identify if there was an error during a block
or bank erase operation. When the Erase Status
bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to
the block or bank and still failed to verify that it has
erased correctly.
The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/
Erase Controller inactive).
Once set High, the Erase Status bit must be set
Low by a Clear Status Register command or a
hardware reset before a new erase command is issued, otherwise the new command will appear to
fail.
Program/Erase Controller Status Bit (SR7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive in any bank.
When the Program/Erase Controller Status bit is
Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device
is ready to process a new command.
The Program/Erase Controller Status bit is Low
immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller pauses the bit is High.
Program Status Bit (SR4). The Program Status
bit is used to identify if there was an error during a
program operation.
The Program Status bit should be read once the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
When the Program Status bit is High (set to ‘1’),
the Program/Erase Controller has applied the
maximum number of pulses to the Word and still
failed to verify that it has programmed correctly.
Attempting to program a '1' to an already programmed bit while VPP = VPPH will also set the
Program Status bit High. If VPP is different from
VPPH, SR4 remains Low (set to '0') and the attempt
is not shown.
Once set High, the Program Status bit must be set
Low by a Clear Status Register command or a
hardware reset before a new program command is
issued, otherwise the new command will appear to
fail.
Erase Suspend Status Bit (SR6). The
Erase
Suspend Status bit indicates that an erase operation has been suspended in the addressed block.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Program/Erase Resume command.
The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller
Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend Latency
time of the Program/Erase Suspend command being issued therefore the memory may still com-
VPP Status Bit (SR3). The VPP Status bit is used
to identify an invalid voltage on the VPP pin during
program and erase operations. The VPP pin is only
sampled at the beginning of a program or erase
operation. Program and erase operations are not
guaranteed if VPP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage.
when the VPP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the VPP Lockout
Voltage, VPPLK, the memory is protected and program and erase operations cannot be performed.
24/83
M30L0R8000T0, M30L0R8000B0
Once set High, the VPP Status bit must be set Low
by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will
appear to fail.
Once set High, the Block Protection Status bit
must be set Low by a Clear Status Register command or a hardware reset before a new program
or erase command is issued, otherwise the new
command will appear to fail.
Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a program
operation has been suspended in the addressed
block. The Program Suspend Status bit should
only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive).
When the Program Suspend Status bit is High (set
to ‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Program/Erase Resume command.
SR2 is set within the Program Suspend Latency
time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.
Bank Write/Multiple Word Program Status Bit
(SR0). The Bank Write Status bit indicates whether the addressed bank is programming or erasing.
In Buffer Enhanced Factory Program mode the
Multiple Word Program bit shows if the device is
ready to accept a new Word to be programmed to
the memory array.
The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to ‘0’).
When both the Program/Erase Controller Status bit
and the Bank Write Status bit are Low (set to ‘0’),
the addressed bank is executing a program or
erase operation. When the Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank
Write Status bit is High (set to ‘1’), a program or
erase operation is being executed in a bank other
than the one being addressed.
In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’),
the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to ‘1’) the
device is not ready for the next Word.
For further details on how to use the Status Register, see the Flowcharts and Pseudo codes provided in APPENDIX C.
Block Protection Status Bit (SR1). The Block
Protection Status bit is used to identify if a Program or Block Erase operation has tried to modify
the contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a program or erase operation has been attempted on a locked block.
25/83
M30L0R8000T0, M30L0R8000B0
Table 9. Status Register Bits
Bit
SR7
SR6
SR5
SR4
SR3
SR2
SR1
Name
P/E.C. Status
Erase Suspend Status
Erase Status
Program Status
VPP Status
Type
Logic Level
Definition
'1'
Ready
'0'
Busy
'1'
Erase Suspended
'0'
Erase In progress or Completed
'1'
Erase Error
'0'
Erase Success
'1'
Program Error
'0'
Program Success
'1'
VPP Invalid, Abort
'0'
VPP OK
'1'
Program Suspended
'0'
Program In Progress or Completed
'1'
Program/Erase on protected Block, Abort
'0'
No operation to protected blocks
Status
Status
Error
Error
Error
Program Suspend Status Status
Block Protection Status
Error
SR7 = ‘1’ Not Allowed
'1'
SR7 = ‘0’
Bank Write Status
Status
Program or erase operation in a bank other than
the addressed bank
SR7 = ‘1’ No Program or erase operation in the device
'0'
SR7 = ‘0’ Program or erase operation in addressed bank
SR0
SR7 = ‘1’ Not Allowed
Multiple Word Program
Status (Enhanced
Factory Program mode)
'1'
SR7 = ‘0’
SR7 = ‘1’ the device is exiting from BEFP
'0'
SR7 = ‘0’
Note: Logic level '1' is High, '0' is Low.
26/83
the device is NOT ready for the next Word
Status
the device is ready for the next Word
M30L0R8000T0, M30L0R8000B0
CONFIGURATION REGISTER
The Configuration Register is used to configure
the type of bus access that the memory will perform. Refer to Read Modes section for details on
read operations.
The Configuration Register is set through the
Command Interface using the Set Configuration
Register command. After a reset or power-up the
device is configured for asynchronous read (CR15
= 1). The Configuration Register bits are described
in Table 11. They specify the selection of the burst
length, burst type, burst X latency and the read operation. Refer to Figures 6 and 7 for examples of
synchronous burst configurations.
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations.
When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit
is set to ’0’, read operations are synchronous.
Synchronous Burst Read is supported in both parameter and main blocks and can be performed
across banks.
On reset or power-up the Read Select bit is set to
’1’ for asynchronous access.
Wait signal indicates whether the data output are
valid or a WAIT state must be inserted.
When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is set
to ‘1’ the Wait signal is active High.
Data Output Configuration Bit (CR9)
The Data Output Configuration bit is used to configure the output to remain valid for either one or
two clock cycles during synchronous mode.
When the Data Output Configuration Bit is ’0’ the
output data is valid for one clock cycle, when the
Data Output Configuration Bit is ’1’ the output data
is valid for two clock cycles.
The Data Output Configuration must be configured using the following condition:
■
tK > tKQV + tQVK_CPU
where
■
tK is the clock period
■
tQVK_CPU is the data setup time required by
the system CPU
■
tKQV is the clock to data valid time.
If this condition is not satisfied, the Data Output
Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6., X-Latency and Data Output Configuration Example.
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available (refer to Figure 6., X-Latency and Data Output Configuration Example.).
For correct operation the X-Latency bits can only
assume the values in Table 11., Configuration
Register.
Table 10. shows how to set the X-Latency parameter, taking into account the frequency used to
read the Flash memory in Synchronous mode.
Wait Configuration Bit (CR8)
Table 10. X-Latency Settings
Burst Type Bit (CR7)
fmax
tKmin
X-Latency (Min)
30MHz
33ns
3
40MHz
25ns
4
54MHz
19ns
5
The Wait Configuration bit is used to control the
timing of the Wait output pin, WAIT, in Synchronous Burst Read mode.
When WAIT is asserted, Data is Not Valid and
when WAIT is de-asserted, Data is Valid.
When the Wait Configuration bit is Low (set to ’0’)
the Wait output pin is asserted during the WAIT
state. When the Wait Configuration bit is High (set
to ’1’), the Wait output pin is asserted one data cycle before the WAIT state.
The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads.
The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses only.
See Table 12., Burst Type Definition, for the sequence of addresses output from a given starting
address in sequential mode.
Wait Polarity Bit (CR10)
The Wait Polarity bit is used to set the polarity of
the Wait signal used in Synchronous Burst Read
mode. During Synchronous Burst Read mode the
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during syn-
27/83
M30L0R8000T0, M30L0R8000B0
chronous read operations. When the
Edge bit is Low (set to ’0’) the falling
Clock is the active edge. When the
Edge bit is High (set to ’1’) the rising
Clock is the active edge.
Valid
edge
Valid
edge
Clock
of the
Clock
of the
Wrap Burst Bit (CR3)
The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst
reads can be confined inside the 4, 8 or 16 Word
boundary (wrap) or overcome the boundary (no
wrap).
When the Wrap Burst bit is Low (set to ‘0’) the
burst read wraps. When it is High (set to ‘1’) the
burst read does not wrap.
Burst length Bits (CR2-CR0)
The Burst Length bits are used to set the number
of Words to be output during a Synchronous Burst
Read operation as result of a single address latch
cycle.
28/83
They can be set for 4 Words, 8 Words, 16 Words
or continuous burst, where all the Words are read
sequentially. In continuous burst mode the burst
sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16 Words nowrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output.
If the starting address is aligned to an 8 Word
boundary no WAIT states are needed and the
WAIT output is not asserted.
If the starting address is not aligned to the 8 Word
boundary, WAIT will be asserted when the burst
sequence crosses the first 16 Word boundary to
indicate that the device needs an internal delay to
read the successive Words in the array.
WAIT will be asserted only once during a continuous burst access. See also Table 12., Burst Type
Definition.
CR14, CR5 and CR4 are reserved for future use.
M30L0R8000T0, M30L0R8000B0
Table 11. Configuration Register
Bit
CR15
CR14
CR13-CR11
Description
Value
Description
0
Synchronous Read
1
Asynchronous Read (Default at power-on)
010
2 clock latency(1)
011
3 clock latency
100
4 clock latency
101
5 clock latency
110
6 clock latency
111
7 clock latency (default)
Read Select
Reserved
X-Latency
Other configurations reserved
CR10
CR9
CR8
CR7
CR6
CR5-CR4
CR3
CR2-CR0
0
WAIT is active Low
1
WAIT is active high (default)
0
Data held for one clock cycle
1
Data held for two clock cycles (default)1
0
WAIT is active during WAIT state
1
WAIT is active one data cycle before WAIT state (default)1
0
Reserved
1
Sequential (default)
0
Falling Clock edge
1
Rising Clock edge (default)
0
Wrap
1
No Wrap (default)
001
4 Words
010
8 Words
011
16 Words
111
Continuous (default)
Wait Polarity
Data Output
Configuration
Wait Configuration
Burst Type
Valid Clock Edge
Reserved
Wrap Burst
Burst Length
Note: 1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.
29/83
M30L0R8000T0, M30L0R8000B0
Mode
Table 12. Burst Type Definition
Sequential
Start
Add.
4 Words
8 Words
16 Words
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6...
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-4-5-6-7...
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-5-6-7-8...
3
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-6-7-8-9...
7-4-5-6
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13...
Continuous Burst
Wrap
...
7
...
12
12-13-14-15
12-13-14-15-8-9-10-11 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11
12-13-14-15-16-17...
13
13-14-15-12
13-14-15-8-9-10-11-12 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12
13-14-15-16-17-18...
14
14-15-12-13
14-15-8-9-10-11-12-13 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-17-18-19...
15
15-12-13-14
15-8-9-10-11-12-13-14 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17-18-19-20...
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8--9-10-11-12-13-14-1516
2
2-3-4-5
2-3-4-5-6-7-8-9...
2-3-4-5--6-7-8-9-10-11-12-13-14-1516-17
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-1617-18
7-8-9-10
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-15-16-17-18-1920-21-22
12
12-13-14-15
12-13-14-15-16-17-1819
12-13-14-15-16-17-18-19-20-21-2223-24-25-26-27
13
13-14-15-16
13-14-15-16-17-18-1920
13-14-15-16-17-18-19-20-21-22-2324-25-26-27-28
14
14-15-16-17
14-15-16-17-18-19-2021
14-15-16-17-18-19-20-21-22-23-2425-26-27-28-29
15
15-16-17-18
15-16-17-18-19-20-2122
15-16-17-18-19-20-21-22-23-24-2526-27-28-29-30
No-wrap
...
30/83
7
...
Same as for Wrap
(Wrap /No Wrap
has no effect on
Continuous Burst)
M30L0R8000T0, M30L0R8000B0
Figure 6. X-Latency and Data Output Configuration Example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
A23-A0
VALID ADDRESS
tQVK_CPU
tK
tKQV
DQ15-DQ0
VALID DATA VALID DATA
Ai11050
Note: 1. The settings shown are X-latency = 4, Data Output held for one clock cycle.
31/83
M30L0R8000T0, M30L0R8000B0
Figure 7. Wait Configuration Example
E
K
L
A23-A0
DQ15-DQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
AI10598
32/83
M30L0R8000T0, M30L0R8000B0
READ MODES
Read operations can be performed in two different
ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for
the data output, the read operation is asynchronous; if the data output is synchronized with clock,
the read operation is synchronous.
The read mode and format of the data output are
determined by the Configuration Register. (See
Configuration Register section for details). All
banks support both asynchronous and synchronous read operations.
Asynchronous Read Mode
In Asynchronous Read operations the clock signal
is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash
Interface or Electronic Signature depending on the
command issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations.
Asynchronous Read operations can be performed
in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only
Asynchronous Page Read takes full advantage of
the internal page storage so different timings are
applied.
In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The
Page has a size of 8 Words and is addressed by
address inputs A0, A1 and A2.
The first read operation within the Page has a
longer access time (tAVQV, Random access time),
subsequent reads within the same Page have
much shorter access times (tAVQV1, Page access
time). If the Page changes then the normal, longer
timings apply again.
The device features an Automatic Standby mode.
During Asynchronous Read operations, after a
bus inactivity of 150ns, the device automatically
switches to the Automatic Standby mode. In this
condition the power consumption is reduced to the
standby value and the outputs are still driven.
In Asynchronous Read mode, the WAIT signal is
always de-asserted.
See Table 23., Asynchronous Read AC Characteristics, Figure 10., Asynchronous Random Access Read AC Waveforms, and Figure
11., Asynchronous Page Read AC Waveforms, for
details.
Synchronous Burst Read Mode
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank
boundaries.
Synchronous Burst Read mode can only be used
to read the memory array. For other read operations, such as Read Status Register, Read CFI
and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access
Read must be used.
In Synchronous Burst Read mode the flow of the
data output depends on parameters that are configured in the Configuration Register.
A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit
CR6 in the Configuration Register) after the falling
edge of Latch Enable or Chip Enable, whichever
occurs last. Addresses are internally incremented
and data is output on each data cycle after a delay
which depends on the X latency bits CR13-CR11
of the Configuration Register.
The number of Words to be output during a Synchronous Burst Read operation can be configured
as 4 Words, 8 Words, 16 Words or Continuous
(Burst Length bits CR2-CR0). The data can be
configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9).
The order of the data output can be modified
through the Wrap Burst bit in the Configuration
Register. The burst sequence is sequential and
can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap).
The WAIT signal may be asserted to indicate to
the system that an output delay will occur. This delay will depend on the starting address of the burst
sequence and on the burst configuration.
WAIT is asserted during the X latency, the WAIT
state and at the end of a 4, 8 and 16 Word burst. It
is only de-asserted when output data are valid. In
Continuous Burst Read mode a WAIT state will occur when crossing the first 16 Word boundary. If
the starting address is aligned to the Burst Length
(4, 8 or 16 Words) the wrapped configuration has
no impact on the output sequence.
The WAIT signal can be configured to be active
Low or active High by setting CR10 in the Configuration Register.
See Table 24., Synchronous Read AC Characteristics, and Figure 12., Synchronous Burst Read
AC Waveforms, for details.
33/83
M30L0R8000T0, M30L0R8000B0
Synchronous Burst Read Suspend. A
Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority
devices. It can be suspended during the initial access latency time (before data is output) in which
case the initial latency time can be reduced to zero, or after the device has output data. When the
Synchronous Burst Read operation is suspended,
internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often
as required as long as the operating conditions of
the device are met.
A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the current
address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output
Enable, G, goes High.
When Output Enable, G, becomes Low again and
the Clock signal restarts, the Synchronous Burst
Read operation is resumed exactly where it
stopped.
34/83
WAIT will revert to high-impedance when Output
Enable, G, or Chip Enable, E, goes High.
See Table 24., Synchronous Read AC Characteristics, and Figure 14., Synchronous Burst Read
Suspend AC Waveforms, for details.
Single Synchronous Read Mode
Single Synchronous Read operations are similar
to Synchronous Burst Read operations except that
the memory outputs the same data to the end of
the operation.
Synchronous Single Reads are used to read the
Electronic Signature, Status Register, CFI, Block
Protection Status, Configuration Register Status
or Protection Register. When the addressed bank
is in Read CFI, Read Status Register or Read
Electronic Signature mode, the WAIT signal is asserted during the X latency, the WAIT state and at
the end of a 4, 8 and 16 Word burst. It is only deasserted when output data are valid.
See Table 24., Synchronous Read AC Characteristics, and Figure 12., Synchronous Burst Read
AC Waveforms, for details.
M30L0R8000T0, M30L0R8000B0
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Multiple Bank Architecture of the
M30L0R8000x0 gives greater flexibility for software developers to split the code and data spaces
within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one
bank while another bank is being programmed or
erased.
The Dual Operations feature means that while programming or erasing in one bank, read operations
are possible in another bank with zero latency
(only one bank at a time is allowed to be in program or erase mode).
If a read operation is required in a bank, which is
programming or erasing, the program or erase operation can be suspended.
Also if the suspended operation was erase then a
program command can be issued to another
block, so the device can have one block in Erase
Suspend mode, one programming and other
banks in read mode.
Bus Read operations are allowed in another bank
between setup and confirm cycles of program or
erase operations.
By using a combination of these features, read operations are possible at any moment in the
M30L0R8000x0 device.
Dual operations between the Parameter Bank and
either of the CFI, the OTP or the Electronic Signature memory space are not allowed. Table 15.
shows which dual operations are allowed or not
between the CFI, the OTP, the Electronic Signature locations and the memory array.
Tables 13 and 14 show the dual operations possible in other banks and in the same bank.
Table 13. Dual Operations Allowed In Other Banks
Commands allowed in another bank
Read
Array
Read
Status
Register
Read
CFI
Query
Read
Electronic
Signature
Program,
Buffer Program
Block
Erase
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
Yes
Yes
Yes
Yes
–
–
Yes
–
Erasing
Yes
Yes
Yes
Yes
–
–
Yes
–
Program Suspended
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase Suspended
Yes
Yes
Yes
Yes
Yes
–
–
Yes
Status of bank
Program/ Program/
Erase
Erase
Suspend Resume
Table 14. Dual Operations Allowed In Same Bank
Commands allowed in same bank
Status of bank
Read
Array
Read
Read
Read
Status
Electronic
CFI Query
Register
Signature
Program,
Buffer
Program
Block
Erase
Program/ Program/
Erase
Erase
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
–(2)
Yes
Yes
Yes
–
–
Yes
–
Erasing
–(2)
Yes
Yes
Yes
–
–
Yes
–
Program Suspended
Yes(1)
Yes
Yes
Yes
–
–
–
Yes
Erase Suspended
Yes(1)
Yes
Yes
Yes
Yes(1)
–
–
Yes
Note: 1. Not allowed in the Word that is being erased or programmed.
2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
35/83
M30L0R8000T0, M30L0R8000B0
Table 15. Dual Operation Limitations
Commands allowed
Current Status
Read Main Blocks
Read CFI / OTP /
Electronic Signature
Read Parameter
Blocks
No
Located in
Parameter
Bank
Not Located in
Parameter
Bank
Programming / Erasing
Parameter Blocks
Programming /
Erasing Main
Blocks
Programming OTP
Located in
Parameter Bank
Not Located in
Parameter Bank
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
In Different Bank
Only
No
No
No
No
BLOCK LOCKING
The M30L0R8000x0 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.
■
Lock/Unlock - this first level allows software
only control of block locking.
■
■
Lock-Down - this second level requires
hardware interaction before locking can be
changed.
VPP ≤ VPPLK - the third level offers a complete
hardware protection against program and
erase on all blocks.
The protection status of each block can be set to
Locked, Unlocked, and Locked-Down. Table 16.,
defines all of the possible protection states (WP,
DQ1, DQ0), and APPENDIX C., Figure 25., shows
a flowchart for the locking operations.
Reading a Block’s Lock Status
The lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode issue the Read Electronic Signature command. Subsequent reads at the address
specified in Table 7., will output the protection status of that block.
The lock status is represented by DQ0 and DQ1.
DQ0 indicates the Block Lock/Unlock status and is
set by the Lock command and cleared by the Unlock command. DQ0 is automatically set when entering Lock-Down. DQ1 indicates the Lock-Down
status and is set by the Lock-Down command.
DQ1 cannot be cleared by software, only by a
hardware reset or power-down.
36/83
The following sections explain the operation of the
locking system.
Locked State
The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
program or erase operations. Any program or
erase operations attempted on a locked block will
return an error in the Status Register. The Status
of a Locked block can be changed to Unlocked or
Locked-Down using the appropriate software
commands. An Unlocked block can be Locked by
issuing the Lock command.
Unlocked State
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be unlocked by issuing the Unlock command.
Lock-Down State
Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status cannot be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the
device is reset or powered-down.
M30L0R8000T0, M30L0R8000B0
The Lock-Down function is dependent on the Write
Protect, WP, input pin.
When WP=0 (VIL), the blocks in the Lock-Down
state (0,1,x) are protected from program, erase
and protection status changes.
When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing
the software command, where they can be erased
and programmed.
When the Lock-Down function is disabled (WP=1)
blocks can be locked (1,1,1) and unlocked (1,1,0)
as desired. When WP=0 blocks that were previously Locked-Down return to the Lock-Down state
(0,1,x) regardless of any changes that were made
while WP=1.
Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state.
Locking Operations During Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command, then
check the Status Register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After completing any desired lock, read, or program operations,
resume the erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operations cannot be performed during a
program suspend.
Table 16. Lock Status
Current
Protection Status(1)
(WP, DQ1, DQ0)
Next Protection Status(1)
(WP, DQ1, DQ0)
Current State
Program/Erase
Allowed
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
After
WP transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
1,0,1(2)
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
0,0,1(2)
no
0,0,1
0,0,0
0,1,1
1,0,1
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
37/83
M30L0R8000T0, M30L0R8000B0
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of
Program/ Erase cycles per block are shown in Table 17. Exact erase times may change depending
on the memory array condition. The best case is
when all the bits in the block are at ‘0’ (pre-programmed). The worst case is when all the bits in
the block are at ‘1’ (not preprogrammed). Usually,
the system overhead is negligible with respect to
the erase time. In the M30L0R8000x0 the maximum number of Program/Erase cycles depends
on the VPP voltage supply used.
Table 17. Program/Erase Times and Endurance Cycles
Parameter
Condition
Min
Parameter Block (16 KWord)
Erase
VPP = VDD
Unit
0.4
1
2.5
s
1
3
4
s
4
s
Word Program
30
60
µs
Buffer Program
30
60
µs
Word Program
90
180
µs
Buffer Program
90
180
µs
Buffer (32 Words) (Buffer Program)
440
880
µs
Main Block (64 KWord) (Buffer Program)
880
Single Word
ms
Suspend
Latency
Program
20
25
µs
Erase
20
25
µs
Program/
Erase Cycles
(per Block)
Main Blocks
100,000
cycles
Parameter Blocks
100,000
cycles
Erase
Parameter Block (16 KWord)
Main Block (64 KWord)
Single Cell
Single Word
VPP = VPPH
Max
1.2
SIngle Cell
Program(3)
Typical
after
100kW/E
Cycles
Not Preprogrammed
Main Block (64 KWord)
Preprogrammed
Typ
Buffer (32 Words)
Program(3)
Program/
Erase Cycles
(per Block)
Note: 1.
2.
3.
4.
38/83
2.5
s
1
4
s
Word Program
30
60
µs
Word Program
85
170
µs
Buffer Enhanced Factory
Program(4)
10
µs
Buffer Program
340
Buffer Enhanced Factory
Program
320
µs
640
ms
640
ms
Buffer Program
10
s
Buffer Enhanced Factory
Program
10
s
Buffer Program
Main Block (64 KWords) Buffer Enhanced Factory
Program
Bank (16 Mbits)
0.4
680
µs
Main Blocks
1000
cycles
Parameter Blocks
2500
cycles
TA = –25 to 85°C; VDD = 1.7V to 2V; VDDQ = 1.7V to 2V.
Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution).
Excludes the time needed to execute the command sequence.
This is an average value on the entire device.
M30L0R8000T0, M30L0R8000B0
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 18. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
Ambient Operating Temperature
–25
85
°C
TBIAS
Temperature Under Bias
–25
85
°C
TSTG
Storage Temperature
–65
125
°C
TLEAD
Lead Temperature During Soldering
(1)
°C
TA
VIO
Input or Output Voltage
–0.5
3.8
V
VDD
Supply Voltage
–0.2
2.5
V
Input/Output Supply Voltage
–0.2
2.5
V
Program Voltage
–0.2
12.6
V
Output Short Circuit Current
100
mA
Time for VPP at VPPH
100
hours
VDDQ
VPP
IO
tVPPH
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
39/83
M30L0R8000T0, M30L0R8000B0
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 19., Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when relying on the quoted parameters.
Table 19. Operating and AC Measurement Conditions
M30L0R8000T0/B
Parameter
85
Units
Min
Max
VDD Supply Voltage
1.7
2.0
V
VDDQ Supply Voltage
1.7
2.0
V
VPP Supply Voltage (Factory environment)
8.5
9.5
V
VPP Supply Voltage (Application environment)
–0.4
VDDQ+0.4
V
Ambient Operating Temperature
–25
85
°C
Load Capacitance (CL)
30
Input Rise and Fall Times
pF
5
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 8. AC Measurement I/O Waveform
ns
0 to VDDQ
V
VDDQ/2
V
Figure 9. AC Measurement Load Circuit
VDDQ
VDDQ
VDDQ
VDDQ/2
VDD
0V
16.7kΩ
AI06161
DEVICE
UNDER
TEST
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
AI06162
Table 20. Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
40/83
Test Condition
Min
Max
Unit
VIN = 0V
6
8
pF
VOUT = 0V
8
12
pF
M30L0R8000T0, M30L0R8000B0
Table 21. DC Characteristics - Currents
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
Supply Current
Asynchronous Read (f=5MHz)
IDD1
Supply Current
Synchronous Read (f=54MHz)
Test Condition
Typ
Max
Unit
0V ≤ VIN ≤ VDDQ
±1
µA
0V ≤ VOUT ≤ VDDQ
±1
µA
E = VIL, G = VIH
13
15
mA
4 Word
16
18
mA
8 Word
18
20
mA
16 Word
23
25
mA
Continuous
25
27
mA
IDD2
Supply Current
(Reset)
RP = VSS ± 0.2V
50
110
µA
IDD3
Supply Current (Standby)
E = VDDQ ± 0.2V
K=Vss
50
110
µA
IDD4
Supply Current (Automatic Standby)
E = VIL, G = VIH
50
110
µA
VPP = VPPH
8
20
mA
VPP = VDD
10
25
mA
VPP = VPPH
8
20
mA
VPP = VDD
10
25
mA
Program/Erase in one Bank,
Asynchronous Read in another
Bank
23
40
mA
Program/Erase in one Bank,
Synchronous Read (Continuous
f=54MHz) in another Bank
35
52
mA
E = VDDQ ± 0.2V
K=Vss
50
110
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP Supply Current (Read)
VPP ≤ VDD
0.2
5
µA
VPP Supply Current (Standby)
VPP ≤ VDD
0.2
5
µA
Supply Current (Program)
IDD5 (1)
Supply Current (Erase)
Supply Current
IDD6 (1,2) (Dual Operations)
IDD7(1)
Supply Current Program/ Erase
Suspended (Standby)
VPP Supply Current (Program)
IPP1(1)
VPP Supply Current (Erase)
IPP2
IPP3(1)
Note: 1. Sampled only, not 100% tested.
2. VDD Dual Operation current is the sum of read and program or erase currents.
41/83
M30L0R8000T0, M30L0R8000B0
Table 22. DC Characteristics - Voltages
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VIL
Input Low Voltage
0
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
IOH = –100µA
VDDQ –0.1
VPP1
VPP Program Voltage-Logic
Program, Erase
1.3
1.8
3.3
V
VPPH
VPP Program Voltage Factory
Program, Erase
8.5
9.0
9.5
V
VPPLK
Program or Erase Lockout
0.4
V
VLKO
VDD Lock Voltage
1
V
VRPH
RP pin Extended High Voltage
3.3
V
42/83
V
M30L0R8000T0, M30L0R8000B0
Figure 10. Asynchronous Random Access Read AC Waveforms
tAVAV
A0-A23
VALID
VALID
tAVLH
tAXQX
tLHAX
tAVQV
L(1)
tLLLH
tLLQV
tELLH
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGHQX
tGLQV
tGHQZ
tGLQX
DQ0-DQ15
Hi-Z
VALID
tGLTV
tEHTZ
tELTV
WAIT(2)
tGHTZ
Hi-Z
AI10590
Note: 1. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2. Write Enable, W, is High, WAIT is active Low.
43/83
44/83
Hi-Z
tAVAV
VALID ADDRESS
tELQV
Valid Address Latch
tGLQX
tGLQV
tELTV
tGLTV
tELQX
tELLH
tLLQV
tLLLH
tAVLH
Note 1. WAIT is active Low.
DQ0-DQ15
WAIT (1)
G
E
L
A0-A2
A3-A23
Enabled
Outputs
tLHAX
VALID
DATA
VALID
DATA
tAVQV1
VALID
DATA
VALID
DATA
Valid Data
VALID
DATA
VALID
DATA
VALID
DATA
VALID
DATA
VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD.
VALID ADDRESS
AI08907b
Standby
M30L0R8000T0, M30L0R8000B0
Figure 11. Asynchronous Page Read AC Waveforms
M30L0R8000T0, M30L0R8000B0
Table 23. Asynchronous Read AC Characteristics
Symbol
Alt
Read Timings
85
Unit
tAVAV
tRC
Address Valid to Next Address Valid
Min
85
ns
tAVQV
tACC
Address Valid to Output Valid (Random)
Max
85
ns
tAVQV1
tPAGE
Address Valid to Output Valid (Page)
Max
25
ns
tAXQX (1)
tOH
Address Transition to Output Transition
Min
0
ns
Chip Enable Low to Wait Valid
Max
14
ns
tELTV
tELQV (2)
tCE
Chip Enable Low to Output Valid
Max
85
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
Min
0
ns
Chip Enable High to Wait Hi-Z
Max
14
ns
tEHTZ
(1)
tOH
Chip Enable High to Output Transition
Min
2
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
Max
14
ns
tGLQV (2)
tOE
Output Enable Low to Output Valid
Max
20
ns
tGLQX (1)
tOLZ
Output Enable Low to Output Transition
Min
0
ns
Output Enable Low to Wait Valid
Max
14
ns
tEHQX
tGLTV
tGHQX (1)
tOH
Output Enable High to Output Transition
Min
2
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
Max
14
ns
Output Enable High to Wait Hi-Z
Max
14
ns
tGHTZ
Latch Timings
M30L0R8000T0/B
Parameter
tAVLH
tAVADVH
Address Valid to Latch Enable High
Min
7
ns
tELLH
tELADVH
Chip Enable Low to Latch Enable High
Min
10
ns
tLHAX
tADVHAX
Latch Enable High to Address Transition
Min
7
ns
Min
7
ns
Max
85
ns
tLLLH
tLLQV
tADVLADVH Latch Enable Pulse Width
tADVLQV
Latch Enable Low to Output Valid (Random)
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
45/83
46/83
Hi-Z
tELKH
Hi-Z
tLLLH
Address
Latch
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
X Latency
tGLTV
tGLQX
Note 2
Note 1
VALID
Valid Data Flow
tKHTV
tKHQV
VALID
Note 2
tKHTX
tKHQX
VALID
Boundary
Crossing
Note 2
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
WAIT
G
E
K(4)
L
A0-A23
DQ0-DQ15
Data
Valid
tGHQZ
tGHQX
AI10591
Standby
tEHTZ
tEHQZ
tEHQX
tEHEL
VALID
M30L0R8000T0, M30L0R8000B0
Figure 12. Synchronous Burst Read AC Waveforms
M30L0R8000T0, M30L0R8000B0
Figure 13. Single Synchronous Read AC Waveforms
A0-A23
VALID ADDRESS
tAVKH
L
tLLKH
K(2)
tELKH
tKHQV
tELQV
E
tGLQV
tGLQX
G
tELQX
DQ0-DQ15
tGHTZ
Hi-Z
VALID
tKHTV
tGLTV
WAIT(1,2)
Hi-Z
Ai11053
Note: 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one.
47/83
48/83
tELKH
Hi-Z
Hi-Z
tLLLH
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
tGLTV
tGLQV
tGLQX
Note 1
tKHQV
VALID
VALID
tGHTZ
tGHQZ
Note 3
tGLTV
tGLQV
tGHQZ
tGHQX
tEHEL
tEHQZ
AI08910
tEHTZ
NOT VALID
tEHQX
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. The CLOCK signal can be held high or low
4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.
Here, the active edge is the rising one.
WAIT(2)
G
E
K(4)
L
A0-A23
DQ0-DQ15
M30L0R8000T0, M30L0R8000B0
Figure 14. Synchronous Burst Read Suspend AC Waveforms
M30L0R8000T0, M30L0R8000B0
Figure 15. Clock input AC Waveform
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
Table 24. Synchronous Read AC Characteristics
M30L0R8000T0/B
Symbol
Alt
Parameter
Unit
Clock Specifications
Synchronous Read Timings
85
tAVKH
tAVCLKH
Address Valid to Clock High
Min
7
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
7
ns
tELTV
Chip Enable Low to Wait Valid
Max
14
ns
tEHEL
Chip Enable Pulse Width (subsequent
synchronous reads)
Min
14
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
14
ns
tKHAX
tCLKHAX
Clock High to Address Transition
Min
7
ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
14
ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
3
ns
tLLKH
tADVLCLKH
Latch Enable Low to Clock High
Min
7
ns
tKHKH
tCLK
Clock Period (f=54MHz)
Min
18.5
ns
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High
Min
4.5
ns
tf
tr
Clock Fall or Rise Time
Max
3
ns
Note: 1. Sampled only, not 100% tested.
2. For other timings please refer to Table 23., Asynchronous Read AC Characteristics.
49/83
50/83
K
VPP
WP
DQ0-DQ15
W
G
E
L
A0-A23
tWHDX
CONFIRM COMMAND
OR DATA INPUT
tVPHWH
tWHVPL
tWHWPL
tELKV
tWHEL
tWHGL
tWHAV
tWHAX
CMD or DATA
VALID ADDRESS
tAVWH
tWPHWH
tWHWL
tWHEH
tWHLL
tWLWH
tLHAX
COMMAND
tLLLH
SET-UP COMMAND
tDVWH
tGHWL
tELWL
tELLH
tAVLH
BANK ADDRESS
tAVAV
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
Ai11051
M30L0R8000T0, M30L0R8000B0
Figure 16. Write AC Waveforms, Write Enable Controlled
M30L0R8000T0, M30L0R8000B0
Table 25. Write AC Characteristics, Write Enable Controlled
M30L0R8000T0/B
Symbol
Alt
Parameter
Unit
85
tAVAV
tWC
Address Valid to Next Address Valid
Min
85
ns
tAVLH
Address Valid to Latch Enable High
Min
7
ns
tAVWH(3)
Address Valid to Write Enable High
Min
45
ns
Data Valid to Write Enable High
Min
45
ns
Chip Enable Low to Latch Enable High
Min
10
ns
Chip Enable Low to Write Enable Low
Min
0
ns
tELQV
Chip Enable Low to Output Valid
Min
85
ns
tELKV
Chip Enable High to Clock Valid
Min
7
ns
tGHWL
Output Enable High to Write Enable Low
Min
17
ns
tLHAX
Latch Enable High to Address Transition
Min
7
ns
tLLLH
Latch Enable Pulse Width
Min
7
ns
Write Enable High to Address Valid
Min
0
ns
tDVWH
tDS
tELLH
Write Enable Controlled Timings
tELWL
tCS
tWHAV(3)
tWHAX(3)
tAH
Write Enable High to Address Transition
Min
0
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
ns
Write Enable High to Chip Enable Low
Min
20
ns
tWHGL
Write Enable High to Output Enable Low
Min
0
ns
tWHLL
Write Enable High to Latch Enable Low
Min
0
ns
Protection Timings
tWHEL(2)
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
20
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
ns
tQVWPL
Output (Status Register) Valid to Write Protect Low
Min
0
ns
VPP High to Write Enable High
Min
200
ns
tWHVPL
Write Enable High to VPP Low
Min
200
ns
tWHWPL
Write Enable High to Write Protect Low
Min
200
ns
tWPHWH
Write Protect High to Write Enable High
Min
200
ns
tVPHWH
tVPS
Note: 1. Sampled only, not 100% tested.
2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System
designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after
issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read
after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued,
tWHEL is 0ns.
3. Meaningful only if L is always kept low.
51/83
52/83
K
VPP
WP
DQ0-DQ15
E
G
W
L
A0-A23
tGHEL
tELEH
tLHAX
COMMAND
SET-UP COMMAND
tDVEH
tLLLH
tELLH
tWLEL
tAVLH
BANK ADDRESS
tEHDX
tEHEL
tEHWH
CMD or DATA
tEHAX
CONFIRM COMMAND
OR DATA INPUT
tVPHEH
tWPHEH
tAVEH
VALID ADDRESS
tAVAV
tEHVPL
tEHWPL
tELKV
tWHEL
tEHGL
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
Ai11052
M30L0R8000T0, M30L0R8000B0
Figure 17. Write AC Waveforms, Chip Enable Controlled
M30L0R8000T0, M30L0R8000B0
Table 26. Write AC Characteristics, Chip Enable Controlled
M30L0R8000T0/B
Symbol
Alt
Parameter
Unit
85
Chip Enable Controlled Timings
tAVAV
tWC
Address Valid to Next Address Valid
Min
85
ns
tAVEH
Address Valid to Chip Enable High
Min
45
ns
tAVLH
Address Valid to Latch Enable High
Min
7
ns
tDVEH
tDS
Data Valid to Chip Enable High
Min
45
ns
tEHAX
tAH
Chip Enable High to Address Transition
Min
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
20
ns
Chip Enable High to Output Enable Low
Min
0
ns
Chip Enable High to Write Enable High
Min
0
ns
Chip Enable Low to Clock Valid
Min
7
ns
Chip Enable Low to Chip Enable High
Min
45
ns
tELLH
Chip Enable Low to Latch Enable High
Min
10
ns
tELQV
Chip Enable Low to Output Valid
Min
85
ns
tGHEL
Output Enable High to Chip Enable Low
Min
17
ns
tLHAX
Latch Enable High to Address Transition
Min
7
ns
tLLLH
Latch Enable Pulse Width
Min
7
ns
Write Enable High to Chip Enable Low
Min
20
ns
Write Enable Low to Chip Enable Low
Min
0
ns
tEHVPL
Chip Enable High to VPP Low
Min
200
ns
tEHWPL
Chip Enable High to Write Protect Low
Min
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
ns
tQVWPL
Output (Status Register) Valid to Write Protect
Low
Min
0
ns
VPP High to Chip Enable High
Min
200
ns
Write Protect High to Chip Enable High
Min
200
ns
tEHGL
tEHWH
tCH
tELKV
tELEH
tCP
tWHEL(2)
Protection Timings
tWLEL
tVPHEH
tWPHEH
tCS
tVPS
Note: 1. Sampled only, not 100% tested.
2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System
designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after
issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read
after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued,
tWHEL is 0ns.
53/83
M30L0R8000T0, M30L0R8000B0
Figure 18. Reset and Power-up AC Waveforms
tPHWL
tPHEL
tPHGL
tPHLL
W, E, G, L
tPLWL
tPLEL
tPLGL
tPLLL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06976
Table 27. Reset and Power-up AC Characteristics
Symbol
Parameter
tPLWL
tPLEL
tPLGL
tPLLL
Reset Low to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
tPHWL
tPHEL
tPHGL
tPHLL
Test Condition
85
Unit
During Program
Min
25
µs
During Erase
Min
25
µs
Other Conditions
Min
80
ns
Reset High to
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
Min
30
ns
tPLPH (1,2)
RP Pulse Width
Min
50
ns
tVDHPH (3)
Supply Voltages High to Reset High
Min
100
µs
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
54/83
M30L0R8000T0, M30L0R8000B0
PACKAGE MECHANICAL
Figure 19. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Bottom View Package Outline
D
D1
e
SE
E
E2
E1
b
BALL "A1"
ddd
FE
FE1
FD
SD
A2
A
A1
BGA-Z42
Note: Drawing is not to scale.
Table 28. TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
Max
0.0472
0.200
0.0079
A2
0.850
0.0335
b
0.350
0.300
0.400
0.0138
0.0118
0.0157
D
8.000
7.900
8.100
0.3150
0.3110
0.3189
D1
5.600
0.2205
ddd
0.100
9.900
E
10.000
E1
7.200
0.2835
E2
8.800
0.3465
e
0.800
FD
1.200
0.0472
FE
1.400
0.0551
FE1
0.600
0.0236
SD
0.400
0.0157
SE
0.400
0.0157
–
10.100
0.0039
–
0.3937
0.0315
0.3898
0.3976
–
–
55/83
M30L0R8000T0, M30L0R8000B0
PART NUMBERING
Table 29. Ordering Information Scheme
Example:
M30 L 0 R 8 0 0 0 T 0 ZAQT
Device Type
M30 = Multiple Flash Chip Package
Flash Device Identifier 1
L = Multi-Level, Multiple Bank, Burst Mode
Flash Device Identifier 2
0 = no other architecture
Operating Voltage
R = VDD = 1.7V to 2.0V, VDDQ = 1.7V to 2.0V
Flash 1 Density
8 = 256 Mbit
Flash 2 Density
0 = No Die
Flash 3 Density
0 = No Die
Flash 4 Density
0 = No Die
Parameter Block Location
T = Top Boot
B = Bottom Boot
Product Version
0 = 0.13µm Technology Multi-Level Design
Package
ZAQ = TFBGA88 8x10mm, 0.8mm pitch, quadruple stacked footprint
Packing Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-Free and RoHS Package, Standard Packing
F = Lead-Free and RoHS Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
56/83
M30L0R8000T0, M30L0R8000B0
APPENDIX A. BLOCK ADDRESS TABLES
The following set of equations can be used to calculate a complete set of block addresses using the information contained in Tables 30, 31, 32, 33, 34 and 35.
To calculate the Block Base Address from the Block Number:
First it is necessary to calculate the Bank Number and the Block Number Offset. This can be achieved
using the following formulas:
Bank_Number = (Block_Number − 3) / 16
Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)
If Bank_Number = 0, the Block Base Address can be directly read from Table 30. or Table 33. (Parameter
Bank Block Addresses) in the Block Number Offset row. Otherwise:
Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset
To calculate the Bank Number and the Block Number from the Block Base Address:
If the address is in the range of the Parameter Bank, the Bank Number is 0 and the Block Number can be
directly read from Table 30. or Table 33. (Parameter Bank Block Addresses), in the row that corresponds
to the address given. Otherwise, the Block Number can be calculated using the formulas below:
For the top configuration (M30L0R8000T0):
Block_Number = ((NOT address) / 216) + 3
For the bottom configuration (M30L0R8000B0):
Block_Number = (address / 216) + 3
For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas:
Bank_Number = (Block_Number − 3) / 16
Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)
57/83
M30L0R8000T0, M30L0R8000B0
Table 30. M30L0R8000T0 - Parameter Bank
Block Addresses
Table 32. M30L0R8000T0 - Block Addresses in
Main Banks
Block
Number
Size
(KWords)
Address Range
Block Number
Offset
0
16
FFC000-FFFFFF
0
0F0000
1
16
FF8000-FFBFFF
1
0E0000
2
16
FF4000-FF7FFF
2
0D0000
3
16
FF0000-FF3FFF
3
0C0000
4
64
FE0000-FEFFFF
4
0B0000
5
64
FD0000-FDFFFF
5
0A0000
6
64
FC0000-FCFFFF
6
090000
7
64
FB0000-FBFFFF
7
080000
8
64
FA0000-FAFFFF
8
070000
9
64
F90000-F9FFFF
9
060000
10
64
F80000-F8FFFF
10
050000
11
64
F70000-F7FFFF
11
040000
12
64
F60000-F6FFFF
12
030000
13
64
F50000-F5FFFF
13
020000
14
64
F40000-F4FFFF
14
010000
15
64
F30000-F3FFFF
15
000000
16
64
F20000-F2FFFF
17
64
F10000-F1FFFF
18
64
F00000-F0FFFF
Table 31. M30L0R8000T0 - Main Bank Base
Addresses
Bank
Number
Block
Numbers
Bank Base Address
1
19-34
E00000
2
35-50
D00000
3
51-66
C00000
4
67-82
B00000
5
83-98
A00000
6
99-114
900000
7
115-130
800000
8
131-146
700000
9
147-162
600000
10
163-178
500000
11
179-194
400000
12
195-210
300000
13
211-226
200000
14
227-242
100000
15
243-258
000000
58/83
Block Base Address Offset
Note: There are two Bank Regions: Bank Region 1 contains all the
banks that are made up of main blocks only; Bank Region 2
contains the banks that are made up of the parameter and
main blocks (Parameter Bank).
M30L0R8000T0, M30L0R8000B0
Table 33. M30L0R8000B0 - Parameter Bank
Block Addresses
Table 35. M30L0R8000B0 - Block Addresses in
Main Banks
Block
Number
Size
(KWords)
Address Range
Block Number
Offset
18
64
0F0000-0FFFFF
15
0F0000
17
64
0E0000-0EFFFF
14
0E0000
16
64
0D0000-0DFFFF
13
0D0000
15
64
0C0000-0CFFFF
12
0C0000
14
64
0B0000-0BFFFF
11
0B0000
13
64
0A0000-0AFFFF
10
0A0000
12
64
090000-09FFFF
9
090000
11
64
080000-08FFFF
8
080000
10
64
070000-07FFFF
7
070000
9
64
060000-06FFFF
6
060000
8
64
050000-05FFFF
5
050000
7
64
040000-04FFFF
4
040000
6
64
030000-03FFFF
3
030000
5
64
020000-02FFFF
2
020000
4
64
010000-01FFFF
1
010000
3
16
00C000-00FFFF
0
000000
2
16
008000-00BFFF
1
16
004000-007FFF
0
16
000000-003FFF
Block Base Address Offset
Note: There are two Bank Regions: Bank Region 2 contains all the
banks that are made up of main blocks only; Bank Region 1
contains the banks that are made up of the parameter and
main blocks (Parameter Bank).
Table 34. M30L0R8000B0 - Main Bank Base
Addresses
Bank
Number
Block
Numbers
Bank Base Address
15
243-258
F00000
14
227-242
E00000
13
211-226
D00000
12
195-210
C00000
11
179-194
B00000
10
163-178
A00000
9
147-162
900000
8
131-146
800000
7
115-130
700000
6
99-114
600000
5
83-98
500000
4
67-82
400000
3
51-66
300000
2
35-50
200000
1
19-34
100000
59/83
M30L0R8000T0, M30L0R8000B0
APPENDIX B. COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the Read CFI Query Command is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 36, 37,
38, 39, 40, 41, 42, 43, 44 and 45 show the ad-
dresses used to retrieve the data. The Query data
is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15)
are set to 0.
The CFI data structure also contains a security
area where a 64 bit unique security number is written (see Figure 5., Protection Register Memory
Map). This area can be accessed only in Read
mode by the final user. It is impossible to change
the security number after it has been written by
ST. Issue a Read Array command to return to
Read mode.
Table 36. Query Structure Overview
Offset
Sub-section Name
Description
000h
Reserved
Reserved for algorithm-specific information
010h
CFI Query Identification String
Command set ID and algorithm data offset
01Bh
System Interface Information
Device timing & voltage information
027h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Security Code Area
Lock Protection Register
Unique device Number and
User Programmable OTP
080h
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 37, 38, 39 and 40. Query data is always presented on the lowest order data outputs.
Table 37. CFI Query Identification String
Offset
Sub-section Name
Description
000h
0020h
001h
880Dh
880Eh
002h
Reserved
Reserved
003h-00Fh
Reserved
Reserved
010h
0051h
011h
0052h
012h
0059h
013h
0001h
014h
0000h
015h
offset = P = 000Ah
016h
0001h
017h
0000h
018h
0000h
019h
value = A = 0000h
01Ah
0000h
60/83
Manufacturer Code
Device Code
Value
ST
Top
Bottom
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 40.)
P = 10Ah
Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported
NA
Address for Alternate Algorithm extended Query table
NA
M30L0R8000T0, M30L0R8000B0
Table 38. CFI Query System Interface Information
Offset
Data
Description
Value
01Bh
0017h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
1.7V
01Ch
0020h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
2V
01Dh
0085h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
8.5V
01Eh
0095h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
9.5V
01Fh
0008h
Typical time-out per single byte/word program = 2n µs
n
256µs
512µs
020h
0009h
Typical time-out for Buffer Program = 2 µs
021h
000Ah
Typical time-out per individual block erase = 2n ms
1s
022h
0000h
Typical time-out for full chip erase = 2n ms
NA
023h
0001h
Maximum time-out for word program = 2n times typical
512µs
024h
0001h
Maximum time-out for Buffer Program = 2n times typical
1024µs
n
025h
0002h
Maximum time-out per individual block erase = 2 times typical
4s
026h
0000h
Maximum time-out for chip erase = 2n times typical
NA
61/83
M30L0R8000T0, M30L0R8000B0
Table 39. Device Geometry Definition
Data
027h
0019h
Device Size = 2n in number of bytes
028h
029h
0001h
0000h
Flash Device Interface Code description
02Ah
02Bh
0006h
0000h
Maximum number of bytes in multi-byte program or page = 2n
64 Bytes
02Ch
0002h
Number of identical sized erase block regions within the device
bit 7 to 0 = x = number of Erase Block Regions
2
02Dh
02Eh
00FEh
0000h
Erase Block Region 1 Information
Number of identical-size erase blocks = 00FEh+1
02Fh
030h
0000h
0002h
Erase Block Region 1 Information
Block size in Region 1 = 0200h * 256 Byte
031h
032h
0003h
0000h
Erase Block Region 2 Information
Number of identical-size erase blocks = 0003h+1
033h
034h
0080h
0000h
Erase Block Region 2 Information
Block size in Region 2 = 0080h * 256 Byte
035h
038h
Reserved
02Dh
02Eh
0003h
0000h
Erase Block Region 1 Information
Number of identical-size erase block = 0003h+1
02Fh
030h
0080h
0000h
Erase Block Region 1 Information
Block size in Region 1 = 0080h * 256 bytes
031h
032h
00FEh
0000h
Erase Block Region 2 Information
Number of identical-size erase block = 00FEh+1
033h
034h
0000h
0002h
Erase Block Region 2 Information
Block size in Region 2 = 0200h * 256 bytes
035h
038h
Reserved
BOTTOM DEVICES
TOP DEVICES
Offset
62/83
Description
Reserved for future erase block region information
Reserved for future erase block region information
Value
32 MBytes
x16
Async.
255
128 KByte
4
32 KByte
NA
4
32 KBytes
255
128 KBytes
NA
M30L0R8000T0, M30L0R8000B0
Table 40. Primary Algorithm-Specific Extended Query Table
Offset
Data
(P)h = 10Ah
0050h
0052h
Description
Value
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
0049h
"R"
"I"
(P+3)h =10Dh
0031h
Major version number, ASCII
"1"
(P+4)h = 10Eh
0033h
Minor version number, ASCII
"3"
(P+5)h = 10Fh
00E6h
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
0003h
(P+7)h = 111h
0000h
(P+8)h = 112h
0000h
(P+9)h = 113h
0001h
bit 0 Chip Erase supported(1 = Yes, 0 = No)
bit 1 Erase Suspend supported(1 = Yes, 0 = No)
bit 2 Program Suspend supported(1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported(1 = Yes, 0 = No)
bit 4 Queued Erase supported(1 = Yes, 0 = No)
bit 5 Instant individual block locking supported(1 = Yes, 0 = No)
bit 6 Protection bits supported(1 = Yes, 0 = No)
bit 7 Page mode read supported(1 = Yes, 0 = No)
bit 8 Synchronous read supported(1 = Yes, 0 = No)
bit 9 Simultaneous operation supported(1 = Yes, 0 = No)
bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31
bit field of optional features follows at the end of the bit-30
field.
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
Yes
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
(P+A)h = 114h
0003h
(P+B)h = 115h
0000h
Block Protect Status
Defines which bits in the Block Status Register section of the Query are
implemented.
bit 0 Block protect Status Register Lock/Unlock
bit active (1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Yes
Yes
VDD Logic Supply Optimum Program/Erase voltage (highest performance)
(P+C)h = 116h
0018h
(P+D)h = 117h
0090h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
1.8V
VPP Supply Optimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
9V
63/83
M30L0R8000T0, M30L0R8000B0
Table 41. Protection Register Information
Offset
Data
(P+E)h = 118h
0002h
(P+F)h = 119h
0080h
(P+10)h = 11Ah
0000h
(P+ 11)h = 11Bh
0003h
(P+12)h = 11Ch
0003h
(P+13)h = 11Dh
0089h
(P+14)h = 11Eh
0000h
(P+15)h = 11Fh
0000h
(P+16)h = 120h
0000h
(P+17)h = 121h
0000h
(P+18)h = 122h
0000h
0
(P+19)h = 123h
0000h
0
(P+1A)h = 124h
0010h
16
(P+1B)h = 125h
0000h
0
(P+1C)h = 126h
0004h
16
64/83
Description
Number of protection register fields in JEDEC ID space. 0000h indicates
that 256 fields are available.
Protection Field 1: Protection Description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
Protection Register 2: Protection Description
Bits 0-31 protection register address
Bits 32-39 n number of factory programmed regions (lower byte)
Bits 40-47 n number of factory programmed regions (upper byte)
Bits 48-55 2n bytes in factory programmable region
Bits 56-63 n number of user programmable regions (lower byte)
Bits 64-71 n number of user programmable regions (upper byte)
Bits 72-79 2n bytes in user programmable region
Value
2
80h
00h
8 Bytes
8 Bytes
89h
00h
00h
00h
0
M30L0R8000T0, M30L0R8000B0
Table 42. Burst Read Information
Offset
Data
Description
Value
(P+1D)h = 127h
0004h
Page-mode read capability
bits 0-7 ’n’ such that 2n HEX value represents the number of read-page
bytes. See offset 0028h for device word width to
determine page-mode data output width.
(P+1E)h = 128h
0004h
Number of synchronous mode read configuration fields that follow.
4
(P+1F)h = 129h
0001h
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 ’n’ such that 2n+1 HEX value represents the maximum number of
continuous synchronous reads when the device is configured
for its maximum word width. A value of 07h indicates that the
device is capable of continuous linear bursts that will output
data until the internal burst counter reaches the end of the
device’s burstable address space. This field’s 3-bit value can
be written directly to the read configuration register bit 0-2 if
the device is configured for its maximum word width. See
offset 0028h for word width to determine the burst data output
width.
4
(P+20)h = 12Ah
0002h
Synchronous mode read capability configuration 2
8
(P-21)h = 12Bh
0003h
Synchronous mode read capability configuration 3
16
(P+22)h = 12Ch
0007h
Synchronous mode read capability configuration 4
Cont.
16 Bytes
Table 43. Bank and Erase Block Region Information
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
(P+23)h = 12Dh
02h
(P+23)h = 12Dh
02h
Number of Bank Regions within the device
Note: 1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32, 33, 34 and 35 in APPENDIX A.
65/83
M30L0R8000T0, M30L0R8000B0
Table 44. Bank and Erase Block Region 1 Information
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
(P+24)h = 12Eh
0Fh
(P+24)h = 12Eh
01h
(P+25)h = 12Fh
00h
(P+25)h = 12Fh
00h
(P+26)h = 130h
11h
(P+26)h = 130h
11h
Number of program or erase operations allowed in Bank
Region 1:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in other banks
while a bank in same region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in other banks
while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in Bank Region 1
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region(2).
(P+27)h = 131h
(P+28)h = 132h
00h
00h
(P+27)h = 131h
(P+28)h = 132h
(P+29)h = 133h
01h
(P+29)h = 133h
02h
(P+2A)h = 134h
0Fh
(P+2A)h = 134h
03h
(P+2B)h = 135h
00h
(P+2B)h = 135h
00h
(P+2C)h = 136h
00h
(P+2C)h = 136h
80h
(P+2D)h = 137h
02h
(P+2D)h = 137h
00h
(P+2E)h = 138h
64h
(P+2E)h = 138h
64h
(P+2F)h = 139h
00h
(P+2F)h = 139h
00h
(P+30)h = 13Ah
(P+31)h = 13Bh
66/83
02h
03h
Number of identical banks within Bank Region 1
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks in each
bank
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
02h
Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
(P+31)h = 13Bh
03h
Bank Region 1 (Erase Block Type 1): Page mode and
Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+32)h = 13Ch
0Eh
(P+33)h = 13Dh
00h
(P+34)h = 13Eh
00h
(P+35)h = 13Fh
02h
(P+36)h = 140h
64h
(P+37)h = 141h
00h
(P+30)h = 13Ah
Bank Region 1 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks in each
bank
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
M30L0R8000T0, M30L0R8000B0
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
(P+38)h = 142h
(P+39)h = 143h
Data
02h
Bank Regions 1 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 1 (Erase Block Type 2): Page mode and
Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Note: 1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32, 33, 34 and 35 in APPENDIX A.
Table 45. Bank and Erase Block Region 2 Information
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
(P+32)h = 13Ch
01h
(P+3A)h = 144h
0Fh
(P+33)h = 13Dh
00h
(P+3B)h = 145h
00h
Number of identical banks within bank region 2
(P+34)h = 13Eh
11h
(P+3C)h = 146h
11h
Number of program or erase operations allowed in Bank
Region 2:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
(P+35)h = 13Fh
00h
(P+3D)h = 147h
00h
Number of program or erase operations allowed in other
banks while a bank in this region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
00h
Number of program or erase operations allowed in other
banks while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in Bank Region 2
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region.(2)
(P+36)h = 140h
00h
(P+3E)h = 148h
(P+37)h = 141h
02h
(P+3F)h = 149h
01h
(P+38)h = 142h
0Eh
(P+40)h = 14Ah
0Fh
(P+39)h = 143h
00h
(P+41)h = 14Bh
00h
(P+3A)h = 144h
00h
(P+42)h = 14Ch
00h
(P+3B)h = 145h
02h
(P+43)h = 14Dh
02h
(P+3C)h = 146h
64h
(P+44)h = 14Eh
64h
(P+3D)h = 147h
00h
(P+45)h = 14Fh
00h
(P+3E)h = 148h
02h
(P+46)h = 150h
02h
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks in
each bank
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 1): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
67/83
M30L0R8000T0, M30L0R8000B0
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
(P+3F)h = 149h
03h
(P+40)h = 14Ah
03h
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+44)h =14Eh
64h
(P+45)h = 14Fh
00h
(P+46)h = 150h
(P+47)h = 151h
Offset
(P+47)h = 151h
Data
03h
Bank Region 2 (Erase Block Type 1):Page mode and
Synchronous mode capabilities (defined in Table 42.)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks in
each bank
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
02h
Bank Region 2 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank Region 2 (Erase Block Type 2): Page mode and
Synchronous mode capabilities (defined in Table 42.)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h
(P+48)h = 152h
Feature Space definitions
(P+49)h = 153h
(P+43)h = 153h
Reserved
Note: 1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Tables 30, 31, 32, 33, 34 and 35 in APPENDIX A.
68/83
M30L0R8000T0, M30L0R8000B0
APPENDIX C. FLOWCHARTS AND PSEUDO CODES
Figure 20. Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0x40);
/*writeToFlash (addressToProgram, 0x10);*/
/*see note (3)*/
Write 40h or 10h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram);
"see note (3)";
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06170b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or
after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
69/83
M30L0R8000T0, M30L0R8000B0
Figure 21. Buffer Program Flowchart and Pseudo Code
Start
Buffer Program E8h
Command,
Start Address
status_register=readFlash (Start_Address);
Read Status
Register
SR7 = 1
Buffer_Program_command (Start_Address, n, buffer_Program[] )
/* buffer_Program [] is an array structure used to store the address and
data to be programmed to the Flash memory (the address must be within
the segment Start Address and Start Address+n) */
{
do {writeToFlash (Start_Address, 0xE8) ;
NO
} while (status_register.SR7==0);
YES
writeToFlash (Start_Address, n);
Write n(1),
Start Address
Write Buffer Data,
Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data);
/*buffer_Program[0].address is the start address*/
X=0
X=n
x = 0;
YES
while (x<n)
NO
Write Next Buffer Data,
Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data)
x++;
X=X+1
}
Program
Buffer to Flash
Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status
Register
SR7 = 1
do {status_register=readFlash (Start_Address);
NO
} while (status_register.SR7==0);
YES
Full Status
Register Check(3)
full_status_register_check();
}
End
AI08913b
Note: 1. n + 1 is the number of data being programmed.
2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to
buffer_Program[].address
3. Routine for Error Check by reading SR3, SR4 and SR1.
70/83
M30L0R8000T0, M30L0R8000B0
Figure 22. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR2 = 1
NO
Program Complete
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
YES
Read Data
}
else
Write FFh
{ writeToFlash (bank_address, 0xFF) ;
Read data from
another address
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if program has completed */
Write 70h(1)
}
Program Continues with
Bank in Read Status
Register Mode
}
AI10117b
Note: The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
71/83
M30L0R8000T0, M30L0R8000B0
Figure 23. Block Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (blockToErase, 0x20) ;
/*see note (2) */
Write 20h (2)
writeToFlash (blockToErase, 0xD0) ;
/* only A14-A23 are significant */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (blockToErase) ;
/* see note (2) */
/* E or G must be toggled*/
Read Status
Register (2)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1)
YES
Command
Sequence Error (1)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
SR4, SR5 = 1
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
NO
SR5 = 0
NO
Erase Error (1)
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
YES
SR1 = 0
NO
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI10593
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
72/83
M30L0R8000T0, M30L0R8000B0
Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR6 = 1
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
Write FFh
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Read Data
YES
Write FFh
}
else
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
Read data from another block
or
Program/Protection Register Program
or
Block Lock/Unlock/Lock-Down
/*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
Write 70h(1)
}
}
Erase Continues with
Bank in Read Status
Register Mode
AI10116b
Note: The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
73/83
M30L0R8000T0, M30L0R8000B0
Figure 25. Locking Operations Flowchart and Pseudo Code
Start
locking_operation_command (address, lock_operation) {
writeToFlash (address, 0x60) ; /*configuration setup*/
/* see note (1) */
Write 60h (1)
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
Write
01h, D0h or 2Fh
writeToFlash (address, 0x90) ;
/*see note (1) */
Write 90h (1)
Read Block
Lock States
Locking
change
confirmed?
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
NO
YES
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/
/*see note (1) */
Write FFh (1)
}
End
AI06176b
Note: 1. Any address within the bank can equally be used.
74/83
M30L0R8000T0, M30L0R8000B0
Figure 26. Protection Register Program Flowchart and Pseudo Code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (3) */
Write C0h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram) ;
/* see note (3) */
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06177b
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or
after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
75/83
M30L0R8000T0, M30L0R8000B0
Figure 27. Buffer Enhanced Factory Program Flowchart and Pseudo Code
Start
NO
writeToFlash (start_address, 0x80) ;
Write D0h to
Address WA1
writeToFlash (start_address, 0xD0) ;
Read Status
Register
do {
do {
status_register = readFlash (start_address);
SR7 = 0
Initialize count
X=0
SR4 = 1
Read Status Register
SR3 and SR1for errors
Write PDX
Address WA1
Exit
Increment Count
X=X+1
NO
Buffer_Enhanced_Factory_Program_Command
(start_address, DataFlow[]) {
Write 80h to
Address WA1
YES
NO
SETUP PHASE
if (status_register.SR4==1) { /*error*/
if (status_register.SR3==1) error_handler ( ) ;/*VPP error */
if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */
PROGRAM AND }
VERIFY PHASE while (status_register.SR7==1)
x=0; /* initialize count */
do {
writeToFlash (start_address, DataFlow[x]);
x++;
X = 32
NO
YES
}while (x<32)
do {
Read Status
Register
status_register = readFlash (start_address);
SR0 = 0
}while (status_register.SR0==1)
YES
NO
Last data?
} while (not last data)
YES
Write FFFFh to
Address = NOT WA1
Read Status
Register
NO
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
do {
status_register = readFlash (start_address)
SR7 = 1
}while (status_register.SR7==0)
YES
Full Status Register
Check
full_status_register_check();
End
}
76/83
AI07302a
M30L0R8000T0, M30L0R8000B0
APPENDIX D. COMMAND INTERFACE STATE TABLES
Table 46. Command Interface States - Modify Table, Next State
Current CI State
Read Program Buffer
Setup Program
Array(2)
(3,4)
(3,4)
(FFh)
(10/40h)
(E8h)
Block
Erase,
Setup
(3,4)
Command Input
Erase Confirm
P/E Resume,
BEFP Block Unlock
Setup
confirm,
(80h) BEFP Confirm
(20h)
(3,4)
(D0h)
Ready
Lock/CR Setup
OTP
Program
Ready
Buffer
Program
Program
Setup
Setup
Erase
Setup
Ready (Lock Error)
Setup
Busy
Setup
Busy
Suspend
Setup
Buffer
Load 1
Buffer
Load 2
Buffer
Program,
Program/
Erase
Suspend
(B0h)
BEFP
Setup
Read
Clear Electronic
Read
status Signature,
Status
Register Register Read CFI
(5)
Query
(70h)
(50h)
(90h, 98h)
Ready
Ready
(unlock block)
Ready (Lock Error)
OTP Busy
Program Busy
Program Busy
Program
Suspend
Program Busy
Program Suspend
Program Busy
Program Suspend
Buffer Program Load 1 (give word count load (N-1));
if N=0 go to Buffer Program Confirm. Else (N not =0) go to Buffer Program Load 2 (data load)
Buffer Program Confirm when count =0; Else Buffer Program Load 2
(note: Buffer Program will fail at this point if any block address is different from the first address)
Buffer
Buffer Program
Ready (error)
Ready (error)
Program Confirm
Busy
Buffer
Busy
Buffer Program Busy
Program
Buffer Program Busy
Suspend
Buffer Program
Suspend
Buffer Program Suspend
Buffer Program Suspend
Busy
Setup
Ready (error)
Erase Busy
Ready (error)
Erase
Busy
Erase Busy
Erase Busy
Suspend
Erase
Buffer
Program
Erase
Program
Suspend
in Erase
Erase Suspend
Erase Busy
Erase Suspend
Suspend
Setup
Suspend
Suspend
Setup
Program Busy in Erase Suspend
Program
Suspend in
Program Busy in Erase Suspend
Program
Busy
Program Busy in Erase Suspend
Erase
in Erase
Suspend
Suspend
Program Busy
Suspend
Program Suspend in Erase Suspend
in Erase
Program Suspend in Erase Suspend
Suspend
77/83
M30L0R8000T0, M30L0R8000B0
Current CI State
Setup
Buffer
Load 1
Buffer
Load 2
Buffer
Program
in Erase
Suspend
Confirm
Busy
Suspend
Lock/CR Setup
in Erase Suspend
Setup
Buffer
EFP
Busy
Block
Erase,
Setup
Read Program Buffer
Setup Program
Array(2)
(3,4)
(3,4)
(FFh)
(10/40h)
(E8h)
(3,4)
(20h)
Command Input
Erase Confirm
P/E Resume,
BEFP Block Unlock
Setup
confirm,
(80h) BEFP Confirm
(3,4)
Buffer
Program,
Program/
Erase
Suspend
(B0h)
Read
Clear
Electronic
Read
status
Signature,
Status
Register Register Read CFI
(5)
Query
(70h)
(50h)
(90h, 98h)
(D0h)
Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N
not =0) go to Buffer Program Load 2
Buffer Program Load 2 in Erase Suspend (data load)
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note:
Buffer Program will fail at this point if any block address is different from the first address)
Buffer Program
Ready (error)
Busy in Erase
Ready (error)
Suspend
Buffer
Program
Buffer Program Busy in Erase
Buffer Program Busy in Erase Suspend
Suspend in
Suspend
Erase
Suspend
Buffer Program
Buffer Program Suspend in Erase Suspend
Busy in Erase Buffer Program Suspend in Erase Suspend
Suspend
Erase Suspend (Lock Error)
Ready (error)
Erase Suspend
Erase Suspend (Lock Error)
BEFP Busy
Ready (error)
BEFP Busy (6)
Note: 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller.
2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output.
3. The two cycle command should be issued to the same bank address.
4. If the P/E.C. is active, both cycles are ignored.
5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
6. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other
commands are treated as data.
78/83
M30L0R8000T0, M30L0R8000B0
Table 47. Command Interface States - Modify Table, Next Output
Current CI State
Read Program
Buffer
Array
Setup Program
(3)
(4,5)
(E8h)
(FFh) (10/40h)
Block
Erase,
Setup
(4,5)
(20h)
Command Input
Erase
Confirm
P/E
Resume, Program/ Read
BEFP
Block
Erase
Status
Setup Unlock
Suspend Register
(80h) confirm,
(B0h)
(70h)
BEFP
Confirm
Clear
status
Register
(50h)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
(4,5)
(D0h)
Program Setup
Erase Setup
OTP Setup
Program in Erase Suspend
BEFP Setup
BEFP Busy
Buffer Program Setup
Buffer Program Load 1
Buffer Program Load 2
Buffer Program Confirm
Buffer Program Setup in
Erase Suspend
Buffer Program Load 1 in
Erase Suspend
Buffer Program Load 2 in
Erase Suspend
Buffer Program Confirm in
Erase Suspend
Lock/CR Setup
Lock/CR Setup in Erase
Suspend
Status Register
Status
Register
OTP Busy
Ready
Program Busy
Erase Busy
Buffer Program Busy
Program/Erase Suspend
Buffer Program Suspend
Program Busy in Erase
Suspend
Buffer Program Busy in
Erase Suspend
Program Suspend in Erase
Suspend
Buffer Program Suspend in
Erase Suspend
Array
Status Register
Output Unchanged
Status
Output
Register Unchanged Electronic
Signature/
CFI
Note: 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A
bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend
on the bank output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller.
3. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/E.C. is active, both cycles are ignored.
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M30L0R8000T0, M30L0R8000B0
Table 48. Command Interface States - Lock Table, Next State
Command Input
Current CI State
Ready
Lock/CR Setup
OTP
Program
Buffer
Program
Lock/CR
Setup(2)
(60h)
OTP Setup
(2)
(C0h)
Lock/CR
Setup
OTP Setup
Block
Block Lock
Lock-Down
Confirm
Confirm
(01h)
(2Fh)
Ready (Lock error)
Ready
WSM
Operation
Completed
N/A
Ready (Lock error)
N/A
N/A
Ready
Setup
Program Busy
N/A
Busy
Program Busy
Ready
Suspend
Program Suspend
N/A
Setup
Buffer Program Load 1 (give word count load (N-1));
N/A
Buffer
Load 1
Buffer Program Load 2(6)
Buffer
Load 2
see note (6)
N/A
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail
at this point if any block address is different from the first address)
N/A
Exit
Confirm
Ready (error)
N/A
Busy
Buffer Program Busy
Ready
Suspend
Buffer Program Suspend
N/A
Setup
Ready (error)
N/A
Busy
Erase Busy
Ready
Lock/CR
Setup in
Erase
Suspend
Erase Suspend
Setup
Busy
N/A
Program Busy in Erase Suspend
N/A
Program Busy in Erase Suspend
Erase
Suspend
Suspend
Program Suspend in Erase Suspend
Setup
Buffer Program Load 1 in Erase Suspend (give word count load (N-1))
Buffer
Load 1
Buffer
Load 2
Buffer Program Load 2 in Erase Suspend(7)
Ready (error)
Busy
Buffer Program Busy in Erase Suspend
Suspend
Buffer Program Suspend in Erase Suspend
Erase Suspend (Lock error)
Erase Suspend
Setup
Busy
Exit
see note (7)
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase
Suspend (note: Buffer Program will fail at this point if any block address is different from the first
address)
Confirm
Lock/CR Setup
in Erase Suspend
BEFP
Illegal
Command
(5)
OTP Busy
Busy
Suspend
Buffer
Program in
Erase
Suspend
Block
Address
(WA0) (3)
(XXXXh)
Ready
Setup
Erase
Program in
Erase
Suspend
Set CR
Confirm
(03h)
Erase Suspend
(Lock error)
Ready (error)
BEFP Busy (4)
N/A
N/A
N/A
Exit
BEFP
Busy(4)
N/A
Note: 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller, WA0 = Address in a block different from first BEFP address.
2. If the P/E.C. is active, both cycles are ignored.
3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
4. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other
commands are treated as data.
5. Illegal commands are those not defined in the command set.
6. if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load).
7. if N=0 go to Buffer Program Confirm in Erase Suspend. Else (N ≠ 0) go to Buffer Program Load 2 in Erase Suspend.
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M30L0R8000T0, M30L0R8000B0
Table 49. Command Interface States - Lock Table, Next Output
Current CI State
Program Setup
Erase Setup
OTP Setup
Program in Erase
Suspend
BEFP Setup
BEFP Busy
Buffer Program
Setup
Buffer Program
Load 1
Buffer Program
Load 2
Buffer Program
Confirm
Buffer Program
Setup in Erase
Suspend
Buffer Program
Load 1 in Erase
Suspend
Buffer Program
Load 2 in Erase
Suspend
Buffer Program
Confirm in Erase
Suspend
Lock/CR Setup
Lock/CR Setup in
Erase Suspend
OTP Busy
Ready
Program Busy
Erase Busy
Buffer Program
Busy
Program/Erase
Suspend
Buffer Program
Suspend
Program Busy in
Erase Suspend
Buffer Program in
Erase Suspend Busy
Program Suspend in
Erase Suspend
Buffer Program
Suspend in Erase
Suspend
Lock/CR
Setup (3)
(60h)
OTP
Setup(3)
(C0h)
Block Lock
Confirm
(01h)
Command Input
Block
Set CR
Lock-Down
Confirm
Confirm
(03h)
(2Fh)
BEFP Exit(4)
(FFFFh)
Illegal
Command
(5)
WSM
Operation
Completed
Status Register
Output
Unchanged
Status Register
Status
Register
Output Unchanged
Array
Status Register
Array
Output
Unchanged
Note: 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A
bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend
on the bank's output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller, WA0 = Address in a block different from first BEFP address.
3. If the P/E.C. is active, both cycles are ignored.
4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
5. Illegal commands are those not defined in the command set.
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M30L0R8000T0, M30L0R8000B0
REVISION HISTORY
Table 50. Document Revision History
Date
Version
24-Nov-2003
0.1
First Issue.
0.2
70ns speed class added, maximum operating frequency increased to 66MHz. Dual
operation limitations added (Table 15.). Read CFI Query Command clarified. Write to
Buffer and Program command renamed Buffer Program.
Ambient temperature conditions modified during Buffer Enhanced Factory Program
operations. Notes to Table 17., Program/Erase Times and Endurance Cycles
modified. IDD1 (for f=54MHz), IDD2, IDD3 and IDD4, IDD6 and IDD7 parameters modified
and IDD1 (for f=66MHz) added in Table 21., DC Characteristics - Currents.
Package specifications updated in Table 28., TFBGA88 8x10mm - 8x10 ball array,
0.8mm pitch, Package Mechanical Data.
APPENDIX A., BLOCK ADDRESS TABLES updated.
Data and/or values modified at address offsets 027h, 02Dh, 02Fh, 021h and 033h in
Table 39., Device Geometry Definition. Note 2 to Tables 43, 44 and 45 clarified.
Small text changes.
0.3
Lead-free packages are compliant with the ST ECOPACK specification.
Table 11., Configuration Register modified. AC waveforms simplified.
Table 48., Command Interface States - Lock Table, Next State modified. APPENDIX
C., FLOWCHARTS AND PSEUDO CODES revised.
70ns speed class removed, operating frequency 66MHz removed.
Daisy chain information removed.
1.0
VPP is 12V tolerant (VPP max changed in Table 18., Absolute Maximum Ratings).
APPENDIX A., BLOCK ADDRESS TABLES and APPENDIX D., COMMAND
INTERFACE STATE TABLES revised. Alt symbol to tAVWH and tAVEH removed from
Table 25., Write AC Characteristics, Write Enable Controlled and Table 26., Write
AC Characteristics, Chip Enable Controlled.
2.0
Device changed from PRELIMINARY DATA TO full Datasheet.
tWHQV AC parameter removed throughout the document.
VPP clarified for enabling program and erase operations in VPP Program Supply
Voltage, page 11 . Clarification of device behavior when block is protected for all
Program commands in the COMMAND INTERFACE section.
Wait at Boundary table replaced by X-Latency Bits (CR13-CR11), page 27.
Figure 6., X-Latency and Data Output Configuration Example modified.
VLKO modified in Table 22., DC Characteristics - Voltages. AC parameter values
tEHQX, tEHQZ, tGHQX, tGHQZ and tGHTZ modified in Table 23., Asynchronous Read AC
Characteristics. tGLTV modified in Figure 13., Single Synchronous Read AC
Waveforms.
27-Apr-2004
21-Oct-2004
28-Jan-2005
18-May-2005
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Revision Details
M30L0R8000T0, M30L0R8000B0
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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