ON MC74VHCT374A Octal d−type flip−flop with 3−state output Datasheet

MC74VHCT374A
Octal D−Type Flip−Flop
with 3−State Output
The MC74VHCT374A is an advanced high speed CMOS octal
flip−flop with 3−state output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
This 8−bit D−type flip−flop is controlled by a clock input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT374A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
•
•
MARKING
DIAGRAMS
20
1
High Speed: fmax = 140 MHz (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 1.6 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 276 FETs or 69 Equivalent Gates
Pb−Free Packages are Available*
VHCT374A
AWLYYWWG
SOIC−20WB
SUFFIX DW
CASE 751D
1
20
1
Features
•
•
•
•
•
•
•
•
•
•
http://onsemi.com
VHCT
374A
ALYWG
G
TSSOP−20
SUFFIX DT
CASE 948E
1
20
1
74VHCT374
AWLYWWG
SOEIAJ−20
SUFFIX M
CASE 967
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
INPUTS
OE
L
L
L
H
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 4
1
OUTPUT
CP
D
Q
L, H,
X
H
L
X
X
H
L
No Change
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Publication Order Number:
MC74VHCT374A/D
MC74VHCT374A
DATA
INPUTS
2
5
6
9
12
15
16
19
3
D0
4
D1
7
D2
8
D3
13
D4
14
D5
17
D6
18
D7
11
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
1
OE
1
20
VCC
Q0
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
CP
GND
Figure 2. Pin Assignment
Figure 1. Logic Diagram
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Outputs in 3−State
High or Low State
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage
Vin
DC Input Voltage
Vout
DC Output Voltage
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
Outputs in 3−State
High or Low State
VCC =5.0V ±0.5V
http://onsemi.com
2
Min
Max
Unit
4.5
5.5
V
0
5.5
V
0
0
5.5
VCC
V
− 40
+ 85
_C
0
20
ns/V
MC74VHCT374A
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DC ELECTRICAL CHARACTERISTICS
Test Conditions
TA = 25°C
VCC
V
Min
4.5 to 5.5
2.0
Typ
TA = − 40 to 85°C
Max
Min
Max
Unit
V
0.8
V
Symbol
VIH
Parameter
Minimum High−Level Input Voltage
VIL
Maximum Low−Level Input Voltage
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
IOH = − 50mA
4.5
4.4
IOH = − 8mA
4.5
3.94
VOL
Maximum Low−Level Output
Voltage
Vin = VIH or VIL
IOL = 50mA
4.5
4.5
0.36
0.44
Iin
Maximum Input Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
mA
IOZ
Maximum 3−State Leakage Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.25
± 2.5
mA
ICC
Maximum Quiescent Supply Current
Vin = VCC or GND
5.5
4.0
40.0
mA
ICCT
Quiescent Supply Current
Per Input: VIN = 3.4V
Other Input: VCC or GND
5.5
1.35
1.50
mA
IOPD
Output Leakage Current
VOUT = 5.5V
0
0.5
5.0
mA
2.0
4.5 to 5.5
IOL = 8mA
0.8
4.5
4.4
V
3.80
0.0
0.1
0.1
V
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
fmax
Min
Typ
90
85
140
130
TA = − 40 to 85°C
Max
Max
Unit
MHz
1.0
1.0
10.5
11.5
ns
10.2
11.2
1.0
1.0
11.5
12.5
ns
11.2
1.0
12.0
ns
1.0
1.0
ns
10
10
pF
Parameter
Maximum Clock Frequency
(50% Duty Cycle)
Test Conditions
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
tPLH,
tPHL
Maximum Propagation Delay,
CP to Q
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
4.1
5.6
9.4
10.4
tPZL,
tPZH
Output Enable Time,
OE to Q
VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kW CL = 50pF
6.5
7.3
tPLZ,
tPHZ
Output Disable Time
OE to Q
VCC = 5.0 ± 0.5V
RL = 1kW
CL = 50pF
7.0
Output to Output Skew
VCC = 5.0 ± 0.5V
(Note 1)
CL = 50pF
tOSLH,
tOSHL
Cin
Maximum Input Capacitance
4
Cout
Maximum 3−State Output Capacitance
(Output in High−Impedance State)
9
Min
80
95
pF
Typical @ 25°C, VCC = 5.0V
25
CPD
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
VOLP
Parameter
Typ
Max
1.2
1.6
Unit
V
−1.2
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
−1.6
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25°C
Limit
Unit
Minimum Pulse Width, CP
VCC = 5.0 ± 0.5 V
6.5
8.5
ns
tsu
Minimum Setup Time, D to CP
VCC = 5.0 ± 0.5 V
2.5
2.5
ns
th
Minimum Hold Time, D to CP
VCC = 5.0 ± 0.5 V
2.5
2.5
ns
Parameter
Test Conditions
http://onsemi.com
3
Typ
Limit
TA = − 40 to 85°C
tw
Symbol
MC74VHCT374A
ORDERING INFORMATION
Package
Shipping †
MC74VHCT374ADWR2
SOIC−20WB
1000 / Tape & Reel
MC74VHCT374ADWRG
SOIC−20WB
(Pb−Free)
1000 / Tape & Reel
MC74VHCT374ADTR2
TSSOP−20*
2500 / Tape & Reel
MC74VHCT374ADTRG
TSSOP−20*
2500 / Tape & Reel
MC74VHCT374AMEL
SOEIAJ−20
2000 / Tape & Reel
MC74VHCT374AMELG
SOEIAJ−20
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
3V
1.5V
CP
GND
tW
1/fmax
tPHL
tPLH
Q
VOH
1.5V
VOL
Figure 3. Switching Waveform
3V
OE
1.5V
GND
tPZL
tPLZ
tPZH
tPHZ
HIGH
IMPEDANCE
1.5V
Q
Q
VOL +0.3V
VOH −0.3V
1.5V
HIGH
IMPEDANCE
Figure 4. Switching Waveform
VALID
D
3V
1.5V
GND
th
tsu
3V
CP
1.5V
GND
Figure 5. Switching Waveform
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4
MC74VHCT374A
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C L*
*Includes all probe and jig capacitance
Figure 6. Test Circuit
TEST POINT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
OUTPUT
DEVICE
UNDER
TEST
C L*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
D0
3
D1
4
D
Q
D
C
CP
OE
D2
7
Q
D3
8
D
C
Q
D4
13
D
C
Q
D5
14
D
C
Q
D6
17
D
C
Q
D7
18
D
C
Q
D
C
Q
C
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
Figure 8. Expanded Logic Diagram
http://onsemi.com
5
15
Q5
16
Q6
19
Q7
MC74VHCT374A
PACKAGE DIMENSIONS
SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
1
10
20X
DIM
A
A1
B
C
D
E
e
H
h
L
q
B
B
0.25
M
T A
B
S
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
e
18X
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
SEATING
PLANE
A1
C
T
TSSOP−20
D5 SUFFIX
CASE 948E−02
ISSUE B
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74VHCT374A
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
20
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
0.13 (0.005)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.032
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MC74VHCT374A/D