® Numonyx™ StrataFlash (P30) Embedded Memory Datasheet Product Features High performance — 85 ns initial access — 52 MHz with zero wait states, 17ns clock-to-data output synchronous-burst read mode — 25 ns asynchronous-page read mode — 4-, 8-, 16-, and continuous-word burst mode — Buffered Enhanced Factory Programming (BEFP) at 5 μs/ byte (Typ) — 1.8 V buffered programming at 7 μs/byte (Typ) Quality and Reliability — Operating temperature: –40 °C to +85 °C — Minimum 100,000 erase cycles per block — ETOX™ VIII process technology Software — 20 μs (Typ) program suspend — 20 μs (Typ) erase suspend — Numonyx™ Flash Data Integrator optimized — Basic Command Set and Extended Command Set compatible — Common Flash Interface capable Voltage and Power — VCC (core) voltage: 1.7 V – 2.0 V — VCCQ (I/O) voltage: 1.7 V – 3.6 V — Standby current: 20μA (Typ) for 64-Mbit — 4-Word synchronous read current: 13 mA (Typ) at 40 MHz — One-Time Programmable Registers: • 64 unique factory device identifier bits • 2112 user-programmable OTP bits — Selectable OTP Space in Main Array: • Four pre-defined 128-KByte blocks (top or bottom configuration) • Up to Full Array OTP Lockout — Absolute write protection: V PP = VSS — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down Architecture — Multi-Level Cell Technology: Highest Density at Lowest Cost — Asymmetrically-blocked architecture — Four 32-KByte parameter blocks: top or bottom configuration — 128-KByte main blocks Security Density and Packaging — 56- Lead TSOP package (64, 128, 256, 512- Mbit) — 64- Ball Numonyx™ Easy BGA package (64, 128, 256, 512- Mbit) — Numonyx™ QUAD+ SCSP (64, 128, 256, 512- Mbit) — 16-bit wide data bus Order Number: 306666-11 November 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Legal L ines and D isc laim er s Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Numonyx, B.V., All Rights Reserved. Datasheet 2 November 2007 Order Number: 306666-11 P30 Contents 1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 6 1.3 Conventions ....................................................................................................... 7 2.0 Functional Overview .................................................................................................. 8 2.1 Virtual Chip Enable Description.............................................................................. 8 3.0 Package Information ............................................................................................... 10 3.1 56-Lead TSOP................................................................................................... 10 3.2 64-Ball Easy BGA Package .................................................................................. 11 3.3 QUAD+ SCSP Packages ...................................................................................... 13 4.0 Ballout and Signal Descriptions ............................................................................... 16 4.1 Signal Ballout ................................................................................................... 16 4.2 Signal Descriptions ............................................................................................ 19 4.3 Dual-Die Configurations ..................................................................................... 21 4.4 Memory Maps ................................................................................................... 22 5.0 Maximum Ratings and Operating Conditions............................................................ 25 5.1 Absolute Maximum Ratings................................................................................. 25 5.2 Operating Conditions ......................................................................................... 25 6.0 Electrical Specifications ........................................................................................... 26 6.1 DC Current Characteristics.................................................................................. 26 6.2 DC Voltage Characteristics.................................................................................. 27 7.0 AC Characteristics ................................................................................................... 28 7.1 AC Test Conditions ............................................................................................ 28 7.2 Capacitance...................................................................................................... 29 7.3 AC Read Specifications....................................................................................... 29 7.4 AC Write Specifications ...................................................................................... 36 7.5 Program and Erase Characteristics....................................................................... 39 8.0 Power and Reset Specifications ............................................................................... 41 8.1 Power-Up and Power-Down................................................................................. 41 8.2 Reset Specifications........................................................................................... 41 8.3 Power Supply Decoupling ................................................................................... 42 9.0 Device Operations ................................................................................................... 43 9.1 Bus Operations ................................................................................................. 43 9.1.1 Reads ................................................................................................... 43 9.1.2 Writes................................................................................................... 44 9.1.3 Output Disable ....................................................................................... 44 9.1.4 Standby ................................................................................................ 44 9.1.5 Reset.................................................................................................... 44 9.2 Device Commands............................................................................................. 45 9.3 Command Definitions......................................................................................... 46 10.0 Read 10.1 10.2 10.3 Operations ...................................................................................................... 48 Asynchronous Page-Mode Read ........................................................................... 48 Synchronous Burst-Mode Read............................................................................ 48 Read Configuration Register................................................................................ 49 10.3.1 Read Mode ............................................................................................ 50 10.3.2 Latency Count........................................................................................ 50 November 2007 Order Number: 306666-11 Datasheet 3 P30 10.3.3 WAIT Polarity .........................................................................................52 10.3.4 Data Hold ..............................................................................................53 10.3.5 WAIT Delay............................................................................................53 10.3.6 Burst Sequence ......................................................................................54 10.3.7 Clock Edge.............................................................................................54 10.3.8 Burst Wrap ............................................................................................55 10.3.9 Burst Length ..........................................................................................55 10.3.10 End of Word Line (EOWL) Considerations ...................................................55 11.0 Programming Operations .........................................................................................56 11.1 Word Programming ............................................................................................56 11.1.1 Factory Word Programming......................................................................57 11.2 Buffered Programming .......................................................................................57 11.3 Buffered Enhanced Factory Programming ..............................................................58 11.3.1 BEFP Requirements and Considerations .....................................................58 11.3.2 BEFP Setup Phase ...................................................................................59 11.3.3 BEFP Program/Verify Phase ......................................................................59 11.3.4 BEFP Exit Phase......................................................................................60 11.4 Program Suspend ..............................................................................................60 11.5 Program Resume ...............................................................................................60 11.6 Program Protection ............................................................................................61 12.0 Erase Operations......................................................................................................62 12.1 Block Erase .......................................................................................................62 12.2 Erase Suspend ..................................................................................................62 12.3 Erase Resume ...................................................................................................63 12.4 Erase Protection ................................................................................................63 13.0 Security Modes ........................................................................................................64 13.1 Block Locking ....................................................................................................64 13.1.1 Lock Block .............................................................................................64 13.1.2 Unlock Block ..........................................................................................64 13.1.3 Lock-Down Block ....................................................................................64 13.1.4 Block Lock Status ...................................................................................65 13.1.5 Block Locking During Suspend ..................................................................65 13.2 Selectable One-Time Programmable Blocks ...........................................................66 13.3 Protection Registers ...........................................................................................66 13.3.1 Reading the Protection Registers...............................................................67 13.3.2 Programming the Protection Registers .......................................................68 13.3.3 Locking the Protection Registers ...............................................................68 14.0 Special Read States..................................................................................................69 14.1 Read Status Register..........................................................................................69 14.1.1 Clear Status Register ..............................................................................70 14.2 Read Device Identifier ........................................................................................70 14.3 CFI Query .........................................................................................................71 A Write State Machine.................................................................................................72 B Flowcharts ...............................................................................................................79 C Common Flash Interface ..........................................................................................87 D Additional Information.............................................................................................97 E Ordering Information for Discrete Products .............................................................98 F Ordering Information for SCSP Products ..................................................................99 Datasheet 4 November 2007 Order Number: 306666-11 P30 Revision History Revision Date Revision April 2005 -001 Description Initial Release Revised discrete memory maps in Section 4.4, “Memory Maps” on page 22 Added memory maps for 512-Mbit top parameter devices in Section 4.4, “Memory Maps” on page 22 August 2005 -002 Fixed size of Programming Region for 256-Mbit to be 8-Mbit in Section 4.4, “Memory Maps” on page 22 and Section 11.0, “Programming Operations” on page 56 Removed power supply sequencing requirement in Section 8.1, “Power-Up and PowerDown” on page 41 Updated conditions for Table 15, “Capacitance” on page 29 Updated CFI table in Appendix C, “Common Flash Interface” Added note to Table 34, “Device ID codes” on page 71 for stacked Device ID codes Synchronous burst read operation is currently not supported for the TSOP package Updated 512-Mbit Easy BGA Ball Height (symbol A1) in Figure 2, “Easy BGA Mechanical September 2005 -003 November 2005 -004 Updated read access speed for 265M TSOP package February 2006 -005 Removed all references to 1 Gigabit. Specifications” on page 11 April 2006 -006 • • • • • • • • Added 52 MHz capabilities, Added TSOP Package information for 512 Mb throughout the document, Added Section 2.1, “Virtual Chip Enable Description” on page 8, Modified figures in Section 4.3, “Dual-Die Configurations” on page 21, Modified Table 9, “512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP)” on page 23, Modified Notes 5 & 6 to Reset Specifications table in Section 8.2, “Reset Specifications” on page 41, Added additional note on 512 Mb capability in Table 31, “Selectable OTP Block Mapping” on page 66. Updated the following tables to 52 MHz: Table 16, “AC Read Specifications for 64/ 128- Mbit Densities” on page 29 and Table 17, “AC Read Specifications for 256/512-Mbit Densities” on page 30. May 2006 -007 May-2006 -008 • Added notes 1, 2, and 3 to Table 15, “Capacitance” on page 29. June - 2007 -009 • • • • • • Correct typos and add clarifications Enabled specific burst operation on TSOP packages. Updated device commands table. Updaed description on synchronous burst operation. Added EOWL description. Updated flowcharts November 2007 -010 • • Updated for 65nm lithography Added W602 - Erase to Suspend November 2007 11 • Applied Numonyx branding. November 2007 Order Number: 306666-11 Datasheet 5 P30 1.0 Introduction This document provides information about the Numonyx™ StrataFlash® Embedded Memory (P30) product and describes its features, operation, and specifications. The Numonyx™ StrataFlash® Embedded Memory (P30) product is the latest generation of Numonyx™ StrataFlash® memory devices. Offered in 64-Mbit up through 512-Mbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, highspeed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronous-burst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices. The P30 product family is manufactured using Intel* 130 nm ETOX™ VIII process technology. The P30 product family is also planned on the Intel* 65nm process lithography. 65nm AC timing changes are noted in this datasheet, and should be taken into account for all new designs. 1.1 Nomenclature 1.8 V: VCC (core) voltage range of 1.7 V – 2.0 V 3.0 V: VCCQ (I/O) voltage range of 1.7 V – 3.6 V 9.0 V: VPP voltage range of 8.5 V – 9.5 V Block: A group of bits, bytes, or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The P30 has two block sizes: 32-KByte and 128-KByte. Main block: An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. Parameter block: An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Top parameter device: A device with its parameter blocks located at the highest physical address of its memory map. Bottom parameter device: A device with its parameter blocks located at the lowest physical address of its memory map. 1.2 Acronyms BEFP: Buffer Enhanced Factory Programming CUI: Command User Interface MLC: Multi-Level Cell OTP: One-Time Programmable PLR: Protection Lock Register PR: Protection Register RCR: Read Configuration Register Datasheet 6 November 2007 Order Number: 306666-11 P30 RFU: Reserved for Future Use SR: Status Register WSM: Write State Machine 1.3 Conventions VCC: Signal or voltage connection VCC: Signal or voltage level 0x: Hexadecimal number prefix 0b: Binary number prefix SR[4]: Denotes an individual register bit. A[15:0]: Denotes a group of similarly named signals, such as address or data bus. A5: Denotes one element of a signal group membership, such as an individual address bit. Bit: Binary unit Byte: Eight bits Word: Two bytes, or sixteen bits Kbit: 1024 bits KByte: 1024 bytes KWord: 1024 words Mbit: 1,048,576 bits MByte: 1,048,576 bytes MWord: 1,048,576 words November 2007 Order Number: 306666-11 Datasheet 7 P30 2.0 Functional Overview This section provides an overview of the features and capabilities of the P30. The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power up or return from reset, the device defaults to asynchronous pagemode read. Configuring the Read Configuration Register enables synchronous burstmode reads. In synchronous burst mode, output data is synchronized with a usersupplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for lowvoltage systems, the P30 supports read operations with VCC at 1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the fastest flash array programming performance with VPP at 9.0 V, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP ≤ VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (16 bits). The P30 protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable (OTP). 2.1 Virtual Chip Enable Description The P30 512Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and TSOP packages. (Refer to Figure 9 on page 21 and Figure 10 on page 21). Address A24 (Quad+ package) or A25 (Easy BGA and TSOP packages) is then used to select between the die pair with F1-CE# / CE# asserted depending upon the package option used. When chip enable is asserted and QUAD+ A24 (Easy BGA/TSOP A25) is low (VIL), The lower parameter die is selected; when chip enable is asserted and QUAD+ A24 (Easy BGA/TSOP A25) is high (VIH), the upper parameter die is selected. Refer to Table 1 and Table 2 for additional details. Table 1: Virtual Chip Enable Truth Table for 512 Mb (QUAD+ Package) Die Selected F1-CE# A24 Lower Param Die L L Upper Param Die L H Datasheet 8 November 2007 Order Number: 306666-11 P30 Table 2: Virtual Chip Enable Truth Table for 512 Mb (Easy BGA & TSOP Packages) Die Selected CE# A25 Lower Param Die L L Upper Param Die L H November 2007 Order Number: 306666-11 Datasheet 9 P30 3.0 Package Information 3.1 56-Lead TSOP Figure 1: TSOP Mechanical Specifications Z A2 See Note 2 See Notes 1 and 3 Pin 1 e See Detail B E Y D1 A1 D Seating Plane See Detail A A Detail A Detail B C 0 b L [231369-90] Table 3: TSOP Package Dimensions (Sheet 1 of 2) Millimeters Product Information Inches Symbol Notes Min Nom Max Min Nom Max A - - 1.200 - - 0.047 Standoff A1 0.050 - - 0.002 - - Package Body Thickness A2 0.965 0.995 1.025 0.038 0.039 0.040 Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008 Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008 Package Body Length D1 18.200 18.400 18.600 0.717 0.724 0.732 Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559 Package Height Lead Pitch e - 0.500 - - 0.0197 - Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795 Datasheet 10 November 2007 Order Number: 306666-11 P30 Table 3: TSOP Package Dimensions (Sheet 2 of 2) Millimeters Product Information Inches Symbol Notes Min Nom Max Min Nom Max 0.500 0.600 0.700 0.020 0.024 0.028 Lead Tip Length L Lead Count N - 56 - - 56 - Lead Tip Angle ý 0° 3° 5° 0° 3° 5° Seating Plane Coplanarity Y - - 0.100 - - 0.004 Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014 Notes: 1. 2. 3. 4. One dimple on package denotes Pin 1. If two dimples, then the larger dimple denotes Pin 1. Pin 1 will always be in the upper left corner of the package, in reference to the product mark. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://developer.Numonyx.com/design/flash/packtech. 3.2 64-Ball Easy BGA Package Figure 2: Easy BGA Mechanical Specifications Ball A1 Corner D 1 E Ball A1 Corner 2 3 4 S1 5 6 7 8 8 A A B B C C D D E E F F G G H H Top View - Ball side down 7 6 5 4 3 2 1 S2 b e Bottom View - Ball Side Up A1 A2 A Seating Plane Y Note: Drawing not to scale November 2007 Order Number: 306666-11 Datasheet 11 P30 Table 4: Easy BGA Package Dimensions Millimeters Product Information Package Height (64/128/256-Mbit) Package Height (512-Mbit) Inches Symbol A Notes Min Nom Max Min Nom Max - - 1.200 - - 0.0472 A - - 1.300 - - 0.0512 Ball Height A1 0.250 - - 0.0098 - - Package Body Thickness (64/128/256Mbit) A2 - 0.780 - - 0.0307 - Package Body Thickness (512-Mbit) A2 - 0.910 - - 0.0358 - Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976 E 12.900 13.000 13.100 0.5079 0.5118 0.5157 [e] - 1.000 - - 0.0394 - Package Body Length Pitch Ball (Lead) Count N - 64 - - 64 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630 Corner to Ball A1 Distance Along E S2 2.900 3.000 3.100 0.1142 0.1181 0.1220 Notes: 1. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology http://developer.Numonyx.com/design/flash/packtech. Datasheet 12 November 2007 Order Number: 306666-11 P30 3.3 Figure 3: QUAD+ SCSP Packages 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index Mark S1 1 2 3 4 5 6 7 8 8 A A B B C C D D E E F D 7 6 5 4 3 2 1 S2 F G G H H J J K K L L M M e b E Top View - Ball Down A2 Bottom View - Ball Up A1 A Y D raw ing not to sc ale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D November 2007 Order Number: 306666-11 Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 9.900 7.900 1.100 0.500 Millimeters Nom Max 1.200 0.860 0.375 0.425 10.000 10.100 8.000 8.100 0.800 88 0.100 1.200 1.300 0.600 0.700 Min 0.0079 0.0128 0.3898 0.3110 0.0433 0.0197 Inches Nom 0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 Max 0.0472 0.0167 0.3976 0.3189 0.0039 0.0512 0.0276 Datasheet 13 P30 Figure 4: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm) S1 A 1 Index Mark 1 2 3 4 5 6 7 8 8 A A B B C C D D E E F D 7 6 5 4 3 2 1 S2 F G G H H J K K e J L L M M b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y D raw ing not to scale. Note: Dimensions A1, A2, and b are preliminary Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet 14 Symbol A A1 A2 b D E e N Y S1 S2 Min 0.117 0.300 10.900 7.900 1.100 1.000 Millimeters Nom Max 1.000 0.740 0.350 0.400 11.00 11.100 8.00 8.100 0.80 88 0.100 1.200 1.300 1.100 1.200 Min 0.0046 0.0118 0.4291 0.3110 0.0433 0.0394 Inches Nom 0.0291 0.0138 0.4331 0.3150 0.0315 88 0.0472 0.0433 Max 0.0394 0.0157 0.4370 0.3189 0.0039 0.0512 0.0472 November 2007 Order Number: 306666-11 P30 Figure 5: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm) S1 A 1 Index Mark 1 2 3 4 5 6 7 8 8 A A B B C C D D 7 6 5 4 3 2 1 S2 E E F D F G G H H J K K e J L L M M b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y D raw ing not to scale . Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D November 2007 Order Number: 306666-11 Symbol A A1 A2 b D E e N Y S1 S2 Min 0.200 0.325 10.900 7.900 1.100 1.000 Millimeters Nom Max 1.200 0.860 0.375 0.425 11.000 11.100 8.000 8.100 0.800 88 0.100 1.200 1.300 1.100 1.200 Min 0.0079 0.0128 0.4291 0.3110 0.0433 0.0394 Inches Nom 0.0339 0.0148 0.4331 0.3150 0.0315 88 0.0472 0.0433 Max 0.0472 0.0167 0.4370 0.3189 0.0039 0.0512 0.0472 Datasheet 15 P30 4.0 Ballout and Signal Descriptions 4.1 Signal Ballout Figure 6: 56-Lead TSOP Pinout (64/128/256/512- Mbit) A16 A15 A14 A13 A12 A11 A10 A9 A23 A22 A21 VSS VCC WE# WP# A20 A19 A18 A8 A7 A6 A5 A4 A3 A2 A24 A25 VSS Notes: 1. 2. 3. 4. 5. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Intel StrataFlash® Embedded Memory (P30) 56-Lead TSOP Pinout 14 mm x 20 mm Top View 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WAIT A17 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 ADV# CLK RST# VPP DQ11 DQ3 DQ10 DQ2 VCCQ DQ9 DQ1 DQ8 DQ0 VCC OE# VSS CE# A1 A1 is the least significant address bit. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC). A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC). Please refer to the latest specification update for synchronous read operation with the TSOP package. The synchronous read input signals (i.e. ADV# and CLK) should be tied off to support asynchronous reads. See Section 4.2, “Signal Descriptions” on page 19. Datasheet 16 November 2007 Order Number: 306666-11 P30 Figure 7: 64-Ball Easy BGA Ballout (64/128/256/512-Mbit) 1 2 3 4 5 6 7 8 8 7 A1 A6 A8 VPP A13 VCC A18 A22 A22 A18 A2 VSS A9 CE# A14 A25 A19 RFU RFU A3 A7 A10 A12 A15 WP# A20 A21 A4 A5 A11 RST# VCCQ VCCQ A16 A17 6 5 4 3 2 1 VCC A13 VPP A8 A6 A1 A19 A25 A14 CE# A9 VSS A2 A21 A20 WP# A15 A12 A10 A7 A3 A17 A16 VCCQ VCCQ RST# A11 A5 A4 A A B B C C D D E E DQ4 DQ3 DQ9 DQ1 DQ8 RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE# OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU A23 RFU WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23 RFU VSS VCC VSS DQ13 VSS DQ7 A24 DQ13 VSS VCC VSS RFU DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU RFU DQ15 CLK F F G G DQ2 VCCQ DQ5 DQ6 DQ14 WE# H H Easy BGA Top View- Ball side down Notes: 1. 2. 3. 4. A24 DQ7 VSS Easy BGA Bottom View- Ball side up A1 is the least significant address bit. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC). A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC). November 2007 Order Number: 306666-11 Datasheet 17 P30 Figure 8: 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin 1 Notes: 1. 2. 3. 4. 1 2 3 4 5 6 7 8 A DU DU Depop Depop Depop Depop DU DU A B A4 A18 A19 VSS VCC VCC A21 A11 B C A5 RFU A23 VSS RFU CLK A22 A12 C D A3 A17 A24 VPP RFU RFU A9 A13 D E A2 A7 RFU WP# ADV# A20 A10 A15 E F A1 A6 RFU RST# WE# A8 A14 A16 F G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G H RFU DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H J RFU F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J K F1-CE# RFU RFU RFU RFU VCC VCCQ RFU K L VSS VSS VCCQ VCC VSS VSS VSS VSS L M DU DU Depop Depop Depop Depop DU DU M 1 2 3 4 5 6 7 8 A22 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). A23 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC). A24 is valid for 512-Mbit densities and above; otherwise, it is a no connect (NC). F2-CE# and F2-OE# are no connect (NC) for all densities. Datasheet 18 November 2007 Order Number: 306666-11 P30 4.2 Signal Descriptions This section has signal descriptions for the various P30 packages. Table 5: Symbol TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2) Type Name and Function A[MAX:1] Input ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1]; 512-Mbit: A[25:1]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the dual-die 512-Mbit configuration is accomplished by setting A[25] high (VIH). DQ[15:0] Input/ Output DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are deasserted. Data is internally latched during writes. Input ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. Input FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. WARNING: Chip enable must be driven high when device is not in use. CLK Input CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. OE# Input OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read cycles. OE# high places the data outputs and WAIT in High-Z. RST# Input RESET: Active low input. RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST# high enables normal operation. Exit from reset places the device in asynchronous read array mode. ADV# CE# WAIT Output WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is VOL or VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH. • In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. • In asynchronous page mode, and all write modes, WAIT is deasserted. WE# Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#. WP# Input WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lockdown cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. VPP Power/ Input Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages should not be attempted. Set VPP = VPPL for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL min to perform in-system flash modification. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. VCC Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted. VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. November 2007 Order Number: 306666-11 Datasheet 19 P30 Table 5: Symbol TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2) Type Name and Function RFU — Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement. These should be treated in the same way as a Do Not Use (DU) signal. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated. Table 6: Symbol QUAD+ SCSP Signal Descriptions (Sheet 1 of 2) Type Name and Function A[MAX:0] Input ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0]; 512-Mbit: A[24:0]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the dual-die 512-Mbit configuration is accomplished by setting A[25] high (VIH). DQ[15:0] Input/ Output DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are deasserted. Data is internally latched during writes. Input ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. F1-CE# Input FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. WARNING: Chip enable must be driven high when device is not in use. CLK Input CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. F1-OE# Input OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read cycles. OE# high places the data outputs and WAIT in High-Z. RST# Input RESET: Active low input. RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST# high enables normal operation. Exit from reset places the device in asynchronous read array mode. ADV# WAIT Output WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is VOL or VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH. • In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. • In asynchronous page mode, and all write modes, WAIT is deasserted. WE# Input WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#. WP# Input WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lockdown cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. VPP Datasheet 20 Power/ lnput Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP ≤ VPPLK . Block erase and program at invalid VPP voltages should not be attempted. Set VPP = VPPL for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL min to perform in-system flash modification. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. November 2007 Order Number: 306666-11 P30 Table 6: Symbol QUAD+ SCSP Signal Descriptions (Sheet 2 of 2) Type Name and Function VCC Power Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted. VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. RFU — Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement. These should be treated in the same way as a Do Not Use (DU) signal. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated. 4.3 Dual-Die Configurations Figure 9: 512-Mbit Easy BGA and TSOP Top or Bottom Parameter Block Diagram Easy BGA & TSOP 512-Mbit (Dual-Die) Top or Bottom Parameter Configuration CE# Top Param Die (256-Mbit) WP# OE# WE# RST# VCC VPP VCCQ VSS CLK ADV# Bottom Param Die (256-Mbit) A[MAX:1] DQ[15:0] WAIT Figure 10: 512-Mbit QUAD+ SCSP Top or Bottom Parameter Block Diagram QUAD+ 512-Mbit (Dual-Die) Top or Bottom Parameter Configuration F1-CE# WP# Top Param Die (256-Mbit) OE# VCCQ CLK ADV# VSS Bottom Param Die (256-Mbit) Note: VCC VPP WE# A[MAX:0] RST# DQ[15:0] WAIT Amax = Vih selects the Top parameter Die; Amax = Vil selects the Bottom Parameter Die. November 2007 Order Number: 306666-11 Datasheet 21 P30 4.4 Memory Maps Table 7 through Table 9 show the P30 memory maps. The memory array is divided into multiple 8-Mbit Programming Regions (see Section 11.0, “Programming Operations” on page 56). 66 3FC000 - 3FFFFF 32 130 7FC000 - 7FFFFF 780000 - 78FFFF 128 119 770000 - 77FFFF 128 118 760000 - 76FFFF 360000 - 36FFFF 010000 - 01FFFF 128 0 000000 - 00FFFF Size (KB) Blk 256-Mbit 32 258 FFC000 - FFFFFF FF0000 - FF3FFF 128 254 FE0000 - FEFFFF 248 F80000 - F8FFFF 128 247 F70000 - F7FFFF 128 246 F60000 - F6FFFF ... 128 ... ... 255 ... 32 ... ... 1 ... 128 ... ... 370000 - 37FFFF 54 ... 55 ... 128 128 128 1 010000 - 01FFFF 128 0 000000 - 00FFFF ... 120 ... 128 ... 380000 - 38FFFF Fifteen Programming Regions ... 7E0000 - 7EFFFF ... 7F0000 - 7F3FFF 126 56 128 1 010000 - 01FFFF 128 0 000000 - 00FFFF Discrete Bottom Parameter Memory Maps (all packages) 64-Mbit Size (KB) Blk 128 130 7F0000 - 7FFFFF 128 129 7E0000 - 7EFFFF 12 090000 - 09FFFF 128 11 080000 - 08FFFF ... 128 ... 3F0000 - 3FFFFF 3E0000 - 3EFFFF ... 66 65 ... 128 128 128-Mbit ... Blk ... Seven Programming Regions 127 128 Size (KB) Datasheet 22 32 128 ... 3E0000 - 3EFFFF ... 3F0000 - 3F3FFF 62 ... 63 ... 32 128 ... 32 ... 128-Mbit ... Blk One Programming Region Size (KB) ... 64-Mbit ... Blk ... Size (KB) Fifteen Programming Regions Table 8: Discrete Top Parameter Memory Maps (all packages) ... Thirty-One Programming Regions One Programming Region Seven Programming Regions One Programming Region Table 7: 128 12 090000 - 09FFFF 128 11 080000 - 08FFFF November 2007 Order Number: 306666-11 P30 10 070000 - 07FFFF 128 10 070000 - 07FFFF ... ... 00C000 - 00FFFF 000000 - 003FFF Size (KB) Blk 256-Mbit 128 258 FF0000 - FFFFFF 128 257 FE0000 - FEFFFF 11 080000 - 08FFFF 128 10 070000 - 07FFFF ... 128 128 4 010000 - 01FFFF 32 3 00C000 - 00FFFF ... 090000 - 09FFFF ... 12 ... 128 ... ... 0 ... 32 ... ... 010000 - 01FFFF 3 ... 4 32 ... 128 32 0 000000 - 003FFF ... 128 128 4 010000 - 01FFFF 32 3 00C000 - 00FFFF ... 128-Mbit ... Blk ... Size (KB) ... 64-Mbit ... Blk One Programming Region Size (KB) ... Discrete Bottom Parameter Memory Maps (all packages) ... One Programming Region Thirty-One Programming Regions One Programming Region Table 8: 32 0 000000 - 003FFF Block size is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in KWords where a Word is the size of the flash output bus (16 bits). Note: The Dual- Die P30 memory maps are the same for both parameter options because the devices employ virtual chip enable (Refer to Section 2.1). The parameter option only defines the placement of bottom parameter die. Table 9: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP) (Sheet 1 of 2) 512-Mbit Flash (2x256-Mbit w/ 1CE) Die Stack Config Size (KB) Blk Address Range 32 517 1FFC000 - 1FFFFFF ... ... ... 256-Mbit 32 514 1FF0000 - 1FF3FFF Top Parameter Die 128 513 1FE0000 - 1FEFFFF ... ... ... November 2007 Order Number: 306666-11 128 259 1000000 - 100FFFF 128 258 FF0000 - FFFFFF Datasheet 23 P30 Table 9: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP) (Sheet 2 of 2) 512-Mbit Flash (2x256-Mbit w/ 1CE) Size (KB) Blk ... ... 256-Mbit 128 4 010000 - 01FFFF Bottom Parameter Die 32 3 00C000 - 00FFFF ... ... ... 32 0 000000 - 003FFF Address Range ... Note: Die Stack Config Refer to the appropriate 256-Mbit Memory Map (Table 7 or Table 8) for Programming Region information; Block size is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-Words where a Word is the size of the flash output bus (16 bits). Datasheet 24 November 2007 Order Number: 306666-11 P30 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 10: Parameter Maximum Rating Temperature under bias Notes –40 °C to +85 °C Storage temperature –65 °C to +125 °C Voltage on any signal (except VCC, VPP and VCCQ) –0.5 V to +4.1 V 1 VPP voltage –0.2 V to +10 V 1,2,3 VCC voltage –0.2 V to +2.5 V 1 VCCQ voltage –0.2 V to +4.1 V 1 100 mA 4 Output short circuit current Notes: 1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods less than 20 ns. Maximum DC voltage on VCC is VCC + 0.5 V, which, during transitions, may overshoot to VCC + 2.0 V for periods less than 20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ + 0.5 V, which, during transitions, may overshoot to VCCQ + 2.0 V for periods less than 20 ns. 2. Maximum DC voltage on VPP may overshoot to +11.5 V for periods less than 20 ns. 3. Program/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5.2 Note: Operating Conditions Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Table 11: Operating Conditions Symbol TC VCC Parameter Operating Temperature VCC Supply Voltage Min Max Units Notes –40 +85 °C 1 1.7 2.0 CMOS inputs 1.7 3.6 TTL inputs 2.4 3.6 0.9 3.6 VCCQ I/O Supply Voltage VPPL VPP Voltage Supply (Logic Level) VPPH Factory word programming VPP 8.5 9.5 tPPH Maximum VPP Hours VPP = VPPH - 80 Main and Parameter Blocks VPP = VPPL 100,000 - Main Blocks VPP = VPPH - 1000 Parameter Blocks VPP = VPPH - 2500 Block Erase Cycles 3 V Hours 2 Cycles Notes: 1. TC = Case Temperature. 2. In typical operation VPP program voltage is VPPL. 3. 40Mhz burst operation on the TSOP package has a min Vcc value of 1.85V. Please refer to the latest Specification Update regarding synchronous burst operation with the TSOP package November 2007 Order Number: 306666-11 Datasheet 25 P30 6.0 Electrical Specifications 6.1 DC Current Characteristics Table 12: DC Current Characteristics (Sheet 1 of 2) Sym Parameter ILI Input Load Current ILO Output Leakage Current ICCS, ICCD DQ[15:0], VCC Standby, Power Down ICCWS, ICCES - ±2 µA VCC = VCCMax VCCQ = VCCQ Max VIN = VCCQ or VSS µA VCC = VCCMax VCCQ = VCCQ Max VIN = VCCQ or VSS µA VCC = VCCMax VCCQ = VCCQ Max CE# = VCCQ RST# = VCCQ (for ICCS) RST# = VSS (for ICCD ) WP# = VIH 20 35 128-Mbit 30 75 30 75 256-Mbit 55 115 55 200 512-Mbit 110 230 110 400 14 16 14 16 mA 1-Word Read 9 10 9 10 mA 4-Word Read 13 17 n/a n/a mA BL = 4W 15 19 n/a n/a mA BL = 8W 17 21 n/a n/a mA BL = 16W 21 26 n/a n/a mA BL = Cont. 16 19 n/a n/a mA BL = 4W 19 23 n/a n/a mA BL = 8W 22 26 n/a n/a mA BL = 16W 23 28 n/a n/a mA 36 51 36 51 CE# = VCCQ; suspend in progress 1,3,4 VPP = VPPL, suspend in progress 1,3 VPP = VPPL 1,3 35 128-Mbit 30 75 30 75 256-Mbit 55 115 55 200 512-Mbit 110 230 110 400 0.2 5 0.2 5 µA µA 15 2 15 0.05 0.10 8 22 8 22 BL = Cont. µA 33 20 0.10 1 1,3,5 26 35 2 1,2 VPP = VPPH, pgm/ers in progress 33 20 0.05 1 1,3,5 mA 26 VPP Read VCC = VCCMax CE# = VIL OE# = VIH Inputs: VIL or VIH Notes VPP = VPPL, pgm/ers in progress 64-Mbit IPPR Datasheet 26 ±1 35 VCC Program Current, VCC Erase Current VPP Program Current - 20 IPPES IPPW Max 64-Mbit VPP Standby Current, VPP Program Suspend Current, VPP Erase Suspend Current IPPS, IPPWS, Typ ±10 Synchronous Burst f = 40 MHz VCC Program Suspend Current, VCC Erase Suspend Current Max Test Conditions - Synchronous Burst f = 52MHz ICCW, ICCE Typ Unit ±1 Page-Mode Read f = 13 MHz (5 CLK) ICCR TTL Inputs (V CCQ = 2.4 V - 3.6 V) - WAIT Asynchronous SingleWord f = 5 MHz (1 CLK) Average VCC Read Current CMOS Inputs (VCCQ = 1.7 V - 3.6 V) mA VPP = VPPL, program in progress VPP = VPPH, program in progress November 2007 Order Number: 306666-11 P30 Table 12: DC Current Characteristics (Sheet 2 of 2) Sym IPPE Notes: 1. 2. 3. 4. 5. 6.2 Parameter VPP Erase Current CMOS Inputs (VCCQ = 1.7 V - 3.6 V) TTL Inputs (VCCQ = 2.4 V - 3.6 V) Typ Max Typ Max 0.05 0.10 0.05 0.10 8 22 8 22 Unit mA Test Conditions Notes VPP = VPPL, erase in progress VPP = VPPH, erase in progress All currents are RMS unless noted. Typical values at typical VCC , TC = +25 °C. ICCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted. Sampled, not 100% tested. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR. ICCW, ICCE measured over typical or max times specified in Section 7.5, “Program and Erase Characteristics” on page 39. DC Voltage Characteristics Table 13: DC Voltage Characteristics Sym Parameter CMOS Inputs (VCCQ = 1.7 V – 3.6 V) TTL Inputs (1) (VCCQ = 2.4 V – 3.6 V) Min Max Min Max Unit Test Condition VIL Input Low Voltage 0 0.4 0 0.6 V VIH Input High Voltage VCCQ – 0.4 V VCCQ 2.0 VCCQ V VOL Output Low Voltage - 0.1 - 0.1 V VCC = VCCMin VCCQ = VCCQMin IOL = 100 µA VOH Output High Voltage VCCQ – 0.1 - VCCQ – 0.1 - V VCC = VCCMin VCCQ = VCCQMin IOH = –100 µA VPPLK VPP Lock-Out Voltage - 0.4 - 0.4 V VLKO VCC Lock Voltage 1.0 - 1.0 - V VLKOQ VCCQ Lock Voltage 0.9 - 0.9 - V Notes 2 3 Notes: 1. Synchronous read mode is not supported with TTL inputs. 2. VIL can undershoot to –0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less. 3. VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges. November 2007 Order Number: 306666-11 Datasheet 27 P30 7.0 AC Characteristics 7.1 AC Test Conditions Figure 11: AC Input/Output Reference Waveform VCCQ Input VCCQ/2 Test Points VCCQ/2 Output 0V Note: IO_REF.WMF AC test inputs are driven at VCCQ for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin. Figure 12: Transient Equivalent Testing Load Circuit Device Under Test Out CL Notes: 1. See the following table for component values. 2. Test configuration component value for worst-case speed conditions. 3. CL includes jig capacitance. . Table 14: Test Configuration Component Value For Worst Case Speed Conditions Test Configuration CL (pF) VCCQMin Standard Test 30 Figure 13: Clock Input AC Waveform R201 CLK [C] VIH VIL R202 Datasheet 28 R203 November 2007 Order Number: 306666-11 P30 7.2 Capacitance Table 15: Capacitance Parameter Signals Min Typ Max Unit Input Capacitance Address, Data, CE#, WE#, OE#, RST#, CLK, ADV#, WP# 2 6 7 pF Output Capacitance Data, WAIT 2 4 5 pF Condition Notes Typ temp = 25 °C, Max temp = 85 °C, VCC = (0 V - 2.0 V), VCCQ = (0 V - 3.6 V), Discrete silicon die 1,2,3 Notes: 1. Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values by the number of dies in the stack. 2. Sampled, but not 100% tested. 3. Silicon die capacitance only; add 1 pF for discrete packages. 7.3 AC Read Specifications Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 1 of 2) Num Symbol Parameter Min Max Unit 85 - ns Notes Asynchronous Specifications R1 tAVAV Read cycle time R2 tAVQV Address to output valid - 85 ns R3 tELQV CE# low to output valid - 85 ns R4 tGLQV OE# low to output valid - 25 ns 1,2 R5 tPHQV RST# high to output valid - 150 ns 1 R6 tELQX CE# low to output in low-Z 0 - ns 1,3 R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 tEHQZ CE# high to output in high-Z - 24 ns R9 tGHQZ OE# high to output in high-Z - 24 ns R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 tEHEL CE# pulse width high 20 - ns R12 tELTV CE# low to WAIT valid - 17 ns R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3 R15 tGLTV 1 OE# low to WAIT valid - 17 ns R16 tGLTX OE# low to WAIT in low-Z 0 - ns R17 tGHTZ OE# high to WAIT in high-Z - 20 ns 1,3 1 1,3 Latching Specifications R101 tAVVH Address setup to ADV# high 10 - ns R102 tELVH CE# low to ADV# high 10 - ns R103 tVLQV ADV# low to output valid - 85 ns R104 tVLVH ADV# pulse width low 10 - ns R105 tVHVL ADV# pulse width high 10 - ns R106 tVHAX Address hold from ADV# high 9 - ns November 2007 Order Number: 306666-11 1 1,4 Datasheet 29 P30 Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 2 of 2) Num Symbol Parameter R108 tAPA Page address access R111 tphvh RST# high to ADV# high Min Max Unit - 25 ns 30 - ns - 52 MHz Notes 1 Clock Specifications R200 fCLK CLK frequency TSOP - 40 MHz 19.2 - ns 25 - ns R201 tCLK CLK period R202 tCH/CL CLK high/low time 5 - ns R203 tFCLK/RCLK CLK fall/rise time - 3 ns TSOP 1,3,5,6 (5,6) Synchronous Specifications R301 tAVCH/L Address setup to CLK 9 - ns R302 tVLCH/L ADV# low setup to CLK 9 - ns R303 tELCH/L CE# low setup to CLK 9 - ns R304 tCHQV / tCLQV CLK to output valid - 17 ns 1 R305 tCHQX Output hold from CLK 3 - ns 1,7 R306 tCHAX Address hold from CLK 10 - ns 1,4,7 R307 tCHTV CLK to WAIT valid - 17 ns 1,7 R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1 R312 tCHTX WAIT Hold from CLK 3 - ns 1,7 Notes: 1. See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX , whichever timing specification is satisfied first. 5. Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package. 6. Synchronous read mode is not supported with TTL level inputs. 7. Applies only to subsequent synchronous reads. Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 1 of 3) Num Symbol Parameter Speed Min Max VCC = 1.8 V – 2.0 85 - VCC = 1.7 V – 2.0 88 - Unit Notes Asynchronous Specifications V R1 tAVAV Read cycle time V 256/512-Mb TSOP packages R2 tAVQV Address to output valid - 85 VCC = 1.7 V – 2.0 - 88 - 95 V 256/512-Mb TSOP packages Datasheet 30 95 VCC = 1.8 V – 2.0 V ns ns November 2007 Order Number: 306666-11 P30 Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 2 of 3) Num Symbol Parameter Speed Min Max VCC = 1.8 V – 2.0 - 85 VCC = 1.7 V – 2.0 - 88 - 95 - 25 V R3 tELQV CE# low to output valid V 256/512-Mb TSOP packages Unit Notes ns R4 tGLQV OE# low to output valid ns R5 tPHQV RST# high to output valid - 150 ns 1 R6 tELQX CE# low to output in low-Z 0 - ns 1,3 R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 tEHQZ CE# high to output in high-Z - 24 ns R9 tGHQZ OE# high to output in high-Z - 24 ns R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 tEHEL CE# pulse width high 20 - ns R12 tELTV CE# low to WAIT valid - 17 ns R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3 R15 tGLTV OE# low to WAIT valid - 17 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns R17 tGHTZ OE# high to WAIT in high-Z - 20 ns 10 - ns ns 1,2 1,3 1 1,3 Latching Specifications R101 tAVVH Address setup to ADV# high R102 tELVH CE# low to ADV# high 10 - VCC = 1.8 V – 2.0 - 85 VCC = 1.7 V – 2.0 - 88 - 95 V R103 tVLQV ADV# low to output valid V 256/512-Mb TSOP packages ns R104 tVLVH ADV# pulse width low 10 - ns R105 tVHVL ADV# pulse width high 10 - ns R106 tVHAX Address hold from ADV# high 9 - ns R108 tAPA Page address access - 25 ns R111 tphvh RST# high to ADV# high 30 - ns - 52 MHz - 40 MHz 19.2 - ns 25 - ns 1 1,4 1 Clock Specifications R200 fCLK CLK frequency R201 tCLK CLK period R202 tCH/CL CLK high/low time 5 - ns R203 tFCLK/RCLK CLK fall/rise time - 3 ns TSOP Package TSOP Package 1,3,5,6 Synchronous Specifications(5,6) November 2007 Order Number: 306666-11 Datasheet 31 P30 Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 3 of 3) Num Symbol Parameter Speed Min Max Unit Notes R301 tAVCH/L Address setup to CLK 9 - ns R302 tVLCH/L ADV# low setup to CLK 9 - ns R303 tELCH/L CE# low setup to CLK 9 - ns R304 tCHQV / tCLQV CLK to output valid - 17 ns R305 tCHQX Output hold from CLK 3 - ns 1,7 R306 tCHAX Address hold from CLK 10 - ns 1,4,7 R307 tCHTV CLK to WAIT valid - 17 ns 1,7 R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1 R312 tCHTX WAIT Hold from CLK 3 - ns 1,7 1 Notes: 1. See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX , whichever timing specification is satisfied first. 5. Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package. 6. Synchronous read mode is not supported with TTL level inputs. 7. Applies only to subsequent synchronous reads. Table 18: AC Read Specification differences for 65nm Num Symbol Parameter Min Max Unit Notes 100 - ns 2 ns 2 ns 2 Asynchronous Specifications R1 R2 R3 R103 tAVAV tAVQV tELQV Read cycle time Address to output valid CE# low to output valid TSOP - 100 110 ns 2 - 100 ns 2 110 ns 2 - 100 ns 1,2 110 ns 2 TSOP TSOP tVLQV ADV# low to output valid 110 TSOP Notes: 1. See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew rate. 2. This is the recommended specification for all new designs supporting both 130nm and 65nm lithos, or for new designs that will use the 65nm lithography. Datasheet 32 November 2007 Order Number: 306666-11 P30 Figure 14: Asynchronous Single-Word Read (ADV# Low) R1 R2 Address [A] ADV# R3 R8 CE# [E} R4 R9 OE# [G] R15 R17 WAIT [T] R7 R6 Data [D/Q] R5 RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 15: Asynchronous Single-Word Read (ADV# Latch) R1 R2 Address [A] A[1:0][A] R101 R105 R106 ADV# R3 R8 CE# [E} R4 R9 OE# [G] R15 R17 WAIT [T] R7 R6 R10 Data [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). November 2007 Order Number: 306666-11 Datasheet 33 P30 Figure 16: Asynchronous Page-Mode Read Timing R1 R2 A[Max:2] [A] A[1:0] R101 R105 R106 ADV# R3 R8 CE# [E] R4 R10 OE# [G] R15 R17 WAIT [T] R7 R9 R108 DATA [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 17: Synchronous Single-Word Array or Non-array Read Timing R301 R306 CLK [C] R2 Address [A] R101 R106 R105 R104 ADV# [V] R303 R102 R3 R8 CE# [E] R7 R9 OE# [G] R15 R307 R312 R17 WAIT [T] R4 R304 R305 Data [D/Q] 1. 2. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Datasheet 34 November 2007 Order Number: 306666-11 P30 Figure 18: Continuous Burst Read, Showing An Output Delay Timing R301 R302 R306 R304 R304 R304 CLK [C] R2 R101 Address [A] R106 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 R307 R312 WAIT [T] R304 R4 R7 R305 R305 R305 R305 Data [D/Q] Notes: 1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. Figure 19: Synchronous Burst-Mode Four-Word Read Timing y R302 R301 R306 CLK [C] R2 Address [A] R101 A R105 R102 R106 ADV# [V] R303 R3 R8 CE# [E] R9 OE# [G] R15 R17 R307 WAIT [T] R4 R7 Data [D/Q] Note: R304 R304 R305 Q0 R10 Q1 Q2 Q3 WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low). November 2007 Order Number: 306666-11 Datasheet 35 P30 7.4 AC Write Specifications Table 19: AC Write Specifications Num Symbol Parameter Min Max Unit Notes 150 - ns 1,2,3 W1 tPHWL RST# high recovery to WE# low W2 tELWL CE# setup to WE# low 0 - ns 1,2,3 W3 tWLWH WE# write pulse width low 50 - ns 1,2,4 W4 tDVWH Data setup to WE# high 50 - ns W5 tAVWH Address setup to WE# high 50 - ns W6 tWHEH CE# hold from WE# high 0 - ns W7 tWHDX Data hold from WE# high 0 - ns W8 tWHAX Address hold from WE# high 0 - ns W9 tWHWL WE# pulse width high 20 - ns 200 - ns 0 - ns W10 tVPWH VPP setup to WE# high W11 tQVVL VPP hold from Status read W12 tQVBL WP# hold from Status read W13 tBHWH WP# setup to WE# high W14 tWHGL WE# high to OE# low W16 tWHQV WE# high to read valid 0 - ns 200 - ns 1,2 1,2,5 1,2,3,7 1,2,3,7 0 - ns 1,2,9 tAVQV + 35 - ns 1,2,3,6,10 0 - ns 1,2,3,6,8 Write to Asynchronous Read Specifications W18 tWHAV WE# high to Address valid Write to Synchronous Read Specifications W19 tWHCH/L WE# high to Clock valid 19 - ns W20 tWHVH WE# high to ADV# high 19 - ns 1,2,3,6,10 Write Specifications with Clock Active W21 tVHWL ADV# high to WE# low - 20 ns W22 tCHWL Clock high to WE# low - 20 ns Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 1,2,3,11 Write timing characteristics during erase suspend are the same as write-only operations. A write operation can be terminated with either CE# or WE#. Sampled, not 100% tested. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL). tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read. VPP and WP# should be at a valid level until erase or program success is determined. This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and W20 for synchronous read. When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns. Add 10 ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to reflect this change. These specs are required only when the device is in a synchronous mode and clock is active during address setup phase. Datasheet 36 November 2007 Order Number: 306666-11 P30 Figure 20: Write-to-Write Timing W5 W8 W5 W8 Address [A] W2 W6 W2 W6 CE# [E} W3 W9 W3 WE# [W] OE# [G] W4 W7 W4 W7 Data [D/Q] W1 RST# [P] Figure 21: Asynchronous Read-to-Write Timing R1 R2 W5 W8 Address [A] R3 R8 CE# [E} R4 R9 OE# [G] W2 W3 W6 WE# [W] R15 R17 WAIT [T] R7 W7 R6 Data [D/Q] R10 Q W4 D R5 RST# [P] Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. November 2007 Order Number: 306666-11 Datasheet 37 P30 Figure 22: Write-to-Asynchronous Read Timing W5 W8 R1 Address [A] ADV# [V] W2 W6 R10 CE# [E} W3 W18 WE# [W] W14 OE# [G] R15 R17 WAIT [T] R4 W4 R2 R3 W7 Data [D/Q] R8 R9 D Q W1 RST# [P] Figure 23: Synchronous Read-to-Write Timing Latency Count R301 R302 R306 CLK [C] R2 W5 R101 W18 Address [ A] R105 R102 R106 R104 ADV# [ V] R303 R11 R13 R3 W6 CE# [E] R4 R8 OE# [G] W 21 W 22 W15 W 21 W22 W2 W8 W3 W9 WE# R16 R307 R312 WAIT [T] R304 R7 Data [D/Q] Note: R305 Q W7 D D WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). Clock is ignored during write operation. Datasheet 38 November 2007 Order Number: 306666-11 P30 Figure 24: Write-to-Synchronous Read Timing R302 R301 R2 CLK W5 W8 R306 Address [A] R106 R104 ADV# W6 R303 W2 R11 CE# [E} W18 W19 W20 W3 WE# [W] R4 OE# [G] R15 R307 WAIT [T] W7 R304 W4 R305 R304 R3 D Data [D/Q] Q Q W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). 7.5 Program and Erase Characteristics Table 20: Num Symbol V PPH VPPL Parameter Min Typ Max Min Typ Max Units Notes µs 1 µs 1 Conventional Word Programming W200 tPROG/W Program Time Single word - 130nm - 90 200 - 85 190 Single word - 65nm - 125 150 - 125 150 Single cell - 30 60 - 30 60 Buffered Programming W200 tPROG/W W251 tBUFF W451 tBEFP/W W452 tBEFP/Setup Program Time Single word - 90 200 - 85 190 32-word buffer - 440 880 - 340 680 Buffered Enhanced Factory Programming Program Single word BEFP Setup n/a n/a n/a - 10 - n/a n/a n/a 5 - - µs 1,2 1 Erasing and Suspending November 2007 Order Number: 306666-11 Datasheet 39 P30 Table 20: Num Symbol W500 tERS/PB W501 tERS/MB W600 tSUSP/P W601 tSUSP/E W602 tERS/SUSP Erase Time Suspend Latency VPPH VPPL Parameter Units Min Typ Max Min Typ Max 32-KByte Parameter - 0.4 2.5 - 0.4 2.5 128-KByte Main - 1.2 4.0 - 1.0 4.0 Program suspend - 20 25 - 20 25 Erase suspend - 20 25 - 20 25 Erase to Suspend - 500 - - 500 - Notes s 1 µs 1,3 Notes: Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system 1. overhead. Sampled, but not 100% tested. 2. Averaged over entire device. 3. W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend command. Violating the specification repeatedly during any particular block erase may cause erase failures. Datasheet 40 November 2007 Order Number: 306666-11 P30 8.0 Power and Reset Specifications 8.1 Power-Up and Power-Down Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise VCC and VCCQ should attain their minimum operating voltage before applying VPP. Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions. 8.2 Reset Specifications Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. Table 21: Num Symbol P1 tPLPH P2 tPLRH P3 Notes: 1. 2. 3. 4. 5. 6. 7. tVCCPH Parameter RST# pulse width low Min Max Unit Notes 100 - ns 1,2,3,4 RST# low to device reset during erase - 25 RST# low to device reset during program - 25 VCC Power valid to RST# de-assertion (high) 130nm 60 - VCC Power valid to RST# de-assertion (high) 65nm 300 - 1,3,4,7 µs 1,3,4,7 1,4,5,6 1,4,5,6 These specifications are valid for all device versions (packages and speeds). The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed. Not applicable if RST# is tied to Vcc. Sampled, but not 100% tested. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing. November 2007 Order Number: 306666-11 Datasheet 41 P30 Figure 25: Reset Operation Waveforms P1 (A) Reset during read mode RST# [P] VIH VIL P2 (B) Reset during program or block erase P1 ≤ P2 RST# [P] RST# [P] Abort Complete R5 VIH VIL P2 (C) Reset during program or block erase P1 ≥ P2 R5 Abort Complete R5 VIH VIL P3 (D) VCC Power-up to RST# high 8.3 VCC VCC 0V Power Supply Decoupling Flash memory devices require careful power supply de-coupling. Three basic power supply current considerations are 1) standby current levels, 2) active current levels, and 3) transient peaks produced when CE# and OE# are asserted and deasserted. When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Numonyx Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be placed between power and ground close to the devices. The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance. Datasheet 42 November 2007 Order Number: 306666-11 P30 9.0 Device Operations This section provides an overview of device operations. The system CPU provides control of all in-system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase and wordprogram algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 9.1 Bus Operations CE# low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed block. ADV# low opens the internal address latches. OE# low activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# goes high or continuously flows through if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL). Bus cycles to/from the P30 device conform to standard microprocessor bus operations. Table 22 summarizes the bus operations and the logic levels that must be applied to the device control signal inputs. Table 22: Bus Operations Summary Bus Operation Read RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0 ] Asynchronous VIH X L L L H Deasserted Output Synchronous VIH Running L L L H Driven Output Notes Write VIH X L L H L High-Z Input 1 Output Disable VIH X X L H H High-Z High-Z 2 Standby VIH X X H X X High-Z High-Z 2 Reset VIL X X X X X High-Z High-Z 2,3 Notes: 1. Refer to the Table 23, “Command Bus Cycles” on page 45 for valid DQ[15:0] during a write operation. 2. X = Don’t Care (H or L). 3. RST# must be at VSS ± 0.2 V to meet the maximum specified power-down current. 9.1.1 Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on page 48 for details on the available read modes, and see Section 14.0, “Special Read States” on page 69 for details regarding the available read states. November 2007 Order Number: 306666-11 Datasheet 43 P30 9.1.2 Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 23, “Command Bus Cycles” on page 45 shows the bus cycle sequence for each of the supported device commands, while Table 24, “Command Codes and Definitions” on page 46 describes each command. See Section 7.0, “AC Characteristics” on page 28 for signal-timing details. Note: 9.1.3 Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not be attempted. Output Disable When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a highimpedance (High-Z) state, WAIT is also placed in High-Z. 9.1.4 Standby When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby, average current is measured over the same time interval 5 μs after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 9.1.5 Reset As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Numonyx allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU. After initial power-up or reset, the device defaults to asynchronous Read Array mode, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state. Note: If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, “AC Characteristics” on page 28 for details about signal-timing. Datasheet 44 November 2007 Order Number: 306666-11 P30 9.2 Device Commands Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See Table 23, “Command Bus Cycles” on page 45. Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command. Table 23: Command Bus Cycles Mode Command Read Array Read Program Erase Suspend Block Locking/ Unlocking Protection Configuration Bus Cycles 1 First Bus Cycle Second Bus Cycle Oper Addr(1) Data(2) Oper Addr(1) Data (2) Write DnA 0xFF - - - Read Device Identifier ≥2 Write DnA 0x90 Read DBA + IA ID CFI Query ≥2 Write DnA 0x98 Read DBA + QA QD Read Status Register 2 Write DnA 0x70 Read DnA SRD Clear Status Register 1 Write DnA 0x50 - - - Word Program 2 Write WA 0x40/ 0x10 Write WA WD Buffered Program(3) >2 Write WA 0xE8 Write WA N-1 Buffered Enhanced Factory Program (BEFP)(4) >2 Write WA 0x80 Write WA 0xD0 2 Write BA 0x20 Write BA 0xD0 Block Erase Program/Erase Suspend 1 Write DnA 0xB0 - - - Program/Erase Resume 1 Write DnA 0xD0 - - - Lock Block 2 Write BA 0x60 Write BA 0x01 Unlock Block 2 Write BA 0x60 Write BA 0xD0 Lock-down Block 2 Write BA 0x60 Write BA 0x2F Program Protection Register 2 Write PRA 0xC0 Write PRA PD Program Lock Register 2 Write LRA 0xC0 Write LRA LRD Program Read Configuration Register 2 Write RCD 0x60 Write RCD 0x03 Notes: 1. First command cycle address should be the same as the operation’s target address. DBA = Device Base Address (NOTE: needed for dual-die 512 Mb device) DnA = Address within the device. IA = Identification code address offset. QA = CFI Query address offset. WA = Word address of memory location to be written. BA = Address within the block. PRA = Protection Register address. LRA = Lock Register address. RCD = Read Configuration Register data on QUAD+ A[15:0] or EASY BGA A[16:1]. 2. ID = Identifier data. QD = Query data on DQ[15:0]. SRD = Status Register data. WD = Word data. N = Word count of data to be loaded into the write buffer. PD = Protection Register data. LRD = Lock Register data. 3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming operation. 4. The confirm command (0xD0) is followed by the buffer data. November 2007 Order Number: 306666-11 Datasheet 45 P30 9.3 Command Definitions Valid device command codes and descriptions are shown in Table 24. Table 24: Command Codes and Definitions (Sheet 1 of 2) Mode Code 0xFF Read Write Write Device Mode Read Array Places the device in Read Array mode. Array data is output on DQ[15:0]. 0x70 Read Status Register Places the device in Read Status Register mode. The device enters this mode after a program or erase command is issued. Status Register data is output on DQ[7:0]. 0x90 Read Device ID or Configuration Register Places device in Read Device Identifier mode. Subsequent reads output manufacturer/device codes, Configuration Register data, Block Lock status, or Protection Register data on DQ[15:0]. 0x98 Read Query Places the device in Read Query mode. Subsequent reads output Common Flash Interface information on DQ[7:0]. 0x50 Clear Status Register The WSM can only set Status Register error bits. The Clear Status Register command is used to clear the SR error bits. 0x40 Word Program Setup First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the next write cycle, the address and data are latched and the WSM executes the programming algorithm at the addressed location. During program operations, the device responds only to Read Status Register and Program Suspend commands. CE# or OE# must be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array reads. The Read Array command must be issued to read array data after programming has finished. 0x10 Alternate Word Program Setup Equivalent to the Word Program Setup command, 0x40. 0xE8 Buffered Program This command loads a variable number of words up to the buffer size of 32 words onto the program buffer. 0xD0 Buffered Program Confirm The confirm command is Issued after the data streaming for writing into the buffer is done. This instructs the WSM to perform the Buffered Program algorithm, writing the data from the buffer to the flash memory array. 0x80 BEFP Setup First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode (BEFP). The CUI then waits for the BEFP Confirm command, 0xD0, that initiates the BEFP algorithm. All other commands are ignored when BEFP mode begins. 0xD0 BEFP Confirm If the previous command was BEFP Setup (0x80), the CUI latches the address and data, and prepares the device for BEFP mode. Block Erase Setup First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM performs the erase algorithm on the block addressed by the Erase Confirm command. If the next command is not the Erase Confirm (0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and places the device in read status register mode. Block Erase Confirm If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and the WSM erases the addressed block. During blockerase operations, the device responds only to Read Status Register and Erase Suspend commands. CE# or OE# must be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array reads 0xB0 Program or Erase Suspend This command issued to any device address initiates a suspend of the currently-executing program or block erase operation. The Status Register indicates successful suspend operation by setting either SR[2] (program suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write State Machine remains in the suspend mode regardless of control signal states (except for RST# asserted). 0xD0 Suspend Resume This command issued to any device address resumes the suspended program or block-erase operation. 0x20 Erase 0xD0 Suspend Datasheet 46 Description November 2007 Order Number: 306666-11 P30 Table 24: Command Codes and Definitions (Sheet 2 of 2) Mode Block Locking/ Unlocking Protection Code Device Mode 0x60 Lock Block Setup First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. 0x01 Lock Block If the previous command was Block Lock Setup (0x60), the addressed block is locked. 0xD0 Unlock Block If the previous command was Block Lock Setup (0x60), the addressed block is unlocked. If the addressed block is in a lock-down state, the operation has no effect. 0x2F Lock-Down Block If the previous command was Block Lock Setup (0x60), the addressed block is locked down. 0xC0 Program Protection Register Setup First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock Register program operation. The second cycle latches the register address and data, and starts the programming algorithm 0x60 Read Configuration Register Setup First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the Set Read Configuration Register command (0x03) is not the next command, the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. 0x03 Read Configuration Register If the previous command was Read Configuration Register Setup (0x60), the CUI latches the address and writes A[15:0] to the Read Configuration Register. Following a Configure Read Configuration Register command, subsequent read operations access array data. Configuration November 2007 Order Number: 306666-11 Description Datasheet 47 P30 10.0 Read Operations The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power-up or a reset. The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array (see Section 10.3, “Read Configuration Register” on page 49). The device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. Upon power-up, or after a reset, the device defaults to Read Array. To change the read state, the appropriate read command must be written to the device (see Section 9.2, “Device Commands” on page 45). See Section 14.0, “Special Read States” on page 69 for details regarding Read Status, Read ID, and CFI Query modes. The following sections describe read-mode operations in detail. 10.1 Asynchronous Page-Mode Read Following a device power-up or reset, asynchronous page mode is the default read mode and the device is set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 10.3, “Read Configuration Register” on page 49). To perform an asynchronous page-mode read, an address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access time tAVQV delay. (see Section 7.0, “AC Characteristics” on page 28). In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest two address bits determine which word of the 4-word page is output from the data buffer at any given time. 10.2 Synchronous Burst-Mode Read To perform a synchronous burst-read, an initial address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which case the address is latched on the next valid CLK edge while ADV# is asserted. During synchronous array and non-array read modes, the first word is output from the data buffer on the next valid CLK edge after the initial access latency delay (see Section 10.3.2, “Latency Count” on page 50). Subsequent data is output on valid CLK edges following a minimum delay. However, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. Refer to the following waveforms for more detailed information: • Figure 17, “Synchronous Single-Word Array or Non-array Read Timing” on page 34 • Figure 18, “Continuous Burst Read, Showing An Output Delay Timing” on page 35 • Figure 19, “Synchronous Burst-Mode Four-Word Read Timing” on page 35 Datasheet 48 November 2007 Order Number: 306666-11 P30 10.3 Read Configuration Register The Read Configuration Register (RCR) is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register command (see Section 9.2, “Device Commands” on page 45). RCR contents can be examined using the Read Device Identifier command, and then reading from offset 0x05 (see Section 14.2, “Read Device Identifier” on page 70). The RCR is shown in Table 25. The following sections describe each RCR bit. Table 25: Read Configuration Register Description Read Configuration Register (RCR) Read Mode RES Latency Count WAIT Polarity Data Hold WAIT Delay Burst Seq CLK Edge RES RES Burst Wrap Burst Length RM R LC[2:0] WP DH WD BS CE R R BW BL[2:0] 15 14 10 9 8 7 6 5 4 3 Bit 13 15 Read Mode (RM) 14 Reserved (R) 13:11 10 9 8 7 6 5:4 3 2:0 Note: 12 11 Name Latency Count (LC[2:0]) 0 Reserved bits should be cleared (0) 010 =Code 2 011 =Code 3 100 =Code 4 101 =Code 5 110 =Code 6 111 =Code 7 (default) (Other bit settings are reserved) 0 =WAIT signal is active low 1 =WAIT signal is active high (default) Data Hold (DH) 0 =Data held for a 1-clock data cycle 1 =Data held for a 2-clock data cycle (default) 0 =WAIT deasserted with valid data 1 =WAIT deasserted one data cycle before valid data (default) Burst Sequence (BS) 0 =Reserved 1 =Linear (default) Clock Edge (CE) 0 = Falling edge 1 = Rising edge (default) Reserved (R) Reserved bits should be cleared (0) Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0] 1 =No Wrap; Burst accesses do not wrap within burst length (default) Burst Length (BL[2:0]) 1 0 = Synchronous burst-mode read 1 = Asynchronous page-mode read (default) Wait Polarity (WP) Wait Delay (WD) 2 Description 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =Continuous-word burst (default) (Other bit settings are reserved) Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0). Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1) combination is not supported. Table 25, “Read Configuration Register Description” on page 49 is shown using the QUAD+ package. For EASY BGA and TSOP packages, the table reference should be adjusted using address bits A[16:1]. November 2007 Order Number: 306666-11 Datasheet 49 P30 10.3.1 Read Mode The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is cleared, synchronous burst mode is selected. 10.3.2 Latency Count The Latency Count (LC) bits tell the device how many clock cycles must elapse from the rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value and Figure 26 shows the data output latency for the different settings of LC. The maximum Latency Count for P30 would be Code 4 based on the Max Clock frequency specification of 52 mhz, and there will be zero WAIT States when bursting within the word line. Please also refer to “End of Word Line (EOWL) Considerations” on page 55 for more information on EOWL. Refer to Table 26, “Latency Count (LC) and Frequency Support” on page 51 for Latency Code Settings. Datasheet 50 November 2007 Order Number: 306666-11 P30 Figure 26: First-Access Latency Count CLK [C] Address [A] Valid Address ADV# [V] Code 0 (Reserved) Valid Output DQ15-0 [D/Q] Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Code 1 (Reserved DQ15-0 [D/Q] Code 2 DQ15-0 [D/Q] Code 3 DQ15-0 [D/Q] Code 4 DQ15-0 [D/Q] Code 5 DQ15-0 [D/Q] Code 6 DQ15-0 [D/Q] Code 7 DQ15-0 [D/Q] Valid Output Table 26: Latency Count (LC) and Frequency Support Latency Count Settings Note: Frequency Support (MHz) 2 £ 27 3 £ 40 4 £ 52 Synchronous burst read operation is currently not supported for the TSOP package. November 2007 Order Number: 306666-11 Datasheet 51 P30 Figure 27: Example Latency Count Setting using Code 3 0 1 2 3 tData 4 CLK CE# ADV# A[MAX:0] Address Code 3 High-Z D[15:0] Data R103 10.3.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL ) of WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted, RST# deasserted). 10.3.3.1 WAIT Signal Function The WAIT signal indicates data valid when the device is operating in synchronous mode (RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus. When the device is operating in synchronous non-array read mode, such as read status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid on the bus. WAIT behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. When the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See Figure 15, “Asynchronous Single-Word Read (ADV# Latch)” on page 33, and Figure 16, “Asynchronous Page-Mode Read Timing” on page 34. Table 27: WAIT Functionality Table (Sheet 1 of 2) Condition WAIT Notes CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ High-Z 1 CE# =’0’, OE# = ‘0’ Active 1 Synchronous Array Reads Active 1 Synchronous Non-Array Reads Active 1 Datasheet 52 November 2007 Order Number: 306666-11 P30 Table 27: WAIT Functionality Table (Sheet 2 of 2) Condition WAIT All Asynchronous Reads Deasserted All Writes High-Z Notes 1 1,2 Notes: 1. Active: WAIT is asserted until data becomes valid, then deasserts 2. When OE# = VIH during writes, WAIT = High-Z 10.3.4 Data Hold For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the “data cycle”. When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see Figure 28). The processor’s data setup time and the flash memory’s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for determining the Data Hold configuration is shown below: To set the device at one clock data hold for subsequent reads, the following condition must be satisfied: tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns) tDATA = Data set up to Clock (defined by CPU) For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above: 20 ns + 4 ns ≤ 25 ns The equation is satisfied and data will be available at every clock period with data hold setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods must be used. Figure 28: Data Hold Timing CLK [C] 1 CLK Data Hold D[15:0] [Q] 2 CLK Data Hold D[15:0] [Q] 10.3.5 Valid Output Valid Output Valid Output Valid Output Valid Output WAIT Delay The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid data (default). When WD is cleared, WAIT is deasserted during valid data. November 2007 Order Number: 306666-11 Datasheet 53 P30 10.3.6 Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 28 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting. Table 28: Burst Sequence Word Ordering Burst Addressing Sequence (DEC) Start Addr. (DEC) Burst Wrap (RCR[3]) 0 4-Word Burst (BL[2:0] = 0b001) 8-Word Burst (BL[2:0] = 0b010) 16-Word Burst (BL[2:0] = 0b011) Continuous Burst (BL[2:0] = 0b111) 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-… 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-… 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-… 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-… 4 0 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10… 5 0 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3-4 5-6-7-8-9-10-11… 6-7-8-9-10-11-12-… 7-8-9-10-11-12-13… 6 0 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2-3-45 7 0 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3-4-56 … … … … … … 14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-… 15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-… … … … … … 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-… 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-… 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-… 3 1 3-4-5-6 4 1 5 1 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11… 6 1 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-… 7 1 7-8-9-10-11-12-1314 7-8-9-10-11…21-22 7-8-9-10-11-12-13… … … 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10… … … … 14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-… 15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-… 10.3.7 … … 0 Clock Edge The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT. Datasheet 54 November 2007 Order Number: 306666-11 P30 10.3.8 Burst Wrap The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs. 10.3.9 Burst Length The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 28, “Burst Sequence Word Ordering” on page 54). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space. 10.3.10 End of Word Line (EOWL) Considerations When performing synchronous burst reads with BW set (no wrap) and DH reset (1 clock cycle), an output “delay” requiring additions clock Wait States may occur when the burst sequence crosses its first device-row (16-word) boundary. The delay would take place only once, and will not occur if the burst sequence does not cross a device-row boundary. The WAIT signal informs the system of this delay when it occurs. If the burst sequence’s start address is 4-word aligned (i.e. 0x00h, 0x04h, 0x08h, 0x0Ch) then no delay occurs. If the start address is at the end of a 4-word boundary (i.e. 0x03h, 0x07h, 0x0Bh, 0x0Fh), the worst case delay (number of Wait States required) will be one clock cycle less than the first access Latency Count (LC-1) when crossing the first device-row boundary (i.e. 0x0Fh to 0x10h). Other address misalignments may require wait states depending upon the LC setting and the starting address alignment. For example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but the same LC setting of 3 with a starting address of 0xFE would require 1 wait state when crossing the first device row boundary. November 2007 Order Number: 306666-11 Datasheet 55 P30 11.0 Programming Operations The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See Section 9.0, “Device Operations” on page 43 for details on the various programming commands issued to the device. The following sections describe device programming in detail. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block must be unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 13.0, “Security Modes” on page 64 for details on locking and unlocking blocks. The Product Name is segmented into multiple 8-Mbit Programming Regions. See Section 4.4, “Memory Maps” on page 22 for complete addressing. Execute in Place (XIP) applications must partition the memory such that code and data are in separate programming regions. XIP is executing code directly from flash memory. Each Programming Region should contain only code or data but not both. The following terms define the difference between code and data. System designs must use these definitions when partitioning their code and data for the P30 device. • Code: Execution code ran out of the flash device on a continuous basis in the system. • Data: Information periodically programmed into the flash device and read back (e.g. execution code shadowed and executed in RAM, pictures, log files, etc.). 11.1 Word Programming Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 9.0, “Device Operations” on page 43). This is followed by a second write to the device with the address and data to be programmed. The device outputs Status Register data when read. See Figure 38, “Word Program Flowchart” on page 79. VPP must be above VPPLK, and within the specified VPPL min/ max values. During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, “Erase Operations” on page 62). The Status Register can be examined for programming progress and errors by reading at any address. The device remains in the Read Status Register state until another command is written to the device. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the device during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. Datasheet 56 November 2007 Order Number: 306666-11 P30 Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed. 11.1.1 Factory Word Programming Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with VPP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, “Operating Conditions” on page 25 for limitations when VPP = VPPH. Note: 11.2 When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the VPP supply. Figure 29, “Example VPP Supply Connections” on page 61 shows examples of device power supply configurations. Buffered Programming The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, “Device Commands” on page 45), Status Register information is updated and reflects the availability of the buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 40, “Buffer Program Flowchart” on page 81). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. When Buffered Programming has completed, additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, “Operating Conditions” on page 25 for limitations when operating the device with VPP = VPPH). November 2007 Order Number: 306666-11 Datasheet 57 P30 If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command. 11.3 Buffered Enhanced Factory Programming Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash programming. The enhanced programming algorithm used in BEFP eliminates traditional programming elements that drive up overhead in device programmer systems. BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 41, “BEFP Flowchart” on page 82). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of BEFP saves host programming equipment the address-bus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM’s internal verification to ensure that the device has programmed properly. This eliminates the external post-program verification and its associated overhead. 11.3.1 BEFP Requirements and Considerations Table 29: BEFP Requirements Parameter/Issue Requirement Notes Case Temperature TC = 25 °C ± 5 °C VCC Within operating range VPP Driven to VPPH Setup and Confirm Target block unlocked before issuing the BEFP Setup and Confirm commands Programming The first-word address (WA0) of the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired Buffer Alignment WA0 must align with the start of an array buffer boundary Note: 1. 1 Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. Datasheet 58 November 2007 Order Number: 306666-11 P30 Table 30: BEFP Considerations Parameter/Issue Requirement Notes Cycling For optimum performance, cycling must be limited below 100 erase cycles per block. 1 Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block 2 Suspend BEFP cannot be suspended Programming the flash memory array Programming to the flash memory array can occur only when the buffer is full. Note: 1. 2. 3. 3 Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. If the number of words is less than 32, remaining locations must be filled with 0xFFFF. 11.3.2 BEFP Setup Phase After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and BEFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect VPP level. Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer. 11.3.3 BEFP Program/Verify Phase After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is available. Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For BEFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the BEFP algorithm will be aborted and the program fails and (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is November 2007 Order Number: 306666-11 Datasheet 59 P30 only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is ready for the next buffer fill. Note: Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. The host programming system continues the BEFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block’s range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the BEFP Exit phase. 11.3.4 BEFP Exit Phase When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. When exiting the BEFP algorithm with a block address change, the read mode will not change. After BEFP exit, any valid command can be issued to the device. 11.4 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued to any device address. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 39, “Program Suspend/Resume Flowchart” on page 80). When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The device continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.5, “Program and Erase Characteristics” on page 39. To read data from the device, the Read Array command must be issued. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid commands during a program suspend. During a program suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at its programming level, and WP# must remain unchanged while in program suspend. If RST# is asserted, the device is reset. 11.5 Program Resume The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any address. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 39, “Program Suspend/ Resume Flowchart” on page 80). Datasheet 60 November 2007 Order Number: 306666-11 P30 11.6 Program Protection When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is at or below VPPLK, programming operations halt and SR[3] is set indicating a VPPlevel error. Block lock registers are not affected by the voltage level on VPP; they may still be programmed and read, even if VPP is less than VPPLK. Figure 29: Example VPP Supply Connections VCC VPP VCC VPP VPP=VPPH VCC VPP • Low Voltage and Factory Programming November 2007 Order Number: 306666-11 PROT # VCC VPP ≤ 10K Ω • Factory Programming with VPP = VPPH • Complete write/Erase Protection when VPP ≤ VPPLK VCC VCC • Low-voltage Programming only • Logic Control of Device Protection VCC VCC VPP • Low Voltage Programming Only • Full Device Protection Unavailable Datasheet 61 P30 12.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. 12.1 Block Erase Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, “Device Commands” on page 45). Next, the Block Erase Confirm command is written to the address of the block to be erased. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 42, “Block Erase Flowchart” on page 83). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, “Programming Operations” on page 56). The Status Register can be examined for block erase progress and errors by reading any address. The device remains in the Read Status Register state until another command is written. SR[0] indicates whether the addressed block is erasing. Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because VPP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed. 12.2 Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address. A block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 39, “Program Suspend/Resume Flowchart” on page 80). When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The device continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.5, “Program and Erase Characteristics” on page 39. To read data from the device (other than an erase-suspended block), the Read Array command must be issued. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands Datasheet 62 November 2007 Order Number: 306666-11 P30 during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. During an erase suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset. 12.3 Erase Resume The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any address. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 39, “Program Suspend/Resume Flowchart” on page 80). 12.4 Erase Protection When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error. November 2007 Order Number: 306666-11 Datasheet 63 P30 13.0 Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 13.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block LockDown command along with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations (see Section 11.6, “Program Protection” on page 61 and Section 12.4, “Erase Protection” on page 63). The P30 device also offers four pre-defined areas in the main array that can be configured as One-Time Programmable (OTP) for the highest level of security. These include the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks. This is available for top or bottom parameter devices. 13.1.1 Lock Block To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block’s address (see Section 9.2, “Device Commands” on page 45 and Figure 44, “Block Lock Operations Flowchart” on page 85). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits may be modified and/or read even if VPP is at or below VPPLK. 13.1.2 Unlock Block The Unlock Block command is used to unlock blocks (see Section 9.2, “Device Commands” on page 45). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 30, “Block Locking State Diagram” on page 65). 13.1.3 Lock-Down Block A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, “Device Commands” on page 45). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-down state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-down blocks revert to the locked state upon reset or power up the device (see Figure 30, “Block Locking State Diagram” on page 65). Datasheet 64 November 2007 Order Number: 306666-11 P30 13.1.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 14.2, “Read Device Identifier” on page 70). Data bits DQ[1:0] display the addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the addressed block’s lock-down bit. Figure 30: Block Locking State Diagram Power-Up/Reset Locked [X01] LockedDown 4,5 [011] Hardware Locked 5 [011] WP# Hardware Control Unlocked [X00] Software Locked [111] Unlocked [110] Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) W P# hardware control Notes: 13.1.5 1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don’t Care. 2. DQ1 indicates Block Lock-Down status. DQ1 = ‘0’, Lock-Down has not been issued to this block. DQ1 = ‘1’, Lock-Down has been issued to this block. 3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ0 = ‘1’, block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked-Down states. Block Locking During Suspend Block lock and unlock changes can be performed during an erase suspend. To change block locking during an erase operation, first issue the Erase Suspend command. Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept another command. Next, write the desired lock command sequence to a block, which changes the lock state of that block. After completing block lock or unlock operations, resume the erase operation using the Erase Resume command. Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. November 2007 Order Number: 306666-11 Datasheet 65 P30 If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, “Write State Machine” on page 72, which shows valid commands during an erase suspend. 13.2 Selectable One-Time Programmable Blocks Any of four pre-defined areas from the main array (the four 32-KB parameter blocks together as one and three adjacent 128 KB main blocks) can be configured as OTP so further program and erase operations are not allowed. This option is available for top or bottom parameter devices. Table 31: Selectable OTP Block Mapping Density 256-Mbit 128-Mbit 64-Mbit Top Parameter Configuration Bottom Parameter Configuration blocks 258:255 (parameters) blocks 3:0 (parameters) block 254 (main) block 4 (main) block 253 (main) block 5 (main) block 252 (main) block 6 (main) blocks 130:127 (parameters) blocks 3:0 (parameters) block 126 (main) block 4 (main) block 125 (main) block 5 (main) block 124 (main) block 6 (main) blocks 66:63 (parameters) blocks 3:0 (parameters) block 62 (main) block 4 (main) block 61 (main) block 5 (main) block 60 (main) block 6 (main) Notes: 1. The 512-Mbit devices will have multiple die and selectable OTP areas depending on the placement of the parameter blocks. 2. When programming the OTP bits for a Top Parameter Device, the following upper address bits must also be driven properly: A[Max:17] driven high (VIH) for TSOP and Easy BGA packages, and A[Max:16] driven high (VIH) for QUAD+ SCSP. Note: 13.3 Please see your local Numonyx representative for details about the Selectable OTP implementation. Protection Registers The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 31, “Protection Register Map” on page 67). Datasheet 66 November 2007 Order Number: 306666-11 P30 The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked. . Figure 31: Protection Register Map 0x109 128-bit Protection Register 16 (User-Programmable) 0x102 0x91 128-bit Protection Register 1 (User-Programmable) 0x8A Lock Register 1 0x89 0x88 0x85 0x84 0x81 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 64-bit Segment (User-Programmable) 128-Bit Protection Register 0 64-bit Segment (Factory-Programmed) Lock Register 0 0x80 13.3.1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Reading the Protection Registers The Protection Registers can be read from any address. To read the Protection Register, first issue the Read Device Identifier command at any address to place the device in the Read Device Identifier state (see Section 9.2, “Device Commands” on page 45). Next, perform a read operation using the address offset corresponding to the register to be read. Table 33, “Device Identifier Information” on page 70 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time. November 2007 Order Number: 306666-11 Datasheet 67 P30 13.3.2 Programming the Protection Registers To program any of the Protection Registers, first issue the Program Protection Register command at the parameter’s base address plus the offset to the desired Protection Register (see Section 9.2, “Device Commands” on page 45). Next, write the desired Protection Register data to the same Protection Register address (see Figure 31, “Protection Register Map” on page 67). The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 45, “Protection Register Programming Flowchart” on page 86). Issuing the Program Protection Register command outside of the Protection Register’s address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set). Note: When programming the OTP bits for a Top Parameter Device, the following upper address bits must also be driven properly: A[Max:17] driven high (VIH) for TSOP and Easy BGA packages, and A[Max:16] driven high (VIH) for QUAD+ SCSP. 13.3.3 Locking the Protection Registers Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, “Device Commands” on page 45). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 33, “Device Identifier Information” on page 70). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, preprogrammed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: Datasheet 68 After being locked, the Protection Registers cannot be unlocked. November 2007 Order Number: 306666-11 P30 14.0 Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous single-word mode. When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a nonarray read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. Refer to the following waveforms for more detailed information: • Figure 14, “Asynchronous Single-Word Read (ADV# Low)” on page 33 • Figure 15, “Asynchronous Single-Word Read (ADV# Latch)” on page 33 • Figure 17, “Synchronous Single-Word Array or Non-array Read Timing” on page 34 14.1 Read Status Register To read the Status Register, issue the Read Status Register command at any address. Status Register information is available to which the Read Status Register, Word Program, or Block Erase command was issued. Status Register data is automatically made available following a Word Program, Block Erase, or Block Lock command sequence. Reads from the device after any of these command sequences outputs the device’s status until another valid command is written (e.g. Read Array command). The Status Register is read using single asynchronous-mode or synchronous burst mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. The Device Write Status bit (SR[7]) provides overall status of the device. Status register bits SR[6:1] present status and error information about the program, erase, suspend, VPP, and block-locked operations. Table 32: Status Register Description (Sheet 1 of 2) Status Register (SR) Default Value = 0x80 Device Write Status Erase Suspend Status Erase Status Program Status VPP Status Program Suspend Status Block-Locked Status BEFP Status DWS ESS ES PS VPPS PSS BLS BWS 7 6 5 4 3 2 1 0 Bit Name Description 7 Device Write Status (DWS) 0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid. 6 Erase Suspend Status (ESS) 0 = Erase suspend not in effect. 1 = Erase suspend in effect. 5 Erase Status (ES) 0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 4 Program Status (PS) 0 = Program successful. 1 = Program fail or program sequence error when set with SR[5,7] November 2007 Order Number: 306666-11 Datasheet 69 P30 Table 32: Status Register Description (Sheet 2 of 2) Status Register (SR) Default Value = 0x80 3 VPP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation. 2 Program Suspend Status (PSS) 0 = Program suspend not in effect. 1 = Program suspend in effect. 1 Block-Locked Status (BLS) 0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted. 0 BEFP Status (BWS) Note: After Buffered Enhanced Factory Programming (BEFP) data is loaded into the buffer: 0 = BEFP complete. 1 = BEFP in-progress. Always clear the Status Register prior to resuming erase operations. It avoids Status Register ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status. 14.1.1 Clear Status Register The Clear Status Register command clears the status register. It functions independent of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity. A device reset also clears the Status Register. 14.2 Read Device Identifier The Read Device Identifier command instructs the device to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data (see Section 9.2, “Device Commands” on page 45 for details on issuing the Read Device Identifier command). Table 33, “Device Identifier Information” on page 70 and Table 34, “Device ID codes” on page 71 show the address offsets and data values for this device. Table 33: Device Identifier Information (Sheet 1 of 2) Address(1) Data Manufacturer Code 0x00 0089h Device ID Code 0x01 Item Block Lock Configuration: Table 34) Lock Bit: • Block Is Unlocked • Block Is Locked ID (see DQ 0 = 0b0 BBA + 0x02 DQ 0 = 0b1 • Block Is not Locked-Down DQ 1 = 0b0 • Block Is Locked-Down DQ 1 = 0b1 Read Configuration Register 0x05 RCR Contents Lock Register 0 0x80 PR-LK0 64-bit Factory-Programmed Protection Register 0x81–0x84 Factory Protection Register Data 64-bit User-Programmable Protection Register 0x85–0x88 User Protection Register Data Datasheet 70 November 2007 Order Number: 306666-11 P30 Table 33: Device Identifier Information (Sheet 2 of 2) Item Address(1) Lock Register 1 128-bit User-Programmable Protection Registers Data 0x89 PR-LK1 0x8A–0x109 Protection Register Data Notes: 1. BBA = Block Base Address. Table 34: Device ID codes Device Identifier Codes ID Code Type Device Code Note: 14.3 Device Density –T (Top Parameter) –B (Bottom Parameter) 64-Mbit 8817 881A 128-Mbit 8818 881B 256-Mbit 8919 891C The 512-Mbit devices do not have a Device ID associated with them. Each die within the stack can be identified by either of the 256-Mbit Device ID codes depending on its parameter option. CFI Query The CFI Query command instructs the device to output Common Flash Interface (CFI) data when read. See Section 9.2, “Device Commands” on page 45 for details on issuing the CFI Query command. Appendix C, “Common Flash Interface” on page 87 shows CFI information and address offsets within the CFI database. November 2007 Order Number: 306666-11 Datasheet 71 P30 Appendix A Write State Machine Figure 32 through Figure 37 show the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM state does not depend on the partition’s output state. Figure 32: Write State Machine—Next State Table (Sheet 1 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State Ready Read Array (2) Program (3,4) (FFH) (10H/40H) Ready Program Setup Buffered Program (BP) Erase Setup (3,4) Buffered Enhanced Factory Pgm Setup (3, 4) (E8H) (20H) BP Setup Erase Setup (80H) Confirm BP / Prg / Erase Suspend Read Status (B0H) (70H) Setup Clear Status Register Read ID/Query (5) Lock, Unlock, Lock-down, CR setup (4) (8) (D0H) (50H) (90H, 98H) (60H) Lock/CR Setup Ready Ready (Unlock Block) Ready (Lock Error) OTP Busy Busy Word Program Busy Setup Word Program BE Confirm, P/E Resume, ULB, BEFP Setup Ready (Lock Error) Lock/CR Setup OTP Word Word Program Suspend Program Busy Busy Word Program Busy Word Program Suspend Suspend Word Program Busy Word Program Suspend Setup BP Load 1 BP Load 1 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP BP Confirm Ready (Error) BP Busy BP Busy BP Suspend BP Busy Setup Ready (Error) Erase Busy Suspend Datasheet 72 Erase Suspend Word Program Setup in Erase Suspend BP Setup in Erase Suspend BP Suspend Ready (Error) Erase Suspend Erase Busy Busy BP Busy BP Suspend BP Suspend Erase Ready (Error) BP Busy Erase Suspend Erase Busy Erase Busy Erase Suspend Lock/CR Setup in Erase Suspend November 2007 Order Number: 306666-11 P30 Figure 33: Write State Machine—Next State Table (Sheet 2 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State Read Array (2) (FFH) Word Program (3,4) (10H/40H) Buffered Program (BP) (E8H) Buffered Erase Enhanced (3,4) Factory Pgm Setup Setup (3, 4) (20H) Word Program Suspend in Erase Suspend (B0H) (70H) Clear Status Register (D0H) Word Program Suspend in Erase Suspend Read ID/Query (90H, 98H) Lock, Unlock, Lock-down, CR setup (4) (60H) Word Program Busy in Erase Suspend Word Program Busy in Erase Suspend Busy Word Program Suspend in Erase Suspend BP Load 1 BP Load 1 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Confirm Erase Suspend (Error) BP Busy in Erase Suspend Lock/CR Setup in Erase Suspend Setup Ready (Error in Erase Suspend) BP Suspend in Erase Suspend BP Busy in Erase Suspend BP Suspend BEFP Busy (5) (50H) Setup BP Busy Buffered Enhanced Factory Program Mode Read Status Confirm (8) Word Program Busy in Erase Suspend Busy Suspend BP in Erase Suspend BP / Prg / Erase Suspend Word Program Busy in Erase Suspend Setup Word Program in Erase Suspend (80H) BE Confirm, P/E Resume, ULB, BP Busy in Erase Suspend BP Suspend in Erase Suspend BP Busy in Erase Suspend BP Suspend in Erase Suspend Erase Suspend (Lock Error) Erase Suspend (Unlock Block) Erase Suspend (Lock Error [Botch]) Ready (Error) BEFP Loading Data (X=32) Ready (Error) BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) November 2007 Order Number: 306666-11 Datasheet 73 P30 Figure 34: Write State Machine—Next State Table (Sheet 3 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State OTP Setup (4) (C0H) Ready OTP Setup Lock/CR Setup Ready (Lock Error) OTP Word Program Lock Block Confirm (8) Lock-Down Block Confirm (8) (01H) (2FH) Write RCR Block Address (8) Confirm (?WA0) (03H) 9 (XXXXH) Illegal Cmds or BEFP Data (1) WSM Operation Completes (all other codes) Ready Ready (Lock Block) Ready (Lock Down Blk) Setup Ready (Set CR) Ready (Lock Error) OTP Busy Busy N/A Ready Setup Word Program Busy N/A Busy Word Program Busy Ready Suspend Word Program Suspend Setup BP Load 1 BP Load 1 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; ELSE BP load 2 Ready (BP Load 2 BP Load 2 Ready BP BP Confirm BP Busy BP Suspend Setup Busy Ready (Error) (Proceed if unlocked or lock error) Ready (Error) BP Busy BP Confirm if Data load into Program Buffer is complete; ELSE BP Load 2 N/A Ready (Error) Ready BP Suspend N/A Ready (Error) Erase Busy Ready Erase Suspend N/A Erase Suspend Datasheet 74 November 2007 Order Number: 306666-11 P30 Figure 35: Write State Machine—Next State Table (Sheet 4 of 6) Command Input to Chip and resulting Chip Next State Current Chip (7) State Word Program in Erase Suspend OTP Setup (4) Lock Block Confirm (8) Lock-Down Block Confirm (8) Write RCR Confirm (8) Block Address (?WA0) 9 Illegal Cmds or BEFP Data (1) (C0H) (01H) (2FH) (03H) (XXXXH) (all other codes) Setup Word Program Busy in Erase Suspend NA Busy Word Program Busy in Erase Suspend Busy Erase Suspend Suspend Word Program Suspend in Erase Suspend N/A Setup BP Load 1 BP Load 1 BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Confirm Ready (Error in Erase Suspend) BP in Erase Suspend November 2007 Order Number: 306666-11 Ready (BP Load 2 BP Load 2 Ready Ready (Error) (Proceed if unlocked or lock error) BP Busy BP Busy in Erase Suspend BP Suspend BP Suspend in Erase Suspend Lock/CR Setup in Erase Suspend Buffered Enhanced Factory Program Mode WSM Operation Completes Erase Suspend (Lock Error) Erase Suspend (Lock Block) Erase Suspend (Lock Down Block) Erase Suspend (Set CR) BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 N/A Ready (Error) Erase Suspend Erase Suspend (Lock Error) Setup Ready (Error) Ready (BEFP Loading Data) Ready (Error) BEFP Busy BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) Ready BEFP Busy N/A Ready Datasheet 75 P30 Figure 36: Write State Machine—Next State Table (Sheet 5 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State Current chip state Read Array (2) Word Program Setup (3,4) BP Setup (FFH) (10H/40H) (E8H) BE Confirm, Buffered P/E Enhanced Erase Resume, Setup (3,4) Factory Pgm ULB Confirm Setup (3, 4) (8) (20H) (30H) Program/ Erase Suspend Read Status (B0H) (70H) (D0H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Status Read Lock/CR Setup, Lock/CR Setup in Erase Susp Status Read Clear Status Register (5) (50H) Datasheet 76 (90H, 98H) Lock, Unlock, Lock-down, CR setup (4) (60H) Status Read OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend Read ID/Query Read Array Status Read Output does not change. Status Read Output mux does not change. Status Read ID Read November 2007 Order Number: 306666-11 P30 Figure 37: Write State Machine—Next State Table (Sheet 6 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State OTP Current chip state Setup (4) (C0H) Lock Block Confirm Lock-Down Block (8) (01H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Confirm (2FH) (8) Write CR Confirm (8) (03H) Block Address (?WA0) Illegal Cmds or (FFFFH) (all other codes) BEFP Data (1) Status Read Lock/CR Setup, Lock/CR Setup in Erase Susp Status Read Array Read Status Read Output does not change. OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend WSM Operation Completes Status Read Output does not change. Array Read Output does not change. Notes: 1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase], etc.) 2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. 5. The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). 6. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored. November 2007 Order Number: 306666-11 Datasheet 77 P30 7. 8. 9. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. WA0 refers to the block address latched during the first write cycle of the current operation. Datasheet 78 November 2007 Order Number: 306666-11 P30 Appendix B Flowcharts Figure 38: Word Program Flowchart WORD PROGRAM PROCEDURE Bus Operation Command Start Write Write 0x40, Word Address (Setup) Write Data, Word Address Program Data = 0x40 Setup Addr = Location to program Write Data Data = Data to program Addr = Location to program Read None Status register data Idle None Check SR[7] 1 = WSM Ready 0 = WSM Busy (Confirm) Program Suspend Loop Read Status Register No SR[7] = Comments 0 Suspend? Yes Repeat for subsequent Word Program operations. Full Status Register check can be done after each program, or after a sequence of program operations. 1 Full Status Check (if desired) Write 0xFF after the last operation to set to the Read Array state. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register SR[3] = Bus Command Operation 1 SR[4] = Idle None Check SR[3]: 1 = VPP Error Idle None Check SR[4]: 1 = Data Program Error Idle None Check SR[1]: 1 = Block locked; operation aborted VPP Range Error 0 1 Program Error 1 Device Protect Error Comments 0 SR[1] = If an error is detected, clear the Status Register before continuing operations - only the Clear Staus Register command clears the Status Register error bits. 0 Program Successful November 2007 Order Number: 306666-11 Datasheet 79 P30 Figure 39: Program Suspend/Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Bus Command Operation Start Read Status Write Write 70 h Write Program Suspend Write B0h Any Address 0 Status register data Initiate a read cycle to update Status register Addr = Suspended block (BA) Standby Check SR.7 1 = WSM ready 0 = WSM busy Standby Check SR.2 1 = Program suspended 0 = Program completed 1 SR.2 = Read 0 Program Completed 1 Array Data = 70h Addr = Block to suspend (BA ) Program Data = B0h Suspend Addr = X Read Read Status Register SR.7 = Read Status Comments Write Read Array Data = FFh Addr = Block address to read (BA) Write FFh Read Read Array Data Done Reading Program Yes Resume Write Read array data from block other than the one being programmed Program Data = D0 h Resume Addr = Suspended block (BA) No Read Array Write D0 h Any Address Write FFh Program Resumed Read Array Data PGM_SUS.WMF Datasheet 80 November 2007 Order Number: 306666-11 P30 Figure 40: Buffer Program Flowchart Start Bus Operation Command Write Write to Buffer No Use Single Word Programming Yes Get Next Target Address Issue Write to Buffer Command E8h and Block Address Data = N-1 = Word Count N = 0 corresponds to count = 1 Addr = Block Address Write (Notes 3, 4) Data = Write Buffer Data Addr = Start Address Write (Notes 5, 6) Data = Write Buffer Data Addr = Block Address Read No 0 = No Standby Timeout or Count Expired? 1 = Yes Write Buffer Data, Start Address X= X+1 X=0 Write Buffer Data, Block Address Yes Data = D0H Addr = Block Address Status register Data CE# and OE# low updates SR Addr = Block Address Check SR.7 1 = WSM Ready 0 = WSM Busy Full status check can be done after all erase and write sequences complete. Write FFh after the last operation to reset the device to read array mode. No No Program Confirm 1. Word count values on DQ0-DQ7 are loaded into the Count register. Count ranges for this device are N = 0000h to 0001Fh. 2. The device outputs the status register when read. 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A4–A0 of the start address = 0). 5. The device aborts the Buffered Program command if the current address is outside the original block address. 6. The Status register indicates an "improper command sequence" if the Buffered Program command is aborted. Follow this with a Clear Status Register command. Yes Write Word Count, Block Address X = N? Write (Notes 1, 2) Write Read Status Register (at Block Address) Is WSM Ready? SR.7 = Check SR.7 1 = Device WSM is Busy 0 = Device WSM is Ready Standby Set Timeout or Loop Counter Data = E8H Addr = Block Address SR.7 = Valid Addr = Block Address Read Device Supports Buffer Writes? Comments Abort Bufferred Program? Yes Write Confirm D0h and Block Address Write to another Block Address Buffered Program Aborted Read Status Register No SR.7 =? 0 Suspend Program Yes Suspend Program Loop Full Status Check if Desired 1 Yes Another Buffered Programming? No Program Complete November 2007 Order Number: 306666-11 Datasheet 81 P30 Figure 41: BEFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE Setup Phase Program & Verify Phase Exit Phase Start Read Status Reg. Read Status Reg. V PP applied Block Unlocked No (SR[0]=1) No (SR[7]=0) Data Stream Ready? BEFP Exited? Yes (SR[0]=0) W rite 80h @ 1 st Word Address W rite D0h @ 1 st Word Address BEFP Setup delay Full Status Check Procedure W rite Data @ 1 st W ord Address Program Complete Increment Count: X = X+1 Read Status Reg. BEFP Setup Done? Yes (SR[7]=1) Initialize Count: X=0 N Check X = 32? Yes (SR[7]=0) Y Read Status Reg. No (SR[7]=1) No (SR [0]=1) Check V P P, Lock errors (SR[3,1]) Program Done? Yes (SR[0]=0) Exit N Last Data? Y W rite 0xFFFF, Address Not within Current Block BEFP Setup BEFP Exit BEFP Program & Verify Bus State Operation Write Unlock Block V PPH applied to VPP Write (Note 1) BEFP Setup Data = 0x80 @ 1 st W ord Address Com ments Bus State Operation Com ments Bus State Operation Com ments Read Status Register Data = Status Register Data Address = 1 st W ord Addr. Read Status Register Data = Status Register Data Address = 1 st W ord Addr. Standby Data Stream Ready? Check SR[0]: 0 = Ready for Data 1 = Not Ready for Data Standby Check Exit Status Standby Initialize Count X=0 Repeat for subsequent blocks ; Write (note 2) Load Buffer Data = Data to Program Address = 1 st W ord Addr. After BEFP exit, a full Status Register check can determine if any program error occurred ; Standby Increment Count X = X+1 See full Status Register check procedure in the W ord Program flowchart. Standby Buffer Full? X = 32? Yes = Read SR[0] No = Load Next Data W ord W rite 0xFF to enter Read Array state . Read Status Register Data = Status Reg. Data Address = 1 st W ord Addr. Standby Program Done? Check SR[0]: 0 = Program Done 1 = Program in Progress Standby Last Data? st Write BEFP Confirm Data = 0x80 @ 1 W ord 1 Address Read Status Register Data = Status Register Data Address = 1 st W ord Addr. Standby BEFP Setup Done? Standby Error Condition Check Check SR[7]: 0 = BEFP Ready 1 = BEFP Not Ready If SR[7] is set, check: SR[3] set = V PP Error SR[1] set = Locked Block Write Check SR [7]: 0 = Exit Not Completed 1 = Exit Completed No = Fill buffer again Yes = Exit Exit Prog & Data = 0xFFFF @ address Verify Phase not in current block NOTES: 1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary. 2. W rite-buffer contents are programmed sequentially to the flash array starting at the first word address (W SM internally increments addressing ). Datasheet 82 November 2007 Order Number: 306666-11 P30 Figure 42: Block Erase Flowchart BLOCK ERASE PROCEDURE Bus Comments Operation Command Block Data = 0x20 Write Erase Addr = Block to be erased (BA) Setup Start Write 0x20, (Block Erase) Block Address Write Write 0xD0, (Erase Confirm) Block Address Suspend Erase Loop Read Status Register No 0 SR[7] = Suspend Erase 1 Erase Data = 0xD0 Confirm Addr = Block to be erased (BA) Read None Status Register data. Idle None Check SR[7]: 1 = WSM ready 0 = WSM busy Yes Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures. Full Erase Status Check (if desired) Write 0xFF after the last operation to enter read array mode. Block Erase Complete FULL ERASE STATUS CHECK PROCEDURE Read Status Register SR[3] = Bus Command Operation 1 VPP Range Error 0 SR[4,5] = 1,1 Command Sequence Error Idle None Check SR[3]: 1 = VPP Range Error Idle None Check SR[4,5]: Both 1 = Command Sequence Error Idle None Check SR[5]: 1 = Block Erase Error Idle None Check SR[1]: 1 = Attempted erase of locked block; erase aborted. 0 SR[5] = 1 Block Erase Error 1 Block Locked Error 0 SR[1] = Comments Only the Clear Status Register command clears SR[1, 3, 4, 5]. If an error is detected, clear the Status register before attempting an erase retry or other error recovery. 0 Block Erase Successful November 2007 Order Number: 306666-11 Datasheet 83 P30 Figure 43: Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Bus Command Operation Start Read Status Write Write 70h Any Address Write Erase Suspend Write B0h Any Address Read Read Status Register SR.7 = SR.6 = 0 Read Read or Program ? Read Array Data No Check SR.6 1 = Erase suspended 0 = Erase completed Read or Write Program Loop Status register data. Toggle CE# or OE# to update Status register Addr =X Standby Write Program Data = B0h Erase Addr = Same partition address as Suspend above Check SR.7 1 = WSM ready 0 = WSM busy Erase Completed 1 Data = 70 h Addr = Any device address Standby 0 1 Read Status Comments Write Read Array Data = FFh or 40h or Program Addr = Block to program or read Read array or program data from/to block other than the one being erased Program Data = D0h Resume Addr = Any address Done? Yes Erase Resume Read Write D0h Any Address Write FFh Any Addres Erase Resumed Read Array Data Read Status Write 70h Any Address Datasheet 84 Array ERAS_SUS.WMF November 2007 Order Number: 306666-11 P30 Figure 44: Block Lock Operations Flowchart LOCKING OPERATIONS PROCEDURE Bus Command Operation Start Lock Setup Write Write 60 h Block Address Lock Confirm Write Write 01 ,D0,2Fh Block Address Lock Setup Comments Data = 60h Addr = Block to lock/unlock/lock-down (BA) Lock, Data = 01h (Lock block) Unlock, or D0h (Unlock block) Lockdown 2Fh (Lockdown block) Confirm Addr = Block to lock/unlock/lock-down (BA) Read ID Plane Write ( Optional) Op tion al Write 90 h No Yes Read Data = 90h Addr = Block address offset +2 ( BA+2 ) Read Block Lock Block Lock status data ( Optional) Status Addr = Block address offset +2 ( BA+2 ) Read Block Lock Status Locking Change ? Read ID Plane Array Confirm locking change on DQ1, DQ0 . (See Block Locking State Transitions Table for valid combinations.) Standby ( Optional) Write Read Array Data = FFh Addr = Block address (BA) Write FFh Any Address Lock Change Complete November 2007 Order Number: 306666-11 LOCK_OP.WMF Datasheet 85 P30 Figure 45: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Bus Operation Command Start Write 0xC0, PR Address Program Data = 0xC0 PR Setup Addr = First Location to Program Write Protection Data = Data to Program Program Addr = Location to Program (Confirm Data) Read Status Register SR[7] = Write (Program Setup) Write PR Address & Data Comments Read None Status Register Data. Idle None Check SR[7]: 1 = WSM Ready 0 = WSM Busy Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error. 0 1 Repeat for subsequent programming operations. Full Status Check (if desired) Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set Read Array state. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data SR[3] = Bus Command Operation 1 SR[4] = 1 Program Error 0 SR[1] = Idle None Check SR[3]: 1 =VPP Range Error Idle None Check SR[4]: 1 =Programming Error Idle None Check SR[1]: 1 =Block locked; operation aborted VPP Range Error 0 Comments Only the Clear Staus Register command clears SR[1, 3, 4]. 1 Register Locked; Program Aborted If an error is detected, clear the Status register before attempting a program retry or other error recovery. 0 Program Successful Datasheet 86 November 2007 Order Number: 306666-11 P30 Appendix C Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command (see Section 9.2, “Device Commands” on page 45). System software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. C.1 Query Structure Output The Query database allows system software to obtain information for controlling the flash device. This section describes the device’s CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0) and 00h in the high byte (DQ15-8). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix has been dropped. In addition, since the upper byte of wordwide devices is always “00h,” the leading “00” has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 35: Summary of Query Structure Output as a Function of Device and Mode Device Device Addresses November 2007 Order Number: 306666-11 Hex Offset 00010: 00011: 00012: Hex Code 51 52 59 ASCII Value "Q" "R" "Y" Datasheet 87 P30 Table 36: Example of Query Structure Output of x16- Devices Word Addressing: Hex Code D15–D0 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Offset AX–A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... C.2 Value Offset AX–A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Byte Addressing: Hex Code D7–D0 51 52 59 P_IDLO P_IDLO P_IDHI ... Value "Q" "R" "Y" PrVendor ID # ID # ... Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. Table 37: Query Structure Offset 00001-Fh 00010h 0001Bh 00027h P(3) Description(1) Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Vendor-defined additional information specific Primary Intel-specific Extended Query Table to the Primary Vendor Algorithm Sub-Section Name Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord). 3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table. C.3 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 38: CFI Identification Datasheet 88 Offset Length Description 10h 3 Query-unique ASCII string “QRY“ 13h 2 15h 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address 17h 2 19h 2 Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Hex Add. Code Value 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13: --01 14: --00 15: --0A 16: --01 17: --00 18: --00 19: --00 1A: --00 November 2007 Order Number: 306666-11 P30 Table 39: System Interface Information Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 20h 21h 22h 23h 24h 25h 26h 1 1 1 1 1 1 1 1 November 2007 Order Number: 306666-11 Description Hex Add. Code 1B: --17 VCC logic supply minimum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 BCD volts 1C: VCC logic supply maximum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 BCD volts 1D: VPP [programming] supply minimum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 HEX volts 1E: VPP [programming] supply maximum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 HEX volts 1F: “n” such that typical single word program time-out = 2n μ-sec 20: “n” such that typical max. buffer write time-out = 2n μ-sec 21: “n” such that typical block erase time-out = 2n m-sec 22: “n” such that typical full chip erase time-out = 2n m-sec “n” such that maximum word program time-out = 2n times typical 23: 24: “n” such that maximum buffer write time-out = 2n times typical 25: “n” such that maximum block erase time-out = 2n times typical 26: “n” such that maximum chip erase time-out = 2n times typical Value 1.7V --20 2.0V --85 8.5V --95 9.5V --08 --09 --0A --00 --01 --01 --02 --00 256μs 512μs 1s NA 512μs 1024μs 4s NA Datasheet 89 P30 C.4 Device Geometry Definition Table 40: Device Geometry Definition Offset 27h 28h Length Description “n” such that device size = 2n in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 2 2Ah 2 2Ch 1 2Dh 31h 35h 4 4 4 7 6 5 4 3 2 1 0 — — — — x64 x32 x16 x8 15 14 13 12 11 10 9 8 — — — — — — — — “n” such that maximum number of bytes in write buffer = 2n Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0–15 = y, y+1 = number of identical-size erase blocks bits 16–31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0–15 = y, y+1 = number of identical-size erase blocks bits 16–31 = z, region erase block(s) size are z x 256 bytes Reserved for future erase block region information A ddress 27: 28: 29: 2A : 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: Datasheet 90 64-Mbit –B --17 --01 --00 --06 --00 --02 --03 --00 --80 --00 --3E --00 --00 --02 --00 --00 --00 --00 –T --17 --01 --00 --06 --00 --02 --3E --00 --00 --02 --03 --00 --80 --00 --00 --00 --00 --00 128-Mbit –B –T --18 --18 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --7E --00 --00 --80 --00 --00 --02 --7E --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00 Code 27: See table below 28: --01 x16 29: 2A: 2B: 2C: --00 --06 --00 64 See table below 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: See table below See table below See table below 256-Mbit –B –T --19 --19 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --FE --00 --00 --80 --00 --00 --02 --FE --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00 November 2007 Order Number: 306666-11 P30 C.5 Numonyx-Specific Extended Query Table Table 41: Primary Vendor-Specific Extended Query Description Offset(1) Length P = 10Ah (Optional flash features and commands) (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string “PRI“ (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional feature and command support (1=yes, 0=no) (P+6)h bits 11–29 are reserved; undefined bits are “0.” If bit 31 is (P+7)h “1” then another 31 bit field of Optional features follows at the end of the bit–30 field. (P+8)h bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Extended Flash Array Blocks supported bit 30 CFI Link(s) to follow bit 31 Another "Optional Features" field to follow (P+9)h 1 (P+A)h (P+B)h 2 (P+C)h 1 (P+D)h 1 Address 112: November 2007 Order Number: 306666-11 Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1–7 reserved; undefined bits are “0” bit 0 Program supported after erase suspend Block status register mask bits 2–15 are Reserved; undefined bits are “0” bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active bit 4 EFA Block Lock-Bit Status register active bit 5 EFA Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0–3 BCD value in 100 mV bits 4–7 BCD value in volts VPP optimum program/erase supply voltage bits 0–3 BCD value in 100 mV bits 4–7 HEX value in volts Discrete –B –T ––--00 --00 Hex Add. Code Value 10A --50 "P" 10B: --52 "R" 10C: --49 "I" 10D: --31 "1" 10E: --34 "4" --E6 10F: 110: --01 111: --00 112: See table below bit 0 = 0 No bit 1 = 1 Yes bit 2 = 1 Yes bit 3 = 0 No bit 4 = 0 No bit 5 = 1 Yes bit 6 = 1 Yes bit 7 = 1 Yes bit 8 = 1 Yes bit 9 = 0 No bit 10 = 0 No See bit 30 table bit 31 below 113: --01 bit 0 114: 115: bit 0 bit 1 bit 4 bit 5 116: =1 --03 --00 =1 =1 =0 =0 --18 Yes Yes Yes No No 1.8V 117: --90 9.0V 512-Mbit –B die 1 (B) --40 –T die 2 (T) --00 die 1 (T) --40 die 2 (B) --00 Datasheet 91 P30 Table 42: Protection Register Information (1) Hex Length Description Offset Add. Code Value P = 10Ah (Optional flash features and commands) (P+E)h 1 118: --02 2 Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection Description 119: --80 80h (P+10)h This field describes user-available One Time Programmable 11A: --00 00h (P+11)h (OTP) Protection register bytes. Some are pre-programmed 11B: --03 8 byte with device-unique serial numbers. Others are user (P+12)h 11C: --03 8 byte programmable. Bits 0–15 point to the Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable. bits bits bits bits (P+13)h (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h 10 0–7 = Lock/bytes Jedec-plane physical low address 8–15 = Lock/bytes Jedec-plane physical high address 16–23 = “n” such that 2n = factory pre-programmed bytes 24–31 = “n” such that 2n = user programmable bytes Protection Field 2: Protection Description Bits 0–31 point to the Protection register physical Lock-word address in the Jedec-plane. Following bytes are factory or user-programmable. bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte) bits 40–47 = “n” ∴ n = factory pgm'd groups (high byte) bits 48–55 = “n” \ 2n = factory programmable bytes/group bits 56–63 = “n” ∴ n = user pgm'd groups (low byte) bits 64–71 = “n” ∴ n = user pgm'd groups (high byte) bits 72–79 = “n” ∴ 2n = user programmable bytes/group 11D: 11E: 11F: 120: 121: 122: 123: 124: 125: 126: --89 --00 --00 --00 --00 --00 --00 --10 --00 --04 89h 00h 00h 00h 0 0 0 16 0 16 Table 43: Burst Read Information (1) Length Description Offset P = 10Ah (Optional flash features and commands) Page Mode Read capability (P+1D)h 1 bits 0–7 = “n” such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. (P+1E)h 1 Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (P+1F)h 1 Synchronous mode read capability configuration 1 Bits 3–7 = Reserved bits 0–2 “n” such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the Read Configuration Register bits 0–2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. (P+20)h 1 Synchronous mode read capability configuration 2 (P+21)h 1 Synchronous mode read capability configuration 3 (P+22)h 1 Synchronous mode read capability configuration 4 Datasheet 92 Hex Add. Code Value 127: --03 8 byte 128: --04 4 129: --01 4 12A: 12B: 12C: --02 --03 --07 8 16 Cont November 2007 Order Number: 306666-11 P30 Table 44: Partition and Erase Block Region Information (1) Offset P = 10Ah Bottom Top (P+23)h Description (Optional flash features and commands) Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing (P+23)h one or more contiguous erase block regions. See table below Address Bot Top Len 1 12D: 12D: Table 45: Partition Region 1 Information Offset(1) P = 10Ah Bottom Top (P+24)h (P+24)h (P+25)h (P+25)h (P+26)h (P+26)h (P+27)h (P+27)h (P+28)h (P+28)h (P+29)h (P+2A)h (P+2B)h Description (Optional flash features and commands) Data size of this Parition Region Information field (# addressable locations, including this field) Number of identical partitions within the partition region Number of program or erase operations allowed in a partition bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+29)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+2A)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0–3 = number of simultaneous Program operations bits 4–7 = number of simultaneous Erase operations (P+2B)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+ (Type n blocks)x(Type n block sizes) November 2007 Order Number: 306666-11 See table below Address Bot Top Len 2 12E: 12E 12F 12F 2 130: 130: 131: 131: 1 132: 132: 1 133: 133: 1 134: 134: 1 135: 135: Datasheet 93 P30 Table 46: Partition Region 1 Information (continued) Offset(1) P = 10Ah Description Bottom Top (Optional flash features and commands) (P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information (P+2D)h (P+2D)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition (P+2E)h (P+2E)h bits 16–31 = z, region erase block(s) size are z x 256 bytes (P+2F)h (P+2F)h (P+30)h (P+30)h Partition 1 (Erase Block Type 1) Block erase cycles x 1000 (P+31)h (P+31)h (P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC bits 0–3 = bits per cell in erase region bit 4 = internal EDAC used (1=yes, 0=no) bits 5–7 = reserve for future use (P+33)h (P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3–7 = reserved for future use Partition Region 1 (Erase Block Type 1) Programming Region Information (P+34)h (P+34)h bits 0–7 = x, 2^x = Programming Region aligned size (bytes) (P+35)h (P+35)h bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7) (P+36)h (P+36)h bits 16–23 = y = Control Mode valid size in bytes (P+37)h (P+37)h bits 24-31 = Reserved (P+38)h (P+38)h bits 32-39 = z = Control Mode invalid size in bytes (P+39)h (P+39)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) (P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information (P+3B)h (P+3B)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition (P+3C)h (P+3C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes (P+3D)h (P+3D)h (P+3E)h (P+3E)h Partition 1 (Erase Block Type 2) Block erase cycles x 1000 (P+3F)h (P+3F)h (P+40)h (P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC bits 0–3 = bits per cell in erase region bit 4 = internal EDAC used (1=yes, 0=no) bits 5–7 = reserve for future use (P+41)h (P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3–7 = reserved for future use Partition Region 1 (Erase Block Type 2) Programming Region Information (P+42)h (P+42)h bits 0–7 = x, 2^x = Programming Region aligned size (bytes) (P+43)h (P+43)h bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7) (P+44)h (P+44)h bits 16–23 = y = Control Mode valid size in bytes (P+45)h (P+45)h bits 24-31 = Reserved (P+46)h (P+46)h bits 32-39 = z = Control Mode invalid size in bytes (P+47)h (P+47)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) Datasheet 94 See table below Address Bot Top Len 4 136: 136: 137: 137: 138: 138: 139: 139: 2 13A: 13A: 13B: 13B: 1 13C: 13C: 1 13D: 13D: 1 13E: 13F: 140: 141: 142: 143: 144: 145: 146: 147: 148: 149: 14A: 13E: 13F: 140: 141: 142: 143: 144: 145: 146: 147: 148: 149: 14A: 1 14B: 14B: 14C: 14D: 14E: 14F: 150: 151: 14C: 14D: 14E: 14F: 150: 151: 6 4 2 6 November 2007 Order Number: 306666-11 P30 Table 47: Partition and Erase Block Region Information Address 12D: 12E: 12F: 130: 131: 132: 133: 134: 135: 136: 137: 138: 139: 13A: 13B: 13C: 13D: 13E: 13F: 140: 141: 142: 143: 144: 145: 146: 147: 148: 149: 14A: 14B: 14C: 14D: 14E: 14F: 150: 151: November 2007 Order Number: 306666-11 64-Mbit –B --01 --24 --00 --01 --00 --11 --00 --00 --02 --03 --00 --80 --00 --64 --00 --02 --03 --00 --80 --00 --00 --00 --80 --3E --00 --00 --02 --64 --00 --02 --03 --00 --80 --00 --00 --00 --80 –T --01 --24 --00 --01 --00 --11 --00 --00 --02 --3E --00 --00 --02 --64 --00 --02 --03 --00 --80 --00 --00 --00 --80 --03 --00 --80 --00 --64 --00 --02 --03 --00 --80 --00 --00 --00 --80 128-Mbit –B –T --01 --01 --24 --24 --00 --00 --01 --01 --00 --00 --11 --11 --00 --00 --00 --00 --02 --02 --03 --7E --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --03 --03 --00 --00 --80 --80 --00 --00 --00 --00 --00 --00 --80 --80 --7E --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --03 --03 --00 --00 --80 --80 --00 --00 --00 --00 --00 --00 --80 --80 256-Mbit –B –T --01 --01 --24 --24 --00 --00 --01 --01 --00 --00 --11 --11 --00 --00 --00 --00 --02 --02 --03 --FE --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --03 --03 --00 --00 --80 --80 --00 --00 --00 --00 --00 --00 --80 --80 --FE --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --03 --03 --00 --00 --80 --80 --00 --00 --00 --00 --00 --00 --80 --80 Datasheet 95 P30 Table 48: CFI Link Information (1) Offset P = 10Ah (P+48)h (P+49)h (P+4A)h (P+4B)h Length (P+4C)h 1 Address 152: 153: 154: 155: 156: Datasheet 96 4 Description (Optional flash features and commands) CFI Link Field bit definitions Bits 0–9 = Address offset (within 32Mbit segment) of referenced CFI table Bits 10–27 = nth 32Mbit segment of referenced CFI table Bits 28–30 = Memory Type Bit 31 = Another CFI Link field immediately follows CFI Link Field Quantity Subfield definitions Bits 0–3 = Quantity field (n such that n+1 equals quantity) Bit 4 = Table & Die relative location Bit 5 = Link Field & Table relative location Bits 6–7 = Reserved Discrete –B –T ––--FF --FF --FF --FF --FF --FF --FF --FF --FF --FF Add. 152: 153: 154: 155: Hex Code Value See table below 156: See table below 512-Mbit –B die 1 (B) --10 --20 --00 --00 --10 –T die 2 (T) --FF --FF --FF --FF --FF die 1 (T) --10 --20 --00 --00 --10 die 2 (B) --FF --FF --FF --FF --FF November 2007 Order Number: 306666-11 P30 Appendix D Additional Information Order/Document Number Note: Document/Tool 309045 P30 Family Specification Update 308291 Schematic Review Checklist for Numonyx™ StrataFlash® Embedded Memory (P30) 300783 Using Numonyx™ Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode 290667 Numonyx™ StrataFlash® Memory (J3) Datasheet 306667 Migration Guide for Numonyx™ StrataFlash® Memory (J3) to Numonyx™ StrataFlash® Embedded Memory (P30/P33) Application Note 812 314750 Numonyx™ StrataFlash® Memory (P30) to Numonyx™ StrataFlash® Embedded Memory (P33) Conversion Guide Application Note 867 290737 Numonyx™ StrataFlash® Synchronous Memory (K3/K18) Datasheet 306669 Migration Guide for Numonyx™ StrataFlash® Synchronous Memory (K3/K18) to Numonyx™ StrataFlash® Embedded Memory (P30) Application Note 825 290701 Numonyx™ Wireless Flash Memory (W18) Datasheet 290702 Numonyx™ Wireless Flash Memory (W30) Datasheet 252802 Numonyx™ Flash Memory Design for a Stacked Chip Scale Package (SCSP) 298161 Numonyx™ Flash Memory Chip Scale Package User’s Guide 253418 Numonyx™ Wireless Communications and Computing Package User's Guide 296514 Numonyx™ Small Outline Package Guide 297833 Numonyx™ Flash Data Integrator (Numonyx™ FDI) User Guide 298136 Numonyx™ Persistent Storage Manager (Numonyx™ PSM) User Guide 306668 Migration Guide for Spansion* S29GLxxxN to Numonyx™ StrataFlash ® Embedded Memory (P30/P33) Application Note 813 Contact your local Numonyx or distribution sales office or visit Numonyx’s World Wide Web home page at http:// www.numonyx.com for technical documentation, tools, or the most current information on Numonyx™ Flash Memory. November 2007 Order Number: 306666-11 Datasheet 97 P30 Appendix E Ordering Information for Discrete Products Figure 46: Decoder for Discrete P30 T E 2 8 F 6 4 0 P 3 0 B 8 5 Package Designator Access Speed TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free Parameter Location 85 ns B = Bottom Parameter T = Top Parameter Product Line Designator 28F = Intel® Flash Memory Product Fam ily Device Density P30 = Intel StrataFlash® Embedded Memory V CC = 1.7 – 2.0 V V CCQ = 1.7 – 3.6 V 640 = 64-Mbit 128 = 128-Mbit 256 = 256-Mbit Table 49: Valid Combinations for Discrete Products Datasheet 98 64-Mbit 128-Mbit 256-Mbit TE28F640P30B85 TE28F128P30B85 TE28F256P30B95 TE28F640P30T85 TE28F128P30T85 TE28F256P30T95 JS28F640P30B85 JS28F128P30B85 JS28F256P30B95 JS28F640P30T85 JS28F128P30T85 JS28F256P30T95 RC28F640P30B85 RC28F128P30B85 RC28F256P30B85 RC28F640P30T85 RC28F128P30T85 RC28F256P30T85 PC28F640P30B85 PC28F128P30B85 PC28F256P30B85 PC28F640P30T85 PC28F128P30T85 PC28F256P30T85 November 2007 Order Number: 306666-11 P30 Appendix F Ordering Information for SCSP Products Flash Family 3/4 Flash Family 1/2 Flash #4 Flash #3 Flash #2 Flash #1 Figure 47: Decoder for SCSP P30 R D 4 8 F 4 0 0 0 P 0 Z B Q 0 Package Designator RD = Intel ® SCSP, leaded P F = Intel® SCSP, lead-free RC = 64-Ball Easy BG A, leaded P C = 64-Ball Easy BG A, lead-free T E = 56-Lead TSO P , leaded JS = 56-Lead T SO P, lead-free Device Details Group Designator 48F = Flash Memory only Q = Q UAD+ ballout 0 = Discrete ballout Flash Density Param eter, M ux Configuration 0 2 3 4 B = Bottom Param eter, Non Mux T = Top Param eter, Non M ux = = = = 0 = O riginal version of the product (refer to the latest version of the datasheet for details) Ballout Designator No die 64-Mbit 128-M bit 256-M bit I/O Voltage, CE# Configuration Z = Individual Chip Enable(s) V = Virtual Chip E nable(s) V C C = 1.7 V – 2.0 V V C C Q = 1.7 V – 3.6 V Product Fam ily P = Intel StrataF lash® Em bedded M em ory 0 = No die Note: For 512-Mbit only, “B” is used for both top and bottom Parameter/Mux configurations. Table 50: Valid Combinations for Dual- Die Products 64-Mbit 128-Mbit 256-Mbit 512-Mbit* RD48F2000P0ZBQ0 RD48F3000P0ZBQ0 RD48F4000P0ZBQ0 RD48F4400P0VBQ0 RD48F2000P0ZTQ0 RD48F3000P0ZTQ0 RD48F4000P0ZTQ0 PF48F4400P0VBQ0 PF48F2000P0ZBQ0 PF48F3000P0ZBQ0 PF48F4000P0ZBQ0 RC48F4400P0VB00 PF48F2000P0ZTQ0 PF48F3000P0ZTQ0 PF48F4000P0ZTQ0 PC48F4400P0VB00 TE48F4400P0VB00 JS48F4400P0VB00 Note: * The “B” parameter is used for both “top” and “bottom” options in the 512-Mbit density. November 2007 Order Number: 306666-11 Datasheet 99