TI CDC2516 3.3-v phase-lock loop clock driver Datasheet

CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
D
D
D
D
D
D
D
D
DGG PACKAGE
(TOP VIEW)
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to Four Banks
of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
On-Chip Series-Damping Resistors
No External RC Network Required
Operates at 3.3-V VCC
Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package
VCC
1Y0
1Y1
GND
GND
1Y2
1Y3
VCC
1G
GND
AVCC
CLK
AGND
AGND
GND
2G
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
description
The CDC2516 is a high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. It
uses a PLL to precisely align, in both frequency
and phase, the feedback output (FBOUT) to the
clock (CLK) input signal. It is specifically designed
for use with synchronous DRAMs. The CDC2516
operates at 3.3-V VCC and provides integrated
series-damping resistors that make it ideal for
driving point-to-point loads.
Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty cycles are adjusted to 50 percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the
G inputs are low, the outputs are disabled to the
logic-low state.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
VCC
4Y0
4Y1
GND
GND
4Y2
4Y3
VCC
4G
GND
AVCC
FBIN
AGND
FBOUT
GND
3G
VCC
3Y0
3Y1
GND
GND
3Y2
3Y3
VCC
Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground.
The CDC2516 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
FUNCTION TABLE
OUTPUTS
INPUTS
1G
2G
3G
4G
CLK
1Y
(0:3)
2Y
(0:3)
3Y
(0:3)
4Y
(0:3)
FBOUT
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
L
H
H
H
L
L
H
H
H
L
H
L
L
H
L
H
L
L
H
L
H
L
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
L
H
H
H
H
H
L
L
L
H
H
L
L
L
H
H
L
L
H
H
H
L
L
H
H
H
L
H
L
H
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
H
L
L
H
H
H
L
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
AVAILABLE OPTIONS
PACKAGE
2
TA
SMALL OUTLINE
(DGG)
0°C to 70°C
CDC2516DGGR
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CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
functional block diagram
1G
9
2
3
6
7
2G
19
22
23
30
27
26
12
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÁÁÁÁÁÁÁ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
PLL
FBIN
AVCC
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
40
47
CLK
1Y2
33
31
4G
1Y1
16
18
3G
1Y0
37
11
46
43
42
35
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4Y0
4Y1
4Y2
4Y3
FBOUT
3
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
Terminal Functions
TERMINAL
NAME
4
NO.
TYPE
DESCRIPTION
CLK
12
I
Clock input. CLK provides the clock signal to be distributed by the CDC2516 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
FBIN
37
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
1G
9
I
Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.
2G
16
I
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
3G
33
I
Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.
4G
40
I
Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.
FBOUT
35
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
1Y(0:3)
2, 3, 6, 7
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output
has an integrated 25-Ω series-damping resistor.
2Y(0:3)
18, 19, 22, 26
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output
has an integrated 25-Ω series-damping resistor.
3Y(0:3)
31, 30, 27, 26
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input. Each output
has an integrated 25-Ω series-damping resistor.
4Y(0:3)
47, 46, 43, 42
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input. Each output
has an integrated 25-Ω series-damping resistor.
AVCC
11, 38
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is
bypassed and CLK is buffered directly to the device outputs.
AGND
13, 14, 36
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
1, 8, 17, 24,
25, 32, 41, 48
Power
Power supply
GND
4, 5, 10, 15,
20, 21, 28, 29,
34, 39, 44, 45
Ground
Ground
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CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high
or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 4)
MIN
MAX
VCC
VIH
Supply voltage
3
3.6
High-level input voltage
2
VIL
VI
Low-level input voltage
IOH
IOL
UNIT
V
V
0.8
V
V
High-level output current
VCC
–12
mA
Low-level output current
12
mA
70
°C
Input voltage
0
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
ICC§
∆ICC
Ci
Co
TEST CONDITIONS
VCC
II = –18 mA
IOH = –100 µA
TYP‡
3V
MIN to MAX
IOH = –12 mA
IOH = – 6 mA
IOL = 100 µA
IOL = 12 mA
3V
VCC – 0.2
2.4
3V
2.1
IO = 0, Outputs: low or high
Other inputs at VCC or GND
MAX
UNIT
–1.2
V
V
MIN to MAX
IOL = 6 mA
VI = VCC or GND
VI = VCC or GND
One input at VCC – 0.6 V,
MIN
0.2
3V
0.8
3V
0.55
V
3.6 V
±5
µA
3.6 V
20
µA
3.3 V to 3.6 V
500
µA
VI = VCC or GND
VO = VCC or GND
3.3 V
4
pF
3.3 V
6
pF
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ For ICC of AVCC, see Figure 5. For dynamic digital ICC, see Figure 6.
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5
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
fclock
Clock frequency
Input clock duty cycle
Stabilization time†
MIN
MAX
UNIT
25
125
MHz
40%
60%
1
ms
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 5 and Figures 1 and 2)‡
FROM
(INPUT)
TO
(OUTPUT)
tphase error
reference
(see Figure 3)
66 MHz < CLKIN↑ < 100 MHz
FBIN↑
tphase error, – jitter,
(see Note 6)
CLKIN↑ = 100 MHz
FBIN↑
PARAMETER
tsk(o)§
Jitter(pk-pk)
VCC = 3.3 V
± 0.165 V
MIN
TYP
– 360
VCC = 3.3 V
± 0.3 V
MAX
MIN
50
TYP
UNIT
MAX
–0.7...0.18
ns
–170
ps
Any Y or FBOUT
Any Y or FBOUT
200
ps
F(clkin > 66 MHz)
Any Y or FBOUT
–100
100
ps
F(clkin ≤ 66 MHz)
Any Y or FBOUT
45%
55%
F(clkin > 66 MHz)
Any Y or FBOUT
43%
55%
0.7
2.1
ns
Any Y or FBOUT
1.7
2.5
1.2
2.5
‡ These parameters are not production tested.
§ The tsk(o) specification is only valid for equal loading of all outputs.
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is – 460 ps to 150 ps for the 5% VCC range.
ns
Duty cycle
tr
tf
6
Any Y or FBOUT
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1.9
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
3V
Input
50% VCC
50% VCC
0V
tpd
From Output
Under Test
30 pF
500 W
Output
2V
0.4 V
tr
50% VCC
VOH
2V
0.4 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
CLKIN
FBIN
tphase error
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Phase Error and Skew Calculations
8
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CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
CLOCK FREQUENCY
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
0
57%
VDD = 3.3 V
TA = 25°C
–100
VDD = 3.3 V
CL = 30 pF
55%
–200
53%
Output Duty Cycle
Phase Error – ps
–300
–400
–500
–600
–700
51%
49%
47%
–800
45%
–900
–1000
35
75
55
95
115
43%
135
30
50
fclk – Clock Frequency – MHz
70
Figure 3
500
VDD = 3.3 V
TA = 25°C
VCC = 3.6 V
Bias = 0/3 V
CL = 30 pF to GND
TA = 25°C
450
Dynamic Supply Current – mA
Analog Supply Current – mA
130
DYNAMIC SUPPLY CURRENT
vs
CLOCK FREQUENCY
9
7
6
5
4
3
2
1
0
25
110
Figure 4
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
8
90
fclk – Clock Frequency – MHz
400
350
300
250
200
150
100
50
35
45
55
65
75
85
95 105 115 125
0
0
20
fclk – Clock Frequency – MHz
40
60
80
100
120
140
fclk – Clock Frequency – MHz
Figure 5
Figure 6
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CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
PINS **
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
1
Gage Plane
24
A
0,25
0°– 8°
0,75
0,50
Seating Plane
1,20 MAX
0,05 MIN
0,10
4040078 / D 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-153
10
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Copyright  1998, Texas Instruments Incorporated