Renesas HD404889TE Low-voltage as microcomputers with on-chip lcd circuit Datasheet

HD404889/HD404899/HD404878/
HD404868 Series
Low-Voltage AS Microcomputers with On-Chip LCD Circuit
REJ03B0051-0600H
Rev. 6.00
Sep.08.2003
Description
The HD404889, HD404899, and HD404868 Series comprise low-voltage, 4-bit single-chip
microcomputers with a variety of on-chip supporting functions that include an LCD circuit, A/D converter,
multifunctional timers, and large-current I/O pins. These devices are suitable for system and display panel
control in a wide range of applications, including pagers, remote controllers, and home appliances equipped
with an LCD display.
The HD404878 Series comprises low-voltage, 4-bit single-chip microcomputers with no on-chip A/D
converter.
Each series is equipped with a 32.768 kHz sub-resonator for realtime clock use, providing a time counting
facility, and a variety of low-power modes to reduce current drain.
The HD4074889, HD4074899, and HD4074869 are ZTAT™ microcomputers with on-chip PROM that
drastically shortens development time and ensures a smooth transition from debugging to mass production.
(The PROM programming specifications are the same as for the 27256 type.)
TM
TM
ZTAT : Zero Turn-Around Time. ZTAT is a trademark of Renesas Technology Corp.
Rev.6.00, Sep.08.2003, page 1 of 197
HD404889/HD404899/HD404878/HD404868 Series
Features
• 46 I/O pins (HD404889/HD404899/HD404878 Series)
41 I/O pins (HD404868 Series)
Large-current I/O pins (source: 10 mA max.):4
Large-current I/O pins (sink: 15 mA max.): 8 (HD404889/HD404899/HD404878 Series)
6 (HD404868 Series)
LCD segment multiplexed pins:16
Analog input multiplexed pins: 6 (HD404889 and HD404899 Series)
4 (HD404868 Series)
• Four Timer/counters
8-bit timer: 2 (HD404889/HD404899/HD404878 Series)
1 (HD404868 Series)
16-bit timer:1 (Can also be used as two 8-bit timer)
• 8-bit input capture circuit (HD404889/HD404899/HD404878 Series)
• Two timer outputs (including PWM out-put)
• Two event counter inputs (edge-programmable) (HD404889/HD404899/HD404878 Series)
One event counter input (edge-programmable) (HD404868 Series)
• Clock-synchronous 8-bit serial interface
• A/D converter
6 channels × 8-bit (HD404889 Series)
6 channels × 10-bit (HD404899 Series)
4 channels × 10-bit (HD404868 Series)
• LCD controller/driver (32 segments × 4 commons) (HD404889/HD404899/HD404878 Series)
(24 segments × 4 commons) (HD404868 Series)
• On-chip oscillators
 Main clock (ceramic resonator, crystal resonator, or external clock operation possible)
 Sub-clock (32.768 kHz crystal resonator)
• Interrupts
External: 3 (including one edge-programmable)
Internal : 6 (HD404889 and HD404899 Series)
: 5 (HD404878 and HD404868 Series)
• Subroutine stack up to 16 levels, including interrupts
• Four Low-power dissipation modes
• Module standby (timers, serial interface, A/D converter)
• System clock division software switching (1/4 or 1/32)
• Inputs for return from stop mode (wakeup): 4
• Instruction execution time
Min. 0.89 µs (fOSC = 4.5 MHz)
• Operation voltage
1.8 V to 5.5 V
Rev.6.00, Sep.08.2003, page 2 of 197
HD404889/HD404899/HD404878/HD404868 Series
Cautions about operation!
• Electrical properties presented on the data sheet for the mask ROM and ZTATTM versions will surely
and sufficiently satisfy the standard values. However, real capabilities, operation margin, noise margin,
and other properties may vary depending on differences of manufacturing processes, internal wiring
patterns, etc. Therefore, it is requested for users to carry out an evaluation test for each product on an
actual system under the same conditions to see its operation.
• Memory register, data area, and stack area values are unstable immediately after power is turned on.
They must be initialized before use.
Ordering Information
HD404889 Series
Type
Product Name Model Name
Mask ROM HD404888
HD404888H
ROM (Words)
RAM (Digits)
Package
8,192
1,344
80-pin plastic QFP
(FP-80A)
HD404888TE
HD4048812
HD4048812H
80-pin plastic TQFP
(TFP-80C)
12,288
HD4048812TE
HD404889
TM
ZTAT
HD404889H
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
16,384
80-pin plastic QFP
(FP-80A)
HD404889TE
80-pin plastic TQFP
(TFP-80C)
HCD404889
HCD404889
Chip*
HD4074889
HD4074889H
HD4074889TE
TM
2
16,384
1
80-pin plastic QFP*
(FP-80A)
1
80-pin plastic TQFP*
(TFP-80C)
Notes: 1. ZTAT chip shipment is not supported.
2. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
Rev.6.00, Sep.08.2003, page 3 of 197
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
Type
Product Name Model Name
Mask ROM HD404898
HD404898H
ROM (Words)
RAM (Digits)
Package
8,192
1,344
80-pin plastic QFP
(FP-80A)
HD404898TE
HD4048912
HD4048912H
80-pin plastic TQFP
(TFP-80C)
12,288
80-pin plastic QFP
(FP-80A)
HD4048912TE
HD404899
TM
ZTAT
HD404899H
80-pin plastic TQFP
(TFP-80C)
16,384
80-pin plastic QFP
(FP-80A)
HD404899TE
80-pin plastic TQFP
(TFP-80C)
HCD404899
HCD404899
Chip*
HD4074899
HD4074899H
2
1
16,384
80-pin plastic QFP*
(FP-80A)
1
HD4074899TE
80-pin plastic TQFP*
(TFP-80C)
TM
Notes: 1. ZTAT chip shipment is not supported.
2. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details. In planning stage.
HD404878 Series
Type
Product Name Model Name
Mask ROM HD404874
HD404874H
ROM (Words)
RAM (Digits)
Package
4,096
880
80-pin plastic QFP
(FP-80A)
HD404874TE
HD404878
HD404878H
80-pin plastic TQFP
(TFP-80C)
8,192
HD404878TE
HCD404878
TM
ZTAT
80-pin plastic QFP
(FP-80A)
80-pin plastic TQFP
(TFP-80C)
2
HCD404878
Chip*
1
HD4074889 or HD4074899 is used.*
TM
Notes: 1. ZTAT chip shipment is not supported.
2. The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details. In planning stage.
Rev.6.00, Sep.08.2003, page 4 of 197
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
Type
Product Name Model Name
Mask ROM HD404864
HD404864H
ROM (Words)
RAM (Digits)
Package
4,096
408
64-pin plastic QFP
(FP-64A)
HD404864S
HD404868
TM
ZTAT
HD404868H
64-pin plastic DILP
(DP-64S)
8,192
64-pin plastic QFP
(FP-64A)
HD404868S
64-pin plastic DILP
(DP-64S)
HCD404868
HCD404868
Chip*1
HD4074869
HD4074869H
HD4074869S
Note: 1. In planning stage
Rev.6.00, Sep.08.2003, page 5 of 197
16,384
64-pin plastic QFP
(FP-64A)
64-pin plastic DILP
(DP-64S)
HD404889/HD404899/HD404878/HD404868 Series
List of Functions
Product Name
ROM (words)
RAM (digit)
HD404888
HD4048812
8,192
12,288
HD404889
HCD404889
16,384
1,344
I/O
46 (max)
Large-current I/O pins
4 (source, 10 mA max), 8 (sink, 15 mA max)
LCD segment multiplexed pins
16
Analog input multiplexed pins
6
Timer/counter
16-bit timer: 1 (Can also be used as two 8-bit timer),
8-bit timer: 2
Input capture
8 bit × 1
Timer output
2 (PWM output possible)
Event input
2 (edge selection possible)
Serial interface
1 (8-bit synchronous)
A/D converter
8 bits × 6 channels
Max. 32 seg × 4 com
LCD circuit
Interrupt sources
External
3 (edge selection possible for 1)
Internal
6
Low-power modes
4
Stop mode
O
Watch mode
O
Standby mode
O
Subactive mode
O
Module standby
O
System clock division software switching
O
Main oscillator
Ceramic oscillation
O
Crystal oscillation
O
Crystal oscillation
O (32.768kHz)
Sub-oscillator
Minimum instruction execution time
Operating voltage (V)
Package
0.89µs(fOSC=4.5MHz)
1.8 to 5.5
80-pin plastic QFP (FP-80A)
Chip
80-pin plastic TQFP (TFP-80C)
Guaranteed operation temperature(°C)
Rev.6.00, Sep.08.2003, page 6 of 197
–20 to +75
+75
HD404889/HD404899/HD404878/HD404868 Series
Product Name
ROM (words)
HD4074889
HD404898
HD4048912
HD404899
16,384PROM
8,192
12,288
16,384
RAM (digit)
1,344
I/O
46 (max)
Large-current I/O pins
4 (source, 10 mA max), 8 (sink, 15 mA max)
LCD segment multiplexed pins
16
Analog input multiplexed pins
6
Timer/counter
16-bit timer: 1 (Can also be used as two 8-bit timer),
8-bit timer: 2
8 bit × 1
Input capture
Timer output
2 (PWM output possible)
Event input
2 (edge selection possible)
Serial interface
1 (8-bit synchronous)
8 bits × 6
channels
A/D converter
Max. 32 seg × 4 com
LCD circuit
Interrupt sources
10 bits × 6 channels
External
3 (edge selection possible for 1)
Internal
6
Low-power modes
4
Stop mode
O
Watch mode
O
Standby mode
O
Subactive mode
O
Module standby
O
System clock division software switching
O
Main oscillator
Ceramic oscillation
O
Crystal oscillation
O
Sub-oscillator
Crystal oscillation
O (32.768kHz)
Minimum instruction execution time
Operating voltage (V)
Package
Guaranteed operation temperature(°C)
Rev.6.00, Sep.08.2003, page 7 of 197
0.89µs(fOSC=4.5MHz)
2.0 to 5.5
1.8 to 5.5
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
–20 to +75
HD404889/HD404899/HD404878/HD404868 Series
Product Name
ROM (words)
HD40C4899
HD4074899
HD404874
HD404878
16,384
16,384PROM
4,096
8,192
RAM (digit)
1,344
880
I/O
46 (max)
Large-current I/O pins
4 (source, 10 mA max), 8 (sink, 15 mA max)
LCD segment multiplexed pins
16
Analog input multiplexed pins
Timer/counter
6
—
16-bit timer: 1 (Can also be used as two 8-bit timer),
8-bit timer: 2
8 bit × 1
Input capture
Timer output
2 (PWM output possible)
Event input
2 (edge selection possible)
Serial interface
1 (8-bit synchronous)
10 bits × 6 channels
A/D converter
Max. 32 seg × 4 com
LCD circuit
Interrupt sources
—
External
3 (edge selection possible for 1)
Internal
6
5
Low-power modes
4
Stop mode
O
Watch mode
O
Standby mode
O
Subactive mode
O
Module standby
O
System clock division software switching
O
Main oscillator
Ceramic oscillation
O
Crystal oscillation
O
Crystal oscillation
O (32.768kHz)
Sub-oscillator
Minimum instruction execution time
Operating voltage (V)
Package
0.89µs(fOSC=4.5MHz)
1.8 to 5.5
Chip
2.0 to 5.5
1.8 to 5.5
80-pin plastic QFP (FP-80A)
80-pin plastic TQFP (TFP-80C)
Guaranteed operation temperature(°C)
Rev.6.00, Sep.08.2003, page 8 of 197
+75
–20 to +75
HD404889/HD404899/HD404878/HD404868 Series
Product Name
ROM (words)
RAM (digit)
I/O
HCD404878
HD404864
HD404868
HD4074869
8,192
4,096
8,192
16,384PROM
880
408
46 (max)
Large-current I/O pins
4 (source,
10 mA max),
8 (sink,
15 mA max)
41 (max)
4 (source, 10 mA max), 6 (sink, 15 mA max)
LCD segment multiplexed pins
Analog input multiplexed pins
Timer/counter
16
—
16-bit timer: 1
(Can also be
used as two
8-bit timer),
8-bit timer: 2
Input capture
8 bit × 1
Timer output
Event input
—
2 (PWM output possible)
2 (edge
selection
possible)
Serial interface
1 (edge selection possible)
1 (8-bit synchronous)
A/D converter
—
10 bits × 4 channels
Max. 32 seg × Max. 24 seg × 4 com
4 com
LCD circuit
Interrupt sources
4
16-bit timer: 1 (Can also be used as two 8-bit
timer), 8-bit timer: 1
External
3 (edge selection possible for 1)
Internal
5
Low-power modes
4
Stop mode
O
Watch mode
O
Standby mode
O
Subactive mode
O
Module standby
O
System clock division software switching
O
Main oscillator
Ceramic oscillation
O
Crystal oscillation
O
Sub-oscillator
Crystal oscillation
O (32.768kHz)
Minimum instruction execution time
Operating voltage (V)
0.89µs(fOSC=4.5MHz)
1.8 to 5.5
Package
Chip
Guaranteed operation temperature(°C)
+75
2.0 to 5.5
64-pin plastic QFP (FP-64A)
64-pin plastic DILP (DP-64S)
Rev.6.00, Sep.08.2003, page 9 of 197
–20 to +75
HD404889/HD404899/HD404878/HD404868 Series
Pin Arrangement
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
V0
V1
V2
V3
COM4
COM3
COM2
COM1
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
HD404889/HD404899 Series
AVcc
R70/AN0
R71/AN1
R72/AN2
R73/AN3
R80/AN4
R81/AN5
AVss
TEST
OSC1
OCS2
GND
X2
X1
RESET
FP-80A
TFP-80C
(Top View)
D4
D5
D6
D7
D8
D9
D10
D11
R00/WU0
R01/WU1
R02/WU2
R03/WU3
R10/EVNB
R11/EVND
R12/BUZZ
R13/TOB
R20/TOC
R21/SCK
R22/SI/SO
R23
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Vcc
D0/INT0
D1/INT1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Rev.6.00, Sep.08.2003, page 10 of 197
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG20
SEG19
SEG18
SEG17
R63/SEG16
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
HD404889/HD404899/HD404878/HD404868 Series
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
V0
V1
V2
V3
COM4
COM3
COM2
COM1
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
HD404878 Series
NC
R70
R71
R72
R73
R80
R81
NC
TEST
OSC1
OSC2
GND
X2
X1
RESET
FP-80A
TFP-80C
(Top View)
D4
D5
D6
D7
D8
D9
D10
D11
R00/WU0
R01/WU1
R02/WU2
R03/WU3
R10/EVNB
R11/EVND
R12/BUZZ
R13/TOB
R20/TOC
R21/SCK
R22/SI/SO
R23
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Vcc
D0/INT0
D1/INT1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Rev.6.00, Sep.08.2003, page 11 of 197
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG20
SEG19
SEG18
SEG17
R63/SEG16
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
HD404889/HD404899/HD404878/HD404868 Series
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
V1
V2
V3
COM4
COM3
COM2
COM1
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
R63/SEG16
HD404868 Series
R70/AN0
R71/AN1
R72/AN2
R73/AN3
TEST
OSC1
OSC2
GND
X2
X1
RESET
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
FP-64A
(Top View)
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
R23
D4
D5
D6
D7
D8
D9
R00/WU0
R01/WU1
R02/WU2
R10/EVNB
R11
R12/BUZZ
R13/TOB
R20/TOC
R21/SCK
R22/SI/SO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Vcc
D0/INT0
D1/INT1
D2
D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
COM1
COM2
COM3
COM4
V3
V2
V1
R70/AN0
R71/AN1
R72/AN2
R73/AN3
TEST
OSC1
OSC2
GND
X2
X1
RESET
Vcc
D0/INT0
D1/INT1
D2
D3
D4
D5
D6
D7
D8
D9
R00/WU0
R01/WU1
R02/WU2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Rev.6.00, Sep.08.2003, page 12 of 197
DP-64S
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
R63/SEG16
R62/SEG15
R61/SEG14
R60/SEG13
R53/SEG12
R52/SEG11
R51/SEG10
R50/SEG9
R43/SEG8
R42/SEG7
R41/SEG6
R40/SEG5
R33/SEG4
R32/SEG3
R31/SEG2
R30/SEG1
R23
R22/SI/SO
R21/SCK
R20/TOC
R13/TOB
R12/BUZZ
R11
R10/EVNB
HD404889/HD404899/HD404878/HD404868 Series
Pad Arrangement
1
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
79
80
HCD404889, HCD404899
Model Name
2
60
3
59
5
57
7
55
4
58
6
56
8
54
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
39
40
37
38
35
36
33
34
31
32
29
30
27
28
25
26
23
24
22
21
41
Model Name: HD404889 (HD404889)
HD404899 (HD404899)
Rev.6.00, Sep.08.2003, page 13 of 197
HD404889/HD404899/HD404878/HD404868 Series
Pad Coordinates
HCD404889, HCD404899
Y
Chip size (X × Y):
Coordinates:
Home point position: Chip center
Pad size (X × Y):
90 × 90 (µm)
Mold
X
Chip center
(X=0,Y=0)
Rev.6.00, Sep.08.2003, page 14 of 197
4.63 × 4.77 (mm)
Pad center
Chip thickness:
280 (µm)
HD404889/HD404899/HD404878/HD404868 Series
Coodinates
Coodinates
Pad No.
Pad name
X (µm)
Y (µm)
Pad No.
Pad name
X (µm)
Y (µm)
1
AVCC
–2129
1779
41
R30/SEG1
2129
–1787
2
R70/AN0
–2129
1589
42
R31/SEG2
2129
–1616
3
R71/AN1
–2129
1417
43
R32/SEG3
2129
–1445
4
R72/AN2
–2129
1246
44
R33/SEG4
2129
–1273
5
R73/AN3
–2129
1074
45
R40/SEG5
2129
–1102
6
R80/AN4
–2129
903
46
R41/SEG6
2129
–973
7
R81/AN5
–2129
732
47
R42/SEG7
2129
–759
8
AVSS
–2129
506
48
R43/SEG8
2129
–588
9
TEST
–2129
103
49
R50/SEG9
2129
–417
10
OSC1
–2129
–68
50
R51/SE10
2129
–245
11
OSC2
–2129
–240
51
R52/SEG11
2129
–74
12
GND
–2129
–434
52
R53/SEG12
2129
98
13
X2
–2129
–605
53
R60/SEG13
2129
269
14
X1
–2129
–776
54
R61/SEG14
2129
440
15
RESETN
–2129
–948
55
R62/SEG15
2129
612
16
VCC
–2129
–1119
56
R63/SEG16
2129
783
17
D0/INT0N
–2129
–1290
57
SEG17
2129
954
18
D1/INT1
–2129
–1462
58
SEG18
2129
1126
19
D2
–2129
–1633
59
SEG19
2129
1297
20
D3
–2129
–1804
60
SEG20
2129
1477
21
D4
–1677
–2199
61
SEG21
1588
2199
22
D5
–1506
–2199
62
SEG22
1407
2199
23
D6
–1335
–2199
63
SEG23
1236
2199
24
D7
–1163
–2199
64
SEG24
1064
2199
25
D8
–992
–2199
65
SEG25
893
2199
26
D9
–821
–2199
66
SEG26
722
2199
27
D10
–649
–2199
67
SEG27
550
2199
28
D11
–478
–2199
68
SEG28
379
2199
29
R00/WU0N
–307
–2199
69
SEG29
208
2199
30
R01/WU1N
–135
–2199
70
SEG30
36
2199
31
R02/WU2N
36
–2199
71
SEG31
–135
2199
32
R03/WU3N
208
–2199
72
SEG32
–307
2199
33
R10/EVNB
379
–2199
73
COM1
–478
2199
34
R11/EVND
550
–2199
74
COM2
–649
2199
35
R12/BUZZ
722
–2199
75
COM3
–821
2199
36
R13/TOB
893
–2199
76
COM4
–992
2199
37
R20/TOC
1064
–2199
77
V3
–1163
2199
38
R21/SCKN
1236
–2199
78
V2
–1335
2199
39
R22/Si/SO
1407
–2199
79
V1
–1506
2199
40
R23
1588
–2199
80
V0
–1677
2199
Rev.6.00, Sep.08.2003, page 15 of 197
HD404889/HD404899/HD404878/HD404868 Series
Pad Arrangement
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
77
78
HCD404878
Model Name
1
58
2
57
4
55
6
53
8
51
10
49
12
47
14
45
16
43
18
41
3
56
5
54
7
52
9
50
11
48
13
46
15
44
17
42
40
37
38
35
36
33
34
31
32
29
30
27
28
25
26
23
24
21
22
20
19
39
Model Name: HD404878 (HCD404878)
Rev.6.00, Sep.08.2003, page 16 of 197
HD404889/HD404899/HD404878/HD404868 Series
Pad Coordinates
HCD404878
Y
X
Rev.6.00, Sep.08.2003, page 17 of 197
4.13 × 4.26 (mm)
Coordinates:
Pad center
Home point position: Chip center
Pad size (X × Y):
90 × 90 (µm)
Mold
Chip center
(X=0,Y=0)
Chip size (X × Y):
Chip thickness:
280 (µm)
HD404889/HD404899/HD404878/HD404868 Series
Coodinates
Coodinates
Pad No.
Pad name
X (µm)
Y (µm)
Pad No.
Pad name
X (µm)
Y (µm)
1
R70
–1879
1446
40
R31/SEG2
1879
–1405
2
R71
–1879
1280
41
R32/SEG3
1879
–1239
3
R72
–1879
1114
42
R33/SEG4
1879
–1072
4
R73
–1879
948
43
R40/SEG5
1879
–906
5
R80
–1879
781
44
R41/SEG6
1879
–740
6
R81
–1879
615
45
R42/SEG7
1879
–573
7
TEST
–1879
449
46
R43/SEG8
1879
–407
8
OSC1
–1879
282
47
R50/SEG9
1879
–241
9
OSC2
–1879
116
48
R51/SE10
1879
–74
10
GND
–1879
–73
49
R52/SEG11
1879
92
11
X2
–1879
–239
50
R53/SEG12
1879
258
12
X1
–1879
–406
51
R60/SEG13
1879
425
13
RESETN
–1879
–572
52
R61/SEG14
1879
591
14
VCC
–1879
–738
53
R62/SEG15
1879
757
15
D0/INT0N
–1879
–905
54
R63/SEG16
1879
924
16
D1/INT1
–1879
–1071
55
SEG17
1879
1087
17
D2
–1879
–1237
56
SEG18
1879
1246
18
D3
–1879
–1404
57
SEG19
1879
1405
19
D4
–1654
–1943
58
SEG20
1879
1564
20
D5
–1488
–1943
59
SEG21
1509
1943
21
D6
–1322
–1943
60
SEG22
1351
1943
22
D7
–1155
–1943
61
SEG23
1192
1943
23
D8
–989
–1943
62
SEG24
1033
1943
24
D9
–823
–1943
63
SEG25
874
1943
25
D10
–656
–1943
64
SEG26
716
1943
26
D11
–490
–1943
65
SEG27
557
1943
27
R00/WU0N
–324
–1943
66
SEG28
398
1943
28
R01/WU1N
–158
–1943
67
SEG29
239
1943
29
R02/WU2N
9
–1943
68
SEG30
81
1943
30
R03/WU3N
175
–1943
69
SEG31
–78
1943
31
R10/EVNB
341
–1943
70
SEG32
–237
1943
32
R11/EVND
508
–1943
71
COM1
–411
1943
33
R12/BUZZ
674
–1943
72
COM2
–570
1943
34
R13/TOB
840
–1943
73
COM3
–728
1943
35
R20/TOC
1007
–1943
74
COM4
–887
1943
36
R21/SCKN
1173
–1943
75
V3
–1038
1943
37
R22/Si/SO
1339
–1943
76
V2
–1194
1943
38
R23
1506
–1943
77
V1
–1351
1943
39
R30/SEG1
1879
–1571
78
V0
–1507
1943
Rev.6.00, Sep.08.2003, page 18 of 197
HD404889/HD404899/HD404878/HD404868 Series
Pin Description
HD404889/HD404899/HD404878 Series
Pin Number
Item
Symbol
FP-80A
TFP-80C
I/O
Function
Power supply
VCC
16
—
Apply the power supply voltage to this pin.
GND
12
—
Connect to ground.
Test
TEST
9
Input
Not for use by the user application. Connect to
GND potential.
Reset
RESET
15
Input
Used to reset the MCU.
Oscillation
OSC1
10
Input
OSC2
11
Output
Internal oscillator input/output pins. Connect a
ceramic resonator, crystal resonator, or external
oscillator circuit.
X1
14
Input
X2
13
Output
D0–D11
17–28
I/O
I/O pins addressed bit by bit. D0 to D3 are largecurrent source pins (max. 10 mA), and D4 to D11
are large-current sink pins (max. 15 mA).
R00–R63
R70–R81
29–56, 2–7
I/O
I/O pins, addressed in 4-bit units.
Interrupt
INT0,INT1
17,18
Input
External interrupt input pins
Wakeup
WU0–WU3
29–32
Input
Input pins used for transition from stop mode to
active mode.
Serial interface
SCK
38
I/O
Serial interface clock I/O pin
SI
39
Input
Serial interface receive data input pin
Port
Timer
LCD
Realtime clock oscillator input/output pins.
Connect a 32.768 kHz crystal. If 32.768 kHz
crystal oscillation is not used, fix the ×1 pin to VCC
and leave the ×2 pin open.
SO
39
Output Serial interface transmit data output pin
TOB,TOC
36,37
Output Timer output pins
EVNB,EVND
33,34
Input
Event count input pins
V0–V3
80–77
—
LCD driver power supply pins. The on-chip power
supply dividing resistor can be disconnected by
software. Power supply conditions are:
VCC≥V1≥V2≥V3≥GND.
COM1–COM4 73–76
Output LCD common signal pins
SEG1–SEG32 41–72
Output LCD segment signal pins
Rev.6.00, Sep.08.2003, page 19 of 197
HD404889/HD404899/HD404878/HD404868 Series
Pin Number
Item
1
A/D converter*
Symbol
FP-80A
TFP-80C
I/O
Function
AVCC
1
—
A/D converter power supply pin. Connect as close
as possible to the VCC pin so as to be at the same
potential as VCC.
AVSS
8
—
Ground pin for AVCC. Connect as close as
possible to the GND pin so as to be at the same
potential as GND.
A/D converter analog input pins
AN0–AN5
2–7
Input
Buzzer output
BUZZ
35
Output Timer overflow toggle output or divided system
clock output pin
Other
NC
1, 8*
2
—
Notes: 1. Applies to HD404889 and HD404899 series.
2. Applies to HD404878 series.
Rev.6.00, Sep.08.2003, page 20 of 197
Connect to ground potential.
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
Pin Number
Item
Symbol
FP-64A
DP-64S I/O
Function
Power supply
VCC
12
19
—
Apply the power supply voltage to this pin.
GND
8
15
—
Connect to ground.
Test
TEST
5
12
Input
Not for use by the user application. Connect
to GND potential.
Reset
RESET
11
18
Input
Used to reset the MCU.
Oscillation
OSC1
6
13
Input
OSC2
7
14
Output
Internal oscillator input/output pins. Connect
a ceramic resonator, crystal resonator, or
external
oscillator circuit.
X1
10
17
Input
X2
9
16
Output
D0–D9
13–22
20–29
I/O
I/O pins addressed bit by bit. D0 to D3 are
large-current source pins (max. 10 mA), and
D4 to D9 are large-current sink pins (max. 15
mA).
R00–R02
R10–R63
R70–R73
23–25
26–49
1–4
30–32
33–56
8–11
I/O
I/O pins, addressed in 4-bit units.
Interrupt
INT0,INT1
13,14
20, 21
Input
External interrupt input pins
Wakeup
WU0–WU2
23–25
30–32
Input
Input pins used for transition from stop mode
to active mode.
Serial interface
SCK
31
38
I/O
Serial interface clock I/O pin
SI
32
39
Input
Serial interface receive data input pin
SO
32
39
Output Serial interface transmit data output pin
Port
Timer
LCD
Realtime clock oscillator input/output pins.
Connect a 32.768 kHz crystal. If 32.768 kHz
crystal oscillation is not used, fix the ×1 pin to
VCC and leave the ×2 pin open.
TOB,TOC
29, 30
36, 37
Output Timer output pins
EVNB
26
33
Input
Event count input pins
V1–V3
64–62
7–5
—
LCD driver power supply pins. The on-chip
power supply dividing resistor can be
disconnected by software. Power supply
conditions are: VCC≥ V1≥ V2≥ V3≥ GND.
COM1–COM4 58–61
1–4
Output LCD common signal pins
SEG1–SEG24 34–57
41–64
Output LCD segment signal pins
A/D converter
AN0–AN3
1–4
8–11
Input
Buzzer output
BUZZ
28
35
Output Timer overflow toggle output or divided
system clock output pin
Rev.6.00, Sep.08.2003, page 21 of 197
A/D converter analog input pins
HD404889/HD404899/HD404878/HD404868 Series
Block DiagramG
WU0
WU1
WU2
WU3
TEST
OSC1
OSC2
X1
X2
Vcc
GND
RESET
HD404889/HD404899 Series
ROM
D Port
HMCS400 CPU
External interrupt
control circuit
INT1
8-bit timer A
TOB
R1 Port
INT0
R0 Port
RAM
SCK
Synchronous
serial interface
SI/SO
AVcc
AN0
AN1
AN2
AN3
AN4
AN5
AVss
A/D converter
8-bit × 6 channels
(HD404889 Series)
10-bit × 6 channels
(HD404899 Series)
LCD circuit
32-segment × 4 common
BUZZ
Buzzer output circuit
R8 Port
R7 Port
SEG1
to
SEG32
COM1
to
COM4
V0
V1
V2
V3
R3 Port
8-bit timer D
R4 Port
EVND
R5 Port
8-bit timer C
R6 Port
TOC
R2 Port
8-bit timer B
EVNB
: Data bus
Rev.6.00, Sep.08.2003, page 22 of 197
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
P-MOS largecurrent buffer
N-MOS largecurrent buffer
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
R30
R31
R32
R33
R40
R41
R42
R43
R50
R51
R52
R53
R60
R61
R62
R63
R70
R71
R72
R73
R80
R81
: Signal line
HD404889/HD404899/HD404878/HD404868 Series
WU0
WU1
WU2
WU3
TEST
OSC1
OSC2
X1
X2
Vcc
GND
RESET
HD404878 Series
ROM
D Port
HMCS400 CPU
External interrupt
control circuit
INT1
8-bit timer A
TOB
R1 Port
INT0
R0 Port
RAM
EVND
8-bit timer D
SCK
Clock-synchronous
8-bit serial interface
R6 Port
R5 Port
SI/SO
R3 Port
8-bit timer C
R4 Port
TOC
R2 Port
8-bit timer B
EVNB
LCD circuit
32-segment × 4 common
BUZZ
Buzzer output circuit
R8 Port
R7 Port
SEG1
to
SEG32
COM1
to
COM4
V0
V1
V2
V3
: Data bus
Rev.6.00, Sep.08.2003, page 23 of 197
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
P-MOS largecurrent buffer
N-MOS largecurrent buffer
R00
R01
R02
R03
R10
R11
R12
R13
R20
R21
R22
R23
R30
R31
R32
R33
R40
R41
R42
R43
R50
R51
R52
R53
R60
R61
R62
R63
R70
R71
R72
R73
R80
R81
: Signal line
HD404889/HD404899/HD404878/HD404868 Series
WU0
WU1
WU2
TEST
OSC1
OSC2
X1
X2
VCC
GND
RESET
HD404868 Series
D Port
R0 Port
R00
R01
R02
R1 Port
R10
R11
R12
R13
R2 Port
R20
R21
R22
R23
R3 Port
R30
R31
R32
R33
R4 Port
R40
R41
R42
R43
R5 Port
INT0
R50
R51
R52
R53
R6 Port
RAM
ROM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
R60
R61
R62
R63
R7 Port
HMCS400 CPU
R70
R71
R72
R73
External interrupt control circuit
INT1
8-bit timer A
EVNB
TOB
8-bit timer B
TOC
8-bit timer C
SCK
SI/SO
Clock-synchronous 8-bit serial interface
AN0
AN1
AN2
AN3
A/D converter
4 channels × 10-bit
SEG1
~
~
SEG24
COM1
~
~
COM4
V1
V2
V3
BUZZ
Rev.6.00, Sep.08.2003, page 24 of 197
LCD circuit
24-segment × 4 common
Buzzer output circuit
P-MOS largecurrent buffer
N-MOS largecurrent buffer
HD404889/HD404899/HD404878/HD404868 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and is described below.
Vector address area ($0000 to $000F): When an MCU reset or interrupt handling is performed, the
program is executed from the vector address. A JMPL instruction should be used to branch to the start
address of the reset routine or the interrupt routine.
Zero page subroutine area ($0000 to $003F):A branch can be made to a subroutine in the area $0000 to
$003F with the CAL instruction.
Pattern area ($0000 to $0FFF): ROM data in the area $0000 to $0FFF can be referenced as pattern data
with the P instruction.
Program area ($0000 to $0FFF(HD404874, HD404864)), ($0000 to $1FFF (HD404888, HD404898,
HD404878, HD404868, HCD404878)), ($0000 to $2FFF (HD4048812, HD4048912)), ($0000 to $3FFF
(HD404889, HD404899, HCD404889, HCD404899, HD4074899, HD4074889, HD4074869))
Rev.6.00, Sep.08.2003, page 25 of 197
HD404889/HD404899/HD404878/HD404868 Series
$0000
$0000
Vector addresses
(16 words)
$0001
$000F
$0002
Zero page subroutine area
(64 words)
$003F
$0003
$0004
$0005
$0006
HD404874/HD404864
pattern/program area
(4,096 words)
$0007
$0008
$0009
$000A
$0FFF
$000B
HD404888/HD404898/HD404878/
HD404868/HCD404878
pattern/program area
(8,192 words)
$000C
$000D
$000E
$000F
JMPL instruction
(Jump to reset routine)
JMPL instruction
(Jump to WU0 to WU3 routine)
JMPL instruction
(Jump to INT0 routine)
JMPL instruction
(Jump to INT1 routine)
JMPL instruction
(Jump to timer A routine)
JMPL instruction
(Jump to timer B/timer D routine)
JMPL instruction
(Jump to timer C routine)
JMPL instruction
(Jump to A/D or serial interface routine)
$1FFF
HD4048812/HD4048912
pattern/program area
(12,288 words)
$2FFF
HD404889/HD4074889/
HD404899/HD4074899/HD4074869/
HCD404889/HCD404899
pattern/program area
(16,384 words)
$3FFF
Figure 1 ROM Memory Map
RAM Memory Map
The MCU has on-chip RAM comprising a memory register area, LCD data area, data area, and stack area.
In addition to these areas, an interrupt control bit area, special register area, and register flag area are
mapped onto RAM memory space as a RAM-mapped register area.The RAM memory map is shown in
figure 2 and described below.
Memory register, LCD data area, data area, and stack area values are unstable immediately after
power is turned on. They must be initialized before use.
Rev.6.00, Sep.08.2003, page 26 of 197
HD404889/HD404899/HD404878/HD404868 Series
HD404889 Series
$000
RAM-mapped
register area
$03F
$040
$04F
$050
Memory register (MR) area
(16 digits)
LCD data area
(32 digits)
$06F
$070
Not used
$08F
$090
Data (464 digits)
Data (464 digits)
V = 1 (bank = 1)
V = 0 (bank = 0)
$25F
$260
Data (304 digits)
$38F
$390
Not used
$3BF
$3C0
Stack area
(64 digits)
$3FF
Notes: R
W
: Read
: Write
R/W : Read/Write
*Two registers are mapped onto the
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Interrupt control bit area
Speed Select Reg.
(SSR)
Miscellaneous Reg.
(MIS)
Edge Select Reg.
(ESR)
Not used
Port Mode Reg.0
(PMR0)
Port Mode Reg.1
(PMR1)
Port Mode Reg.2
(PMR2)
Port Mode Reg.3
(PMR3)
Port Mode Reg.4
(PMR4)
Module Standby Reg.1
(MSR1)
Module Standby Reg.2
(MSR2)
Timer Mode Reg.A
(TMA)
Timer Mode Reg.B1
(TMB1)
Timer Mode Reg.B2
(TMB2)
(TRBL/TWBL)
Timer-B
(TRBU/TWBU)
Timer Mode Reg.C1
(TMC1)
Timer Mode Reg.C2
(TMC2)
(TRCL/TWCL)
Timer-C
(TRCU/TWCU)
Timer Mode Reg.D1
(TMD1)
Timer Mode Reg.D2
(TMD2)
(TRDL/TWDL)
Timer-D
(TRDU/TWDU)
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
Not used
Register flag area
Serial Mode Reg.1
Serial Mode Reg.2
Serial Data Reg.Lower
Serial Data Reg.Upper
A/D Mode reg.
Not used
A/D Data Reg.Lower
A/D Data Reg.Upper
LCD Control Reg.
LCD Mode Reg.
Buzzer Mode Reg.
Not used
Port D0~D3 DCR
Port D4~D7 DCR
Port D8~D11 DCR
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
(SMR1) W
(SMR2) W
(SRL) R/W
(SRU) R/W
(AMR) W
(ADRL)
(ADRU)
(LCR)
(LMR)
(BMR)
R
R
W
W
W
(DCD0)
(DCD1)
(DCD2)
W
W
W
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
W
W
W
W
W
W
W
W
W
Not used
Vreg.
(V) R/W
$012
$013
Timer Read Reg.B Lower
Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL) W
(TWBU) W
$016
$017
Timer Read Reg.C Lower
Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL) W
(TWCU) W
$01A
$01B
Timer Read Reg.D Lower
Timer Read Reg.D Upper
(TRDL)
(TRDU)
R
R
Timer Write Reg.D Lower
Timer Write Reg.D Upper
(TWDL) W
(TWDU) W
same address ($012, $013, $016,
$017, $01A, $01B).
Figure 2 RAM Memory Map
Rev.6.00, Sep.08.2003, page 27 of 197
**
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
$000
RAM-mapped
register area
$03F
$040
$04F
$050
Memory register (MR) area
(16 digits)
LCD data area
(32 digits)
$06F
$070
Not used
$08F
$090
Data (464 digits)
Data (464 digits)
V = 1 (bank = 1)
V = 0 (bank = 0)
$25F
$260
Data (304 digits)
$38F
$390
Not used
$3BF
$3C0
Stack area
(64 digits)
$3FF
Notes: R
W
: Read
: Write
R/W : Read/Write
*Two registers are mapped onto the
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
Interrupt control bit area
Speed Select Reg.
(SSR)
Miscellaneous Reg.
(MIS)
Edge Select Reg.
(ESR)
Not used
Port Mode Reg.0
(PMR0)
Port Mode Reg.1
(PMR1)
Port Mode Reg.2
(PMR2)
Port Mode Reg.3
(PMR3)
Port Mode Reg.4
(PMR4)
Module Standby Reg.1
(MSR1)
Module Standby Reg.2
(MSR2)
Timer Mode Reg.A
(TMA)
Timer Mode Reg.B1
(TMB1)
Timer Mode Reg.B2
(TMB2)
(TRBL/TWBL)
Timer-B
(TRBU/TWBU)
Timer Mode Reg.C1
(TMC1)
Timer Mode Reg.C2
(TMC2)
(TRCL/TWCL)
Timer-C
(TRCU/TWCU)
Timer Mode Reg.D1
(TMD1)
Timer Mode Reg.D2
(TMD2)
(TRDL/TWDL)
Timer-D
(TRDU/TWDU)
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
Not used
Register flag area
Serial Mode Reg.1
Serial Mode Reg.2
Serial Data Reg.Lower
Serial Data Reg.Upper
A/D Mode reg.
A/D Data Reg.Lower
A/D Data Reg.Middle
A/D Data Reg.Upper
LCD Control Reg.
LCD Mode Reg.
Buzzer Mode Reg.
Not used
Port D0~D3 DCR
Port D4~D7 DCR
Port D8~D11 DCR
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
(SMR1) W
(SMR2) W
(SRL) R/W
(SRU) R/W
(AMR) W
(ADRL) R
(ADRM) R
(ADRU) R
(LCR) W
(LMR) W
(BMR) W
(DCD0)
(DCD1)
(DCD2)
W
W
W
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
W
W
W
W
W
W
W
W
W
Not used
Vreg.
(V) R/W
$012
$013
Timer Read Reg.B Lower
Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL) W
(TWBU) W
$016
$017
Timer Read Reg.C Lower
Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL) W
(TWCU) W
$01A
$01B
Timer Read Reg.D Lower
Timer Read Reg.D Upper
(TRDL)
(TRDU)
R
R
Timer Write Reg.D Lower
Timer Write Reg.D Upper
(TWDL) W
(TWDU) W
same address ($012, $013, $016,
$017, $01A, $01B).
Figure 2 RAM Memory Map (cont)
Rev.6.00, Sep.08.2003, page 28 of 197
*
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
$000
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
RAM-mapped
register area
$03F
$040
$04F
$050
Memory register (MR) area
(16 digits)
LCD data area
$06F
$070
(32 digits)
Not used
$08F
$090
Data (768 digits)
$38F
$390
Not used
$3BF
$3C0
Stack area
(64 digits)
$3FF
Notes: R
W
: Read
: Write
R/W : Read/Write
*Two registers are mapped onto the
Interrupt control bit area
Speed Select Reg.
(SSR)
Miscellaneous Reg.
(MIS)
Edge Select Reg.
(ESR)
Not used
Port Mode Reg.0
(PMR0)
Port Mode Reg.1
(PMR1)
Port Mode Reg.2
(PMR2)
Port Mode Reg.3
(PMR3)
Port Mode Reg.4
(PMR4)
Module Standby Reg.1
(MSR1)
Module Standby Reg.2
(MSR2)
Timer Mode Reg.A
(TMA)
Timer Mode Reg.B1
(TMB1)
Timer Mode Reg.B2
(TMB2)
(TRBL/TWBL)
Timer-B
(TRBU/TWBU)
Timer Mode Reg.C1
(TMC1)
Timer Mode Reg.C2
(TMC2)
(TRCL/TWCL)
Timer-C
(TRCU/TWCU)
Timer Mode Reg.D1
(TMD1)
Timer Mode Reg.D2
(TMD2)
(TRDL/TWDL)
Timer-D
(TRDU/TWDU)
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
Not used
Register flag area
Serial Mode Reg.1
Serial Mode Reg.2
Serial Data Reg.Lower
Serial Data Reg.Upper
(SMR1) W
(SMR2) W
(SRL) R/W
(SRU) R/W
Not used
LCD Control Reg.
LCD Mode Reg.
Buzzer Mode Reg.
Not used
Port D0~D3 DCR
Port D4~D7 DCR
Port D8~D11 DCR
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
Port R8 DCR
(LCR)
(LMR)
(BMR)
W
W
W
(DCD0)
(DCD1)
(DCD2)
W
W
W
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
W
W
W
W
W
W
W
W
W
Not used
$012
$013
Timer Read Reg.B Lower
Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL) W
(TWBU) W
$016
$017
Timer Read Reg.C Lower
Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL) W
(TWCU) W
$01A
$01B
Timer Read Reg.D Lower
Timer Read Reg.D Upper
(TRDL)
(TRDU)
R
R
Timer Write Reg.D Lower
Timer Write Reg.D Upper
(TWDL) W
(TWDU) W
same address ($012, $013, $016,
$017, $01A, $01B).
Figure 2 RAM Memory Map (cont)
Rev.6.00, Sep.08.2003, page 29 of 197
*
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018
$019
$01A
$01B
$01C
$01D
$01E
$01F
$020
$021
$022
$023
$024
$025
$026
$027
$028
$029
$02A
$02B
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
$000
RAM-mapped
register area
$03F
$040 Memory register (MR) area
(16 digits)
$04F
$050
LCD data area
(24 digits)
$067
$068
Not used
$08F
$090
Data
(304 digits)
$1BF
$1C0
Not used
$3BF
$3C0
Stack area
(64 digits)
$3FF
Notes:
R : Read
W : Write
R/W: Read/Write
*Two registers are mapped
onto the same address
($012, $013, $016, $017).
Interrupt control bit area
Speed Select Reg.
Miscellaneous Reg.
Edge Select Reg.
(SSR) W
(MIS) W
(ESR) W
Not used
Port Mode Reg.0
Port Mode Reg.1
Port Mode Reg.2
Port Mode Reg.3
Port Mode Reg.4
Module Standby Reg.1
Module Standby Reg.2
Timer Mode Reg.A
Timer Mode Reg.B1
Timer Mode Reg.B2
Timer B
Timer Mode Reg.C1
Timer Mode Reg.C2
Timer C
(PMR0)
(PMR1)
(PMR2)
(PMR3)
(PMR4)
(MSR1)
(MSR2)
(TMA)
(TMB1)
(TMB2)
(TRBL/TWBL)
(TRBU/TWBU)
(TMC1)
(TMC2)
(TRCL/TWCL)
(TRCU/TWCU)
W
W
W
W
W
W
W
W
W
W
R/W
R/W
W
W
R/W
R/W
Not used
Register flag area
Serial Mode Reg.1
Serial Mode Reg.2
Serial Mode Reg.Lower
Serial Mode Reg.Upper
A/D Mode reg.
A/D Data Reg.Lower
A/D Data Reg.Middle
A/D Data Reg.Upper
LCD Control Reg.
LCD Mode Reg.
Buzzer Mode Reg.
Not used
Port D0–D3 DCR
Port D4–D7 DCR
Port D8–D9 DCR
Not used
Port R0 DCR
Port R1 DCR
Port R2 DCR
Port R3 DCR
Port R4 DCR
Port R5 DCR
Port R6 DCR
Port R7 DCR
(SMR1)
(SMR2)
(SRL)
(SRU)
(AMR)
(ADRL)
(ADRM)
(ADRU)
(LCR)
(LMR)
(BMR)
W
W
R/W
R/W
W
R
R
R
W
W
W
(DCD0) W
(DCD1) W
(DCD2) W
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
W
W
W
W
W
W
W
W
Not used
$012
$013
Timer Read Reg.B Lower
Timer Read Reg.B Upper
(TRBL)
(TRBU)
R
R
Timer Write Reg.B Lower
Timer Write Reg.B Upper
(TWBL)
(TWBU)
W
W
$016
$017
Timer Read Reg.C Lower
Timer Read Reg.C Upper
(TRCL)
(TRCU)
R
R
Timer Write Reg.C Lower
Timer Write Reg.C Upper
(TWCL)
(TWCU)
W
W
Figure 2 RAM Memory Map (cont)
Rev.6.00, Sep.08.2003, page 30 of 197
*
HD404889/HD404899/HD404878/HD404868 Series
RAM-mapped register area ($000 to $03F):
• Interrupt control bit area ($000 to $003)
This area consists of bits used for interrupt control. Its configuration is shown in figure 3. Individual
bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD,
TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction
restrictions are shown in figure 4.
• Special register area ($004 to $01F, $024 to $03F)
This area comprises mode registers and data registers for external interrupts, the serial interface, timers,
LCD, A/D converter, etc., and I/O pin data control registers. Its configuration is shown in figures 2 and
5. These registers are of three kinds: write-only (W), read-only (R), and read/write (R/W). The
SEM/SEMD and REM/REMD instructions can be used on the LCD control register (LCR: $02C) and
the third bit of buzzer mode register (BMR3: $02E, 3), but RAM bit manipulation instructions cannot
be used on the other registers.
• Register flag area ($020 to $023)
This area consists of the DTON and WDON flags and interrupt control bits. Its configuration is shown
in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD,
REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and
instruction restrictions are shown in figure 4.
Memory register (MR) area ($040 to $04F):
In this data area, the 16 memory register digits (MR(0) to MR(15)) can also be accessed by the registerregister instructions LAMR and XMRA. The configuration of this area is shown in figure 6.
LCD data area: $050 to $06F (HD404889/HD404899/HD404878 Series)
$050 to $067 (HD404868 Series)
This 32-digit data area stores data to be displayed on an LCD. Data written in this area is automatically
outputed to segments as display data. "1" data indicates "on" and "0" data "off" (see the section of the LCD
circuit for details).
Data area:
$090 to $38F (HD404889/HD404899/HD404878 Series)
$090 to $1BF (HD404868 Series)
For the 464 digits from $090 to $25F, the bank can be switched according to the value of the bank register
(V: $03F) (figure 7). The bank register value must always be set when accessing the area from $090 to
$25F. The data area from $260 to $38F can be addressed without a bank register setting.
Stack area ($3C0 to $3FF):
This is the stack area used to save the contents of the program counter (PC), status flag (ST), and carry flag
(CA) when a subroutine call (CAL or CALL instruction) or interrupt handling is performed. As four digits
are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. The saved
data and saved status information are shown in figure 6. The program counter is restored by the RTN and
Rev.6.00, Sep.08.2003, page 31 of 197
HD404889/HD404899/HD404878/HD404868 Series
RTNI instructions. The status and carry flags are restored by the RTNI instruction, but are not affected by
the RTN instruction. Any part of the area not used for saving can be used as a data area.
Bit 1
RSP
(Stack pointer reset)
Bit 0
IE
(Interrupt enable flag)
IMTB
(Timer B interrupt
mask)
IMAD*3
(A/D converter
interrupt mask)
Bit 2
IFWU*2
(WU0 to WU3
interrupt request flag)
IF1
(INT1 interrupt
request flag)
IFTB
(Timer B interrupt
request flag)
IFAD*3
(A/D converter interrupt
request flag)
IM0
(INT0 interrupt
mask)
IMTA
(Timer A interrupt
mask)
IMTC
(Timer C interrupt
mask)
IF0
(INT0 interrupt
request flag)
IFTA
(Timer A interrupt
request flag)
IFTC
(Timer C interrupt
request flag)
DTON
(DTON flag)
ADSF*3
(A/D start flag)
WDON
(Watchdog on flag)
LSON
(Low speed on flag)
$021
GEF
(Gear enable flag)
Not used
ICEF
(Input capture error
flag)
ICSF
(Input capture status
flag)
$022
IMTD*4
(Timer D interrupt mask)
Not used
Not used
Not used
Not used
RAM address
$000
$001
$002
$003
$020
$023
Bit 3
IMWU*1
(WU0 to WU3
interrupt mask)
IM1
(INT1 interrupt mask)
IMS
(Serial interrupt
mask)
IF
IM
IE
SP
IFTD*4
(Timer D interrupt
request flag)
IFS
(Serial interrupt
request flag)
: Interrupt Request Flag
: Interrupt Mask
: Interrupt Enable Flag
: Stack Pointer
Notes: 1. WU0 to WU2 interrupt mask in the HD404868 Series
2. WU0 to WU2 interrupt request flag in the HD404868 Series
3. Applies to the HD404889, HD404899, and HD404868 Series.
4. Applies to the HD404889, HD404899, and HD404878 Series.
Figure 3 Interrupt Control Bit and Register Flag Area Configuration
Rev.6.00, Sep.08.2003, page 32 of 197
HD404889/HD404899/HD404878/HD404868 Series
Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD
instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not
affected by any other instructions.
The following restrictions apply to individual bits.
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
GEF
Allowed
Allowed
RSP
Not executed
Allowed
Inhibited
Inhibited
Allowed
Not executed
Inhibited
Allowed
Inhibited
Allowed
Allowed
Allowed
Not executed
Inhibited
IE
IM
LSON
IF
ICSF
ICEF
WDON
ADSF*
DTON
Not Used
Not executed in active mode
Used in subactive mode
Not executed
Notes : The WDON bit is reset only by stop mode clearance by means of an MCU reset.
Do not use the REM or REMD instruction on the ADSF bit during A/D conversion.
The DTON bit is always in the reset state in active mode.
If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent
bit, the status flag value will be undetermined.
* Applies to HD404889, HD404899, and HD404868 Series.
Figure 4 Instruction Restrictions
Rev.6.00, Sep.08.2003, page 33 of 197
HD404889/HD404899/HD404878/HD404868 Series
HD404889 Series
RAM address
SSR
MIS
ESR
PMR0
PMR1
PMR2
PMR3
PMR4
MSR1
MSR2
TMA
TMB1
TMB2
TRBL/TWBL
TRBU/TWBU
TMC1
TMC2
TRCL/TWCL
TRCU/TWCU
TMD1
TMD2
TRDL/TWDL
TRDU/TWDU
SMR1
SMR2
SRL
SRU
AMR
ADRL
ADRU
LCR
LMR
BMR
DCD0
DCD1
DCD2
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
V
Bit 3
Bit 2
Bit 1
Bit 0
$000
Interrupt control bit area
$003
System clock frequency
frequency division
System clock selection
$004 32 kHz oscillation stop setting 32 kHzratio
division ratio switching
selection
Interrupt
frame
period
selection
Pull-up
MOS
control
Not
used
$005
Not used
INT1 edge detection selection
$006
Not used
$007
Not used
D1/INT1
D0/INT0
$008
$009
R03/WU3
R02/WU2
R01/WU1
R00/WU0
R13/TOB
R12/BUZZ
R11/EVND
R10/EVNB
$00A
$00B
R20/TOC
R22/SI/SO
R21/SCK
R5/SEG9~12
R4/SEG5~8
R3/SEG1~4
$00C R6/SEG13~16
Not used
Timer B lock on/off
Timer D clock on/off
Timer C clock on/off
$00D
Serial clock on/off
A/D clock on/off
Not used
$00E
$00F TimerA/Timer base
Timer A clock source selection
Reload on/off
Timer B clock source selection
$010
Timer B output mode setting
EVNB edge detection selection
Not used
$011
Timer B register (lower)
$012
Timer B register (upper)
$013
$014
Timer C clock source selection
Reload on/off
Timer C output mode selection
Not used
Not used
$015
Timer C register (lower)
$016
Timer C register (upper)
$017
Timer D clock source selection
$018
Reload on/off
Not used
Input capture selection
EVND edge detection selection
$019
Timer D register (lower)
$01A
$01B
Timer D register (upper)
$01C
Not used
$01F
$020
Register flag area
$023
$024
Serial transfer clock speed selection
Not used
Not used
R22/SI/SO PMOS control SO idle H/L setting
$025
Serial data register (lower)
$026
$027
Serial data register (upper)
Analog channel selection
A/D conversion time
$028
Not used
$029
A/D data register (lower)
$02A
$02B
A/D data register (upper)
Realtime clock mode
Power supply dividing
On-chip power supply switch
Display on/off
$02C
display selection
resistor switch
Input clock selection
Duty selection
$02D
Clock output on/off Buzzer/clock selection
Buzzer/clock source selection
$02E
Not used
$02F
PortD3DCR
PortD2DCR
PortD1DCR
PortD0DCR
$030
PortD7DCR
PortD6DCR
PorD5DCR
PortD4DCR
$031
$032
PortD10DCR
PortD9DCR
PortD8DCR
PortD11DCR
Not used
$033
$034
PortR02DCR
PortR01DCR
PortR00DCR
PortR03DCR
$035
PortR12DCR
PortR11DCR
PortR10DCR
PortR13DCR
$036
PortR23DCR
PortR22DCR
PortR21DCR
PortR20DCR
$037
PortR32DCR
PortR31DCR
PortR30DCR
PortR33DCR
$038
PortR42DCR
PortR41DCR
PortR40DCR
PortR43DCR
$039
PortR53DCR
PortR52DCR
PortR51DCR
PortR50DCR
$03A
PortR63DCR
PortR62DCR
PortR61DCR
PortR60DCR
PortR73DCR
PortR72DCR
PortR71DCR
PortR70DCR
$03B
Not used
$03C
PortR80DCR
PortR81DCR
$03D
Not used
$03E
Not used
$03F
Bank setting
Not used
Figure 5 Special Function Register Area
Rev.6.00, Sep.08.2003, page 34 of 197
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
RAM address
SSR
MIS
ESR
PMR0
PMR1
PMR2
PMR3
PMR4
MSR1
MSR2
TMA
TMB1
TMB2
TRBL/TWBL
TRBU/TWBU
TMC1
TMC2
TRCL/TWCL
TRCU/TWCU
TMD1
TMD2
TRDL/TWDL
TRDU/TWDU
SMR1
SMR2
SRL
SRU
AMR
ADRL
ADRM
ADRU
LCR
LMR
BMR
DCD0
DCD1
DCD2
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
V
Bit 3
Bit 2
Bit 1
Bit 0
$000
Interrupt control bit area
$003
System clock frequency
frequency division
System clock selection
$004 32 kHz oscillation stop setting 32 kHzratio
division ratio switching
selection
Interrupt
frame
period
selection
Pull-up
MOS
control
Not
used
$005
Not used
INT1 edge detection selection
$006
Not used
$007
Not used
D1/INT1
D0/INT0
$008
$009
R03/WU3
R02/WU2
R01/WU1
R00/WU0
R13/TOB
R12/BUZZ
R11/EVND
R10/EVNB
$00A
$00B
R20/TOC
R22/SI/SO
R21/SCK
R5/SEG9~12
R4/SEG5~8
R3/SEG1~4
$00C R6/SEG13~16
Not used
Timer B lock on/off
Timer D clock on/off
Timer C clock on/off
$00D
Serial clock on/off
A/D clock on/off
Not used
$00E
$00F TimerA/Timer base
Timer A clock source selection
Reload on/off
Timer B clock source selection
$010
Timer B output mode setting
EVNB edge detection selection
Not used
$011
Timer B register (lower)
$012
Timer B register (upper)
$013
$014
Timer C clock source selection
Reload on/off
Timer C output mode selection
Not used
Not used
$015
Timer C register (lower)
$016
Timer C register (upper)
$017
Timer D clock source selection
$018
Reload on/off
Not used
Input capture selection
EVND edge detection selection
$019
Timer D register (lower)
$01A
$01B
Timer D register (upper)
$01C
Not used
$01F
$020
Register flag area
$023
$024
Serial transfer clock speed selection
Not used
Not used
R22/SI/SO PMOS control SO idle H/L setting
$025
Serial data register (lower)
$026
$027
Serial data register (upper)
Analog channel selection
A/D conversion time
$028
A/D data register (lower)
Not used
$029
A/D data register (middle)
$02A
$02B
A/D data register (upper)
Realtime clock mode
Power supply dividing
On-chip power supply switch
Display on/off
$02C
display selection
resistor switch
Input clock selection
Duty selection
$02D
Clock output on/off Buzzer/clock selection
Buzzer/clock source selection
$02E
Not used
$02F
PortD3DCR
PortD2DCR
PortD1DCR
PortD0DCR
$030
PortD7DCR
PortD6DCR
PorD5DCR
PortD4DCR
$031
$032
PortD10DCR
PortD9DCR
PortD8DCR
PortD11DCR
Not used
$033
$034
PortR02DCR
PortR01DCR
PortR00DCR
PortR03DCR
$035
PortR12DCR
PortR11DCR
PortR10DCR
PortR13DCR
$036
PortR23DCR
PortR22DCR
PortR21DCR
PortR20DCR
$037
PortR32DCR
PortR31DCR
PortR30DCR
PortR33DCR
$038
PortR42DCR
PortR41DCR
PortR40DCR
PortR43DCR
$039
PortR53DCR
PortR52DCR
PortR51DCR
PortR50DCR
$03A
PortR63DCR
PortR62DCR
PortR61DCR
PortR60DCR
PortR73DCR
PortR72DCR
PortR71DCR
PortR70DCR
$03B
Not used
$03C
PortR80DCR
PortR81DCR
$03D
Not used
$03E
Not used
$03F
Bank setting
Not used
Figure 5 Special Function Register Area (cont)
Rev.6.00, Sep.08.2003, page 35 of 197
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
RAM address
SSR
MIS
ESR
PMR0
PMR1
PMR2
PMR3
PMR4
MSR1
MSR2
TMA
TMB1
TMB2
TRBL/TWBL
TRBU/TWBU
TMC1
TMC2
TRCL/TWCL
TRCU/TWCU
TMD1
TMD2
TRDL/TWDL
TRDU/TWDU
SMR1
SMR2
SRL
SRU
LCR
LMR
BMR
DCD0
DCD1
DCD2
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
Bit 3
Bit 2
Bit 1
Bit 0
$000
Interrupt control bit area
$003
System clock frequency
frequency division
System clock selection
$004 32 kHz oscillation stop setting 32 kHzratio
division ratio switching
selection
Interrupt
frame
period
selection
Pull-up
MOS
control
Not
used
$005
Not used
INT1 edge detection selection
$006
Not used
$007
Not used
D1/INT1
D0/INT0
$008
$009
R03/WU3
R02/WU2
R01/WU1
R00/WU0
R13/TOB
R12/BUZZ
R11/EVND
R10/EVNB
$00A
$00B
R20/TOC
R22/SI/SO
R21/SCK
R5/SEG9~12
R4/SEG5~8
R3/SEG1~4
$00C R6/SEG13~16
Not used
Timer B lock on/off
Timer D clock on/off
Timer C clock on/off
$00D
Serial clock on/off
Not used
$00E
$00F TimerA/Timer base
Timer A clock source selection
Reload on/off
Timer B clock source selection
$010
Timer B output mode setting
EVNB edge detection selection
Not used
$011
Timer B register (lower)
$012
Timer B register (upper)
$013
$014
Timer C clock source selection
Reload on/off
Timer C output mode selection
Not used
Not used
$015
Timer C register (lower)
$016
Timer C register (upper)
$017
Timer D clock source selection
$018
Reload on/off
Not used
Input capture selection
EVND edge detection selection
$019
Timer D register (lower)
$01A
$01B
Timer D register (upper)
$01C
Not used
$01F
$020
Register flag area
$023
$024
Serial transfer clock speed selection
Not used
Not used
R22/SI/SO PMOS control SO idle H/L setting
$025
Serial data register (lower)
$026
$027
Serial data register (upper)
$028
$029
Not used
$02A
$02B
Realtime clock mode
Power supply dividing
On-chip power supply switch
Display on/off
$02C
display selection
resistor switch
Input clock selection
Duty selection
$02D
Clock output on/off Buzzer/clock selection
Buzzer/clock source selection
$02E
Not used
$02F
PortD3DCR
PortD2DCR
PortD1DCR
PortD0DCR
$030
PortD7DCR
PortD6DCR
PorD5DCR
PortD4DCR
$031
$032
PortD10DCR
PortD9DCR
PortD8DCR
PortD11DCR
Not used
$033
$034
PortR02DCR
PortR01DCR
PortR00DCR
PortR03DCR
$035
PortR12DCR
PortR11DCR
PortR10DCR
PortR13DCR
$036
PortR23DCR
PortR22DCR
PortR21DCR
PortR20DCR
$037
PortR32DCR
PortR31DCR
PortR30DCR
PortR33DCR
$038
PortR42DCR
PortR41DCR
PortR40DCR
PortR43DCR
$039
PortR53DCR
PortR52DCR
PortR51DCR
PortR50DCR
$03A
PortR63DCR
PortR62DCR
PortR61DCR
PortR60DCR
PortR73DCR
PortR72DCR
PortR71DCR
PortR70DCR
$03B
Not used
$03C
PortR80DCR
PortR81DCR
$03D
Not used
$03E
Not used
$03F
Not used
Figure 5 Special Function Register Area (cont)
Rev.6.00, Sep.08.2003, page 36 of 197
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
RAM address
SSR
MIS
ESR
PMR0
PMR1
PMR2
PMR3
PMR4
MSR1
MSR2
TMA
TMB1
TMB2
TRBL/TWBL
TRBU/TWBU
TMC1
TMC2
TRCL/TWCL
TRCU/TWCU
SMR1
SMR2
SRL
SRU
AMR
ADRL
ADRM
ADRU
LCR
LMR
BMR
DCD0
DCD1
DCD2
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
Bit 3
Bit 2
Bit 1
Bit 0
$000
Interrupt control bit area
$003
System clock frequency
frequency division
System clock selection
$004 32 kHz oscillation stop setting 32 kHzratio
division ratio switching
selection
Interrupt
frame
period
selection
Pull-up
MOS
control
Not
used
$005
Not used
INT1 edge detection selection
$006
Not used
$007
Not used
D1/INT1
D0/INT0
$008
$009
Not used
R02/WU2
R01/WU1
R00/WU0
R13/TOB
R12/BUZZ
Not used
R10/EVNB
$00A
$00B
R20/TOC
R22/SI/SO
R21/SCK
R5/SEG9~12
R4/SEG5~8
R3/SEG1~4
$00C R6/SEG13~16
Not used
Timer B lock on/off
Timer C clock on/off
$00D
Serial clock on/off
A/D clock on/off
Not used
$00E
$00F TimerA/Timer base
Timer A clock source selection
Reload on/off
Timer B clock source selection
$010
EVNB edge detection selection
Timer B output mode selection
Not used
$011
Timer B register (lower)
$012
Timer B register (upper)
$013
$014
Timer C clock source selection
Reload on/off
Timer C output mode selection
Not used
Not used
$015
Timer C register (lower)
$016
Timer C register (upper)
$017
$018
Not used
Not used
$019
Not used
$01A
$01B
Not used
$01C
Not used
$01F
$020
Register flag area
$023
$024
Serial transfer clock speed selection
Not used
Not used
R22/SI/SO PMOS control SO idle H/L setting
$025
Serial data register (lower)
$026
$027
Serial data register (upper)
Analog channel selection
A/D conversion time
$028
A/D data register (lower)
Not used
$029
A/D data register (middle)
$02A
$02B
A/D data register (upper)
Realtime clock mode
Power supply dividing
On-chip power supply switch
Display on/off
$02C
display selection
resistor switch
Input clock selection
Duty selection
$02D
Clock output on/off Buzzer/clock selection
Buzzer/clock source selection
$02E
Not used
$02F
PortD3DCR
PortD2DCR
PortD1DCR
PortD0DCR
$030
PortD6DCR
PorD5DCR
PortD4DCR
PortD7DCR
$031
$032
PortD8DCR
Not used
PortD9DCR
Not used
$033
$034
PortR01DCR
PortR00DCR
Not used
PortR02DCR
$035
PortR12DCR
PortR11DCR
PortR10DCR
PortR13DCR
$036
PortR23DCR
PortR22DCR
PortR21DCR
PortR20DCR
$037
PortR32DCR
PortR31DCR
PortR30DCR
PortR33DCR
$038
PortR42DCR
PortR41DCR
PortR40DCR
PortR43DCR
$039
PortR53DCR
PortR52DCR
PortR51DCR
PortR50DCR
$03A
PortR63DCR
PortR62DCR
PortR61DCR
PortR60DCR
PortR73DCR
PortR72DCR
PortR71DCR
PortR70DCR
$03B
Not used
$03C
$03D
Not used
$03E
Not used
$03F
Not used
Figure 5 Special Function Register Area (cont)
Rev.6.00, Sep.08.2003, page 37 of 197
HD404889/HD404899/HD404878/HD404868 Series
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
MR (0)
MR (1)
MR (2)
MR (3)
MR (4)
MR (5)
MR (6)
MR (7)
MR (8)
MR (9)
MR (10)
MR (11)
MR (12)
MR (13)
MR (14)
MR (15)
(a) Memory registers
960 Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
1,023 Level
16 $3C0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 $3FF
Bit 3
Bit 2
Bit 1
Bit 0
1020
ST
PC13
PC12
PC11
$3FC
1021
PC10
PC9
PC8
PC7
$3FD
1022
CA
PC6
PC5
PC4
$3FE
1023
PC3
PC2
PC1
PC0
$3FF
(b) Stack area
PC13 to PC0
ST
CA
: Program counter
: Status flag
: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Bank register (V: $03F)
Bit
3
2
1
0
Read/Write
—
—
—
R/W
Initial value on reset
—
—
—
0
Bit name
Not Used Not Used Not Used
V0
V0
0
1
Bank area selection
Bank 0 is selected
Bank 1 is selected
Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected.
Applies to HD404889 and HD404899 Series.
Figure 7 Bank Register (V)
Rev.6.00, Sep.08.2003, page 38 of 197
HD404889/HD404899/HD404878/HD404868 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. they are shown in figure 8 and described
below.
3
Accumulator
0
(A)
Initial value: Undefined, R/W
3
B register
0
(B)
Initial value: Undefined, R/W
1
W register
Initial value: Undefined, R/W
X register
Initial value: Undefined, R/W
Y register
Initial value: Undefined, R/W
3
0
(X)
3
0
(Y)
3
SPX register
0
(SPX)
Initial value: Undefined, R/W
3
SPY register
0
(W)
0
(SPY)
Initial value: Undefined, R/W
Carry flag
Initial value: Undefined, R/W
0
(CA)
Status flag
Initial value: 1, no R/W
0
(ST)
Program counter
Initial value: $0000,
no R/W
13
0
(PC)
9
Stack pointer
Initial value: $3FF, no R/W
5
1
1
1
1
0
(SP)
Figure 8 Registers and Flags
Accumulator (A) and B register (B):
The accumulator and B register are 4-bit registers used to hold the result of an ALU operation, and for data
transfer to or from memory, an I/O area, or another register.
Rev.6.00, Sep.08.2003, page 39 of 197
HD404889/HD404899/HD404878/HD404868 Series
W register (W), X register (X) and Y register (Y):
The W register is a 2-bit register, and the X and Y registers are 4-bit registers, used for RAM register
indirect addressing. The Y register is also used for D port addressing.
SPX register (SPX) and SPY register (SPY):
The SPX and SPY registers are 4-bit registers used as X register and Y register auxiliary registers,
respectively.
Carry flag (CA):
This flag holds ALU overflow when an arithmetic/logic instruction is executed. It is also affected by the
SEC, REC, ROTL, and ROTR instructions. The contents of the carry flag are saved to the stack when
interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not
affected by the RTN instruction).
Status flag (ST):
This flag holds ALU overflow when an arithmetic/logic or compare instruction is executed, and the result
of an ALU non-zero or bit test instruction. It is used as the branch condition for the BR, BRL, CAL, and
CALL instructions. The status flag is a latch-type flag, and does not change until the next arithmetic/logic,
compare, or bit test instruction is executed. After a BR, BRL, CAL, or CALL instruction, the status flag is
set to 1 regardless of whether the instruction is executed or skipped. The contents of the status flag are
saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI
instruction (but are not affected by the RTN instruction).
Program counter (PC):
This is a 14-bit binary counter that holds ROM address information.
Stack pointer (SP):
The stack pointer is a 10-bit register that holds the address of the next save space in the stack area. The
stack pointer is initialized to $3FF by an MCU reset. The stack pointer is decremented by 4 each time data
is saved, and incremented by 4 each time data is restored. The upper 4 bits of the stack pointer are fixed at
1111, so that a maximum of 16 stack levels can be used.
There are two ways in which the stack pointer is initialized to $3FF: by an MCU reset as mentioned above,
or by resetting the RSP bit with the REM or REMD instruction.
Reset
An MCU reset is performed by driving the RESET pin low. At power-on, and when subactive mode,
watch mode, or stop mode is cleared, RESET should be input for at least tRC to provide the oscillation
settling time for the oscillator.In other cases, the MCU is reset by inputting RESET for at least two
instruction cycles.
Table 1 shows the areas initialized by an MCU reset, and their initial values.
Rev.6.00, Sep.08.2003, page 40 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (1) Initial Values after MCU Reset
Item
Abbr.
Initial
value
Contents
Program counter
(PC)
$0000
Program executed from ROM start address
Status flag
(ST)
1
Branching by conditional branch instruction enabled
Stack pointer
(SP)
$3FF
Stack level is 0
Interrupt
(IE)
0
All interrupts disabled
(IF)
0
No interrupt requests
Interrupt requests masked
Interrupt enable flag
flags/ mask Interrupt request flag
I/O
Timers
Interrupt mask
(IM)
1
Port data register
(PDR)
All bits 1 "1" level output possible
Data control registers
(DCD0 to 2) All bits 0 Output buffer off (high impedance)
Data control registers
(DCR0 to 7, All bits 0
DCR80,
DCR81)
Port mode register 0
(PMR0)
--00
See port mode register 0 section
Port mode register 1
(PMR1)
0000
See port mode register 1 section
Port mode register 2
(PMR2)
0000
See port mode register 2 section
Port mode register 3
(PMR3)
0000
See port mode register 3 section
Port mode register 4
(PMR4)
0000
See port mode register 4 section
Edge detection select
register
(ESR)
--00
See edge detection select register section
Timer mode register A
(TMA)
0000
See timer mode register A section
Timer mode register B1
(TMB1)
0000
See timer mode register B1 section
Timer mode register B2
(TMB2)
-000
See timer mode register B2 section
Timer mode register C1
(TMC1)
0000
See timer mode register C1 section
Timer mode register C2
(TMC2)
-0--
See timer mode register C2 section
Timer mode register D1
(TMD1)
0000
See timer mode register D1 section
Timer mode register D2
(TMD2)
-000
See timer mode register D2 section
Prescaler S
(PSS)
$000
Prescaler W
(PSW)
$00
Timer/counter A
(TCA)
$00
Timer/counter B
(TCB)
$00
Timer/counter C
(TCC)
$00
Timer/counter D
(TCD)
$00
Timer write register B
(TWBU,L)
$X0
Timer write register C
(TWCU,L)
$X0
Timer write register D
(TWDU,L)
$X0
Rev.6.00, Sep.08.2003, page 41 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (1) (cont) Initial Values after MCU Reset
Abbr.
Initial
value
Contents
Serial mode register 1
(SMR1)
0000
See serial mode register 1 section
Serial mode register 2
(SMR2)
-0X-
See serial mode register 2 section
Serial data register
(SRU,L)
$XX
Item
Serial
interface
Octal counter
A/D
converter
LCD
Bit
registers
Others
000
A/D mode register
(AMR)
0000
See A/D mode register section
A/D data register
(HD404889 Series)
(ADRU,L)
$7F
See A/D data register section
A/D data register
(HD404899 Series)
(ADRU,M,L) $1FF
See A/D data register section
LCD control register
(LCR)
0000
See LCD control register section
LCD mode register
(LMR)
0000
See LCD duty/clock control register section
Low speed on flag
(LSON)
0
See low-power mode section
Watchdog timer on flag
(WDON)
0
See timer C section
A/D start flag
(ADSF)
0
See A/D converter section
Direct transfer on flag
(DTON)
0
See low-power mode section
Input capture status flag
(ICSF)
0
See timer D section
Input capture error flag
(ICEF)
0
See timer D section
Gear enable flag
(GEF)
0
See system clock gear function
Miscellaneous register
(MIS)
0-00
See low-power mode and input/output sections
System clock select
register
(SSR)
0000
See low-power mode and oscillator circuit sections
Module standby register 1 (MSR1)
-000
See timer section
Module standby register 2 (MSR2)
--00
See serial interface and A/D converter sections
Buzzer mode register
0000
See Buzzer mode register section
(BMR)
Notes: 1. The state of registers and flags other than those listed above after an MCU reset is shown in
table 1 (2).
2. X: Indicates invalid value, - indicates that the bit does not exist.
Table 1 (2) Initial Values after MCU Reset
Item
Abbr.
Carry flag
(CA)
Accumulator
(A)
B register
(B)
W register
(W)
After Stop Mode Clearance by WU0 to
WU3 Input
After Other MCU Reset
Retain value immediately prior to
entering stop mode
Value immediately prior to MCU reset is not
guaranteed. Must be initialized by program.
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
RAM
Rev.6.00, Sep.08.2003, page 42 of 197
HD404889/HD404899/HD404878/HD404868 Series
Interrupts
There are a total of nine interrupt sources, comprising wakeup input (WU0 to WU3), external interrupts
(INT0, INT1), timer/counter (timer A, timer B, timer C, timer D) interrupts, a serial interface interrupt, and
an A/D converter interrupt.
Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for
storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control
interrupts as a whole.
Of the interrupt sources, timers B and D share the same vector address, and the A/D converter and serial
interface also share the same vector address. Software must therefore determine which of the interrupt
sources is requesting an interrupt at the start of interrupt handling.
Interrupt control bits and interrupt handling:
The interrupt control bits are mapped onto RAM addresses $000 to $003 and $022 to $023, and can be
accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by
software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are
initialized to 0, and the interrupt masks (IM) are initialized to 1.
Figure 9 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector
addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of
interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an
interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The
vector address corresponding to the interrupt source is generated by the priority control circuit.
The interrupt handling sequence is shown in figure 10, and the interrupt handling flowchart in figure 11.
When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the
second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry
flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the
vector address and instruction execution is resumed from that address.
In each vector address area, a JMPL instruction should be written that branches to the start address of the
interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be
reset by software.
Table 2
Vector Addresses and Interrupt Priorities
Interrupt Source
Priority
Vector Address
RESET
—
$0000
WU0 to WU3
1
$0002
INT0
2
$0004
INT1
3
$0006
Timer A
4
$0008
Timer B, D
5
$000A
Timer C
6
$000C
Serial interface, A/D converter
7
$000E
Rev.6.00, Sep.08.2003, page 43 of 197
HD404889/HD404899/HD404878/HD404868 Series
$000,0
I/E
Interrupt
request
$000,2
(WU0 to WU3
interrupt)
IFWU
$000,3
IMWU
$001,0
(INT0 interrupt)
Priority
control circuit
Vector address
IF0
$001,1
IM0
$001,2
(INT1 interrupt)
IF1
$001,3
IM1
$002,0
(Timer A interrupt)
IFTA
$002,1
IMTA
(Timer B interrupt)
$002,2
$022,2
IFTB
IFTD
$002,3
$022,3
IMTB
IMTD
(Timer D interrupt)
$003,0
(Timer C interrupt)
IFTC
$003,1
IMTC
(A/D interrupt)
$003,2
$023,2
IFAD
IFS
$003,3
$023,3
IMAD
IMS
Figure 9 Block Diagram of Interrupt Control Circuit
Rev.6.00, Sep.08.2003, page 44 of 197
(Serial interrupt)
HD404889/HD404899/HD404878/HD404868 Series
Table 3
Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit
WU0 to
WU3
INT0
INT1
Timer A
Timer B or
Timer D
Timer C
A/D or
Serial
IE
1
1
1
1
1
1
1
IFWU·IMWU
1
0
0
0
0
0
0
IF0·IM0
*
1
0
0
0
0
0
IF1·IM1
*
*
1
0
0
0
0
IFTA·IMTA
*
*
*
1
0
0
0
IFTB·IMTB+IFTD·IMTD *
*
*
*
1
0
0
IFTC·IMTC
*
*
*
*
*
1
0
IFAD·IMAD+IFS·IMS
*
*
*
*
*
*
1
Note: * Operation is not affected whether the value is 0 or 1.
Instruction cycle
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Save to stack
IE reset
Save to stack
Vector address
generated
Execution of JMPL instruction
at vector address
Execution of
instruction at
start address of
interrupt routine
Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction.
Figure 10 Interrupt Sequence
Rev.6.00, Sep.08.2003, page 45 of 197
HD404889/HD404899/HD404878/HD404868 Series
Power ON
RESET="0"?
No
Yes
Interrupt request?
Yes
No
IE="1"?
Yes
Execute instruction
Accept interrupt
Reset MCU
IE←"0"
Stack←(PC)
Stack←(CA)
Stack←(ST)
PC←(PC)+1
PC←$0002
Yes
WU0~WU3
interrupt?
No
PC←$0004
Yes
INT0
interrupt?
No
PC←$0006
Yes
INT1
interrupt?
No
PC←$0008
Yes
Timer A interrupt?
No
PC←$000A
Yes
Timer B, timer D
interrupt?
No
PC←$000C
Yes
Timer C interrupt?
No
PC←$000E
(A/D, serial interrupt)
Figure 11 Interrupt Handling Flowchart
Rev.6.00, Sep.08.2003, page 46 of 197
HD404889/HD404899/HD404878/HD404868 Series
Interrupt enable flag (IE: $000,0):
The interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4.
The interrupt enable flag is reset by interrupt handling and set by the RTNI instruction.
Table 4
Interrupt Enable Flag (IE: $000,0)
Interrupt Enable Flag(IE)
Interrupt Enabling/Disabling
0
Interrupts disabled
1
Interrupts enabled
Wakeup interrupt request flag (IFWU: $000,2):
The wakeup interrupt request flag (IFWU) is set by the detection of a falling edge in WU0 to WU3 input in
active mode, subactive mode,watch mode, or standby mode. In stop mode, when a falling edge is detected
at the wakeup pin, the MCU waits for the oscillation settling time, then switches to active mode. The
wakeup interrupt request flag (IFWU) is not set in this case.
Wakeup interrupt mask (IMWU: $000,3):
This bit masks an interrupt request by the wakeup interrupt request flag.
Edge detection select register (ESR: $006)
Bit
3
2
1
0
Read/Write


W
W
Initial value on reset


0
0
Bit name


ESR1
ESR0
ESR1
ESR0
0
1
0
1
0
1
INT1edge detect
Not detected
Falling edge detection
Rising edge detection
Both rising and falling edge detection
Figure 12 Edge Detection Select Register (ESR)
Rev.6.00, Sep.08.2003, page 47 of 197
HD404889/HD404899/HD404878/HD404868 Series
External interrupt request flags (IF0, IF1: $001):
IF0 is set by a falling edge in the INT0 input, and IF1 is set by a rising edge, falling edge, or both edges in
the INT1 input (table 5).
Interrupt edge selection is performed by means of the edge detection select register (ESR: $006) (figure
12).
Table 5
External Interrupt Request Flags (IF0, IF1: $001)
External Interrupt Request Flags
(IF0, IF1)
Interrupt Request
0
No external interrupt request
1
External interrupt request generated
External interrupt masks (IM0, IM1: $001):
These bits mask interrupt requests by the external interrupt request flags (table 6).
Table 6
External Interrupt Mask (IM: $001)
External Interrupt Masks
(IM0, IM1)
Interrupt Request
0
External interrupt request enabled
1
External interrupt request masked (held pending)
Timer A interrupt request flag (IFTA: $002,0):
The timer A interrupt request flag is set by timer A overflow output (table 7).
Table 7
Timer A Interrupt Request Flag (IFTA: $002,0)
Timer A Interrupt Request
Flag(IFTA)
Interrupt Request
0
No timer A interrupt request
1
Timer A interrupt request generated
Timer A interrupt mask (IMTA: $002,1):
This bit masks an interrupt request by the timer A interrupt request flag (table 8).
Table 8
Timer A Interrupt Mask (IMTA: $002,1)
Timer A Interrupt Mask (IMTA)
Interrupt Request
0
Timer A interrupt request enabled
1
Timer A interrupt request masked (held pending)
Rev.6.00, Sep.08.2003, page 48 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer B interrupt request flag (IFTB: $002,2):
The timer B interrupt request flag is set by timer B overflow output (table 9).
Table 9
Timer B Interrupt Request Flag (IFTB: $002,2)
Timer B Interrupt Request Flag
(IFTB)
Interrupt Request
0
No timer B interrupt request
1
Timer B interrupt request generated
Timer B interrupt mask (IMTB: $002,3):
This bit masks an interrupt request by the timer B interrupt request flag (table 10).
Table 10
Timer B Interrupt Mask (IMTB: $002,3)
Timer B Interrupt Mask (IMTB)
Interrupt Request
0
Timer B interrupt request enabled
1
Timer B interrupt request masked (held pending)
Timer C interrupt request flag (IFTC: $003,0):
The timer C interrupt request flag is set by timer C overflow output (table 11).
Table 11
Timer C Interrupt Request Flag (IFTC: $003,0)
Timer C Interrupt Request Flag
(IFTC)
Interrupt Request
0
No timer C interrupt request
1
Timer C interrupt request generated (held pending)
Timer C interrupt mask (IMTC: $003,1):
This bit masks an interrupt request by the timer C interrupt request flag (table 12).
Table 12
Timer C Interrupt Mask (IMTC: $003,1)
Timer C Interrupt Mask (IMTC)
Interrupt Request
0
Timer C interrupt request enabled
1
Timer C interrupt request masked (held pending)
Rev.6.00, Sep.08.2003, page 49 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer D interrupt request flag (IFTD: $022,2): (Applies to HD404889, HD404899, and HD404878
Series)
The timer D interrupt request flag is set by timer D overflow output, or by an EVND input edge when used
as an input capture timer (table 13).
Table 13
Timer D Interrupt Request Flag (IFTD: $022,2)
Timer D Interrupt Request Flag
(IFTD)
Interrupt Request
0
No timer D interrupt request
1
Timer D interrupt request generated
Timer D interrupt mask (IMTD: $022,3): (Applies to HD404889, HD404899, and HD404878 Series)
This bit masks an interrupt request by the timer D interrupt request flag (table 14).
Table 14
Timer D Interrupt Mask (IMTD: $022,3)
Timer D Interrupt Mask (IMTD)
Interrupt Request
0
Timer D interrupt request enabled
1
Timer D interrupt request masked (held pending)
Serial interrupt request flag (IFS: $023,2):
The serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted
midway (table 15).
Table 15
Serial Interrupt Request Flag (IFS: $023,2)
Serial Interrupt Request Flag (IFS) Interrupt Request
0
No serial interrupt request
1
Serial interrupt request generated
Serial interrupt mask (IMS: $023,3):
This bit masks an interrupt request by the serial interrupt request flag (table 16).
Table 16
Serial Interrupt Mask (IMS: $023,3)
Serial Interrupt Mask (IMS)
Interrupt Request
0
Serial interrupt request enabled
1
Serial interrupt request masked (held pending)
Rev.6.00, Sep.08.2003, page 50 of 197
HD404889/HD404899/HD404878/HD404868 Series
A/D interrupt request flag (IFAD: $003,2): (Applies to HD404889, HD404899, and HD404868 Series)
The A/D interrupt request flag is set on completion of A/D conversion (table 17).
Table 17
A/D Interrupt Request Flag (IFAD: $003,2)
A/D Interrupt Request Flag (IFAD) Interrupt Request
0
No A/D interrupt request
1
A/D interrupt request generated
A/D interrupt mask (IMAD: $003,3): (Applies to HD404889, HD404899, and HD404868 Series)
This bit masks an interrupt request by the A/D interrupt request flag (table 18).
Table 18
A/D Interrupt Mask (IMAD: $003,3)
Serial Interrupt Mask (IMAD)
Interrupt Request
0
A/D interrupt request enabled
1
A/D interrupt request masked (held pending)
Rev.6.00, Sep.08.2003, page 51 of 197
HD404889/HD404899/HD404878/HD404868 Series
Operating Modes
The five operating modes shown in table 19 can be used for the MCU.
The function of each mode is shown in table 20, and the state transition diagram among each mode in
figure 13.
Table 19
Operating Modes and Clock Status
Mode Name
Active
Status
2
Stop
Watch
Subactive*
SBY
RESET
cancellation, instruction
interrupt
request, WU0
to WU3 input
in stop mode
STOP/SBY
instruction in
subactive
mode (when
direct
transfer is
selected)
STOP
instruction
when
TMA3 = 0
STOP
instruction
when
TMA3 = 1
INT0/timer A
or WU0 to
WU3 interrupt
request in
watch mode
System oscillator
OP
OP
Stopped
Stopped
Stopped
Subsystem oscillator
OP
OP
OP *
OP
OP
RESET
input,
STOP/SBY
instruction
RESET
input,
interrupt
request
RESET
input,
WU0 to WU3
input
RESET
input,
INT0/timer A
or WU0 to
WU3 interrupt
request
RESET
input,
STOP/SBY
instruction
Activation method
Cancellation method
Standby
1
Notes: OP: implies in operation.
1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select
register (SSR: $004)
2. Subactive mode is an optional function; specify it on the fnction option list.
Rev.6.00, Sep.08.2003, page 52 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 20
Operation in Low-Power Dissipation Modes
3
Function
Stop Mode
Watch mode
Standby Mode
Subactive Mode*
CPU
Retained
Retained
Retained
OP
RAM
Retained
Retained
Retained
OP
Timer A
Stopped
OP
OP
OP
Timer B
Stopped
Stopped
OP
OP
Stopped
Stopped
OP
OP
OP
OP
Timer C
4
Timer D *
Serial interface
5
A/D *
Stopped
Stopped
1
1
Stopped *
Stopped *
OP
OP
Stopped
Stopped
OP
Stopped
2
LCD
Stopped
OP *
OP
OP
I/O
Retained
Retained
Retained
OP
Notes: OP: implies in operation.
1. Transmission/Reception is activated if a clock is input in external clock mode. However,
interrupts stop.
2. When a 32 kHz clock source is used.
3. Subactive mode is an optional function specified on the function option list.
4. Applies to HD404889, HD404899, and HD404878 Series.
5. Applies to HD404889, HD404899, and HD404868 Series.
Rev.6.00, Sep.08.2003, page 53 of 197
HD404889/HD404899/HD404878/HD404868 Series
Reset by
RESET pin
input or
watchdog timer
fosc
fx
φCPU
φCLK
φPER
: Active
: Active
: Stop
: fcyc
: fcyc
interrupt
fosc
fx
φCPU
φCLK
φPER
: Stop
: Active
: Stop
: Stop
: Stop
to
WU3
Active mode
SBY
instruction
fosc
fx
φCPU
φCLK
φPER
WU0
Reset
Standby mode
Stop mode
(TMA3=0,SSR3=0,LSON=0)
: Active
: Active
: fcyc
: fcyc
: fcyc
(TMA3=0,SSR3=1,LSON=0)
STOP
instruction
fosc : Stop
fx
: Stop
WU0 to WU3
φCPU : Stop
φCLK : Stop
STOP
φPER : Stop
instruction*5
(TMA3=0)
*4
fosc
fx
φCPU
φCLK
φPER
: Active
: Active
: Stop
: fw
: fcyc
SBY
instruction
interrupt
Subactive mode
(TMA3=1)
fosc
fx
φCPU
φCLK
φPER
: Active
: Active
: fcyc
: fw
: fcyc
fosc
fx
φCPU
φCLK
φPER
*1
: Stop
: Active
: fSUB
: fw
: fSUB
STOP
instruction
*2
Timer A, WU0~WU3
or INT0 interrupt
STOP
instruction
Timer A, WU0 to WU3
or INT0 interrupt
*3
Watch mode
fosc :
fx :
fcyc :
fw
fSUB
φCPU
φCLK
φPER
LSON
DTON
TMA3
:
:
:
:
:
:
:
:
Main oscillator frequency
Sub-oscillator frequency
(for realtime clock)
fOSC/32 or fOSC/4 (selected by
software)
fx/8
fx/8 or fx/4 (selected by software)
System clock
Clock for realtime clock
Peripheral function clock
Low speed on flag
Direct transfer on flag
Timer mode register A bit3
fosc
fx
φCPU
φCLK
φPER
: Stop
: Active
: Stop
: fw
: Stop
(TMA3=1,LSON=0)
fosc
fx
φCPU
φCLK
φPER
: Stop
: Active
: Stop
: fw
: Stop
(TMA3=1,LSON=1)
Transition Condition
DTON
LSON
TMA3
*1
STOP/SBY instruction
1
0
1
*2
STOP/SBY instruction
0
0
1
*3
STOP/SBY instruction
Don't care
1
1
*4
STOP/SBY instruction
0
0
0
*5 Applies to HD404899, HD404878 and HD404868 Series.
Figure 13 MCU Status Transitions
Rev.6.00, Sep.08.2003, page 54 of 197
HD404889/HD404899/HD404878/HD404868 Series
Active mode:
In active mode all functions operate. In this mode, the MCU operates on clocks generated by the OSC1 and
OSC2 oscillator circuits.
Standby mode:
In standby mode the oscillators continue to operate but clocks relating to instruction execution halt. As a
result, CPU operation stops, and registers, RAM, and the D port/R port set for output retain their state
immediately prior to entering standby mode. Interrupts, timers, the serial interface, and other peripheral
functions continue to operate.
Power consumption is lower than in active mode due to the halting of the CPU.
The MCU is switched to standby mode by executing the SBY instruction in active mode. Standby mode is
cleared by RESET input or an interrupt request. When standby mode is cleared by RESET input, an MCU
reset is performed. When standby mode is cleared by an interrupt request, the MCU enters active mode and
executes a instruction following the SBY instruction. After executing the instruction, if the interrupt enable
flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt
request is held pending and normal instruction execution is continued.
MCU operation flowchart is shown in figure 14.
Rev.6.00, Sep.08.2003, page 55 of 197
HD404889/HD404899/HD404878/HD404868 Series
Stop mode
No
RESET=0?
No
RESET=0?
Yes
IFWU • IMWU
=1?
Yes
WU0 to WU3
No
=
Watch mode
Standby mode
No
Yes
?
IF0 • IM0 = 1?
Yes
No
Yes
IF1 • IM1 = 1?
No
Yes*
No
IFTA • IMTA
= 1?
Yes
IFTB • IMTB+
No
IFTD • IMTD = 1?
System clock
oscillator started
Yes*
System reset
IFTC • IMTC
= 1?
No
Yes*
IFAD • IMAD+
IFS • IMS = 1? No
Yes*
System clock
oscillator started
Next Instruction
execution
NOP
No
IF = 1,
IM = 0,
IE = 1?
Yes
Note: * Only when clearing from standby mode
Next Instruction
execution
Interrupts
enabled
Figure 14 MCU Operation Flowchart
Rev.6.00, Sep.08.2003, page 56 of 197
System clock
oscillator started
HD404889/HD404899/HD404878/HD404868 Series
Stop mode:
In stop mode, all MCU function stop except that states prior to entry into stop mode are retained. This
mode thus has the lowest power consumption of all operating mode.
In stop mode, the OSC1 and OSC2 oscillators stop. Bit 3 (SSR3) of the system clock select register (SSR:
$004) (figure 24) can be used to select the active (= 0) or stopped (= 1) state for the X1 and X2 oscillators.
The MCU is switched to stop mode by executing a STOP instruction while bit 3 (TMA3) of timer mode
register A (TMA: $00F) is cleared to 0 in active mode. Stop mode is cleared by RESET or WU0 to WU3
input. When stop mode is cleared by RESET, the RESET signal should be input for at least the oscillation
settling time (tRC) (see "AC Characteristics") shown in figure 15. Then, the MCU is initialized and starts
instruction execution from the start (address 0) of the program.
When the MCU detects a falling edge at WU0 to WU3 in stop mode, it automatically waits for the
oscillation settling time, then switches to active mode. After the transition to active mode, the MCU
resumes program execution from the instruction following the STOP instruction.
If stop mode is cleared by wakeup input, RAM data and registers retain their values prior to entering stop
mode.
Stop mode
Oscillator
Internal clock
RESET
tres
STOP instruction executed
(At least oscillation settling time (tRC))
Figure 15 Timing Chart for Clearing Stop Mode by RESET Input
Note: If stop mode is cleared by wakeup input when an external clock is used as the system clock
(OSC1), the subclock should not be stopped in stop mode.
Watch mode:
In watch mode, the realtime clock function (timer A) and LCD function using the X1 and X2 oscillators
operate, but other functions stop. This mode thus has the second lowest power consumption after stop
mode, and is useful for performing realtime clock display only.
In watch mode, the OSC1 and OSC2 oscillators stop but the X1 and X2 oscillators continue to operate.
The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or
by executing a STOP/SBY instruction in subactive mode.
Watch mode is cleared by RESET input or an INT0,timer A or WU0 to WU3 interrupt request. For RESET
input, refer to the section on stop mode. When watch mode is cleared by an INT0,timer A or WU0 to WU3
Rev.6.00, Sep.08.2003, page 57 of 197
HD404889/HD404899/HD404878/HD404868 Series
interrupt request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if
LSON = 0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt
request generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the
timer A interrupt, and, for the INT0 interrupt or WU0 to WU3 interrupt, Tx (T + tRC < Tx < 2T + tRC) if bit 1
and 0 (MIS1, MIS0) of the miscellaneous register are set to 00, or Tx (tRC < Tx < T + tRC) if MIS1 and MIS0
are set to 01 or 10 (figures 16 and 17). Other operations when the transition is made are the same as when
watch mode is cleared (figure 14).
Subactive mode:
In subactive mode, the OSC1 and OSC2 oscillator circuits stop and the MCU operates on clocks generated
by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but
since the operating clocks are slow, power consumption is the lowest after watch mode.
A CPU instruction processing speed of 244 µs or 122 µs can be selected according to whether bit 2 (SSR2)
of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should
be changed (0→1 or 1→0) only in active mode. If the value is changed in subactive mode, the MCU may
operate incorrectly.
Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch
mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct transfer
on flag (DTON: $020,3).
Subactive mode is a function option, and should be specified in the function option list.
Interrupt frame:
In watch mode and subactive mode, øCLK is supplied to the timer A, WU0 to WU3, and INT0 acceptance
circuits. Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two
values can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005)
(figure 17).
In watch mode and subactive mode, the timing for generation of timer A,INT0 and WU0 to WU3 interrupts
is synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt
strobe timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at
the interrupt strobe timing.
Rev.6.00, Sep.08.2003, page 58 of 197
HD404889/HD404899/HD404878/HD404868 Series
Oscillation
stabilization
period
Active mode
Watch mode
Active mode
Interrupt
strobe
INT0
Interrupt
request generation
T
T
Only in case of
transition to active
mode
tRC
TX
T: Interrupt frame period
tRC : Oscillation stabilization period
Note: If the time from the fall of the INT0 or WU0 to WU3 signal until the interrupt is accepted and
active mode is entered and is designated TX, then TX will be in the following range :
T+tRC≤TX≤2T+tRC (MIS1, MIS0=00)
tRC≤TX≤T+tRC (MIS1, MIS0=01 or 10)
Figure 16 Interrupt Frame
Miscellaneous Register (MIS: $005)
1
0
W
W
W
Reset
0
0
0
Bit name
MIS3
MIS1
MIS0
MIS1
MIS0
Bit
3
Read/Write
2
Buffer control
See section 3,
Input/Output,
and Figure 33
0
1
Notes:
0
1
0
1
Interrupt Frame Oscillation Settling Oscillator Circuit
period T(ms)*1
Time tRC(ms)*1
Condition
0.24414
3.90625
3.90625
0.12207(0.24414)*2 External clock input
7.8125
Ceramic resonator
31.25
Crystal resonator
Not used
1. T and tRC values are for use of a 32.768 kHz crystal oscillator at the X1-X2 pins.
2. This value applies only in case of direct transition operation.
Figure 17 Miscellaneous Register (MIS)
Rev.6.00, Sep.08.2003, page 59 of 197
HD404889/HD404899/HD404878/HD404868 Series
Direct transition from subactive to active mode:
A direct transition can be made from subactive mode to active mode by controlling the direct transfer on
flag (DTON: $020,3) and low speed on flag (LSON: $020,0). The procedure is shown below.
(a) Set LSON = 0 and DTON = 1 in subactive mode.
(b) Execute a STOP or SBY instruction.
(c) After the lapse of the MCU internal processing time and the oscillation settling time, the MCU
automatically switches from subactive mode to active mode (figure 18).
Notes: 1. The DTON flag ($020,3) can be set in only subactive mode. It is always in the reset state in
active mode.
2. The condition for transition time TD from the subactive mode to active mode is as follows:
tRC < TD < T + tRC.
STOP/SBY
instruction execution
MCU internal
processing time
Subactive mode
Oscillation
stabilization time
Active mode
(Set LSON =0, DTON =1)
Interrupt strobe
Direct transition
completion timing
T
tRC
TD
T: Interrupt frame period
tRC: Oscillation settling time
TD: Direct transition time
Figure 18 Direct Transition Timing
MCU operation sequence:
The MCU operates in accordance with the flowchart shown in figure 19. RESET input is asynchronous
input, and the MCU immediately enters the reset state upon RESET input, regardless of its current state.
In the low-power mode operation sequence, if a STOP/SBY instruction is executed while the IE flag is
cleared and the interrupt flag is set, releasing the relevant interrupt mask, the STOP/SBY instruction is
canceled (regarded as NOP) and the next instruction is executed. Therefore, when executing a STOP/SBY
instruction, all interrupt flags must be cleared, or interrupts masked, beforehand.
Rev.6.00, Sep.08.2003, page 60 of 197
HD404889/HD404899/HD404878/HD404868 Series
STOP/SBY
instruction
IF=1
IM=0
No
Yes
Stop Mode
Standby/watch mode
No
Interrupt handling
routine
IE=0
Yes
No
IF=1
IM=0
WU0~WU3
No
=
Yes
Yes
Clearing Standby
watch mode
Clearing Stop
mode
Hardware NOP
Execution
NOP
PC ←(PC)+1
PC ←(PC)+2
Hardware NOP
Execution
PC ←(PC)+1
Instruction
Execution
MCU
Operation Cycle
Note: See figure 14, MCU Operation Flowchart, for IF and IM operation.
Figure 19 MCU Operating Sequence (Low-Power Mode Operation)
Rev.6.00, Sep.08.2003, page 61 of 197
Instruction
Execution
HD404889/HD404899/HD404878/HD404868 Series
Usage notes:
In watch mode and subactive mode, an interrupt will not be detected correctly if the INT0 or WU0 to WU3
high or low-level period is shorter than the interrupt frame period.
The MCU’s edge sensing method is shown in figure 20. The MCU samples the INT0 and WU0 to WU3
signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a
falling edge has been generated.
Interrupt detection errors occur since this sampling is performed at the interrupt frame period. If the highlevel period of the INT0 or WU0 to WU3 signal is within an interrupt frame, as shown in figure 21 (a), the
signal will be low at point A and point B, with the result that the falling edge will not be recognized.
Similarly, If the low-level period of the INT0 or WU0 to WU3 signal is within an interrupt frame, as shown
in figure 21 (b), the signal will be high at point A and point B, with the result that the falling edge will not
be recognized.
In watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the INT0
and WU0 to WU3 signals is at least as long as the interrupt frame period.
INT0
or
WU0
to WU3
Sampling
High
Low
Low
Figure 20 Edge Sensing Method
(a) High-level mode
INT0
WU0
(b) Low-level mode
or
to WU3
Interrupt frame
INT0
WU0
Point A: Low
Point B: Low
or
to WU3
Interrupt frame
Figure 21 Sampling Examples
Rev.6.00, Sep.08.2003, page 62 of 197
Point A: High
Point B: High
HD404889/HD404899/HD404878/HD404868 Series
Internal Oscillator Circuit
Figure 22 shows the clock pulse generator circuit. As shown in table 21, a ceramic oscillator or crystal
oscillator can be connected to OSC1 and OSC2, and a 32.768 kHz crystal oscillator can be connected to X1
and X2. External clock operation is possible for the system oscillator. Set bit 1 (SSR1) of the system clock
select register (SSR: $004) according to the frequency of the oscillator connected to OSC1 and OSC2
(figure 24).
Note: If the setting of bit 1 in the system clock select register does not match the frequency of the system
oscillator, the subsystem using 32.768 kHz oscillation will not operate correctly.
LSON
OSC2
CPU
System
oscillator
• RAM
• Registers, flags
• I/O
System
clock
selection
circuit
OSC1
• ROM
φCPU
fOSC 1/4 or 1/32 fcyc Timing
tcyc generation
division
circuit*
circuit
Peripheral
functions
Interrupts
φPER
X2
Sub
system
clock
oscillator
fx
1/8 or 1/4 fSUB Timing
division tsubcyc generator
circuit*
circuit
TMA3 bit
X1
1/8
division
circuit
fW
twcyc
Timing
generation
circuit
Time
base
clock
selection
circuit
φCLK
Timer A
interrupts
Notes: The division ratio can be selected by setting bit 0 or bit 2 in the system clock select register
(SSR:$004).
Figure 22 Clock Pulse Generator Circuit
Rev.6.00, Sep.08.2003, page 63 of 197
HD404889/HD404899/HD404878/HD404868 Series
System Clock Gear Function
The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be
selected by software for the instruction execution time. Efficient power consumption can be achieved by
operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at
the other times. Figure 23 shows the system clock conversion method.
System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the
division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to
distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction.
When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is
entered. In this case a transition is made to standby mode for the duration of the gear conversion, but after
the synchronization time has elapsed, a transition is made automatically to active mode. As soon as the
transition is made to active mode, the gear enable flag is reset.
The same procedure is used for conversion from division-by-32 to division-by-4.
Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may
result if an interrupt is generated during gear conversion.
Division-by-32 setting (SSR0 = 1)
Set gear enable flag
Execute SBY instruction
Synchronization time
Execute next instruction
Division-by-4 setting (SSR0 = 0)
Set gear enable flag
Execute SBY instruction
Synchronization time
Execute next instruction
Figure 23 System Clock Division Ratio Conversion Flowchart
Rev.6.00, Sep.08.2003, page 64 of 197
HD404889/HD404899/HD404878/HD404868 Series
System clock select register (SSR: $004)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
SSR3*
SSR2
SSR1
SSR0
Bit name
System clock division ratio switch
0
Division-by-4 (fcyc - fOSC/4)
1
Division-by-32 (fcyc - fOSC/32)
System clock division ratio switch
0
fosc=0.4−1.0MHz
1
fosc=1.6−4.5MHz
Subsystem clock division ratio switch
0
fSUB=fx/8
1
fSUB=fx/4
Subsystem clock stop setting
0
Subsystem clock operates in stop mode
1
Subsystem clock stops in stop mode
Note: * If the subsystem clock is not used, this bit must be set to 1 following power-on and reset.
If it is set to 0 (the initial value), malfunctioning may occur in the stop mode.
Figure 24 System Clock Select Register
Rev.6.00, Sep.08.2003, page 65 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 21
Oscillator Circuit Examples
Circuit Structure
External clock
operation
Circuit Constants
External
oscillator
OSC1
Open
Ceramic oscillator
(OSC1, OSC2)
OSC2
Ceramic oscillator: CSA4.00MG (Murata)
C1
OSC1
Ceramic
oscillator
Rf
GND
Crystal oscillator
(OSC1, OSC2)
Rf=1MΩ±20%
C1=C2=30pF±20%
OSC2
C2
Rf=1MΩ±20%
C1=C2=10–22pF±20%
C1
OSC1
Crystal
oscillator
Rf
GND
Crystal: Equivalent circuit at left
C0=7pFmax.
RS=100Ωmax.
OSC2
C2
L
OSC1
CS
RS
OSC2
C0
Crystal oscillator
(X1, X2)
Crystal: 32.768 kHz: MX38T (Nihon Denpa
Kogyo)
C1=C2=20pF±20%
RS=14kΩ
C0=1.5pF
C1
X1
Crystal
oscillator
X2
GND
C2
L
CS
X1
RS
X2
C0
Notes: 1. With a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray
capacitance in the interconnecting circuit, and other factors. Suitable constants should be
determined in consultation with the resonator manufacturer.
2. Make the connections between the OSC1 and OSC2 pins (X1 and X2 pins) and external
components as short as possible, and ensure that no other lines cross these lines (see layout
example in figure 25).
3. When 32.768 kHz crystal oscillation is not used, fix the X1 pin at VCC and leave the X2 pin open.
Rev.6.00, Sep.08.2003, page 66 of 197
HD404889/HD404899/HD404878/HD404868 Series
RESET
X1
X2
GND
OSC2
OSC1
TEST
GND
Figure 25 Typical Layouts of Crystal and Ceramic Oscillator
Rev.6.00, Sep.08.2003, page 67 of 197
HD404889/HD404899/HD404878/HD404868 Series
Input/Output
The MCU has 46 input/output pins (D0 to D11, R0 to R7, R80, and R81) in the HD404889, HD404899, and
HD404878 Series, or 41 input/output pins (D0 to D9, R00, R01, R02, and R1 to R7) in the HD404868 Series.
The features of these pins are described below.
• The four pins D0 to D3 are source large-current (10 mA max.) I/O pins.
• The eight pins D4 to D11 are sink large-current (15 mA max.) I/O pins.
• I/O pins comprise pins (D0, D1, R0, R1, R20 to R22, R3 to R7, R80, and R81) that also have a peripheral
function (timer, serial interface, etc.). With these pins, the peripheral function setting has priority over
the D port or R port pin setting. When a peripheral function setting has been made for a pin, the pin
function and input/output mode will be switched automatically in accordance with that setting.
• Selection of input or output for I/O pins, or selection of the port or peripheral function for pins
multiplexed as peripheral function pins, is performed by the program.
• All output of the peripheral function pins are CMOS outputs. The SO pin and R22 port pin can be
designated as NMOS open-drain output by the program.
• A reset clears peripheral function selection. And since the data control registers (DCD, DCR) are also
reset, input/output pins go to the high-impedance state.
Each I/O pin has a built-in pull-up MOS that can be turned on and off individually by the program.
Figure 26 shows the I/O buffer configuration, and table 22 shows I/O pin circuit configuration control by
the program.
Table 23 shows the circuit configuration of each I/O pin.
VCC
Pull-up control signal
pull-up
MOS
MIS3
VCC
PMOS
Buffer control signal
Output data
NMOS
Input data
Input control signal
Figure 26 I/O Pin Circuit Configuration
Rev.6.00, Sep.08.2003, page 68 of 197
DCD, DCR
PDR
HD404889/HD404899/HD404878/HD404868 Series
Table 22
Programmable I/O Circuits
MIS3 (bit 3 of MIS)
0
DCD,DCR
0
PDR
CMOS buffer
1
0
1
PMOS
—
NMOS
—
—
pull-up MOS
Note:
1
0
1
0
1
0
1
0
1
—
—
ON
—
—
ON
—
—
—
—
ON
—
ON
—
—
—
—
—
ON
—
ON
— : OFF
Table 23 Circuit Configurations of I/O Pins
Type
I/O pins
Circuit Configuration
VCC
Pins
Pull-up control signal
VCC
MIS3
Buffer control signal
DCD, DCR
Output data
PDR
Input data
Input control signal
VCC
VCC
D0-D11
R00-R03
R10-R13
R20, R21, R23
R30-R33
R40-R43
R50-R53
R60-R63
R70-R73
R80-R81
R22
Pull-up control signal
Buffer control signal
Output data
MIS3
DCR
SMR22
PDR
Input data
Input control signal
Perip- I/O pins
heral
function
pins
VCC
VCC
Pull-up control signal
Output data
Input data
SCK
MIS3
PDR
I/O control signal
SCK
SCK
Note: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state
and peripheral function selections are cleared.
Rev.6.00, Sep.08.2003, page 69 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 23
Circuit Configurations of I/O Pins (cont)
Type
Circuit Configuration
Perip- Output
heral
pins
function
pins
VCC
VCC
Pins
SO
Pull-up control signal
PMOS control signal
Output data
VCC
VCC
Pull-up control signal
Output data
Input
pins
Input data
MIS3
PDR
SMR22
SO
MIS3
PDR
TOB, TOC,
BUZZ
TOB, TOC, BUZZ
RESET
RESET
VCC
MIS3
PDR
WU0-WU3,
INT0, INT1,
EVNB,
EVND, SI
WU0−WU3 etc.
AN0-AN5*
VCC
MIS3
PDR
A/D input
Input control signal
Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state
and peripheral function selections are cleared.
* Applies to HD404889, HD404899, and HD404868 Series.
Rev.6.00, Sep.08.2003, page 70 of 197
HD404889/HD404899/HD404878/HD404868 Series
D Port
The D port consists of 12 I/O pins (10 I/O pins in the HD404868 Series) that are addressed bit-by-bit.
Ports D0 to D3 are source large-current I/O pins, and ports D4 to D11 (ports D4 to D9 in the HD404868 Series)
are sink large-current I/O pins.
The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD
or TDD instruction.
The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to
$032). The DCD registers are mapped onto memory addresses (figure 27).
Ports D0 and D1 are multiplexed as interrupt input pins INT0 and INT1, respectively. Setting as interrupt
pins is performed by bits 0 and 1 (PMR00, PMR01) of port mode register 0 (PMR0: $008) (figure 28).
Rev.6.00, Sep.08.2003, page 71 of 197
HD404889/HD404899/HD404878/HD404868 Series
Data control registers (DCD0–2 : $030–$032)
(DCR0–8 : $034–$03C)
Register Name
DCD0–DCD2
DCR0–DCR8
Bit
3
2
1
0
Read/Write
W
W
W
W
Reset
0
0
0
0
Bit name
DCD03–DCD23
DCD02–DCD22
DCD01–DCD21
DCD00–DCD20
Read/Write
W
W
W
W
Reset
0
0
0
0
Bit name
DCR03–DCR73
DCR02–DCR72
DCR01–DCR81
DCR00–DCR80
All bits
CMOS buffer control
0
CMOS buffer off (high impedance)
1
CMOS buffer active
Correspondence between each bit of DCD and DCR and ports
Register Name
Bit 3
Bit 2
Bit 1
Bit 0
DCD0
D3
D2
D1
D0
DCD1
D7
D6
D5
D4
DCD2
D11*
D10*
D9
D8
DCR0
R03*
R02
R01
R00
DCR1
R13
R12
R11
R10
DCR2
R23
R22
R21
R20
DCR3
R33
R32
R31
R30
DCR4
R43
R42
R41
R40
DCR5
R53
R52
R51
R50
DCR6
R63
R62
R61
R60
DCR7
R73
R72
R71
R70
R81*
R80*
DCR8
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 27 Data Control Registers (DCD, DCR)
Rev.6.00, Sep.08.2003, page 72 of 197
HD404889/HD404899/HD404878/HD404868 Series
R Port
The R port consists of 34 I/O pins (31 I/O pins in the HD404868 Series) that are addressed in 4-bit units.
Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and
LRB instructions. Output data is stored in the port data register (PDR) for each pin.
The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR8: $034 to
$03C). The DCR registers are mapped onto memory addresses (figure 27).
Ports R00 to R03 are multiplexed as wakeup input pins WU0 to WU3, respectively. Setting of these pins as
peripheral function pins is performed by port mode register 1 (PMR1: $009) (figure 29).
Ports R10 and R11 are multiplexed as peripheral function pins EVNB and EVND, respectively. Setting of
these pins as peripheral function pins is performed by bits 0 and 1 (PMR20, PMR21) of port mode register
2 (PMR2: $00A) (figure 30).
Ports R12 to R13 and R20 are multiplexed as peripheral function pins BUZZ, TOB, and TOC, respectively.
Setting of these pins as peripheral function pins is performed by bits 2 and 3 (PMR22, PMR23) of port
mode register 2 (PMR2: $00A) and bit 0 (PMR30) of port mode register 3 (PMR3: $00B)(figures 30 and
31).
Ports R21 and R22 are multiplexed as peripheral function pins SCK and SI/SO, respectively. Setting of
these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 to PMR33) of port mode register
3 (PMR3: $00B) (figure 31).
Ports R3 to R6 are multiplexed as peripheral function pins SEG1 to SEG16, respectively. Setting of these
pins as segment pins is performed every 4 pins in 4-bit units by port mode register 4 (PMR4: $00C) (figure
32).
Ports R70 to R73 and R80 to R81 also function as peripheral function pins AN0 to AN5 (HD404889,
HD404899, and HD404868 series only). Peripheral function pin setting of these pins is performed using
bits 1 to 3 (AMR1 to AMR3) of the A/D mode register (AMR :$028). (See Figure 74 in A/D Converter.)
Rev.6.00, Sep.08.2003, page 73 of 197
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 0 (PMR0: $008)
Bit
1
0
Read/Write
W
W
Initial value on reset
0
0
PMR01
PMR00
Bit name
3
Not used
2
Not used
PMR00
D0/INT0 pin mode selection
0
D0
1
INT0
PMR01
D1/INT1 pin mode selection
0
D1
1
INT1
Figure 28 Port Mode Register 0 (PMR0: $008)
Rev.6.00, Sep.08.2003, page 74 of 197
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 1 (PMR1: $009)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
PMR13*
PMR12
PMR11
PMR10
Bit name
PMR10
R00/WU0 pin mode selection
0
R00
1
WU0
PMR11
R01/WU1 pin mode selection
0
R01
1
WU1
PMR12
R02/WU2 pin mode selection
0
R02
1
WU2
PMR13
R03/WU3 pin mode selection
0
R03
1
WU3
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 29 Port Mode Register 1 (PMR1: $009)
Rev.6.00, Sep.08.2003, page 75 of 197
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 2 (PMR2: $00A)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
PMR23
PMR22
PMR21*
PMR20
Bit name
PMR23
PMR20
R10/EVNB pin mode selection
0
R10
1
EVNB
PMR21
R11/EVND pin mode selection
0
R11
1
EVND
PMR22
R12/BUZZ pin mode selection
0
R12
1
BUZZ
R13/TOB pin mode selection
0
R13
1
TOB
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 30 Port Mode Register 2 (PMR2: $00A)
Rev.6.00, Sep.08.2003, page 76 of 197
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 3 (PMR3: $00B)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
PMR33
PMR32
PMR31
PMR30
Bit name
PMR30
R20/TOC pin mode selection
0
R20
1
TOC
PMR31
R21/SCK pin mode selection
0
R21
1
SCK
PMR33
PMR32
R22/SI/SO pin mode selection
0
∗
R22
1
0
SI
1
SO
∗ : Don't care
Figure 31 Port Mode Register 3 (PMR3: $00B)
Rev.6.00, Sep.08.2003, page 77 of 197
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 4 (PMR4: $00C)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
PMR43
PMR42
PMR41
PMR40
Bit name
PMR40 R3/SEG1 to SEG4 pin mode selection
PMR41
PMR42
0
R3
1*
SEG1−4
R4/SEG5 to SEG8 pin mode selection
0
R4
1*
SEG5−8
R5/SEG9 to SEG12 pin mode selection
0
R5
1*
SEG9−12
PMR43
R6/SEG13 to SEG16 pin mode selection
0
R6
1*
SEG13−16
* : When use as a segment output pin, write its port data register (PDR) to '0'
Figure 32 Port Mode Register 4 (PMR4: $00C)
Pull-Up MOS Control
Program-controllable pull-ups MOS are incorporated in all I/O pins.
On/off control of all pull-ups MOS is performed by bit 3 (MIS3) of the miscellaneous register (MIS: $005)
and the port data register (PDR) for each pin, enabling the pull-up MOS to be turned on or off
independently for each pin (table 22, figure 33).
Except for analog input multiplexed pins, the pull-up MOS on/off setting can be made independent of the
setting as an on-chip supporting module pin.
Rev.6.00, Sep.08.2003, page 78 of 197
HD404889/HD404899/HD404878/HD404868 Series
Miscellaneous register (MIS: $005)
Bit
3
2
1
0
Read/Write
W

W
W
Initial value on reset
0

0
0
MIS3

MIS1
MIS0
Bit name
tRC selection
(See figure 17 in the
Operating Modes section)
MIS3
pull-up MOS control
0
All pull-ups MOS off
1
pull-up MOS active
Figure 33 Miscellaneous Register (MIS:$005)
Handling of I/O Pins Not Used by User System
If I/O pins that are not used by the user system are left floating, they may generate noise that can result in
chip malfunctions. Therefore, the pin potential must be fixed.
In this case, pull the pins up to VCC with the built-in pull-up MOS or with an external resistor of
approximately 100 kΩ.
Rev.6.00, Sep.08.2003, page 79 of 197
HD404889/HD404899/HD404878/HD404868 Series
Prescalers
The MCU has the following two prescalers, S and W.
The operating conditions for each prescaler are shown in table 24, and the output supply destinations in
figure 34.
Timer A to D input clocks other than external events, serial transfer clocks other than external clocks, and
the LCD circuit operating clock are selected from the prescaler outputs in accordance with the respective
mode register.
Prescaler Operation
Prescaler S (PSS):
Prescaler S is an 11-bit counter that has the system clock as input. When the MCU is reset, prescaler S is
reset to $000, then divides the system clock. Prescaler S operation is stopped by a reset by the MCU, and
in stop mode and watch mode. It does not stop in any other modes.
Prescaler W (PSW):
Prescaler W is a counter that has a clock divided from the X1 input (32 kHz crystal oscillation) as input.
When the MCU is reset, prescaler W is reset to $00, then divides the input clock. Prescaler W can also be
reset by software.
Table 24
Prescaler Operating Conditions
Prescaler
Input Clock
Reset Conditions
Prescaler S
System clock in active and MCU reset, Stop mode
standby modes, Subsystem clearance
clock in subactive mode
Prescaler W
Clock obtained by divisionby-8 of 32.768 kHz
oscillation by subsystem
clock oscillator
MCU reset, Software*
Stop Conditions
MCU reset, Stop mode,
Watch mode
MCU reset, Stop mode
Note: If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00.
Rev.6.00, Sep.08.2003, page 80 of 197
HD404889/HD404899/HD404878/HD404868 Series
Subsystem
clock
Prescaler W
LCD controller
driver circuit
Timer A
Timer B
Timer C
Timer D
System
clock
Clock
selector
Prescaler S
Figure 34 Prescaler Output Destinations
Rev.6.00, Sep.08.2003, page 81 of 197
Serial
interface
HD404889/HD404899/HD404878/HD404868 Series
Timers
The MCU incorporates four timers, A to D, in the HD404889, HD404899, and HD404878 Series, or three
timers, A to C, in the HD404868 Series.
• Timer A: Free-running timer
• Timer B: Multifunctional timer
• Timer C: Multifunctional timer
• Timer D: Multifunctional timer
Timer A is an 8-bit free-running timer. Timers B, C, and D are 8-bit multifunctional timers; Each one of
their have the functions shown in table 25 and their operating mode can be set by the program.
Table 25
Timer Functions
Functios
Clock source
Timer B
Timer C
Timer D
Prescaler S
Available
Available
Available
Available
Prescaler W
Available
—
—
—
External event
—
Available
—
Available
Available
Available
Available
Available
Timer functions Free-running
Timer outputs
Timer A
Time-base
Available
—
—
—
Event counter
—
Available
—
Available
Reload
—
Available
Available
Available
Watchdog
—
—
Available
—
Input Capture
—
—
—
Available
Toggle
—
Available
Available
—
PWM
—
Available
Available
—
Note: — implies not available
Timer A
Timer A Functions
Timer A has the following functions.
• Free-running timer
• Realtime clock time base
The block diagram of timer A is shown in figure 35.
Rev.6.00, Sep.08.2003, page 82 of 197
HD404889/HD404899/HD404878/HD404868 Series
1/4
fW
1/2
t Wcyc
Timer A interrupt
request flag
(IFTA)
Prescaler W
(PSW)
÷2
÷8
÷ 16
÷ 32
32.768-kHz
oscillator
2 fW
1/2 t Wcyc
Clock
Timer
counter A
(TCA) Overflow
φPER
System
clock
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
Internal data bus
Selector
Selector
Prescaler S (PSS)
3
Timer mode
register A
(TMA)
Data bus
Clock line
Signal line
Figure 35 Timer A Block Diagram
Timer A Operation
Free-running timer operation:
The timer A input clock is selected by timer mode register A (TMA: $00F).
Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input
clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value
becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer
A continues counting up after the count value returns to $00, so that an interrupt is generated regularly
every 256 input clock cycles.
Realtime clock time base operation:
Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1.
As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using
the 32.768 kHz crystal oscillator as the basic clock.
When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00
by the program.
Rev.6.00, Sep.08.2003, page 83 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer A Register
Timer A operation is set by means of the following register.
Timer mode register A (TMA: $00F):
Timer mode register A (TMA: $00F) is a 4-bit write-only register. Timer A operation and input clock
selection are set as shown in figure 36.
Rev.6.00, Sep.08.2003, page 84 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register A (TMA: $00F)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
TMA3
TMA2
TMA1
TMA0
TMA3
TMA2
TMA1
TMA0
Source prescaler
0
PSS
2,048 tcyc
1
PSS
1,024 tcyc
0
PSS
512 tcyc
1
PSS
128 tcyc
0
PSS
32 tcyc
1
PSS
8 tcyc
0
PSS
4 tcyc
1
PSS
2 tcyc
0
PSW
32 twcyc
1
PSW
16 twcyc
0
PSW
8 twcyc
1
PSW
2 twcyc
0
PSW
Bit name
Input clock period Operating mode
0
0
1
0
0
Timer A
mode
1
1
0
0
1
1
0
1
1
Time base
mode
1/2 twcyc
1
Not Used
*
PSW, TCA reset
* : Don't care
Notes:
1. twcyc = 244.14 µs (using 32.768 kHz crystal oscillator)
2. Timer/counter overflow output period (s) = input clock period (s) × 256.
3. If PSW and TCA reset is selected during LCD, the LCD enters the halt state
(power switch off). Therefore, to provide continuous LCD the PSW and TCA
reset interval must be minimized by the program.
4. The division ratio must not be changed while time base mode is being used, as this
will result in an error in the overflow period.
Figure 36 Timer Mode Register A (TMA)
Rev.6.00, Sep.08.2003, page 85 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer B
Timer B Functions: Timer B has the following functions.
• Free-running/reload timer
• External event counter
• Timer output operation (toggle output, PWM output)
The block diagram of timer B is shown in figure 37.
Timer B ineterrupt
request flag
(IFTB)
Timer C clock source
TOB
Timer output
control logic
1
Timer read
register BL
(TRBL)
2
÷2
4
Overflow
EVNB
Timer read
register BU
(TRBU)
÷8
÷32
÷128
Timer counter B
÷512
÷2048
3
Free-runnning/Reload control
φPER
Selector
System
clock
Prescaler S
(PSS)
÷4
(TCBL)
(TCBU)
4
4
Timer write register B
(TWBL)
Timer mode
register B1
(TMB1)
3
Timer mode
register B2
(TMB2)
Data bus
Clock line
Signal line
Figure 37 Timer B Block Diagram
Rev.6.00, Sep.08.2003, page 86 of 197
(TWBU)
Internal data bus
Edge detection
logic
HD404889/HD404899/HD404878/HD404868 Series
Timer B Operation
• Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register B1 (TMB1).
Timer B is initialized to the value written to timer write register B (TWBL, TWBU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer B value
reaches $FF, overflow output is generated. Timer B is then set to the value in timer write register B if
the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts
counting up again.
Overflow output sets the timer B interrupt request flag (IFTB). This flag is reset by the program or by
an MCU reset.
For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial
Values after MCU Reset.
• External event counter operation:
When external event input is designated for the input clock, timer B operates as an external event
counter. When external event input is used, the R10/EVNB pin is designated as the EVNB pin by port
mode register 2 (PMR2).
The external event detected edge for timer B can be designated as a falling edge, rising edge, or both
falling and rising edges in the input signal by means of timer mode register B2 (TMB2). If both falling
and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc.
Timer B counts up by 1 each time a falling edge is detected in the signal input at the EVNB pin. Other
operations are the same as for the free-running/reload timer function.
• Timer output operation:
With timer B, the R13/TOB pin is designated as the TOB pin by the setting of bit 3 of port mode
register 2 (PMR2), and toggle waveform output or PWM waveform output can be selected by timer
mode register B2 (TMB2).
 Toggle output:
With toggle output, the output level is changed upon input of the next clock pulse after the timer B
value reaches $FF. Use of this function in combination with the reload timer allows a clock signal
with any period to be output, enabling it to be used as buzzer output. The output waveform is shown
in figure 38 (1).
 PWM output:
With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 38
(2), according to the contents of timer mode register B1 (TMB1) and timer write register B (TWBL,
TWBU). When the waveform is output with bit 3 (TMB13) of timer mode register B1 cleared to 0,
the write to timer write register B to change the duty is effective from the next frame, whereas if the
waveform is output with the TMB13 bit set to 1 (reload setting), the next frame is output
immediately after the timer write register write.
• Module standby:
With timer B, the supply of the system clock to the timer/counter can be halted by setting bit 0 of
module standby register 1 (MSR1: $00D) to 1. In the module standby state, the mode register value is
retained but the counter value is not guaranteed.
Rev.6.00, Sep.08.2003, page 87 of 197
HD404889/HD404899/HD404878/HD404868 Series
(1) Toggle output waveform (timer B, timer C)
Free-running timer
256 clock periods
256 clock periods
(256 − N)
clock periods
(256 − N)
clock periods
Reload timer
(2) PWM output waveform (timer B, timer C)
T × (N + 1)
TMB13 = 0
(free-running timer)
T × 256
T
TMB13 = 1
(reload timer)
T × (256 − N)
Notes:
T: Counter input clock period
The clock input source and division ratio are controlled by
timer mode register B1 and timer mode register C1.
N: Value in timer write register B or timer write register C
When N = 255 (= $FF), PWM output is always fixed at the timer low level.)
)
(
Figure 38 Timer Output Waveforms
Rev.6.00, Sep.08.2003, page 88 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer B Registers
Timer B operation setting and timer B value reading/writing is controlled by the following registers.
Timer mode register B1 (TMB1: $010)
Timer mode register B2 (TMB2: $011)
Timer write register B (TWBL: $012, TWBU: $013)
Timer read register B (TRBL: $012, TRBU: $013)
Port mode register 2 (PMR2: $00A)
Module standby register 1 (MSR1: $00D)
• Timer mode register B1 (TMB1: $010):
Timer mode register B1 (TMB1) is a 4-bit write-only register, used to select free-running/reload timer
operation and the input clock as shown in figure 39.
Timer mode register B1 (TMB1) is reset to $0 by an MCU reset:
A modification of timer mode register B1 (TMB1) becomes effective after execution of two instructions
following the timer mode register B1 (TMB1) write instruction. The program must provide for timer B
initialization by writing to timer write register B (TWBL, TWBU) to be executed after the postmodification mode has become effective.
Timer mode register B1 (TMB1: $010)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
Bit name
0
0
0
0
TMB13
TMB12
TMB11
TMB10
TMB12
TMB11
TMB10
0
0
1
0
1
1
TMB13
Input clock period and input clock source
0
2,048 tcyc
1
512 tcyc
0
128 tcyc
1
32 tcyc
0
8 tcyc
1
4 tcyc
0
2 tcyc
1
R10/EVNB (external event input)
Free-running/reload timer
0
Free-running timer
1
Reload timer
Figure 39 Timer Mode Register B1 (TMB1)
Rev.6.00, Sep.08.2003, page 89 of 197
HD404889/HD404899/HD404878/HD404868 Series
• Timer mode register B2 (TMB2: $011):
Timer mode register B2 (TMB2) is a 3-bit write-only register, used to select the timer B output mode
and EVNB pin detected edge as shown in figure 40.
Timer mode register B2 (TMB2) is reset to $0 by an MCU reset.
Timer mode register B2 (TMB2: $011)
Bit
3
2
1
0
Read/Write

W
W
W
Initial value on reset

0
0
0
Bit name

TMB22
TMB21
TMB20
TMB21 TMB20
0
1
TMB22
EVNB pin detected edge
0
Not detected
1
Falling edge detection
0
Rising edge detection
1
Both rising and falling edge detection
Timer B output waveform
0
Toggle output
1
PWM output
Figure 40 Timer Mode Register B2 (TMB2)
• Timer write register B (TWBL: $012, TWBU:$013):
Timer write register B (TWBL, TWBU) is a write-only register composed of a lower digit (TWBL) and
an upper digit (TWBU) (figures 41 and 42).
The lower digit (TWBL) of timer write register B is reset to $0 by an MCU reset, while the upper digit
(TWBU) is undetermined.
Timer B can be initialized by writing to timer write register B (TWBL, TWBU). To write the data, first
write the lower digit (TWBL). The lower digit write does not change the timer B value. Next, write the
upper digit (TWBU). Timer B is then initialized to the timer write register B (TWBL, TWBU) value.
When writing to timer write register B (TWBL, TWBU) from the second time onward, if it is not
necessary to change the lower digit (TWBL) reload value, timer B initialization is completed by the
upper digit write alone.
Rev.6.00, Sep.08.2003, page 90 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer write register B (lower) (TWBL: $012)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
TWBL3
TWBL2
TWBL1
TWBL0
Bit name
Figure 41 Timer Write Register B (Lower) (TWBL)
Timer write register B (upper) (TWBU: $013)
Bit
Read/Write
Initial value on reset
Bit name
3
2
1
0
W
W
W
W
Undetermined Undetermined Undetermined Undetermined
TWBU3
TWBU2
TWBU1
TWBU0
Figure 42 Timer Write Register B (Upper) (TWBU)
• Timer read register B (TRBL: $012, TRBU: $013):
Timer read register B (TRBL, TRBU) is a read-only register composed of a lower digit (TRBL) and an
upper digit (TRBU) from which the value of the upper digit of timer B is read directly (figures 43 and
44).
First, read the upper digit (TRBU) of timer read register B. The current value of the timer B upper digit
is read and, at the same time, the value of the timer B lower digit is latched in the lower digit (TRBL) of
timer read register B. The timer B value is obtained when the upper digit (TRBU) of timer read register
B is read by reading the lower digit (TRBL) of timer read register B.
Timer read register B (lower) (TRBL: $012)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
Bit name
Undetermined Undetermined Undetermined Undetermined
TRBL3
TRBL2
TRBL1
TRBL0
Figure 43 Timer Read Register B (Lower) (TRBL)
Rev.6.00, Sep.08.2003, page 91 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer read register B (upper) (TRBU: $013)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
Undetermined Undetermined Undetermined Undetermined
Bit name
TRBU3
TRBU1
TRBU2
TRBU0
Figure 44 Timer Read Register B (Upper) (TRBU)
• Port mode register 2 (PMR2: $00A):
Port mode register 2 (PMR2) is a write-only register used to set the function of the R10/EVNB and
R13/TOB pins as shown in figure 45.
Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
Port mode register 2 (PMR2: $00A)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
PMR23
PMR22
PMR21*
PMR20
Bit name
PMR20
R10/EVNB pin mode selection
0
R10
1
EVNB
PMR21
R11/EVND pin mode selection
0
R11
1
EVND
PMR22
R12/BUZZ pin mode selection
0
R12
1
BUZZ
PMR23
R13/TOB pin mode selection
0
R13
1
TOB
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 45 Port Mode Register 2 (PMR2: $00A)
Rev.6.00, Sep.08.2003, page 92 of 197
HD404889/HD404899/HD404878/HD404868 Series
• Module standby register 1 (MSR1: $00D):
Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer B as shown in figure 46.
Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
Module standby register 1 (MSR1: $00D)
Bit
3
2
1
0
Read/Write

W
W
W
Initial value on reset

0
0
0
Bit name

MSR12
MSR11
MSR10
MSR10
Timer B clock supply control
0
Supplied
1
Stopped
MSR11
Timer C clock supply control
0
Supplied
1
Stopped
MSR12
Timer D clock supply control
0
Supplied
1
Stopped
Figure 46 Module Standby Register 1 (MSR1)
Rev.6.00, Sep.08.2003, page 93 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer C
Timer C Functions:Timer : C has the following functions.
• Free-running/reload timer
• Watchdog timer
• Timer output operation (toggle output, PWM output)
The block diagram of timer C is shown in figure 47.
Rev.6.00, Sep.08.2003, page 94 of 197
HD404889/HD404899/HD404878/HD404868 Series
System reset signal
Watchdog on
flag
(WDON)
Timer output
control logic
φPER
Timer B
overflow
Timer read
register CL
(TRCL)
÷2
Timer read
register CU
(TRCU)
4
÷4
Timer counter C
Selector
÷ 512
÷ 2048
3
Timer mode
register C1
(TMC1)
Timer output
control
Data bus
Free-running/reload control
÷8
Prescaler
(PSS) ÷ 32
÷ 128
(TCCL)
(TCCU)
4
4
Timer write register C
(TWCL)
Timer mode
register C2
(TMC2)
Clock line
Signal line
Figure 47 Timer C Block Diagram
Rev.6.00, Sep.08.2003, page 95 of 197
(TWCU)
Internal data bus
System
clock
Watchdog timer
control logic
Overflow
TOC
Timer C
interrupt request
flag
(IFTC)
HD404889/HD404899/HD404878/HD404868 Series
Timer C Operation
• Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register C1 (TMC1).
Timer C is initialized to the value written to timer write register C (TWCL, TWCU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer C value
reaches $FF, overflow output is generated. Timer C is then set to the value in timer write register C
(TWCL, TWCU) if the reload timer function is selected, or to $00 if the free-running timer function is
selected, and starts counting up again.
Overflow output sets the timer C interrupt request flag (IFTC). This flag is reset by the program or by
an MCU reset.
For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial
Values after MCU Reset.
• 16-bit timer operation:
When timer B overflow flag is selected as the clock source, timer C can be used as a 16-bit timer that
counts the timer B clock source pulses. In this case, since the timer B and timer C free-running/reload
settings are independent, the settings should be made to suit the purpose.
• Watchdog timer operation:
By using the timer C overflow output, timer C can be used as a watchdog timer for detecting program
runaway. The watchdog timer is enabled when the watchdog on flag (WDON) is set to 1, and generates
an MCU reset when timer C overflows. Usually, timer C initialization is performed by the program
before the timer C value reaches $FF, so controlling program runaway.
• Timer output operation:
With timer C, the R20/TOC pin is designated as the TOC pin by setting bit 0 of port mode register 3
(PMR3) to 1, and toggle waveform output or PWM waveform output can be selected by timer mode
register C2 (TMC2).
 Toggle output
The operation is similar to that for timer B toggle output.
 PWM output
The operation is similar to that for timer B PWM output.
• Module standby:
The operation is similar to that for timer B module standby.
Rev.6.00, Sep.08.2003, page 96 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer C Registers
Timer C operation setting and timer C value reading/writing is controlled by the following registers.
Timer mode register C1 (TMC1: $014)
Timer mode register C2 (TMC2: $015)
Timer write register C (TWCL: $016, TWCU: $017)
Timer read register C (TRCL: $016, TRCU: $017)
Port mode register 3 (PMR3: $00B)
Module standby register 1 (MSR1: $00D)
• Timer mode register C1 (TMC1: $014):
Timer mode register C1 (TMC1) is a 4-bit write-only register, used to select free-running/reload timer
operation, the input clock, and the prescaler division ratio as shown in figure 48.
Timer mode register C1 (TMC1) is reset to $0 by an MCU reset.
A modification of timer mode register C1 (TMC1) becomes effective after execution of two instructions
following the timer mode register C1 (TMC1) write instruction. The program must provide for timer C
initialization by writing to timer write register C (TWCL, TWCU) to be executed after the postmodification mode has become effective.
Rev.6.00, Sep.08.2003, page 97 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register C1 (TMC1: $014)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
TMC13
TMC12
TMC11
TMC10
TMC12
TMC11
TMC10
Input clock period
0
2,048 tcyc
1
512 tcyc
0
128 tcyc
1
32 tcyc
0
8 tcyc
1
4 tcyc
Bit name
0
0
1
0
1
0
1
TMC13
1
Free-running/reload timer
0
Free-running timer
1
Reload timer
Figure 48 Timer Mode Register C1 (TMC1)
Rev.6.00, Sep.08.2003, page 98 of 197
2 tcyc
Timer B overflow
HD404889/HD404899/HD404878/HD404868 Series
• Timer mode register C2 (TMC2: $015):
Timer mode register C2 (TMC2) is a 1-bit write-only register, used to select the timer C output mode as
shown in figure 49.
Timer mode register C2 (TMC2) is reset to $0 by an MCU reset.
Timer mode register C2 (TMC2: $015)
Bit
3
2
1
0
Read/Write

W


Initial value on reset

0


Bit name

TMC22


TMC22
Timer C output waveform
0
Toggle output
1
PWM output
Figure 49 Timer Mode Register C2 (TMC2)
• Timer write register C (TWCL: $016, TWCU: $017):
Timer write register C (TWCL, TWCU) is a write-only register composed of a lower digit (TWCL) and
an upper digit (TWCU) (figures 50 and 51).
Timer write register C (TWCL, TWCU) operation is similar to that for timer write register B (TWBL,
TWBU).
Timer write register C (lower) (TWCL: $016)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
TWCL3
TWCL2
TWCL1
TWCL0
Bit name
Figure 50 Timer Write Register C (Lower) (TWCL)
Rev.6.00, Sep.08.2003, page 99 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer write register C (upper) (TWCU: $017)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
Bit name
Undetermined Undetermined Undetermined Undetermined
TWCU3
TWCU2
TWCU1
TWCU0
Figure 51 Timer Write Register C (Upper) (TWCU)
• Timer read register C (TRCL: $016, TRCU: $017):
Timer read register C (TRCL, TRCU) is a read-only register composed of a lower digit (TRCL) and an
upper digit (TRCU) from which the value of the upper digit of timer C is read directly (figures 52 and
53).
Timer read register C (TRCL, TRCU) operation is similar to that for timer read register B (TRBL,
TRBU).
Timer read register C (upper) (TRCL: $016)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
Bit name
Undetermined Undetermined Undetermined Undetermined
TRCL3
TRCL2
TRCL1
TRCL0
Figure 52 Timer Read Register C (Lower) (TRCL)
Timer read register C (upper) (TRCU: $017)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
Bit name
Undetermined Undetermined Undetermined Undetermined
TRCU3
TRCU2
TRCU1
Figure 53 Timer Read Register C (Upper) (TRCU)
Rev.6.00, Sep.08.2003, page 100 of 197
TRCU0
HD404889/HD404899/HD404878/HD404868 Series
• Port mode register 3 (PMR3: $00B):
Port mode register 3 (PMR3) is a write-only register used to set the function of the R20/TOC pin as
shown in figure 54.
Port mode register 3 (PMR3) is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
PMR33
PMR32
PMR31
PMR30
Bit name
PMR30
R20/TOC pin mode selection
0
R20
1
TOC
PMR31
R21/SCK pin mode selection
0
R21
1
SCK
PMR33
PMR32
R22/SI/SO pin mode selection
0
∗
R22
1
0
SI
1
SO
∗ : Don't care
Figure 54 Port Mode Register 3 (PMR3)
• Module standby register 1 (MSR1: $00D):
Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer C as shown in figure 46.
Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
Rev.6.00, Sep.08.2003, page 101 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer D (HD404889/HD404899/HD404878 Series)
Timer D functions : Timer D has the following functions.
• Free-running/reload timer
• External event counter
• Input capture timer
Block diagrams of timer D in different operating modes are shown in figures 55-1 and 55-2.
Timer D interrupt
request flag
(IFTD)
Edge detection
logic
Timer read register
DU (TRDU)
φPER
System
clock
4
÷4
÷8
÷ 32
÷ 128
Timer counter D
Selector
÷ 512
Free-running/
reload control
Prescaler S (PSS)
÷2
÷ 2048
(TCDL)
(TCDU)
4
4
Timer write register D
(TWDL)
(TWDU)
3
Timer mode
register D1
(TMD1)
2
Edge detection
control
Data bus
Timer mode
register D2
(TMD2)
Clock line
Signal line
Figure 55-1 Timer D Block Diagram (Reload Timer and Event Counter Modes)
Rev.6.00, Sep.08.2003, page 102 of 197
Internal data bus
Timer read
register DL
(TRDL)
Overflow
EVND
HD404889/HD404899/HD404878/HD404868 Series
Input capture
status flag
(ICSF)
EVND
Edge detection
logic
Input capture
error flag
(ICEF)
Timer D interrupt
request flag
(IFTD)
Read signal
2
φPER
Timer read register D
4
4
÷4
÷8
Timer counter D
Selector
Prescaler S (PSS)
÷2
(TRDU)
÷32
÷128
(TCDL)
÷512
(TCDU)
Input capture
timer control
÷2048
3
3
Time mode
register D1
(TMD1)
Timer mode
register D2
(TMD2)
Data bus
Clock line
Signal line
Figure 55-2 Timer D Block Diagram (Input Capture Timer Mode)
Rev.6.00, Sep.08.2003, page 103 of 197
Internal data bus
(TRDL)
Overflow
System
clock
HD404889/HD404899/HD404878/HD404868 Series
Timer D Operation
• Free-running/reload timer:
Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected
by means of timer mode register D1 (TMD1).
Timer D is initialized to the value written to timer write register D (TWDL, TWDU) by software, and
counts up by 1 each time the input clock is input. When the input clock is input after the timer D value
reaches $FF, overflow output is generated. Timer D is then set to the value in timer write register D
(TWDL, TWDU) if the reload timer function is selected, or to $00 if the free-running timer function is
selected, and starts counting up again.
Overflow output sets the timer D interrupt request flag (IFTD). This flag is reset by the program or by
an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration,
and table 1, Initial Values after MCU Reset.
• External event counter operation:
When external event input is designated for the input clock, timer D operates as an external event
counter. When external event input is used, the R11/EVND pin is designated as the EVND pin by port
mode register 2 (PMR2).
The external event detected edge for timer D can be designated as a falling edge, rising edge, or both
falling and rising edges in the input signal by means of timer mode register D2 (TMD2). If both falling
and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc.
Timer D counts up by 1 each time the edge selected by timer mode register D2 (TMD2) is detected.
Other operations are the same as for the free-running/reload timer function.
• Input capture timer operation:
The input capture timer function is used to measure the time between trigger input edges input at the
EVND pin.
The trigger input edge can be designated as a falling edge, rising edge, or both falling and rising edges
by means of timer mode register D2 (TMD2).
When a trigger input edge is detected at the EVND pin, the current timer D value is stored in timer read
register D (TRDL, TRDU), and the timer D interrupt request flag (IFTD) and input capture status flag
(ICSF) are set. At the same time, timer D is reset to $00 and continues counting up.
If the next trigger input edge is input while the input capture status flag (ICSF) is set, or if timer D
overflows, the input capture error flag (ICEF) is set.
The input capture status flag (ICSF) and input capture error flag (ICEF) are reset to 0 by an MCU reset
or by writing 0 to them.
When timer D is set to operate as an input capture timer, it is reset to $00.
Rev.6.00, Sep.08.2003, page 104 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer D Registers: Timer D operation setting and timer D value reading/writing is controlled by the
following registers.
Timer mode register D1 (TMD1: $018)
Timer mode register D2 (TMD2: $019)
Timer write register D (TWDL: $01A, TWDU: $01B)
Timer read register D (TRDL: $01A, TRDU: $01B)
Port mode register 2 (PMR2: $00A)
Module standby register 1 (MSR1: $00D)
• Timer mode register D1 (TMD1: $018):
Timer mode register D1 (TMD1) is a 4-bit write-only register, used to select free-running/reload timer
operation, the input clock, and the prescaler division ratio as shown in figure 56.
Timer mode register D1 (TMD1) is reset to $0 by an MCU reset.
A modification of timer mode register D1 (TMD1) becomes effective after execution of two
instructions following the timer mode register D1 (TMD1) write instruction. The program must provide
for timer D initialization by writing to timer write register D (TWDL, TWDU) to be executed after the
post-modification mode has become effective.
When timer D is set to operate as an input capture timer, an internal clock should be set as the input
clock.
Rev.6.00, Sep.08.2003, page 105 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register D1 (TMD1: $018)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
Bit name
0
0
0
0
TMD13
TMD12
TMD11
TMD10
TMD12
TMD11
TMD10
0
0
1
0
1
1
TMD13
Input clock period and input clock source
0
2,048 tcyc
1
512 tcyc
0
128 tcyc
1
32 tcyc
0
8 tcyc
1
4 tcyc
0
2 tcyc
1
R11/EVND (external event input)
Free-running/reload timer
0
Free-running timer
1
Reload timer
Figure 56 Timer Mode Register D1 (TMD1)
• Timer mode register D2 (TMD2: $019):
Timer mode register D2 (TMD2) is a 3-bit write-only register, used to select the EVND pin detected
edge and input capture operation as shown in figure 57.
Timer mode register D2 (TMD2) is reset to $0 by an MCU reset.
Rev.6.00, Sep.08.2003, page 106 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer mode register D2 (TMD2: $019)
Bit
3
2
1
0
Read/Write

W
W
W
Initial value on reset

0
0
0
Bit name

TMD22
TMD21
TMD20
TMD21
TMD20
0
1
TMD22
EVND pin detected edge
0
Not detected
1
Falling edge detection
0
Rising edge detection
1
Both rising and falling edge detection
Input capture setting
0
Free-running/reload timer
1
Input capture timer
Figure 57 Timer Mode Register D2 (TMD2)
• Timer write register D (TWDL: $01A, TWDU: $01B):
Timer write register D (TWDL, TWDU) is a write-only register composed of a lower digit (TWDL) and
an upper digit (TWDU) (figures 58 and 59).
Timer write register D (TWDL, TWDU) operation is similar to that for timer write register B (TWBL,
TWBU).
Timer write register D (lower) (TWDL: $01A)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
TWDL3
TWDL2
TWDL1
TWDL0
Bit name
Figure 58 Timer Write Register D (Lower) (TWDL)
Rev.6.00, Sep.08.2003, page 107 of 197
HD404889/HD404899/HD404878/HD404868 Series
Timer write register D (upper) (TWDU: $01B)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
Bit name
Undetermined Undetermined Undetermined Undetermined
TWDU3
TWDU2
TWDU1
TWDU0
Figure 59 Timer Write Register D (Upper) (TWDU)
• Timer read register D (TRDL: $01A, TRDU: $01B):
Timer read register D (TRDL, TRDU) is a read-only register composed of a lower digit (TRDL) and an
upper digit (TRDU) (figures 60 and 61).
Timer read register D (TRDL, TRDU) operation is similar to that for timer read register B (TRBL,
TRBU).
In the input capture timer operating mode, when the timer D value is read after trigger input, it does not
matter whether the lower or upper digit is read first.
Timer read register D (lower) (TRDL: $01A)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
Bit name
Undetermined Undetermined Undetermined Undetermined
TRDL3
TRDL2
TRDL1
TRDL0
Figure 60 Timer Read Register D (Lower) (TRDL)
Timer read register D (upper) (TRDU: $01B)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
Bit name
Undetermined Undetermined Undetermined Undetermined
TRDU3
TRDU2
TRDU1
TRDU0
Figure 61 Timer Read Register D (Upper) (TRDU)
Rev.6.00, Sep.08.2003, page 108 of 197
HD404889/HD404899/HD404878/HD404868 Series
• Port mode register 2 (PMR2: $00A):
Port mode register 2 (PMR2) is a write-only register used to set the R11/EVND pin function as shown in
figure 45.
Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
• Module standby register 1 (MSR1: $00D):
Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the
clock to timer D as shown in figure 46.
Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
Rev.6.00, Sep.08.2003, page 109 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features.
• Multiple transmit clock sources
 External clock
 Internal prescaler output clock
 System clock
• Output level control in idle states
Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows.
• Serial data register (SRL: $026, SRU: $027)
• Serial mode register 1 (SMR1: $024)
• Serial mode register 2 (SMR2: $025)
• Port mode register 3 (PMR3: $00B)
• Octal counter (OC)
• Selector
The block diagram of the serial interface is shown in figure 62.
Rev.6.00, Sep.08.2003, page 110 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial interrupt
request flag
(IFS)
Octal counter
(OC)
Idle control
logic
SCK
I/O control
logic
Serial data
register
(SRL/U)
φPER
1/2
Selector
System
clock
Clock
Internal data bus
SI/SO
Transfer
control
2
Data bus
1/2
Selector
PrescalerS (PSS)
÷2
÷8
÷32
÷128
÷512
÷2048
4
Serial mode
register 1
(SMR1)
Serial mode
register 2
(SMR2)
Clock line
Signal line
Figure 62 Serial Interface Block Diagram
Rev.6.00, Sep.08.2003, page 111 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial Interface Operation
Selecting and changing serial interface operating mode:
The operating modes that can be selected for the serial interface are shown in table 26. The combination of
port mode register 3 (PMR3) values should be selected from this table. When the serial interface operating
mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1
(SMR1).
Note : The serial interface is initialized by writing to serial mode register 1 (SMR1: $024). See serial
mode register 1 for details.
Table 26
Serial Interface Operating Modes
PMR3
Serial interface operating mode
Bit3
Bit2
Bit1
0
*
1
Clock continuous output mode
1
0
1
Receive mode
1
1
1
Transmit mode
*: Don't care
Serial interface pin setting:
The R21/SCK pin and R22/SI/SO pin are set by writing data to port mode register 3 (PMR3). See serial
interface registers for details.
Serial clock source setting:
The serial clock is set by writing data to serial mode register 1 (SMR1). See serial interface registers for
details.
Serial data setting:
Transmit serial data is set by writing data to the serial data register (SRL, SRU).
Receive serial data is obtained by reading the serial data register (SRL, SRU). Serial data is shifted by
means of the serial clock to perform input/output from/to an external device.
The output level of the SO pin is undetermined until the first data is output after a reset by the MCU, or
until high/low control is performed in the idle state.
Transfer control:
Serial interface operation is started by an STS instruction. The octal counter is reset to 000 by the STS
instruction, and is incremented by 1 on each rise of the serial clock. When 8 serial clock pulses have been
input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial
interrupt request flag (IFS) is set, and transfer is terminated.
The serial clock is selected by means of serial mode register 1 (SMR1). See figure 66.
Rev.6.00, Sep.08.2003, page 112 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial interface operating states:
The serial interface has the operating states shown in figure 63 in external clock mode and internal clock
mode.
STS instruction wait state
Serial clock wait state
Transfer state
Clock continuous output state (internal clock mode only)
• STS instruction wait state
Upon MCU reset ((00) and (10) in figure 63), the serial interface enters the STS instruction wait state.
In the STS instruction wait state, the internal state of the serial interface is initialized. Even if the serial
clock is input at this time, the serial interface will not operate. When the STS instruction is executed
((01), (11)), the serial interface enters the serial clock wait state.
• Serial clock wait state
The serial clock wait state is the interval from STS instruction execution until the first serial clock
falling edge. When the serial clock is input in the serial clock wait state ((02), (12)), the octal counter
begins counting, the contents of the serial data register (SRL) begin shifting, and the serial interface
enters the transfer state. However, if clock continuous output mode is selected in internal clock mode,
the serial interface enters the clock continuous output state ((17)) instead of the transfer state.
If a write to serial mode register 1 (SMR1) is performed in the serial clock wait state, the serial interface
enters the STS instruction wait state ((04), (14)).
• Transfer state
The transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising
edge. In the transfer state, if an STS instruction is executed or if eight serial clocks have been input, the
octal counter is cleared to 000, and the serial interface makes a state transition. If an STS instruction is
executed ((05), (15)), the serial interface enters the serial clock wait state. After eight serial clocks have
been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and
enters the STS instruction wait state ((13)) when in internal clock mode.
In internal clock mode, the serial clock stops after output of eight clocks.
If a write to serial mode register 1 (SMR1) is performed in the transfer state ((06), (16)), the serial
interface is initialized and enters the STS instruction wait state.
When the serial interface switches from the transfer state to another state, the octal counter is reset to
000 and the serial interrupt request flag (IFS) is set.
• Clock continuous output state (internal clock mode only)
In the clock continuous output state, no receive or transmit operation is performed, and the serial clock
is only output from the SCK pin. It is therefore effective in internal clock mode.
If the serial clock is input ((17)) when bit 3 (PMR33) of port mode register 3 (PMR3) is cleared to 0 and
the serial interface is in the serial clock wait state, a transition is made to the clock continuous output
state.
If a write to serial mode register 1 (SMR1) is performed in the clock continuous output state ((18)), the
serial interface enters the STS instruction wait state.
Rev.6.00, Sep.08.2003, page 113 of 197
HD404889/HD404899/HD404878/HD404868 Series
STS instruction wait state
MCU reset (00)
(octal counter ="000",
serial clock disabled)
SMR1 write (04)
SMR1 write (06)
STS instruction (01)
(IFS ← "1")
Serial clock (02)
Serial clock wait state
Transfer state
(octal counter ="000")
(octal counter ≠"000")
8 serial clocks (03)
STS instruction (05)
(IFS ← "1")
External clock mode
STS instruction wait state
MCU reset (10)
(octal counter ="000",
serial clock disabled)
SMR1 write (18)
8 serial clocks (13)
Clock continuous output state
SMR1 write (16)
(PMR33 ="0")
(IFS←"1")
SMR1 write (14)
STS instruction (11)
Serial clock (17)
Serial clock (12)
Serial clock wait state
Transfer state
(octal counter ="000")
(octal counter ≠"000")
STS instruction (15)
(IFS←"1")
Internal clock mode
( ) Refer to the text for details on the circled numbers in the figure.
Figure 63 Serial Interface Operating States
Rev.6.00, Sep.08.2003, page 114 of 197
HD404889/HD404899/HD404878/HD404868 Series
Idle high/low control:
When the serial interface is in the STS instruction wait state or the serial clock wait state (i.e. when idle),
the output level of the SO pin can be set arbitrarily by software. Idle high/low control is performed by
writing the output level to bit 1 (SMR21) of serial mode register 2 (SMR2).
An example of idle high/low control is shown in figure 64. Idle high/low control cannot be performed in
the transfer state.
Rev.6.00, Sep.08.2003, page 115 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial clock
wait state
Serial clock
wait state
State
MCU reset
PMR3 write
Transfer state
STS wait state
STS wait state
Port setting
External clock setting
SMR1 write
Dummy write to
cause state transition
Idle H/L setting
SMR2 write
Idle H/L setting
Transmit data write
SRL, SRU write
STS instruction
SCK pin (input)
SO pin
Undefined
Idle
MSB
LSB
Idle
IFS
(Flag reset by transfer
completion processing)
(1) External clock mode
Serial clock
wait state
State
MCU reset
PMR3 write
STS wait state
Transfer state
STS wait state
Port setting
External clock setting
SMR1 write
Idle H/L setting
SMR2 write
Idle H/L setting
Transmit data write
SRL, SRU write
STS instruction
SCK pin (output)
SO pin
Undefined
Idle
LSB
Idle
MSB
IFS
(2) Internal clock mode
(Flag reset by transfer
completion processing)
Figure 64 Examples of Serial Interface Operation Sequence
Rev.6.00, Sep.08.2003, page 116 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial clock error detection (external clock mode):
The serial interface will operate incorrectly in the transfer state if external noise results in unnecessary
pulses being added to the serial clock. Serial clock error detection in such cases is carried out as shown in
figure 65.
If more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth
clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt
request flag (IFS) is set. At the same time, the serial interface exits the transfer state and enters the serial
clock wait state, but returns to the transfer state at the next regular clock pulse falling edge.
Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt
request flag is reset, and a dummy write is performed into serial mode register 1 (SMR1). The serial
interface then returns to the STS wait state, and the serial interrupt request flag (IFS) is set again. It is
therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy
write to serial mode register 1.
Usage notes:
• Initialization after register modification
If a port mode register 3 (PMR3) write is performed in the serial clock wait state or transfer state, a
serial mode register 1 (SMR1) write should be performed again to initialize the serial interface.
• Serial interrupt request flag (IFS:$023, 2) setting
If a serial mode register 1 (SMR1) write or STS instruction is executed during the first low-level
interval of the serial clock in the transfer state, the serial interrupt request flag (IFS) will not be set. To
ensure that the serial interrupt request flag (IFS) is properly set in this case, programming is required to
make sure that the SCK pin is in the 1 state (by executing an input instruction for the R2 port) before
executing a serial mode register 1 (SMR1) write or an STS instruction.
Rev.6.00, Sep.08.2003, page 117 of 197
HD404889/HD404899/HD404878/HD404868 Series
Transfer end
(IFS←"1")
Disable interrupts
IFS←"0"
SMR1 write
Yes
Serial clock
error processing
IFS=1?
No
Normal termination
(1) Serial clock error detection flowchart
Serial clock
wait state
Serial clock
wait state
Transfer state
Transfer state
State
SCK pin
(input)
(Noise)
1
2
3
4
5
6
7
8
Because the serial
interface returns to
the transfer state, a
write to SMR1
resets IFS.
SMR1
write
IFS
Flag set by octal
counter reaching
000
(2) Serial clock error detection sequence
Figure 65 Example of Serial Clock Error Detection
Rev.6.00, Sep.08.2003, page 118 of 197
Flag reset by transfer
end processing
HD404889/HD404899/HD404878/HD404868 Series
Serial Interface Registers
Serial interface operation setting and serial data reading/writing is controlled by the following registers.
Serial mode register 1 (SMR1: $024)
Serial mode register 2 (SMR2: $025)
Serial data register (SRL: $026, SRU: $027)
Port mode register 3 (PMR3: $00B)
Module standby register 2 (MSR2: $00E)
Serial mode register 1 (SMR1: $024):
Serial mode register 1 (SMR1) has the following functions. See figure 66.
• Serial clock selection
• Prescaler division ratio selection
• Serial interface initialization
The serial mode register 1 (SMR1) is a 4-bit write-only register, and is reset to $0 by an MCU reset.
A write to serial mode register 1 (SMR1) halts the supply of the serial clock to the serial data register (SRL,
SRU) and the octal counter, and resets the octal counter to 000. Therefore, if serial mode register 1
(SMR1) is written to during serial interface operation, data transmission/reception will be suspended and
the serial interrupt request flag (IFS) will be set.
A modification of serial mode register 1 (SMR1) becomes effective after execution of two instructions
following the serial mode register 1 (SMR1) write instruction. The program must therefore provide for the
STS instruction to be executed two cycles after the instruction that writes to serial mode register 1 (SMR1).
Rev.6.00, Sep.08.2003, page 119 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial mode register 1 (SMR1: $024)
Bit
3
2
1
0
Read/Write
W
W
W
W
0
0
0
0
Initial value on reset
Bit name
SMR13 SMR12 SMR11 SMR10
SMR13 SMR12 SMR11 SMR10
Output
PSS
(φPER/2048)÷2
4096 tcyc
1
Output
PSS
(φPER/512)÷2
1024 tcyc
0
Output
PSS
(φPER/128)÷2
256 tcyc
1
Output
PSS
(φPER/32)÷2
64 tcyc
0
Output
PSS
(φPER/8)÷2
16 tcyc
1
Output
PSS
(φPER/2)÷2
4 tcyc
φPER
0
0
0
1
1
0
0
1
1
0
1
1
Serial clock
Serial clock
Serial clock
source (PSS division ratio ÷ 2 or 4)
cycle
0
0
1
SCK pin
0
Output
System clock
1
Input
External clock
0
Output
PSS
(φPER/2048)÷4
8192 tcyc
1
Output
PSS
(φPER/512)÷4
2048 tcyc
0
Output
PSS
(φPER/128)÷4
512 tcyc
1
Output
PSS
(φPER/32)÷4
128 tcyc
0
Output
PSS
(φPER/8)÷4
32 tcyc
8 tcyc
1
Output
PSS
(φPER/2)÷4
0
Output
System clock
φPER
1
Input
External clock
tcyc
tcyc
Figure 66 Serial Mode Register 1 (SMR1)
Serial mode register 2 (SMR2: $025):
Serial mode register 2 (SMR2) has the following functions. See figure 67.
• R22/SI/SO pin PMOS control
• Idle high/low control
Serial mode register 2 (SMR2) is a 2-bit write-only register. The register value cannot be modified in the
transfer state.
Bit 2 (SMR22) of serial mode register 2 (SMR2) controls the on/off status of the R22/SI/SO pin PMOS.
The bit 2 (SMR22) only is reset to 0 by an MCU reset.
Bit 1 (SMR21) of serial mode register 2 (SMR2) performs SO pin high/low control in the idle state. The
SO pin changes at the same time as the high/low write.
Rev.6.00, Sep.08.2003, page 120 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial mode register 2 (SMR2: $025)
Bit
3
2
1
0
Read/Write
—
W
W
—
Initial value on reset
—
0
undeternined
—
Bit name
—
SMR22 SMR21
SMR21
SMR22
Idle high/low control
0
SO pin set to low-level output in idle state
1
SO pin set to high-level output in idle state
R22/SI/SO pin output buffer control
0
PMOS active
1
PMOS off (NMOS open-drain output)
Figure 67 Serial Mode Register 2 (SMR2)
Serial data register (SRL: $026, SRU: $027):
The serial data register (SRL, SRU) has the following functions. See figures 68 and 69.
• Transmit data write and shift operations
• Receive data shift and read operations
The data written to the serial data register (SRL, SRU) is output LSB-first from the SO pin in
synchronization with the falling edge of the serial clock.
External data input LSB-first from the SI pin is latched in synchronization with the rising edge of the serial
clock. Figure 70 shows the serial clock and data input/output timing chart.
Writing and reading of the serial data register (SRL, SRU) must be performed only after data
transmission/reception is completed. The data contents are not guaranteed if a read or write is performed
during data transmission or reception.
Rev.6.00, Sep.08.2003, page 121 of 197
HD404889/HD404899/HD404878/HD404868 Series
Serial data register (lower) (SRL: $026)
Bit
Read/Write
3
2
1
0
R/W
R/W
R/W
R/W
Initial value on reset Undetermined Undetermined Undetermined Undetermined
SR3
Bit name
SR2
SR1
SR0
Figure 68 Serial Data Register (SRL)
Serial data register (upper) (SRU: $027)
Bit
Read/Write
3
2
1
0
R/W
R/W
R/W
R/W
Initial value on reset Undetermined Undetermined Undetermined Undetermined
Bit name
SR7
SR6
SR5
SR4
Figure 69 Serial Data Register (SRU)
Serial
clock
1
Serial output
2
3
4
5
6
7
LSB
data
Serial input
data latch
timing
Figure 70 Serial Interface Input/Output Timing Chart
Rev.6.00, Sep.08.2003, page 122 of 197
8
MSB
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 3 (PMR3: $00B):
Port mode register 3 (PMR3) has the following functions. See figure 71.
• R21/SCK pin selection
• R22/SI/SO pin selection
Port mode register 3 (PMR3) is a 4-bit write-only register used to select serial interface pin settings as
shown in figure 71. It is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
Bit name
PMR33 PMR32 PMR31 PMR30
PMR30 R20/TOC pin mode selection
0
R20
1
TOC
PMR31 R21/SCK pin mode selection
0
R21
1
SCK
PMR33 PMR32 R22/SI/SO pin mode selection
0
1
*
R22
0
SI
1
SO
* : Don't care
Figure 71 Port Mode Register 3 (PMR3)
Rev.6.00, Sep.08.2003, page 123 of 197
HD404889/HD404899/HD404878/HD404868 Series
Module standby register 2 (MSR2: $00E):
Module standby register 2 (MSR2) is a write-only register used to designate supply or stopping of the clock
to the serial interface as shown in figure 72.
Module standby register 2 (MSR2) is reset to $0 by an MCU reset.
Module standby register 2 (MSR2: $00E)
Bit
3
2
1
0
Read/Write


W
W
Initial value on reset


0
0
Bit name


MSR21 MSR20
MSR20 Serial clock supply control
0
Supplied
1
Stopped
MSR21 A/D clock supply control
0
Supplied
1
Stopped
Figure 72 Module Standby Register 2 (MSR2)
Rev.6.00, Sep.08.2003, page 124 of 197
HD404889/HD404899/HD404878/HD404868 Series
A/D Converter
HD404889 Series
The MCU has a built-in successive approximation type A/D converter using a resistance ladder method,
capable of digital conversion of six analog inputs with an 8-bit resolution. The A/D converter block
diagram is shown in figure 73.
The A/D converter comprises the following four registers.
• A/D mode register (AMR: $028)
• A/D start flag (ADSF: $020,2)
• A/D data register (ADRL: $02A, ADRU: $02B)
• Module standby register 2 (MSR2: $00E)
Note : Address $029 is a reserved register, and should not be read or written to.
Interrupt flag
(IFAD)
A/D data
register
(ADRU, ADRL)
Encoder
A/D mode
register
(AMR)
Selector
R70/AN0
R71/AN1
R72/AN2
R73/AN3
R80/AN4
R81/AN5
+
COMP
Reference
voltage
–
AVCC
Reference
voltage control
A/D
control
logic
Conversion time control
A/D
start flag
(ADSF)
Operating mode signal (set to 1 in
stop, watch, and subactive modes,
and during module standby)
AVSS
D/A
Figure 73 A/D Converter Block Diagram
Rev.6.00, Sep.08.2003, page 125 of 197
Internal data bus
3
HD404889/HD404899/HD404878/HD404868 Series
A/D mode register (AMR: $028):
The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and
information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the
channel by bits 1, 2, and 3 (figure 74).
A/D start flag (ADSF: $020,2):
A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is
placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 75).
A/D mode register (AMR: $028)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
AMR3
AMR2
AMR1
AMR0
Bit name
AMR0 A/D conversion time
0
65 tcyc
1
125 tcyc
AMR3 AMR2 AMR1 Analog input channel selection
0
0
1
0
1
1
*
No selection
0
AN0
1
AN1
0
AN2
1
AN3
0
AN4
1
AN5
* : Don't care
Figure 74 A/D Mode Register (AMR)
Rev.6.00, Sep.08.2003, page 126 of 197
HD404889/HD404899/HD404878/HD404868 Series
A/D start flag (ADSF: $020,2)
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
DTON
ADSF
WDON
LSON
Bit
Read/Write
Initial value on reset
Bit name
LSON (see low-power mode section)
WDON (see timer section)
A/D start flag (ADSF)
1
A/D conversion starts
0
Indicates end of A/D conversion
DTON (see low-power mode section)
Figure 75 A/D Start Flag (ADSF)
A/D data register (ADRL: $02A, ADRU: $02B):
The A/D data register is a read-only register consisting of a lower and upper 4 bits. This register is not
cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion,
the resulting 8-bit data is stored in this register, and is held until the next conversion operation starts
(figures 76, 77, and 78).
ADRU : $02B
3
2
1
ADRL : $02A
0
3
2
1
0
MSB
LSB
bit7
bit0
Figure 76 A/D Data Register
Rev.6.00, Sep.08.2003, page 127 of 197
Conversion result
HD404889/HD404899/HD404878/HD404868 Series
A/D data register-lower (ADRL: $02A)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
1
1
1
1
ADRL3
ADRL2
ADRL1
ADRL0
Bit name
Figure 77 A/D Data Register-Lower (ADRL)
A/D data register-upper (ADRU: $02B)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
0
1
1
1
ADRU2
ADRU1
ADRU0
Bit name
ADRU3
Figure 78 A/D Data Register-Upper (ADRU)
Module standby register 2 (MSR2: $00E):
Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and
cuts the current (IAD) flowing in the ladder resistor.
Usage notes:
• Use the SEM or SEMD instruction to write to the A/D start flag (ADSF).
• Do not write to the ADSF during A/D conversion.
• Data in the A/D data register is undetermined during A/D conversion.
• As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive
mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to
reduce power consumption.
• When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is
disabled.
Rev.6.00, Sep.08.2003, page 128 of 197
HD404889/HD404899/HD404878/HD404868 Series
A/D Converter
HD404899/HD404868 Series
The MCU has a built-in successive approximation type A/D converter using a resistance ladder method,
capable of digital conversion of six analog inputs (four analog inputs in the HD404868 Series) with a 10-bit
resolution. The A/D converter block diagram is shown in figures 79-1 and 79-2.
The A/D converter comprises the following four registers.
• A/D mode register (AMR: $028)
• A/D start flag (ADSF: $020,2)
• A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B)
• Module standby register 2 (MSR2: $00E)
Interrupt flag
(IFAD)
A/D data
register
(ADRU, ADRM, ADRL)
Encoder
A/D mode
register
(AMR)
Selector
R70/AN0
R71/AN1
R72/AN2
R73/AN3
R80/AN4
R81/AN5
+
COMP
Reference
voltage
–
AVCC
Reference
voltage control
AVSS
D/A
A/D
control
logic
Conversion time control
A/D
start flag
(ADSF)
Operating mode signal (set to 1 in
stop, watch, and subactive modes,
and during module standby)
Figure 79-1 A/D Converter Block Diagram (HD404899 Series)
Rev.6.00, Sep.08.2003, page 129 of 197
Internal data bus
3
HD404889/HD404899/HD404878/HD404868 Series
Interrupt flag
(IFAD)
A/D data
register
(ADRU, ADRM, ADRL)
Encoder
A/D mode
register
(AMR)
Selector
R70/AN0
R71/AN1
R72/AN2
R73/AN3
+
COMP
Reference
voltage
–
VCC
Reference
voltage control
GND
D/A
A/D
control
logic
Conversion time control
A/D
start flag
(ADSF)
Operating mode signal (set to 1 in
stop, watch, and subactive modes,
and during module standby)
Figure 79-2 A/D Converter Block Diagram (HD404868 Series)
Rev.6.00, Sep.08.2003, page 130 of 197
Internal data bus
3
HD404889/HD404899/HD404878/HD404868 Series
A/D mode register (AMR: $028):
The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and
information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the
channel by bits 1, 2, and 3 (figure 80).
A/D start flag (ADSF: $020,2):
A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is
placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 81).
A/D mode register (AMR: $028)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
AMR3
AMR2
AMR1
AMR0
Bit name
AMR0 A/D conversion time
0
65 tcyc
1
125 tcyc
AMR3 AMR2 AMR1 Analog input channel selection
0
0
1
0
1
1
∗
No selection
0
AN0
1
AN1
0
AN2
1
AN3
0
AN4*
1
AN5*
Note: * Applies to HD404899 Series.
Figure 80 A/D Mode Register (AMR)
Rev.6.00, Sep.08.2003, page 131 of 197
HD404889/HD404899/HD404878/HD404868 Series
A/D start flag (ADSF: $020,2)
Bit
Read/Write
Initial value on reset
Bit name
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
DTON
ADSF
WDON
LSON
LSON (see low-power mode section)
WDON (see timer section)
A/D start flag (ADSF)
1
A/D conversion starts
0
Indicates end of A/D conversion
DTON (see low-power mode section)
Figure 81 A/D Start Flag (ADSF)
A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B):
The A/D data register is a read-only register consisting of a middle and upper 4 bits. This register is not
cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion,
the resulting 10-bit data is stored in this register, and is held until the next conversion operation starts
(figures 82, 83, 84, and 85).
ADRU : $02B
3
2
1
ADRM : $02A
0
3
2
1
ADRL : $029
0
3
2
MSB
LSB
bit9
bit0
Conversion result
Figure 82 A/D Data Register
A/D data register-lower (ADRL: $029)
Bit
3
2
1
0
Read/Write
R
R
—
—
Initial value on reset
1
1
—
—
ADRL3
ADRL2
Not used
Not used
Bit name
Figure 83 A/D Data Register-Lower (ADRL)
Rev.6.00, Sep.08.2003, page 132 of 197
HD404889/HD404899/HD404878/HD404868 Series
A/D data register-middle (ADRM: $02A)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
1
1
1
1
ADRM3
ADRM2
ADRM1
ADRM0
Bit name
Figure 84 A/D Data Register-Middle (ADRM)
A/D data register-upper (ADRU: $02B)
Bit
3
2
1
0
Read/Write
R
R
R
R
Initial value on reset
0
1
1
1
ADRU2
ADRU1
ADRU0
Bit name
ADRU3
Figure 85 A/D Data Register-Upper (ADRU)
Module standby register 2 (MSR2: $00E):
Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and
cuts the current (IAD) flowing in the ladder resistor.
Usage notes:
• Use the SEM or SEMD instruction to write to the A/D start flag (ADSF).
• Do not write to the ADSF during A/D conversion.
• Data in the A/D data register is undetermined during A/D conversion.
• As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive
mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to
reduce power consumption.
• When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is
disabled.
Rev.6.00, Sep.08.2003, page 133 of 197
HD404889/HD404899/HD404878/HD404868 Series
LCD Circuit
The MCU incorporates a controller and driver that drive four common signal pins and 32 segment pins (24
segment pins in the HD404868 Series). The controller unit consists of a RAM unit that stores the display
data, a display control register (LCR), and a duty/clock control register (LMR) (figures 86-1 and 86-2).
The LCD circuit allows four different duties and LCD clocks to be controlled by the program, and also
incorporates dual-port RAM, enabling display data to be transferred to the segment signal pins
automatically without program processing. If the 32 kHz oscillator clock is designated as the LCD clock
source, LCD display is also possible in watch mode in which the system clock stops.
Rev.6.00, Sep.08.2003, page 134 of 197
HD404889/HD404899/HD404878/HD404868 Series
VCC
Internal LCD power supply switch
V0
LCD power supply control circuit
V1
V2
V3
LCD display
control register
(LCR)
Common
signal
output
circuit
COM2
COM3
COM4
4
SEG1 to SEG4
2
Pin control
Display
control
32
SEG5 to SEG8
Segment
signal
output
circuit
SEG9 to SEG12
SEG13 to SEG16
2
Clock line
Note:
Dual-port
display RAM
(32 digits)
Clock
Data bus
Signal line
Display data
Duty selection
Selector
SEG17 to SEG32
Port mode
register 4
(PMR4)
LCD input clocks
2
LCD display
mode register
(LMR)
Pin function switching circuit
Figure 86-1 LCD Circuit Block Diagram (HD404889/HD404899/HD404878 Series)
Rev.6.00, Sep.08.2003, page 135 of 197
Internal data bus
COM1
HD404889/HD404899/HD404878/HD404868 Series
VCC
Internal LCD power supply switch
LCD power supply control circuit
V1
V2
V3
LCD display
control register
(LCR)
Common
signal
output
circuit
COM2
COM3
COM4
4
SEG1 to SEG4
2
Pin control
Display
control
24
SEG5 to SEG8
Segment
signal
output
circuit
SEG9 to SEG12
SEG13 to SEG16
2
Clock line
Note:
Dual-port
display RAM
(24 digits)
Clock
Data bus
Signal line
Display data
Duty selection
Selector
SEG17 to SEG24
Port mode
register 4
(PMR4)
LCD input clocks
2
LCD display
mode register
(LMR)
Pin function switching circuit
Figure 86-2 LCD Circuit Block Diagram (HD404868 Series)
Rev.6.00, Sep.08.2003, page 136 of 197
Internal data bus
COM1
HD404889/HD404899/HD404878/HD404868 Series
LCD data area and segment data: $050 to $06F (HD404889/HD404899/HD404878 Series)
$050 to $067 (HD404868 Series)
Figures 87-1 and 87-2 show the LCD RAM area configuration. Each bit of the storage area corresponds to
one of four duties. When data is written to the area corresponding to a particular duty, it is automatically
output to the segment as display data.
$050
$051
$052
$053
$054
$055
$056
$057
$058
$059
$05A
$05B
$05C
$05D
$05E
$05F
bit3
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
bit2
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
bit1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
bit0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
COM4
COM3
COM2
COM1
$060
$061
$062
$063
$064
$065
$066
$067
$068
$069
$06A
$06B
$06C
$06D
$06E
$06F
bit3
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
bit2
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
bit1
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
bit0
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
COM4
COM3
COM2
COM1
Figure 87-1 LCD RAM Area Configuration (Using Dual-Port RAM)
(HD404889/HD404899/HD404878 Series)
$050
$051
$052
$053
$054
$055
$056
$057
$058
$059
$05A
$05B
$05C
$05D
$05E
$05F
bit3
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
bit2
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
bit1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
bit0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
COM4
COM3
COM2
COM1
$060
$061
$062
$063
$064
$065
$066
$067
bit3
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
bit2
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
bit1
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
bit0
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM4
COM3
COM2
COM1
Figure 87-2 LCD RAM Area Configuration (Using Dual-Port RAM) (HD404868 Series)
Rev.6.00, Sep.08.2003, page 137 of 197
HD404889/HD404899/HD404878/HD404868 Series
LCD control register (LCR: $02C):
The LCD control register is a 4-bit write-only register that controls LCD blanking, the on/off state of the
LCD power switch, display in watch mode and subactive mode, and disconnection of the LCD power
supply dividing resistor, as shown in figure 88.
Individual bit in this register can be set and reset by bit manipulation instructions.
• Display on/off control
Off: Segment signals are in the off state, regardless of LCD RAM data.
On: LCD RAM data is output as segment signals.
• Built-in power switch on/off control
Off: The built-in LCD power switch is off.
On: The built-in LCD power switch is on. If V0 and V1 are shorted externally, V1 goes to the VCC
level.
• LCD display in watch mode and subactive mode
Off: In watch mode and subactive mode, all common and segment pins are fixed at GND potential.
The built-in LCD power switch is off.
On: In watch mode and subactive mode, LCD RAM data is output as segment signals.
• LCD power supply dividing resistor switch on/off control
Off: The built-in LCD power supply dividing resistor is disconnected.
On: The built-in LCD power supply dividing resistor is connected.
Rev.6.00, Sep.08.2003, page 138 of 197
HD404889/HD404899/HD404878/HD404868 Series
LCD control register (LCR: $02C)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
Bit name
0
0
0
0
LCR3
LCR2
LCR1
LCR0
LCR0
LCR1
LCR2
LCR3
LCD on/off control
0
Off
1
On
Built-in LCD power switch on/off control
0
Off
1
On
Watch mode/subactive mode LCD display
0
Off
1
On
LCD power supply dividing resistor
0
On
1
Off
Figure 88 LCD Control Register (LCR)
Rev.6.00, Sep.08.2003, page 139 of 197
HD404889/HD404899/HD404878/HD404868 Series
LCD duty/clock control register (LMR: $02D):
The LCD duty/clock control register is a 4-bit write-only register used to set four kinds of display duty ratio
and LCD reference clock (figure 89). Table 27 shows the LCD frame frequencies for each duty setting.
LCD duty/clock control register (LMR: $02D)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
Bit name
0
0
0
0
LMR3
LMR2
LMR1
LMR0
LMR1
LMR0
Duty factor
0
1/4
1
1/3
0
1/2
1
1 (static drive)
0
1
LMR3
0
1
LMR2
LCD circuit clock
0
CL0=32.768kHz × Duty/128
1
CL1=32.768kHz × Duty/256
0
CL2=φPER × Duty/256
1
When TMA3 = 0, CL3 =φPER × Duty/2048
When TMA3 = 1, CL3 = 32.768 kHz × Duty/512
Figure 89 LCD Duty/Clock Control Register (LMR)
Rev.6.00, Sep.08.2003, page 140 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 27
LCD Frame Frequencies for Each Duty Setting
Frame Period
Duty
LMR3 LMR2
fosc=400kHz
fosc=800kHz
fosc=2.0MHz
fosc=4.0MHz
Division Division Division Division Division Division Division Division
by 4
by 32
by 4
by 32
by 4
by 32
by 4
by 32
Static 0
1
0
CL0
256Hz
1
CL1
128Hz
0
CL2
390.6Hz 48.8Hz
1
CL3* 48.8Hz
0
CL0
128Hz
1
CL1
64Hz
0
CL2
195.3Hz 24.4Hz
1
CL3* 24.4Hz
6.1Hz
781.3Hz 97.7Hz
1953Hz 244.1Hz 3906Hz 488.3Hz
97.7Hz
244.1Hz 30.5Hz
12.2Hz
488.3Hz 61.0Hz
64Hz
1/2
0
1
3.1Hz
390.6Hz 48.8Hz
976.6Hz 122.1Hz 1953Hz 244.1Hz
48.8Hz
122.1Hz 15.3Hz
244.1Hz 30.5Hz
6.1Hz
32Hz
1/3
0
1
0
CL0
85.3Hz
1
CL1
42.7Hz
0
CL2
130.1Hz 16.3Hz
1
CL3* 16.3Hz
260.2Hz 32.5Hz
650Hz
81.3Hz
1301Hz 162.6Hz
2.0Hz
32.5Hz
81.3Hz
10.2Hz
162.6Hz 20.3Hz
12.2Hz
195.3Hz 24.4Hz
488.3Hz 61.0Hz
976.6Hz 122.1Hz
1.5Hz
24.4Hz
61.0Hz
122.1Hz 15.3Hz
4.1Hz
21.3Hz
1/4
0
1
0
CL0
64Hz
1
CL1
32Hz
0
CL2
97.7HZ
1
CL3* 12.2Hz
16Hz
Rev.6.00, Sep.08.2003, page 141 of 197
3.1Hz
7.6Hz
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 4 (PMR4: $00C):
Port mode register 4 (PMR4) is a 4-bit write-only register that enables the R3 to R6 port pins to be switched
to SEG1 to SEG16 pin functions in 4-port units (figure 90).
Port mode register 4 (PMR4: $00C)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
Bit name
PMR43 PMR42 PMR41 PMR40
PMR40
PMR41
PMR42
PMR43
Note:
*
R3/SEG1 to SEG4 pin mode selection
0
R3
1*
SEG1Ð4
R4/SEG5 to SEG8 pin mode selection
0
R4
1*
SEG5Ð8
R5/SEG9 to SEG12 pin mode selection
0
R5
1*
SEG9Ð12
R6/SEG13 to SEG16 pin mode selection
0
R6
1*
SEG13Ð16
When use as a segment output pin, write its port data resister (PDR) to "0"
Figure 90 Port Mode Register 4 (PMR4: $00C)
Rev.6.00, Sep.08.2003, page 142 of 197
HD404889/HD404899/HD404878/HD404868 Series
LCD drive voltage (VLCD):
Example of LCD drive power supply wiring are shown in figures 91-1 and 91-2. The LCD drive voltage
(VLCD) should be within the following range.
2.2≤VLCD≤VCC (V)
If the LCD drive voltage is applied from off-chip, connect the V0 pin to VCC and turn the LCD power
switch (LCD control register) off. (HD404889/HD404899/HD404878 Series)
When the power supply voltage is used as the LCD drive voltage, the V0 and V1 pins should be shorted.
(HD404889/HD404899/HD404878 Series)
VCC
V0
V1
V2
V3
GND
VCC
1
4-digit LCD
COM1
SEG1
to
SEG32
32
Static drive (power supply voltage used for VLCD)
VCC
V0
V1
V2
V3
GND
VCC
2
8-digit LCD
COM1
COM2
SEG1
to
SEG32
32
1/2 duty, 1/2 bias drive (power supply voltage used for VLCD)
VCC
VLCD
VCC
V0
V1
V2
V3
GND
COM1
to
COM3
SEG1
to
SEG32
3
10-digit signed LCD
32
1/3 duty, 1/3 bias drive (external power supply used for VLCD)
VCC
VLCD
VCC
V0
V1
V2
V3
GND
COM1
to
COM4
SEG1
to
SEG32
4
16-digit LCD
32
1/4 duty, 1/3 bias drive (external power supply used for VLCD)
Figure 91-1 Examples of LCD Wiring (HD404889/HD404899/HD404878 Series)
Rev.6.00, Sep.08.2003, page 143 of 197
HD404889/HD404899/HD404878/HD404868 Series
VCC
V1
V2
V3
VCC
GND
1
3-digit LCD
COM1
SEG1
to
SEG24
24
Static drive (power supply voltage used for VLCD)
VCC
V1
V2
V3
VCC
GND
2
6-digit LCD
COM1
COM2
SEG1
to
SEG24
24
1/2 duty, 1/2 bias drive (power supply voltage used for VLCD)
VCC
VCC
VLCD
V1
V2
V3
GND
COM1
to
COM3
SEG1
to
SEG24
3
8-digit LCD
24
1/3 duty, 1/3 bias drive (external power supply used for VLCD)
VCC
VCC
VLCD
V1
V2
V3
GND
COM1
to
COM4
SEG1
to
SEG24
4
12-digit LCD
24
1/4 duty, 1/3 bias drive (external power supply used for VLCD)
Figure 91-2 Examples of LCD Wiring (HD404868 Series)
Large LCD panel drive:
If the capacitance of the driven LCD is large, the value of the divided resistance should be reduced by
dividing the resistance in parallel with the built-in divided resistor (see figures 92-1 and 92-2).
As an LCD has a matrix structure, the path of the charge/discharge current flowing to the load capacitance
is complicated. Moreover, the current varies depending on the illumination state, so that it is not possible
to determine the resistance values simply from the LCD load capacitance. The resistance values must
therefore be determined experimentally in accordance with the power consumption requirement of the
equipment, including the LCD. (Adding capacitors C with a value of 0.1 to 0.3 µF is also effective).
A value of 1 kΩ to 10 kΩ is normally set for R.
Rev.6.00, Sep.08.2003, page 144 of 197
HD404889/HD404899/HD404878/HD404868 Series
V0(VCC)
V1
V0(VCC)
V1
R
R
V2
V2
R
R
V3
C
C
V3
C
R
R
GND
GND
Figure 92-1 Large LCD Panel Drive (Using Power Supply Voltage for VLCD)
(HD404889/HD404899/HD404878 Series)
V1
V1
R
R
V2
V2
R
R
V3
C
C
V3
C
R
GND
R
GND
Figure 92-2 Large LCD Panel Drive (Using Power Supply Voltage for VLCD) (HD404868 Series)
Usage Notes
When R30/SEG1 to R60/SEG16 pins are used as segment output pins, write their port data register (PDR) to
“0”.
Rev.6.00, Sep.08.2003, page 145 of 197
HD404889/HD404899/HD404878/HD404868 Series
Buzzer Output Circuit
Buzzer Output Circuit Functions: The buzzer output circuit has the following functions.
• Timer overflow toggle output
• System clock divided clock pulse output
The block diagram of the buzzer output circuit is shown in figure 93.
Buzzer Output Circuit Operation
• Timer overflow toggle output operation
The timer overflow toggle output operation setting is made by bits 1 and 2 of the buzzer mode register
(BMR) and bit 2 of port mode register 2 (PMR2). By clearing bit 2 of the buzzer mode register (BMR)
to 0, selecting timer B or timer C overflow by bit 1, and setting bit 2 of port mode register 2 (PMR2) to
1, a toggle waveform is output from the BUZZ pin with overflow as the trigger.
• System clock divided clock pulse output
The system clock divided clock pulse output operation setting is made by bits 0 to 3 of the buzzer mode
register (BMR) and bit 2 of port mode register 2 (PMR2). Bit 2 of the buzzer mode register (BMR) is
set to 1, the system clock division ratio is selected by bits 0 and 1, and bit 2 of port mode register 2
(PMR2) is set to 1. Clock pulses are output by setting bit 3 of the buzzer mode register (BMR) to 1. If
bit 3 of the buzzer mode register (BMR) is cleared to 0, the BUZZ pin goes low.
The clock pulse width is fixed without regard to the timing set by bit 3 of the buzzer mode register
(BMR), and careful coordination with software is necessary with regard to the number of output pulses.
After a clock pulse modification is made, clock pulses should not be output until 4tcyc after the
modifying instruction.
Only a bit manipulation instruction can be used on bit 3 of the buzzer mode register (BMR).
Buzzer Output Circuit Registers
Buzzer output circuit operation setting is performed by the following registers.
Buzzer mode register (BMR: $02E)
Port mode register 2 (PMR2: $00A)
Buzzer mode register (BMR: $02E):
The buzzer mode register (BMR) is a 4-bit write-only register used to set toggle output by timer overflow
and system clock divided clock pulse output as shown in figure 94.
Bit 3 of the buzzer mode register (BMR) can only accessed by a bit manipulation instruction.
The buzzer mode register (BMR) is reset to $0 by an MCU reset.
Rev.6.00, Sep.08.2003, page 146 of 197
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 2 (PMR2: $00A):
Port mode register 2 (PMR2) is a 4-bit write-only register used to switch the R12/BUZZ pin function as
shown in figure 30.
Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
BUZZ
1/2
(toggle)
1/2
1/3
Selector
φPER
Internal data bus
Selector
Selector
Timer B
overflow
Timer C
overflow
Synchronization
circuit
1/4
Buzzer
mode
register
Data bus
Clock line
Signal line
Figure 93 Buzzer Output Circuit
Rev.6.00, Sep.08.2003, page 147 of 197
HD404889/HD404899/HD404878/HD404868 Series
Buzzer mode register (BMR: $02E)
Bit
3
2
1
0
Read/Write
W
W
W
W
Initial value on reset
0
0
0
0
BMR3
BMR2
BMR1
BMR0
Bit name
BMR2 BMR1 BMR0
0
*
1
*
BUZZ pin output
Division by
2 of timer B overflow
0
Division by
2 of timer C overflow
0
φPER clock
1
φPER/2clock
0
φPER/3clock
1
φPER/4clock
0
1
1
* : Don't care
Clock output control (enabled when BMR2 = 1, bit manipulation instruction)
0
Stopped (low level)
1
Output
Figure 94 Buzzer Mode Register (BMR)
Rev.6.00, Sep.08.2003, page 148 of 197
HD404889/HD404899/HD404878/HD404868 Series
ZTAT
TM
Microcomputer with Built-in Programmable ROM
1. Precautions for use of ZTAT
TM
microcomputer with built-in programmable ROM
TM
(1) Precautions for writing to programmable ROM built in ZTAT
microcomputer
TM
In the ZTAT microcomputer with built-in plastic mold one-time programmable ROM, incomplete
electrical connection between the PROM writer and socket adapter causes writing errors and, makes the
computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points:
(a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with
each other (neither opened nor shorted), before starting the writing process.
(b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no
foreign substance on the contact pin of the socket adapter, which may cause improper electrical
connection.
(c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical
connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it
again.
(d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to
improper electrical connection, carry out the writing process again according to above steps (a), (b), and
(c).
(e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing.
(f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e).
(g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM
writer, socket adapter, etc. for defects.
(h) If any problem is noticed in the written program or in the program after being left at a high temperature,
consult our technical staff.
(2) Precautions when new PROM writer, socket adapter or IC is used
When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing
may become impossible because the noise, overshoot, timing or other electrical characteristics may be
inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points
before starting the writing process.
(a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer,
power source current capacity of VPP, and current consumption at the time of writing to IC are provided
with sufficient margin.
(b) To prevent breakdown of the IC, check that the power source voltage between GND-VCC and GNDVPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter
are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n
connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs,
recheck the power source damping resistance of capacity.
(c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the
socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting
Rev.6.00, Sep.08.2003, page 149 of 197
HD404889/HD404899/HD404878/HD404868 Series
terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power
sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low
inductance.
(d) For stable writing and reading operation, insert the IC into the socket adapter and check the input
waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent
ICs have increased in speed, caution should be exercised against the noise to the power source or
address due to crosstalk from the output data terminal. To avoid these problems, inserting a low
inductance capacitor between the GND and power source or inserting a damping resistance to the
output data terminal is effective.
(e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming
all ICs inserted into the socket adapter.
(f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check
performed to prevent erroneous writing due to improper electrical connection of the power source, etc.,
rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases
due to erroneous writing because of improper connection. Be sure to check the electrical connection
between the PROM writer and socket adapter and IC.
(g) If any abnormality is noticed while checking a written program, consult our technical staff.
2. Programming of Built-in programmable ROM
The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM.
PROM mode is set by driving the RESET, M0, and M1 pins low (or by driving the RESET and M0 pins low
in the HD4074869), and driving the TEST pin to the VPP level.
Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256.
Using a socket adapter for specific use of each product, programming is possible with a general-purpose
PROM writer.
Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the
general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits
to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to
write to a 16kword of built-in PROM writer with a general-purpose PROM, specify 32kbyte address
($0000-$7FFF). An example of PROM memory map is shown in figure 95.
Notes:
1. When programming with a PROM writer, set up each ROM size to the address given in table 30. If it is
programmed erroneously to an address given in table 30 or later, check of writing of PROM may
become impossible. Particularly, caution should be exercised in the case of a plastic package since
reprogramming is impossible with it. Set the data in unused addresses to $FF.
2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the
product may break down due to overcurrent. Be sure to check that they are properly set to the writer
before starting the writing process.
3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product
employs a VPP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will
Rev.6.00, Sep.08.2003, page 150 of 197
HD404889/HD404899/HD404878/HD404868 Series
result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258
specifications.
Table 28
Socket Adapters
Package
Model Name
Manufacturer
FP-80A
Please ask Renesas Technology service section.
TFP-80C
Please ask Renesas Technology service section.
FP-64A
Please ask Renesas Technology service section.
DP-64S
Please ask Renesas Technology service section.
Writing/verification
Programming of the built-in program ROM employs a high speed programming method. With this method,
high speed writing is effected without voltage stress to the device or without damaging the reliability of the
written data.
A basic programming flow chart is shown in figure 96 and a timing chart in figure 97.
For precautions for PROM writing procedure, refer to Section 2, "Characteristics of ZTATTM
Microcomputer's Built-in Programmable ROM and precautions for its Applications."
Table 29
Selection of Mode
Mode
CE
OE
VPP
O0 to O4
Writing
“Low”
“High”
VPP
Data input
Verification
“High”
“Low”
VPP
Data output
Prohibition of programming
“High”
“High”
VPP
High impedance
Table 30
PROM Writer Program Address
ROM size
Address
8k
$0000~$3FFF
12k
$0000~$5FFF
16k
$0000~$7FFF
Rev.6.00, Sep.08.2003, page 151 of 197
HD404889/HD404899/HD404878/HD404868 Series
Programmable Rom (HD4074889, HD4074899, HD4074869)
TM
The HD4074889, HD4074899, and HD4074869 are a ZTAT
can be programmed in PROM mode.
microcomputers with built-in PROM that
PROM Mode Pin Description
HD4074889, HD4074899
Pin No.
MCU Mode
Pin No.
MCU Mode
FP-80A
Pin Name
I/O
Pin Name
PROM Mode
I/O
FP-80A
Pin Name
I/O
Pin Name
I/O
1
AVCC
—
VCC
—
41
R30/SEG1
I/O
A1
I
2
R70/AN0
I/O
VCC
—
42
R31/SEG2
I/O
A2
I
3
R71/AN1
I/O
VCC
—
43
R32/SEG3
I/O
A3
I
4
R72/AN2
I/O
44
R33/SEG4
I/O
A4
I
5
R73/AN3
I/O
45
R40/SEG5
I/O
O0
I/O
6
R80/AN4
I/O
46
R41/SEG6
I/O
O1
I/O
7
R81/AN5
I/O
47
R42/SEG7
I/O
O2
I/O
8
AVSS
—
GND
—
48
R43/SEG8
I/O
O3
I/O
9
TEST
I
VPP
—
49
R50/SEG9
I/O
O4
I/O
10
OSC1
I
VCC
—
50
R51/SEG10
I/O
O4
I/O
11
OSC2
O
51
R52/SEG11
I/O
O3
I/O
12
GND
—
52
R53/SEG12
I/O
O2
I/O
13
X2
O
53
R60/SEG13
I/O
O1
I/O
14
X1
I
GND
—
54
R61/SEG14
I/O
O0
I/O
15
RESET
I
RESET
I
55
R62/SEG15
I/O
16
VCC
—
VCC
—
56
R63/SEG16
I/O
17
D0/INT0
I/O
A0
I
57
SEG17
O
18
D1/INT1
I/O
58
SEG18
O
19
D2
I/O
A5
I
59
SEG19
O
20
D3
I/O
A6
I
60
SEG20
O
21
D4
I/O
A7
I
61
SEG21
O
22
D5
I/O
A8
I
62
SEG22
O
23
D6
I/O
A9
I
63
SEG23
O
24
D7
I/O
A10
I
64
SEG24
O
25
D8
I/O
A11
I
65
SEG25
O
26
D9
I/O
A12
I
66
SEG26
O
27
D10
I/O
A13
I
67
SEG27
O
28
D11
I/O
A14
I
68
SEG28
O
29
R00/WU0
I/O
VCC
—
69
SEG29
O
30
R01/WU1
I/O
70
SEG30
O
31
R02/WU2
I/O
71
SEG31
O
32
R03/WU3
I/O
72
SEG32
O
33
R10/EVNB
I/O
73
COM1
O
34
R11/EVND
I/O
M0
I
74
COM2
O
35
R12/BUZZ
I/O
M1
I
75
COM3
O
36
R13/TOB
I/O
CE
I
76
COM4
O
37
R20/TOC
I/O
77
V3
—
38
R21/SCK
I/O
OE
I
78
V2
—
39
R22/SI/SO
I/O
XM0
O
79
V1
—
VCC
—
40
R23
I/O
XM1
O
80
V0
—
VCC
—
GND
Rev.6.00, Sep.08.2003, page 152 of 197
—
PROM Mode
HD404889/HD404899/HD404878/HD404868 Series
HD4074869
Pin No.
FP-64A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MCU Mode
DP-64S
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Pin Name
R70/AN0
R71/AN1
R72/AN2
R73/AN3
TEST
OSC1
OSC2
GND
X2
X1
RESET
VCC
D0/INT0
D1/INT1
D2
D3
D4
D5
D6
D7
D8
D9
R00/WU0
R01/WU1
R02/WU2
R10/EVNB
R11
R12/BUZZ
R13/TOB
R20/TOC
R21/SCKN
R22/SI/SO
PROM Mode
I/O
I/O
I/O
I/O
I/O
I
I
O
—
O
I
I
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin No.
Pin Name
VCC
VCC
I/O
—
—
VPP
VCC
—
—
GND
—
GND
RESET
VCC
A0
—
I
—
I
A5
A6
A7
A8
A9
A10
A11
A12
VCC
I
I
I
I
I
I
I
I
—
A13
M0
CE
XM1
OE
XM0
I
I
I
O
I
O
FP-64A
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MCU Mode
DP-64S
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
Pin Name
R23
R30/SEG1
R31/SEG2
R32/SEG3
R33/SEG4
R40/SEG5
R41/SEG6
R42/SEG7
R43/SEG8
R50/SEG9
R51/SEG10
R52/SEG11
R53/SEG12
R60/SEG13
R61/SEG14
R62/SEG15
R63/SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM1
COM2
COM3
COM4
V3
V2
V1
PROM Mode
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
Pin Name
A14
A1
A2
A3
A4
O0
O1
O2
O3
O4
O4
O3
O2
O1
O0
I/O
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
—
Notes: 1. I/O: I/O pin, I: Input-only pin, O: Output-only pin
2. As there are two each of pins O0 to O4, the respective pairs should be shorted.
3. Unused data pins (O5 to O7) on the PROM programmer side should be handled as shown below
on the socket.
VCC
O5, O6, O7
4. Pin A9 should be handled as shown below on the socket.
VCC
A9
HD4074889
HD4074899
HD4074869
Rev.6.00, Sep.08.2003, page 153 of 197
Writer side
HD404889/HD404899/HD404878/HD404868 Series
2. Pin Functions in PROM Mode
VPP:
Applies the on-chip PROM programming voltage (12.5 V ±0.3 V).
CE:
CE
Inputs a control signal to set the on-chip PROM to the write/verify enabled state.
OE:
OE
Inputs a data output control signal during verification.
A0 to A14:
On-chip PROM address input pins.
O0 to O4:
On-chip PROM data bus I/O pins.
As there are two each of pins O0 to O4, the respective pairs should be shorted.
M0, M1, RESET,
RESET TEST:
PROM mode setting pins. PROM mode is set by driving the M0, M1, and RESET pins low (or by driving
the M0, and RESET pins low in the HD4074869), and driving the TEST pin to the VPP level.
Other pins:
VCC, AVCC, R70/AN0, R71/AN1, OSC1, V0, and V1 should be connected to VCC potential.
GND, AVSS, and X1 should be connected to GND potential.
Other pins should be left open.
Rev.6.00, Sep.08.2003, page 154 of 197
HD404889/HD404899/HD404878/HD404868 Series
$0000
$0001
.
.
.
$001F
$0020
.
.
.
$007F
$0080
.
.
.
1
1
1
1
1
1
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5
Lower 5 bits
Upper 5 bits
$0000
Vector address
$000F
$0010
Zero-page subroutine
(64 words)
$003F
$0040
Pattern
(4,096 words)
$0FFF
$1000
$1FFF
$2000
Program
(16,384 words)
JMPL instruction
(jump to RESET routine)
JMPL instruction
(jump to WU0 to WU3
JMPL instruction
(jump to INT0 routine)
JMPL instruction
(jump to INT1 routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B, timer D routine)
JMPL instruction
(jump to timer C routine)
JMPL instruction
(jump to A/D, serial routine)
$3FFF
$7FFF
Upper three bits are not to be used
(fill them with 111)
Figure 95 Memory Map in PROM Mode
Rev.6.00, Sep.08.2003, page 155 of 197
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
HD404889/HD404899/HD404878/HD404868 Series
Start
Set Prog./Verify Mode
VPP=12.5±0.3V, VCC=6.0±0.25V
Address=0
n=0
Yes
n+1→n
No
Program tPW = 1ms±5%
n<S
S=25
NoGo
Verify
Go
Program tOPW = 3nms
Last
Address?
No
Yes
Set Read Mode
VCC=5.0±0.5V, VPP=VCC±0.6V
NoGo
Read
All Address
Go
End
Fail
Figure 96 Flowchart of High-Speed Programming
Rev.6.00, Sep.08.2003, page 156 of 197
Address + 1→Address
HD404889/HD404899/HD404878/HD404868 Series
Programming Electrical Characteristics
DC Characteristics (VCC = 6V ±0.25V, VPP = 12.5V ±0.3V, VSS = 0V, Ta = 25°C ±5°C,
unless otherwise specified)
Item
Symbol
Test Conditions
min
typ
max
Unit
Input high voltage
O0 to O4,A0 to A14,
OE, CE
VIH
2.2
—
VCC+0.3 V
Input low voltage
O0 to O4,A0 to A14,
OE, CE
VIL
–0.3
—
0.8
Output high voltage
O0 to O4
VOH
IOH=–200µA
2.4
—
—
V
Output low voltage
O0 to O4
VOL
IOL=1.6mA
—
—
0.4
V
Input leakage current O0 to O4,A0 to A14,
OE, CE
IIL
Vin=5.25V/0.5V
—
—
2
µA
VCC current
ICC
—
—
30
mA
VPP current
IPP
—
—
40
mA
V
AC Characteristics (VCC = 6V ±0.25V, VPP = 12.5V ±0.3V, Ta = 25°C ±5°C, unless
otherwise specified)
Item
Symbol
Test Conditions
min
typ
max
Unit
Address setup time
tAS
See figure 89
2
—
—
µs
OE setup time
tOES
2
—
—
µs
Data setup time
tDS
2
—
—
µs
Address hold time
tAH
0
—
—
µs
Data hold time
tDH
2
—
—
µs
Data output disable time
tDF
—
—
130
ns
VPP setup time
tVPS
2
—
—
µs
Program pulse width
tPW
0.95
1.0
1.05
ms
CE pulse width during overprogramming
tOPW
2.85
—
78.75
ms
VCC setup time
tVCS
2
—
—
µs
Data output delay time
tOE
0
—
500
ns
Notes: Input pulse level: 0.8 V to 2.2 V
Input rise/fall times: ≤ 20ns
Input timing reference levels: 1.0 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Rev.6.00, Sep.08.2003, page 157 of 197
HD404889/HD404899/HD404878/HD404868 Series
Write
Verify
Address
tAH
tAS
Data
Data In Stable
tDS
VPP
VPP
VCC
VCC VCC
GND
Data Out Valid
tDF
tDH
tVPS
tVCS
CE
tPW
OE
tOES
tOPW
Figure 97 PROM Write/Verify Timing
Rev.6.00, Sep.08.2003, page 158 of 197
tOE
HD404889/HD404899/HD404878/HD404868 Series
Notes on PROM Programming
Principles of Programming/Erasure: A memory cell in a ZTAT™ microcomputer is the same as an
EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot
electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an
SiO2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the
corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 98).
The charge in a memory cell may decrease with time. This decrease is usually due to one of the following
causes:
• Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure
principle.
• Heat excites trapped electrons, allowing them to escape.
• High voltages between the control gate and drain may erase electrons.
If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However,
electron erasure does not often occur because defective devices are detected and removed at the testing
stage.
Control gate
Control gate
SiO2
SiO2
Floating gate
Floating gate
Drain
Source
N+
N+
Write (0)
Drain
Source
N+
N+
Erasure (1)
Figure 98 Cross-Sections of a PROM Cell
PROM Programming: PROM memory cells must be programmed under specific voltage and timing
conditions. The higher the programming voltage VPP and the longer the programming pulse tPW is applied,
the more electrons are injected into the floating gates. However, if VPP exceeds specifications, the pn
junctions may be permanently damaged. Pay particular attention to overshooting in the PROM
programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may
reduce breakdown voltages.
The ZTAT™ microcomputer is electrically connected to the PROM programmer by a socket adapter.
Therefore, note the following points:
• Check that the socket adapter is firmly mounted on the PROM programmer.
• Do not touch the socket adapter or the LSI during the programming. Touching them may affect the
quality of the contacts, which will cause programming errors.
Rev.6.00, Sep.08.2003, page 159 of 197
HD404889/HD404899/HD404878/HD404868 Series
PROM Reliability after Programming: In general, semiconductor devices retain their reliability,
provided that some initial defects can be excluded. These initial defects can be detected and rejected by
screening. Baking devices under high-temperature conditions is one method of screening that can rapidly
eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure
section.)
ZTAT™ microcomputer devices are extremely reliable because they have been subjected to such a
screening method during the wafer fabrication process, but Renesas Technology recommends that each
device be exposed to 150°C at one atmosphere for at least 48 hours after it is programmed, to ensure its
best performance. The recommended screening procedure is shown in figure 99.
Note: If programming errors occur continuously during PROM programming, suspend programming and
check for problems in the PROM programmer or socket adapter. If programming verification
indicates errors in programming or after high-temperature exposure, please inform Renesas
Technology.
Programming, verification
Exposure to high temperature, without power
150°C ± 10°C, 48 h +8 h *
−0 h
Program read check
VCC = 4.5 V or 5.5 V
Note:
Exposure time is measured from when the temperature in the heater reaches 150°C.
Figure 99 Recommended Screening Procedure
Rev.6.00, Sep.08.2003, page 160 of 197
HD404889/HD404899/HD404878/HD404868 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 100 and described below.
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.
W register
W1 W0
RAM address
X register
X3
X2
X1
Y register
X0
Y3
Y2
Y1
Y0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Indirect Addressing
1st word of Instruction
Opcode
2nd word of Instruction
d
RAM address
9
d8
d7
d6
d5
d4
d3
d2
d1
d0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction
Opcode
0
RAM address
0
0
1
0
m1
m0
0
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 100 RAM Addressing Modes
Rev.6.00, Sep.08.2003, page 161 of 197
m3 m2
HD404889/HD404899/HD404878/HD404868 Series
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 101 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 103. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross assembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 102. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter.
Rev.6.00, Sep.08.2003, page 162 of 197
HD404889/HD404899/HD404878/HD404868 Series
1st word of instruction
[JMPL]
[BRL]
[CALL]
Opcode
p3
Program counter
2nd word of instruction
p2
p1
p0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Direct Addressing
Instruction
[BR]
Program counter
Opcode
b6
b7
b5
b4
b3
b2
b1
b0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Current Page Addressing
Instruction
[CAL]
0
Program counter
0
0
0
d5
Opcode
0
0
0
d4
d3
d2
d1
d0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Zero Page Addressing
Instruction
[TBR]
Opcode
p3
p2
p1
p0
B register
B3
0
Program counter
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 101 ROM Addressing Modes
Rev.6.00, Sep.08.2003, page 163 of 197
HD404889/HD404899/HD404878/HD404868 Series
Instruction
[P]
Opcode
p3
p2
p1
p0
B register
B3
0
B2 B1
Accumulator
B0
A3
A2
A1
A0
0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0
Address Designation
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
ROM data
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10
If RO 9 = 1
Pattern Output
Figure 102 P Instruction
256 (n − 1) + 255
BR
AAA
256n
AAA
BBB
256n + 254
256n + 255
256 (n + 1)
NOP
BR
BR
BBB
AAA
NOP
Figure 103 Branching when the Branch Destination is on a Page Boundary
Rev.6.00, Sep.08.2003, page 164 of 197
HD404889/HD404899/HD404878/HD404868 Series
Instruction Set
The MCU Series has 101 instructions, classified into the following 10 groups:
• Immediate instructions
• Register-to-register instructions
• RAM addressing instructions
• RAM register instructions
• Arithmetic instructions
• Compare instructions
• RAM bit manipulation instructions
• ROM addressing instructions
• Input/output instructions
• Control instructions
The functions of these instructions are listed in tables 31 to 40, and an opcode map is shown in table 41.
Table 31
Immediate Instructions
Mnemonic
Operation Code
Load A from immediate
LAI i
1 0 0 0 1 1 i3
i2
i1
i0
i→A
1/1
Load B from immediate
LBI i
1 0 0 0 0 0 i3
i2
i1
i0
i→B
1/1
Load memory from
immediate
LMID i,d
0 1 1 0 1 0 i3 i2 i1 i0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
i→M
2/2
Load memory from
immediate, increment Y
LMIIY i
1 0 1 0 0 1 i3
i → M, Y + 1 → Y
NZ
1/1
Status
Words/
Cycles
Table 32
Function
i2
i1
i0
Status
Words/
Cycles
Operation
Register-Register Instructions
Operation
Mnemonic
Operation Code
Function
Load A from B
LAB
0 0 0 1 0 0 1 0 0 0
B→A
1/1
Load B from A
LBA
0 0 1 1 0 0 1 0 0 0
A→B
1/1
Load A from W
LAW
0 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
W→A
2/2*
Load A from Y
LAY
0 0 1 0 1 0 1 1 1 1
Y→A
1/1
Load A from SPX
LASPX
0 0 0 1 1 0 1 0 0 0
SPX → A
1/1
Load A from SPY
LASPY
0 0 0 1 0 1 1 0 0 0
SPY → A
1/1
Load A from MR
LAMR m
1 0 0 1 1 1 m3 m2 m1 m0
MR (m) → A
1/1
Exchange MR and A
XMRA m
1 0 1 1 1 1 m3 m2 m1 m0
MR (m) ↔ A
1/1
Note:
The assembler automatically provides an operand for the second word of the LAW instruction.
Rev.6.00, Sep.08.2003, page 165 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 33
RAM Address Instructions
Operation
Mnemonic
Operation Code
Load W from immediate
LWI i
0 0 1 1 1 1 0 0 i1
i0
i→W
1/1
Load X from immediate
LXI i
1 0 0 0 1 0 i3
i2
i1
i0
i→X
1/1
Load Y from immediate
LYI i
1 0 0 0 0 1 i3
i2
i1
i0
i→Y
1/1
Load W from A
LWA
0 1 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0
A→W
2/2*
Load X from A
LXA
0 0 1 1 1 0 1 0 0 0
A→X
1/1
Load Y from A
LYA
0 0 1 1 0 1 1 0 0 0
A→Y
1/1
Increment Y
IY
0 0 0 1 0 1 1 1 0 0
Y+1→Y
NZ
1/1
Decrement Y
DY
0 0 1 1 0 1 1 1 1 1
Y–1→Y
NB
1/1
Function
Status
Words/
Cycles
Add A to Y
AYY
0 0 0 1 0 1 0 1 0 0
Y+A→Y
OVF
1/1
Subtract A from Y
SYY
0 0 1 1 0 1 0 1 0 0
Y–A→Y
NB
1/1
Exchange X and SPX
XSPX
0 0 0 0 0 0 0 0 0 1
X ↔ SPX
1/1
Exchange Y and SPY
XSPY
0 0 0 0 0 0 0 0 1 0
Y ↔ SPY
1/1
Exchange X and SPX,
Y and SPY
XSPXY
0 0 0 0 0 0 0 0 1 1
X ↔ SPX,Y ↔ SPY
1/1
Note: The assembler automatically provides an operand for the second word of the LWA instruction.
Rev.6.00, Sep.08.2003, page 166 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 34
RAM Register Instructions
Operation
Mnemonic
Operation Code
Function
Status
Words/
Cycles
LAM
0 0 1 0 0 1 0 0 0 0
M→A
LAMX
0 0 1 0 0 1 0 0 0 1
M→A
X ↔ SPX
LAMY
0 0 1 0 0 1 0 0 1 0
M→A
Y ↔ SPY
LAMXY
0 0 1 0 0 1 0 0 1 1
M→A
X ↔ SPX, Y ↔ SPY
Load A from memory
LAMD d
0 1 1 0 0 1 0 0 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
M→A
2/2
Load B from memory
LBM
0 0 0 1 0 0 0 0 0 0
M→B
1/1
LBMX
0 0 0 1 0 0 0 0 0 1
M→B
X ↔ SPX
LBMY
0 0 0 1 0 0 0 0 1 0
M→B
Y ↔ SPY
LBMXY
0 0 0 1 0 0 0 0 1 1
M→B
X ↔ SPX, Y ↔ SPY
LMA
0 0 1 0 0 1 0 1 0 0
A→M
LMAX
0 0 1 0 0 1 0 1 0 1
A→M
X ↔ SPX
LMAY
0 0 1 0 0 1 0 1 1 0
A→M
Y ↔ SPY
LMAXY
0 0 1 0 0 1 0 1 1 1
A→M
X ↔ SPX, Y ↔ SPY
Load memory from A
LMAD d
0 1 1 0 0 1 0 1 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A→M
Load memory from A,
increment Y
LMAIY
0 0 0 1 0 1 0 0 0 0
A → M, Y + 1 → Y
LMAIYX
0 0 0 1 0 1 0 0 0 1
A → M, Y + 1 → Y
X ↔ SPX
Load memory from A,
decrement Y
LMADY
0 0 1 1 0 1 0 0 0 0
A → M, Y – 1 → Y
LMADYX
0 0 1 1 0 1 0 0 0 1
A → M, Y – 1 → Y
X ↔ SPX
Load A from memory
Load memory from A
Rev.6.00, Sep.08.2003, page 167 of 197
1/1
1/1
2/2
NZ
1/1
NB
1/1
HD404889/HD404899/HD404878/HD404868 Series
Table 34
RAM Register Instructions (cont)
Operation
Mnemonic
Operation Code
Function
Status
Words/
Cycles
XMA
0 0 1 0 0 0 0 0 0 0
M↔A
XMAX
0 0 1 0 0 0 0 0 0 1
M↔A
X ↔ SPX
XMAY
0 0 1 0 0 0 0 0 1 0
M↔A
Y ↔ SPY
XMAXY
0 0 1 0 0 0 0 0 1 1
M↔A
X ↔ SPX, Y ↔ SPY
Exchange memory
and A
XMAD d
0 1 1 0 0 0 0 0 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
M↔A
2/2
Exchange memory
and B
XMB
0 0 1 1 0 0 0 0 0 0
M↔B
1/1
XMBX
0 0 1 1 0 0 0 0 0 1
M↔B
X ↔ SPX
XMBY
0 0 1 1 0 0 0 0 1 0
M↔B
Y ↔ SPY
XMBXY
0 0 1 1 0 0 0 0 1 1
M↔B
X ↔ SPX, Y ↔ SPY
Exchange memory
and A
Rev.6.00, Sep.08.2003, page 168 of 197
1/1
HD404889/HD404899/HD404878/HD404868 Series
Table 35
Arithmetic Instructions
Operation
Mnemonic
Operation Code
Function
Status
Words/
Cycles
Add immediate to A
AI i
1 0 1 0 0 0 i3
A+i→A
OVF
1/1
Increment B
IB
0 0 0 1 0 0 1 1 0 0
B+1→B
NZ
1/1
Decrement B
DB
0 0 1 1 0 0 1 1 1 1
B–1→B
NB
1/1
Decimal adjust for
addition
DAA
0 0 1 0 1 0 0 1 1 0
1/1
Decimal adjust for
subtraction
DAS
0 0 1 0 1 0 1 0 1 0
1/1
Negate A
NEGA
0 0 0 1 1 0 0 0 0 0
A+1→A
B→B
i2
i1
i0
1/1
Complement B
COMB
0 1 0 1 0 0 0 0 0 0
Rotate right A with carry
ROTR
0 0 1 0 1 0 0 0 0 0
1/1
1/1
Rotate left A with carry
ROTL
0 0 1 0 1 0 0 0 0 1
1/1
Set carry
SEC
0 0 1 1 1 0 1 1 1 1
1 → CA
Reset carry
REC
0 0 1 1 1 0 1 1 0 0
0 → CA
Test carry
TC
0 0 0 1 1 0 1 1 1 1
Add A to memory
AM
0 0 0 0 0 0 1 0 0 0
Add A to memory
AMD d
Add A to memory with
carry
1/1
1/1
CA
1/1
M+A→A
OVF
1/1
0 1 0 0 0 0 1 0 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
M+A→A
OVF
2/2
AMC
0 0 0 0 0 1 1 0 0 0
M + A + CA → A
OVF → CA
OVF
1/1
Add A to memory with
carry
AMCD d
0 1 0 0 0 1 1 0 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
M + A + CA → A
OVF → CA
OVF
2/2
Subtract A from memory
with carry
SMC
0 0 1 0 0 1 1 0 0 0
M – A – CA → A
NB → CA
NB
1/1
Subtract A from memory
with carry
SMCD d
0 1 1 0 0 1 1 0 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
M – A – CA → A
NB → CA
NB
2/2
OR A and B
OR
0 1 0 1 0 0 0 1 0 0
A∪B→A
AND memory with A
ANM
0 0 1 0 0 1 1 1 0 0
A∩M→A
NZ
1/1
AND memory with A
ANMD d
0 1 1 0 0 1 1 1 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A∩M→A
NZ
2/2
OR memory with A
ORM
0 0 0 0 0 0 1 1 0 0
A∪M→A
NZ
1/1
OR memory with A
ORMD d
0 1 0 0 0 0 1 1 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A∪M→A
NZ
2/2
EOR memory with A
EORM
0 0 0 0 0 1 1 1 0 0
A⊕M→A
NZ
1/1
EOR memory with A
EORMD d
0 1 0 0 0 1 1 1 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A⊕M→A
NZ
2/2
Rev.6.00, Sep.08.2003, page 169 of 197
1/1
HD404889/HD404899/HD404878/HD404868 Series
Table 36
Compare Instructions
Function
Status
Words/
Cycles
i≠M
NZ
1/1
0 1 0 0 1 0 i3 i2 i1 i0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
i≠M
NZ
2/2
ANEM
0 0 0 0 0 0 0 1 0 0
A≠M
NZ
1/1
ANEMD d
0 1 0 0 0 0 0 1 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A≠M
NZ
2/2
B not equal to memory
BNEM
0 0 0 1 0 0 0 1 0 0
B≠M
NZ
1/1
Y not equal to immediate
YNEI i
0 0 0 1 1 1 i3
i2
i1 i0
Y≠i
NZ
1/1
Immediate less than or
equal to memory
ILEM i
0 0 0 0 1 1 i3
i2
i1 i0
i≤M
NB
1/1
Immediate less than or
equal to memory
ILEMD i,d
0 1 0 0 1 1 i3 i2 i1 i0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
i≤M
NB
2/2
A less than or equal to
memory
ALEM
0 0 0 0 0 1 0 1 0 0
A≤M
NB
1/1
A less than or equal to
memory
ALEMD d
0 1 0 0 0 1 0 1 0 0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
A≤M
NB
2/2
B less than or equal to
memory
BLEM
0 0 1 1 0 0 0 1 0 0
B≤M
NB
1/1
A less than or equal to
immediate
ALEI i
1 0 1 0 1 1 i3
A≤i
NB
1/1
Status
Words/
Cycles
Operation
Mnemonic
Operation Code
Immediate not equal to
memory
INEM i
0 0 0 0 1 0 i3
Immediate not equal to
memory
INEMD i,d
A not equal to memory
A not equal to memory
Table 37
i2
i2
i1 i0
i1 i0
RAM Bit Manipulation Instructions
Operation
Mnemonic
Operation Code
Function
Set memory bit
SEM n
0 0 1 0 0 0 0 1 n1 n0
i → M (n)
1/1
Set memory bit
SEMD n,d
0 1 1 0 0 0 0 1 n1 n0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
i → M (n)
2/2
Reset memory bit
REM n
0 0 1 0 0 0 1 0 n1 n0
0 → M (n)
1/1
Reset memory bit
REMD n,d
0 1 1 0 0 0 1 0 n1 n0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
0 → M (n)
2/2
Test memory bit
TM n
0 0 1 0 0 0 1 1 n1 n0
M (n)
1/1
Test memory bit
TM n,d
0 1 1 0 0 0 1 1 n1 n0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
M (n)
2/2
Rev.6.00, Sep.08.2003, page 170 of 197
HD404889/HD404899/HD404878/HD404868 Series
Table 38
ROM Address Instructions
Operation
Mnemonic
Operation Code
Function
Status
Words/
Cycles
Branch on status 1
BR b
1 1 b7 b6 b5 b4 b3 b2 b1 b0
1
1/1
Long branch on status 1
BRL u
0 1 0 1 1 1 p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
1
2/2
Long jump
unconditionally
JMPL u
0 1 0 1 0 1 p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Subroutine jump on
status 1
CAL a
0 1 1 1 a5 a4 a3 a2 a1 a0
1
1/2
Long subroutine jump
on status 1
CALL u
0 1 0 1 1 0 p3 p2 p1 p0
d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
1
2/2
Table branch
TBR p
0 0 1 0 1 1 p3 p2 p1 p0
1
1/1
Return from subroutine
RTN
0 0 0 0 0 1 0 0 0 0
Return from interrupt
RTNI
0 0 0 0 0 1 0 0 0 1
Table 39
2/2
1/3
1 → IE,
carry restored
ST
1/1
Status
Words/
Cycles
Input/Output Instructions
Operation
Mnemonic
Operation Code
Function
Set discrete I/O latch
SED
0 0 1 1 1 0 0 1 0 0
1 → D (Y)
1/1
Set discrete I/O latch
direct
SEDD m
1 0 1 1 1 0 m3 m2 m1 m0
1 → D (m)
1/1
Reset discrete I/O latch
RED
0 0 0 1 1 0 0 1 0 0
0 → D (Y)
1/1
Reset discrete I/O latch
direct
REDD m
1 0 0 1 1 0 m3 m2 m1 m0
0 → D (m)
1/1
Test discrete I/O latch
TD
0 0 1 1 1 0 0 0 0 0
D (Y)
1/1
Test discrete I/O latch
direct
TDD m
1 0 1 0 1 0 m3 m2 m1 m0
D (m)
1/1
Load A from R-port
register
LAR m
1 0 0 1 0 1 m3 m2 m1 m0
R (m) → A
1/1
Load B from R-port
register
LBR m
1 0 0 1 0 0 m3 m2 m1 m0
R (m) → B
1/1
Load R-port register
from A
LRA m
1 0 1 1 0 1 m3 m2 m1 m0
A → R (m)
1/1
Load R-port register
from B
LRB m
1 0 1 1 0 0 m3 m2 m1 m0
B → R (m)
1/1
Pattern generation
Pp
0 1 1 0 1 1 p3 p2 p1 p0
Rev.6.00, Sep.08.2003, page 171 of 197
1/2
HD404889/HD404899/HD404878/HD404868 Series
Table 40
Control Instructions
Mnemonic
Operation Code
No operation
NOP
0 0 0 0 0 0 0 0 0 0
1/1
Start serial
STS
0 1 0 1 0 0 1 0 0 0
1/1
Standby mode/watch mode*
SBY
0 1 0 1 0 0 1 1 0 0
1/1
Stop mode/watch mode
STOP
0 1 0 1 0 0 1 1 0 1
1/1
Note:
Only after a transition from subactive mode.
Rev.6.00, Sep.08.2003, page 172 of 197
Function
Status
Words/
Cycles
Operation
HD404889/HD404899/HD404878/HD404868 Series
Table 41
Opcode Map
0
R8
L
0
1
2
3
4
R9 H
0
NOP
XSPX XSPY XSPXY ANEM
1
RTN
RTNI
5
6
ALEM
2
0
LBM(XY)
LMAIY(X)
NEGA
B
C
AM
ORM
AMC
EORM
D
E
F
LAB
IB
AYY
LASPY
IY
RED
LASPX
TC
YNEI i(4)
8
9
XMA(XY)
SEM n(2)
LAM(XY)
LMA(XY)
ROTR ROTL
REM n(2)
SMC
DAA
B
TM n(2)
ANM
DAS
LAY
TBR p(4)
C
BLEM
LBA
DB
D
LMADY(X)
SYY
LYA
DY
E
TD
SED
LXA
F
1
A
BNEM
7
A
9
ILEM i(4)
4
6
8
INEM i(4)
3
5
7
XMB(XY)
REC
SEC
LWI i(2)
0
LBI i(4)
1
LYI i(4)
2
LXI i(4)
3
LAI i(4)
4
LBR m(4)
5
LAR m(4)
6
REDD m(4)
7
LAMR m(4)
8
AI i(4)
9
LMIIY i(4)
A
TDD m(4)
B
ALEI i(4)
C
D
LRB m(4)
LRA m(4)
E
SEDD m(4)
F
XMRA m(4)
1-word/2-cycle
instruction
1-word/3-cycle
instruction
Rev.6.00, Sep.08.2003, page 173 of 197
RAM direct address
instruction
(2-word/2-cycle)
2-word/2-cycle
instruction
HD404889/HD404899/HD404878/HD404868 Series
Table 41
Opcode Map (cont)
1
R8
L
0
1
2
3
4
R9 H
0
LAW
ANEMD
1
LWA
ALEMD
5
6
2
0
8
9
A
B
C
AMD
ORMD
AMCD
EORMD
D
E
F
INEMD i(4)
3
4
7
ILEMD i(4)
COMB
OR
STS
5
JMPL p(4)
6
CALL p(4)
7
SBY
STOP
BRL p(4)
8
XMAD
9
LAMD
SEMD n(2)
LMAD
REMD n(2)
SMCD
A
LMID i(4)
B
P p(4)
TMD n(2)
ANMD
C
D
CAL a(6)
E
F
0
1
2
3
4
5
6
7
1
BR b(8)
8
9
A
B
C
D
E
F
1-word/2-cycle
instruction
1-word/3-cycle
instruction
Rev.6.00, Sep.08.2003, page 174 of 197
RAM direct address
instruction
(2-word/2-cycle)
2-word/2-cycle
instruction
HD404889/HD404899/HD404878/HD404868 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Notes
Power supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14.0
V
Pin voltage
VT
–0.3 to VCC+0.3
V
Allowable input current (total)
Σl0
100
mA
2
Allowable output current (total)
–Σ l0
50
mA
3
Allowable input current (per pin)
l0
4
mA
4,5
30
mA
4,6
Allowable output current (per pin)
–l0
4
mA
7,8
20
mA
7,9
1
Operating temperature
Topr
–20 to +75
°C
10
Storage temperature
Tstg
–55 to +125
°C
11
Notes: Permanent damage may occur if these maximum ratings are exceeded. Normal operation must be
under the conditions stated in the electrical characteristics tables. If these conditions are exceeded,
the LSI may malfunction or its reliability may be affected.
1. Applies to the HD4074889, HD4074899, and HD4074869 TEST (VPP) pin.
2. The allowable input current (total) is the sum of all currents flowing from I/O pins to ground at the
same time.
3. The allowable output current (total) is the sum of all currents flowing from VCC to I/O pins.
4. The allowable input current (per pin) is the maximum current allowed to flow from any one I/O pin
to ground.
5. Applies to pins D0 to D3 and R0 to R8.
6. Applies to pins D4 to D11.
7. The allowable output current (per pin) is the maximum current allowed to flow from VCC to any
one I/O pin.
8. Applies to pins D4 to D11 and R0 to R8.
9. Applies to pins D0 to D3.
10. The operating temperature indicates the temperature range in which power can be supplied to
the LSI (voltage Vcc shown in the electrical characteristics tables can be applied).
11. In the case of chips, the storage specification differs from that of the package products. Please
consult your Renesas Technology sales representative for details.
Rev.6.00, Sep.08.2003, page 175 of 197
HD404889/HD404899/HD404878/HD404868 Series
Electrical Characteristics
DC Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899,
HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to +75°C;
HCD404889, HCD404899, HCD404878: VCC=1.8V to 5.5V, GND=0V, Ta=+75°C; HD4074889,
HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise
specified)
Item
Symbol Pins
Input high
voltage
VIH
Input low
voltage
VIL
min.
typ. max.
Unit Test conditions
RESET,SCK, SI,
INT0,INT1, WU0 to WU3,
EVNB, EVND
0.90VCC —
VCC+0.3 V
OSC1
VCC–0.3 —
VCC+0.3 V
RESET,SCK, SI,
INT0,INT1, WU0 to WU3,
EVNB, EVND
–0.3
—
0.10VCC V
OSC1
–0.3
—
0.3
V
External clock
operation
External clock
operation
Output high
voltage
VOH
SCK,SO, BUZZ, TOB,
TOC
VCC–0.5 —
—
V
–IOH=0.3mA
Output low
voltage
VOL
SCK,SO, BUZZ, TOB,
TOC
—
—
0.4
V
IOL=0.4mA
I/O leakage
current
| IIL|
RESET,SCK, SI,INT0,
—
INT1 , WU0 to WU3, EVNB,
EVND, OSC1, TOB, TOC,
SO, BUZZ
—
1
µA
Vin=0V to VCC
Active mode
current
dissipation
lCC1
VCC
lCC2
—
3.0
5.0
mA VCC=5V, fOSC=4MHz 2
0.4
1.0
mA VCC=3V,
fOSC=800kHz
—
1.0
2.0
mA VCC=5V, fOSC=4MHz, 3
LCD on
VCC
—
0.3
0.6
mA VCC=3V,
fOSC=800kHz LCD
on
Subactive
mode current
dissipation
VCC
—
(HD404888, HD4048812,
HD404889, HCD404889,
HD404898, HD4048912,
HD404899, HCD404899,
HD404874, HD404878,
HCD404878, HD404864,
HD404868)
35
60
µA
—
VCC (HD4074889,
HD4074899, HD4074869)
70
120
µA
Rev.6.00, Sep.08.2003, page 176 of 197
1
—
Standby mode lSBY1
current
dissipation
lSBY2
lSUB
Notes
VCC = 3V, LCD on,
32 kHz oscillator
used
2
3
4,5
4,5
HD404889/HD404899/HD404878/HD404868 Series
Item
Symbol Pins
min.
typ. max.
Unit
Test Conditions
Notes
lWTC1
Watch mode
current dissipation
VCC
—
15
30
µA
VCC = 3 V, LCD on,
32 kHz oscillator used
4,5
lWTC2
VCC
—
5
8
µA
VCC = 3 V, LCD off,
32 kHz oscillator used
5
Stop mode current lSTOP
dissipation
VCC
—
—
5
µA
VCC = 3 V, no 32 kHz
oscillator
5
Stop mode
retention voltage
VCC
1.5
—
—
V
no 32 kHz oscillator
6
VSTOP
Notes: 1. Excludes output buffer current.
2. Power supply current when the MCU is in the reset state and there are no I/O currents.
Test Conditions MCU State
Pin States
•
Reset state
•
RESET, TEST: At ground
3. Power supply current when the on-chip timers are operating and there are no I/O currents.
Test Conditions MCU State
Pin States
•
I/O: Same as reset state
•
Standby mode
•
fcyc = fOSC/4
•
RESET: At VCC
•
TEST: At ground
•
D0 to D11, R0 to R8: At VCC
4. Applies when the LCD power supply dividing resistor is connected.
5. Power supply current when there are no I/O currents.
Test Conditions Pin States
•
RESET: At VCC
•
TEST: At ground
•
D0 to D11, R0 to R8: At VCC
6. Voltage needed to retain RAM data.
Rev.6.00, Sep.08.2003, page 177 of 197
HD404889/HD404899/HD404878/HD404868 Series
I/O Characteristics for Standard Pins (HD404888, HD4048812, HD404889, HD404898, HD4048912,
HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to
+75°C; HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless
otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Input high voltage
VIH
R0 to R8
0.7VCC
—
V
VCC+0.3
Test conditions
1
R0 to R7
Input low voltage
VIL
R0 to R8
2
–0.3
—
0.3VCC
V
1
R0 to R7
Output high voltage
VOH
R0 to R8
2
VCC–0.5
—
—
V
–IOH=0.3mA
R0 to R7
Output low voltage
VOL
R0 to R8
I/O leakage current
| IIL |
R0 to R8
—
—
0.4
V
IOL=0.4mA
1
—
—
1
µA
VIN=0V to VCC
1, 3
2
R0 to R7
–IPU
R0 to R8
2, 3
10
50
150
R0 to R7
Notes: 1. Applies to the HD404889, HD404899, and HD404878 Series.
2. Applies to the HD404868 Series.
3. Excludes the current flowing in the output buffer.
Rev.6.00, Sep.08.2003, page 178 of 197
1
2
R0 to R7
MOS pull-up current
Notes
µA
VCC=3V, VIN=0V
1
2
HD404889/HD404899/HD404878/HD404868 Series
I/O Characteristics for High-Current Pins (HD404888, HD4048812, HD404889, HD404898,
HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V,
Ta=–20°C to +75°C; HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V,
Ta=+75°C; HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C,
unless otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Input high voltage
VIH
D0 to D11
0.7VCC
—
V
VCC+0.3
Test conditions
1
D0 to D9
Input low voltage
VIL
D0 to D11
2
–0.3
—
0.3VCC
V
1
D0 to D9
Output high voltage
VOH
D4 to D11
2
VCC–0.5
—
—
V
–IOH=0.3mA
VOL
D0 to D3
VCC–2.0
—
—
V
–IOH=10mA,
VCC=4.5 to 5.5V
D0 to D3
—
—
0.4
V
IOL=0.4mA
D4 to D11
—
—
2.0
V
IOL=15mA
VCC=4.5V to 5.5V
2
—
—
1
µA
VIN =0V to VCC
1, 3
D4 to D9
I/O leakage current
| IIL |
D0 to D11
D0 to D9
MOS pull-up current
–IPU
1
2
D4 to D9
Output low voltage
Notes
D0 to D11
2, 3
10
50
150
D0 to D9
Notes: 1. Applies to the HD404889, HD404899, and HD404878 Series.
2. Applies to the HD404868 Series.
3. Excludes the current flowing in the output buffer.
Rev.6.00, Sep.08.2003, page 179 of 197
1
µA
VCC=3V, VIN=0V
1
2
HD404889/HD404899/HD404878/HD404868 Series
LCD Circuit Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912,
HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta= –20°C to
+75°C; HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless
otherwise specified)
Item
Symbol
Segment driver voltage VDS
drop
Pins
min.
typ. max.
Unit
Test conditions
Notes
SEG1 to
SEG32
—
—
V
Id=3 µA
V1=2.7 to 5.5V
1, 2
0.6
1, 3
SEG1 to
SEG24
Common driver voltage VDC
drop
LCD power supply
dividing resistance
RW
LCD voltage
VLCD
COM1 to
COM4
V1
—
—
50
2.2
0.3
V
Id=3 µA
V1=2.7 to 5.5V
300 900
KΩ
V1-GND
—
V
VCC
1
4, 5
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and GND to each segment pin or each
common pin.
2. Applies to the HD404889, HD404899, and HD404878 Series.
3. Applies to the HD404868 Series.
4. In the HD404889, HD404899, and HD404878 Series, when VLCD is supplied by the internal power
supply, V0 and V1 should be shorted. When VLCD is supplied by an external power supply, the
relationship VCC ≥ VLCD ≥ 2.2 V should be maintained. In this case, the V0 pin should be fixed at
VCC.
5. In the HD404868 Series, when VLCD is supplied by an external power supply, the relationship VCC
≥ VLCD ≥ 2.2 V should be maintained.
Rev.6.00, Sep.08.2003, page 180 of 197
HD404889/HD404899/HD404878/HD404868 Series
A/D Converter Characteristics (HD404888, HD4048812, HD404889: VCC=1.8V to 5.5V, GND=0V,
Ta=–20°C to +75°C; HCD404889: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C; HD4074889: VCC=2.0V to
5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Analog power supply
voltage
AVCC
AVCC
VCC–0.3
VCC
VCC+0.3
V
Analog input voltage
AVin
AN0 to AN5
AVSS
—
AVCC
V
AVCC-AVSS current
IAD
—
—
500
µA
Analog input
capacitance
CAin
—
15
—
pF
Resolution
—
8
—
bit
Number of inputs
0
—
6
channel
Absolute accuracy
—
—
±2.0
LSB
VCC=AVCC=2.7V to 5.5V
—
—
±3.0
LSB
VCC=AVCC=1.8V to 2.7V 2
65
—
125
tcyc
1
—
—
MΩ
AN0 to AN5
Conversion time
Input impedance
AN0 to AN5
Test conditions
Notes
1
VCC=AVCC=5.0V
Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting ranges are 1.8
V≤AVCC≤5.5V (HD404888, HD4048812, HD404889, HCD404889) and 2.0V≤AVCC≤5.5V
(HD4074889)
2. The conversion time is 125tcyc.
Rev.6.00, Sep.08.2003, page 181 of 197
HD404889/HD404899/HD404878/HD404868 Series
(HD404898, HD4048912, HD404899: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to +75°C;
HCD404899: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074899: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Analog power supply
voltage
AVCC
AVCC
VCC–0.3
VCC
VCC+0.3
V
Analog input voltage
AVin
AN0 to AN5
AVSS
—
AVCC
V
AVCC-AVSS current
IAD
—
—
500
µA
Analog input
capacitance
CAin
—
15
—
pF
Resolution
—
10
—
bit
Number of inputs
0
—
6
channel
Conversion time
125
—
—
tcyc
VCC = AVCC = 1.8 V to
less than 2.0 V
65
—
125
tcyc
VCC=AVCC=2.0 V to
5.5V
AN0 to AN5
Absolute accuracy
Input impedance
AN0 to AN5
—
—
±4.0
LSB
1
—
—
MΩ
Test conditions
Notes
1
VCC=AVCC=5.0V
2
Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting ranges are 1.8
V≤AVCC≤5.5V (HD404898, HD4048912, HD404899, HCD404899) and 2.0V≤AVCC≤5.5V
(HD4074899)
2. Applies to HD404898, HD4048912, HD404899, and HCD404899.
(HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to +75°C; HD4074869: VCC =2.0V to
5.5V, GND=0V, Ta=–20°C to +75°C)
Item
Symbol
Pins
min.
typ. max.
Unit
Analog input voltage
AVin
AN0 to AN3
GND
—
VCC
V
Analog input
capacitance
CAin
AN0 to AN3
—
15
—
pF
Resolution
—
10
—
bit
Number of inputs
0
—
4
channel
Absolute accuracy
—
—
±4.0
LSB
Conversion time
125
—
—
Input impedance
AN0 to AN3
Notes
tcyc
VCC = 1.8 V to less
than 2.0 V
1
VCC= 2.0 V to 5.5V
65
—
125
tcyc
1
—
—
MΩ
Note: 1. Applies to HD404864 and HD404868.
Rev.6.00, Sep.08.2003, page 182 of 197
Test conditions
HD404889/HD404899/HD404878/HD404868 Series
AC Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899,
HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to +75°C;,
HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C; HD4074889,
HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless otherwise
specified)
Item
Symbol Pins
min. typ.
max.
Clock oscillation
frequency
fOSC
OSC1, OSC2
0.4
—
4.5
X1,X2
—
32.768 —
Instruction cycle time
tcyc
0.89 —
tsubcyc
Unit
Test conditions
Notes
MHz
Division by 4
1
kHz
10
µs
Division by 4
—
244.14 —
µs
32 kHz oscillator used,
division by 8
—
122.07 —
µs
32 kHz oscillator used,
division by 4
Oscillation settling
tRC
time(external clock and
ceramic oscillator)
OSC1, OSC2
—
—
7.5
ms
2
Oscillation settling
time(crystal oscillator)
tRC
OSC1, OSC2
—
—
30
ms
VCC=2.0 to 5.5V
2
X1,X2
—
—
2
s
Ta=–10 to +60°C
2
External clock highlevel width
tCPH
OSC1
105 —
—
ns
fOSC=4MHZ
3
External clock lowlevel width
tCPL
OSC1
105 —
—
ns
fOSC=4MHZ
3
External clock rise time tCPr
OSC1
—
—
20
ns
fOSC=4MHZ
3
External clock fall time tCPf
OSC1
—
—
20
ns
fOSC=4MHZ
3
INT0 to INT1,
EVNB,EVND, WU0 to
WU3 high-level width
tIH
INT0 to INT1,
EVNB,EVND, WU0 to
WU3
2
—
—
tcyc/tsubcyc
4
INT0 to INT1,
EVNB,EVND, WU0 to
WU3 low-level width
tIL
INT0 to INT1,
EVNB,EVND, WU0 to
WU3
2
—
—
tcyc/tsubcyc
4
RESET low-level width tRSTL
RESET
2
—
—
tcyc
5
RESET rise time
tRSTr
RESET
—
—
20
ms
5
Input capacitance
Cin
All input pins except
TEST
—
—
15
pF
TEST
—
—
15
pF
—
—
40
pF
(HD404888, HD4048812,
HD404889, HCD404889,
HD404899, HD404898,
HD4048912,
HCD404899, HD404874,
HD404878, HCD404878,
HD404864, HD404868)
TEST
(HD4074889,
HD4074899,
HD4074869)
Rev.6.00, Sep.08.2003, page 183 of 197
f=1MHz,Vin=0V
HD404889/HD404899/HD404878/HD404868 Series
Notes: 1. When the subsystem oscillator (32.768 kHz crystal oscillation) is used, use within the range
0.4 MHz≤fOSC≤1.0 MHz or 1.6 MHz≤fOSC≤4.5 MHz. The SSR1 bit of the system clock select
register (SSR) should be set to 0 and 1, respectively.
2. The oscillation settling time is defined as follows:
(1)
The time required for the oscillation to settle after VCC has reached min. at power-on.
(2)
The time required for the oscillation to settle after RESET input has gone low when stop
mode is cleared.
To ensure enough time for the oscillation to settle at power-on hold the RESET input low for at
least time tRC. The oscillation settling time will depend on the circuit constants and stray
capacitance. The resonator should be determined in consultation with the resonator
manufacturer. With regard to the system clock (OSC1, OSC2), bits MIS1 and MIS0 in the
miscellaneous register (MIS) should be set according to the oscillation settling time of the
resonator used.
3. See figure 104.
4. See figure 105.
5. See figure 106.
Serial Interface Timing Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912,
HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=–20°C to
+75°C;, HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75°C;
HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta=–20°C to +75°C, unless
otherwise specified)
Item
Symbol
Pins
min.
typ. max.
Unit
Test conditions
Serial clock cycle time
tScyc
SCK
1
—
—
tcyc
See load in figure 108 1
Serial clock high-level
width
tSCKH
SCK
0.4
—
—
tScyc
See load in figure 108 1
Serial clock low-level
width
tSCKL
SCK
0.4
—
—
tScyc
See load in figure 108 1
Serial clock rise time
tSC Kr
SCK
—
—
100
ns
See load in figure 108 1
Serial clock fall time
tSCKf
SCK
—
—
100
ns
See load in figure 108 1
Serial output data
delay time
tDSO
SO
—
—
300
ns
See load in figure 108 1
Serial input data setup tSSI
time
SI
200
—
—
ns
1
Serial input data hold
time
SI
200
—
—
ns
1
tHSI
Rev.6.00, Sep.08.2003, page 184 of 197
Notes
HD404889/HD404899/HD404878/HD404868 Series
During Serial Clock Input
Item
Symbol
Pins
min.
typ. max.
Unit
Serial clock cycle time
tScyc
SCK
1
—
—
tcyc
1
Serial clock high-level
width
tSCKH
SCK
0.4
—
—
tScyc
1
Serial clock low-level
width
tSCKL
SCK
0.4
—
—
tScyc
1
Serial clock rise time
tSC Kr
SCK
—
—
100
ns
1
Serial clock fall time
tSCKf
SCK
—
—
100
ns
1
Serial output data
delay time
tDSO
SO
—
—
300
ns
See load in figure 108 1
Serial input data setup tSSI
time
SI
200
—
—
ns
1
Serial input data hold
time
SI
200
—
—
ns
1
Note:
tHSI
1. See figure 107.
OSC1
1/fCP
VCC-0.3V
0.3V
tCPL
tCPH
tCPr
tCPf
Figure 104 External Clock Input Waveform
INT0
, INT1, EVNB, EVND, WU0 to WU3
0.9VCC
tIH
tIL
0.1VCC
Figure 105 Interrupt Timing
Rev.6.00, Sep.08.2003, page 185 of 197
Test conditions
Notes
HD404889/HD404899/HD404878/HD404868 Series
RESET
0.9VCC
tRSTL
0.1VCC
tRSTr
Figure 106 Reset Timing
tScyc
SCK
tSCKf
VCC−0.5V(0.9VCC)*
tSCKr
tSCKL
tSCKH
0.4V(0.1VCC)*
tDOS
VCC−0.5V
0.4V
SO
tSSI
tHSI
0.9VCC
0.1VCC
SI
Note : VCC−0.5V and 0.4V are the voltages during serial clock output.
0.9 VCC and 0.1 VCC are the voltages during serial clock input.
Figure 107 Serial Interface Timing
Rev.6.00, Sep.08.2003, page 186 of 197
HD404889/HD404899/HD404878/HD404868 Series
VCC
R1=2.6kΩ
Test point
C=30pF
R=12kΩ
1S2074(H)
or equivalent
Figure 108 Timing Load Circuit
Rev.6.00, Sep.08.2003, page 187 of 197
HD404889/HD404899/HD404878/HD404868 Series
Package Dimensions
As of January, 2003
17.2 ± 0.3
Unit: mm
14
41
60
40
0.65
17.2 ± 0.3
61
80
21
1
2.70
0.12 M
0.10
1.6
0˚ – 8˚
0.10 +0.15
–0.10
0.83
*0.17 ± 0.05
0.15 ± 0.04
*0.32 ± 0.08
0.30 ± 0.06
3.05 Max
20
0.8 ± 0.3
Package Code
JEDEC
JEITA
Mass (reference value)
*Dimension including the plating thickness
Base material dimension
14.0 ± 0.2
FP-80A
—
Conforms
1.2 g
As of January, 2003
Unit: mm
12
60
41
40
80
21
0.5
14.0 ± 0.2
61
0.10
*Dimension including the plating thickness
Base material dimension
Rev.6.00, Sep.08.2003, page 188 of 197
*0.17 ± 0.05
0.15 ± 0.04
1.25
1.00
0.10 M
0.10 ± 0.10
*0.22 ± 0.05
0.20 ± 0.04
20
1.20 Max
1
1.0
0˚ – 8˚
0.5 ± 0.1
Package Code
JEDEC
JEITA
Mass (reference value)
TFP-80C
—
Conforms
0.4 g
HD404889/HD404899/HD404878/HD404868 Series
As of January, 2003
17.2 ± 0.3
Unit: mm
14
33
48
32
0.8
17.2 ± 0.3
49
64
17
1
16
2.70
3.05 Max
0.15 M
0.10 +0.15
–0.10
1.0
*0.17 ± 0.05
0.15 ± 0.04
*0.37 ± 0.08
0.35 ± 0.06
0.10
1.6
0˚ – 8˚
0.8 ± 0.3
Package Code
JEDEC
JEITA
Mass (reference value)
*Dimension including the plating thickness
Base material dimension
FP-64A
—
Conforms
1.2 g
As of January, 2003
Unit: mm
57.6
58.5 Max
33
17.0
18.6 Max
64
32
1.0
1.78 ± 0.25
0.48 ± 0.10
0.51 Min
1.46 Max
2.54 Min 5.08 Max
1
19.05
+ 0.11
0.25 – 0.05
0˚ – 15˚
Package Code
JEDEC
JEITA
Mass (reference value)
Rev.6.00, Sep.08.2003, page 189 of 197
DP-64S
—
Conforms
8.8 g
HD404889/HD404899/HD404878/HD404868 Series
Note on ROM Ordering
Please note the following when ordering HD404888, HD4048812, HD404898 or HD4048912 ROM.
When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of
data as for the 16-kwords version (HD404889, HD404899). The program that converts ROM data to mask
drawing data is the same as that used for the 16-kwords version, and therefore the same amount of data is
necessary. This applies both to orders using EPROM and orders using data transmission.
12-kword ROM version:
HD4048812, HD4048912
Write all-1 data to addresses
$3000 to $3FFF.
8-kword ROM
version: HD404888, HD404898
Write all-1 data to addresses
$2000 to $3FFF.
$0000
$0000
Vector addresses
$000F
$0010
Zero page
subroutine area
(64 words)
$003F
$0040
Vector addresses
$000F
$0010
$003F
$0040
Zero page
subroutine area
(64 words)
Program and pattern
area (8,192 words)
Program and pattern
area (12,288 words)
$1FFF
$2000
Not used
$2FFF
$3000
Not used
$3FFF
Note : Write all-1 data in shaded areas.
Rev.6.00, Sep.08.2003, page 190 of 197
$3FFF
HD404889/HD404899/HD404878/HD404868 Series
Note on ROM Ordering
Please note the following when ordering HD404874 or HD404864 ROM.
When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of
data as for the 8-kwords version (HD404878, HD404868). The program that converts ROM data to mask
drawing data is the same as that used for the 8-kwords version, and therefore the same amount of data is
necessary. This applies both to orders using EPROM and orders using data transmission.
4-kword ROM
version: HD404874, HD404864
Write all-1 data to addresses
$1000 to $1FFF.
$0000
Vector addresses
$000F
$0010
Zero page
subroutine area
(64 words)
$003F
$0040
Program and pattern
area (4,096 words)
$0FFF
$1000
Not used
$1FFF
Note : Write all-1 data in shaded areas.
Rev.6.00, Sep.08.2003, page 191 of 197
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404888, HD4048812, HD404889, HCD404889
Please check off the appropriate applications and enter the necessary information.
Date of order
Year
Month
Day
Customer
Department
Name
ROM code name
LSI number (Renesas Technology entry)
1. ROM Size
❑ HD404888
8 kwords
❑ HD4048812
12 kwords
❑ HD404889
16 kwords
❑ HCD404889
16 kwords
2. Function Options
* ❑
32 kHz CPU operation, realtime clock time base
* ❑
No 32 kHz CPU operation, realtime clock time base
❑
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1
X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
Combined lower/upper type
•
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
❑
Separate lower/upper type
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
❑
Ceramic oscillator
f=
MHz
❑
Crystal oscillator
f=
MHz
❑
External clock
f=
MHz
Rev.6.00, Sep.08.2003, page 192 of 197
HD404889/HD404899/HD404878/HD404868 Series
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑
Not used
—
❑
Yes (used)
❑ FP-80A
❑
Crystal resonator
f = 32.768 kHz
❑
No (not used)
❑ TFP-80C
❑ Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
Option List HD404898, HD4048912, HD404899, HCD404899
Please check off the appropriate applications and enter the necessary information.
Date of order
Year
Month
Day
Customer
Department
Name
ROM code name
LSI number (Renesas Technology entry)
1. ROM Size
❑ HD404898
8 kwords
❑ HD4048912
12 kwords
❑ HD404899
16 kwords
❑ HCD404899
16 kwords
2. Function Options
* ❑
32 kHz CPU operation, realtime clock time base
* ❑
No 32 kHz CPU operation, realtime clock time base
❑
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1
X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
Combined lower/upper type
•
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
❑
Separate lower/upper type
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
Rev.6.00, Sep.08.2003, page 193 of 197
HD404889/HD404899/HD404878/HD404868 Series
4. System Oscillator (OSC1-OSC2)
❑
Ceramic oscillator
f=
MHz
❑
Crystal oscillator
f=
MHz
❑
External clock
f=
MHz
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑
Not used
—
❑
Yes (used)
❑ FP-80A
❑
Crystal resonator
f = 32.768 kHz
❑
No (not used)
❑ TFP-80C
❑ Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
Option List HD404874, HD404878, HCD404878
Please check off the appropriate applications and enter the necessary information.
Date of order
Year
Month
Day
Customer
Department
Name
ROM code name
LSI number (Renesas Technology entry)
1. ROM Size
❑ HD404874
4 kwords
❑ HD404878
8 kwords
❑ HCD404878
8 kwords
2. Function Options
* ❑
32 kHz CPU operation, realtime clock time base
* ❑
No 32 kHz CPU operation, realtime clock time base
❑
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
Combined lower/upper type
•
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
❑
Separate lower/upper type
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
Rev.6.00, Sep.08.2003, page 194 of 197
HD404889/HD404899/HD404878/HD404868 Series
4. System Oscillator (OSC1-OSC2)
❑
Ceramic oscillator
f=
MHz
❑
Crystal oscillator
f=
MHz
❑
External clock
f=
MHz
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑
Not used
—
❑
Yes (used)
❑ FP-80A
❑
Crystal resonator
f = 32.768 kHz
❑
No (not used)
❑ TFP-80C
❑ Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our
sales staff for details.
Option List HD404864, HD404868
Please check off the appropriate applications and enter the necessary information.
Date of order
Year
Month
Day
Customer
Department
Name
ROM code name
LSI number (Renesas Technology entry)
1. ROM Size
❑ HD404864
4 kwords
❑ HD404868
8 kwords
2. Function Options
* ❑
32 kHz CPU operation, realtime clock time base
* ❑
No 32 kHz CPU operation, realtime clock time base
❑
No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1
X2).
3. ROM Code Data Organization
For a microcomputer with EPROM mounted (including a ZTAT™ microcomputer), specify the combined upper/lower
type.
❑
Combined lower/upper type
•
Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU...
❑
Separate lower/upper type
•
The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
Rev.6.00, Sep.08.2003, page 195 of 197
HD404889/HD404899/HD404878/HD404868 Series
4. System Oscillator (OSC1-OSC2)
❑
Ceramic oscillator
f=
MHz
❑
Crystal oscillator
f=
MHz
❑
External clock
f=
MHz
5. Subsystem Oscillator (X1 X2)
6. Stop Mode
7. Package
❑
Not used
—
❑
Yes (used)
❑ FP-64A
❑
Crystal resonator
f = 32.768 kHz
❑
No (not used)
❑ DP-64S
Rev.6.00, Sep.08.2003, page 196 of 197
HD404889/HD404899/HD404878/HD404868 Series
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.6.00, Sep.08.2003, page 197 of 197