APW7065C Synchronous Buck PWM Controller Features General Description • • The APW7065C uses fixed 300kHz switching frequency, voltage mode, synchronous PWM controller which drives Single 12V Power Supply Required Fast Transient Response dual N-channel MOSFETs. The device integrates the control, monitoring and protection functions into a - 0~90% Duty Ratio • • 0.8V Reference with 1% Accuracy • • • • Shutdown Function by Controlling COMP single package, provides one controlled power output with under-voltage and over-current protections. Pin Voltage The APW7065C provides excellent regulation for Internal Soft-Start (1.7ms) Function output load variation. The internal 0.8V temperature-compensated reference voltage is designed to meet the re- Voltage Mode PWM Control Design quirement of low output voltage applications. An built-in digital soft-start with fixed soft-start interval prevents the Under-Voltage Protection Over-Current Protection • • • - Sense Low Side MOSFET’s RDS(ON) output voltage from overshoot as well as limiting the input current. 300kHz Fixed Switching Frequency The APW7065C with excellent protection functions: SOP-8 Package POR, OCP and UVP. The Power-On-Reset (POR) circuit can monitor VCC supply voltage exceeds its thresh- Lead Free and Green Devices Available old voltage while the controller is running, and a built-in digital soft-start provides output with controlled voltage (RoHS Compliant) rise. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the lower Simplified Application Circuit MOSFET’s RDS(ON), comparing with internal VOCP (0.29V), when the output current reaches the trip point, the IC 12V VIN shuts off the converter and initiates a new soft-start process. After two over-current events are counted, L APW7065C VOUT the device turns off both high-side and low-side MOSFETs and the converter's output is latched to be floating. It requires a POR of VCC to restart. The UnderVoltage Protection (UVP) monitors the voltage of FB pin for short-circuit protection, when the VFB is less than 50% of VREF (0.4V), the controller will shutdown the IC Pin Configuration directly. BOOT 1 8 PHASE UGATE 2 7 COMP GND 3 6 FB LGATE 4 5 VCC Applications • • Graphics Card Mother Board SOP-8 (APW7065C) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 1 www.anpec.com.tw APW7065C Ordering and Marking Information Package Code K : SOP-8 Operating Ambient Temp. Range E : -20 to 70 °C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7065C Assembly Material Handling Code Temp. Range Package Code APW7065C K : APW7065 XXXXX C XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Parameter Rating Unit VCC to GND -0.3 ~ 16 V BOOT to PHASE -0.3 ~ 16 V Symbol VCC VBOOT VUGATE VLGATE VPHASE VCOMP, VFB TJ TSTG TSDR UGATE to PHASE LGATE to GND PHASE to GND <400ns pulse width -5 ~ VBOOT+5 >400ns pulse width -0.3 ~ VBOOT+0.3 <400ns pulse width -5 ~ VCC+5 >400ns pulse width -0.3 ~ VCC+0.3 <200ns pulse width -10 ~ 30 >200ns pulse width -0.3 ~ 16 COMP, FB to GND V V V -0.3 ~ 7 Junction Temperature Range Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds V -20 ~ 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Value Junction-to-Ambient Thermal Resistance in Free Air Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 SOP-8 2 160 Unit o C/W www.anpec.com.tw APW7065C Recommended Operating Conditions Symbol Parameter VCC VCC Supply Voltage VOUT Converter Output Voltage VIN Converter Input Voltage IOUT Converter Output Current TA Unit 10.8 ~ 13.2 V 0.8 ~ 5 V 2.9 ~ 13.2 V 0 ~ 25 Ambient Temperature Range Junction Temperature Range TJ Range A -20 ~ 70 o -20 ~ 125 o C C Electrical Characteristics Unless otherswise specified, these specifications apply over VCC=12V, and TA =-20~70oC. Typlcal values are at TA=25oC. Symbol Parameter APW7065C Test Conditions Unit Min Typ Max SUPPLY CURRENT IVCC VCC Nominal Supply Current UGATE and LGATE Open - 5 10 mA VCC Shutdown Supply Current UGATE, LGATE = GND - 1 2 mA Rising VCC Threshold 9 9.5 10 V Falling VCC Threshold 7.5 8 8.5 V COMP Shutdown Threshold - 1.2 - V COMP Shutdown Hysteresis - 0.1 - V 270 300 345 kHz - 1.6 - VP-P - 0.8 - V -1.0 - +1.0 % POWER-ON-RESET OSCILLATOR FOSC ∆VOSC Free Running Frequency Ramp Amplitude REFERENCE VOLTAGE VREF Reference Voltage Measured at FB Pin Accuracy TA =-20~70°C ERROR AMPLIFIER Gain GBWP SR Open Loop Gain RL=10K, CL=10pF(Note2) - 88 - dB Open Loop Bandwidth RL=10K, CL=10pF(Note2) - 15 - MHz Slew Rate RL=10K, CL=10pF(Note2) - 6 - V/µs - 0.1 1 µA FB Input Current VFB = 0.8V (Note2) VCOMP COMP High Voltage - 5.5 - V VCOMP COMP Low Voltage - 0 - V ICOMP COMP Source Current VCOMP=2V - 5 - mA ICOMP COMP Sink Current VCOMP=2V - 5 - mA Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 3 www.anpec.com.tw APW7065C Electrical Characteristics (Cont.) Unless otherswise specified, these specifications apply over VCC=12V, and TA =-20~70oC. Typlcal values are at TA=25oC. APW7065C Symbol Parameter Test Conditions Unit Min Typ Max GATE DRIVERS IUGATE Upper Gate Source Current VBOOT = 12V, VUGATE -VPHASE = 2V - 2.6 - A IUGATE Upper Gate Sink Current VBOOT = 12V, VUGATE -VPHASE = 2V - 1.05 - A ILGATE Lower Gate Source Current VCC = 12V, VLGATE = 2V - 4.9 - A ILGATE Lower Gate Sink Current VCC = 12V, VLGATE = 2V - 1.4 - A RUGATE Upper Gate Source Impedance VBOOT = 12V, IUGATE = 0.1A - 2 3 Ω RUGATE Upper Gate Sink Impedance VBOOT = 12V, IUGATE = 0.1A - 1.6 2.4 Ω RLGATE Lower Gate Source Impedance VCC = 12V, ILGATE = 0.1A - 1.3 1.95 Ω RLGATE Lower Gate Sink Impedance VCC = 12V, ILGATE = 0.1A - 1.25 1.88 Ω - 20 - ns 0.27 0.29 0.31 V 45 50 55 % TD Dead Time PROTECTIONS VOCP Over-Current Reference Voltage TA =-20~70°C VUVP Under-Voltage Threshold Trip Point Percent of VREF SOFT-START TSS Soft-Start Interval 1 1.7 2.6 ms Tdelay Delay Time (Note 2) 1.1 1.6 2.1 ms Note 2: Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 4 www.anpec.com.tw APW7065C Typical Operating Characteristics Switching Frequency vs. Junction Temperature Reference Voltage vs. Junction Temperature 0.804 310 0.802 Reference Voltage(V) Switching Frequency(KHz) VCC=12V VCC=12V 305 300 295 290 285 280 275 -40 0.8 0.798 0.796 0.794 0.792 -20 0 20 40 60 80 -40 100 120 -20 0 20 40 60 80 100 120 Junction Temperature (°C ) Junction Temperature (°C ) Operating Waveforms Power Off Power On V CC=12V, V IN=12V V CC=12V, V IN=12V V OUT =1.2V, L=1µH V OUT =1.2V, L=1µH CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH1: VCC (5V/div) CH2: VOUT (1V/div) CH3: VCOMP (1V/div) CH4: VUGATE (20Vdiv) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 CH1: VCC (5V/div) CH2: VOUT (1V/div) CH3: VCOMP (1V/div) CH4: VUGATE (20Vdiv) Time: 10ms/div 5 www.anpec.com.tw APW7065C Operating Waveforms Shutdown (EN=GND) EN (EN=VCC) V CC=12V, V IN=12V V OUT =1.2V, L=1µH V CC=12V, V IN=12V V OUT =1.2V, L=1µH CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH1: VCOMP (1V/div) CH2: VOUT (1V/div) CH3: VUGATE (20V/div) CH4: VLGATE (10Vdiv) Time: 2ms/div CH1: VCOMP (1V/div) CH2: VOUT (1V/div) CH3: VUGATE (20V/div) CH4: VLGATE (10Vdiv) Time: 50µs/div UGATE Rising UGATE Falling V CC=12V, V IN =12V V OUT =1.2V, L=1µH V CC=12V, V IN =12V V OUT =1.2V, L=1µH CH1 CH1 CH2 CH2 CH3 CH3 CH1: VUGATE (20V/div) CH2: VLGATE (5V/div) CH3: VPHASE (10V/div) Time: 50ns/div Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 CH1: VUGATE (20V/div) CH2: VLGATE (5V/div) CH3: VPHASE (10V/div) Time: 50ns/div 6 www.anpec.com.tw APW7065C Operating Waveforms (Cont.) Under Voltage Protection Load Transient Response V CC=12V, V IN=12V V OUT =1.2V, L=4.7µH V CC=12V, V IN =12V V OUT =1.2V, L=1µH CH1 CH1 0 CH2 10A CH3 0A CH2 CH4 CH1: VOUT (500mV/div) CH2: IOUT (5A/div) CH1: IL (10A/div) CH2: VOUT (1V/div) Time: 200µs/div CH3: VUGATE (20V/div) CH3: VLGATE (10V/div) Time: 100µs/div Over Current Protection Short Test V CC=12V, V IN=12V V OUT =1.2V, L=1µH CH1 V CC=12V, V IN=12V, V OUT =1.2V L_side:APM3023, Rds(ON)=17mΩ CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH1: IL (10A/div) CH2: VOUT (1V/div) CH1: IL (10A/div) CH2: VOUT (2V/div) CH3: VUGATE (20V/div) CH3: VLGATE (10V/div) Time: 2ms/div CH3: VUGATE (20V/div) Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 CH3: VLGATE (10V/div) Time: 5ms/div 7 www.anpec.com.tw APW7065C Function Description COMP (Pin 7) BOOT (Pin 1) This pin is the output of PWM error amplifier. It is used to A bootstrap circuit with a diode connected to VCC is used to create a voltage suitable to drive a logic-level N-channel MOSFET. set the compensation components. In addition, if the pin is pulled below 1.2V, it will disable the device. UGATE (Pin 2) PHASE (Pin 8) Connect this pin to the high-side N-channel MOSFET’s This pin is the return path for the upper gate driver. Con- gate. This pin provides gate drive for the high-side MOSFET. nect this pin to the upper MOSFET source. This pin is also used to monitor the voltage drop across the MOSFET GND (Pin 3) for over-current protection. The GND terminal provides return path for the IC’s bias current and the low-side MOSFET driver’s pull-low current. Connect the pin to the system ground via very low impedance layout on PCBs. LGATE (Pin 4) Connect this pin to the low-side N-channel MOSFET’s gate. This pin provides gate drive for the low-side MOSFET. VCC (Pin 5) Connect this pin to a 12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. It is recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. FB (Pin 6) This pin is the inverting input of the internal error amplifier. Connect this pin to the output (VOUT) of the converter via an external resistor divider for closed-loop operation. The output voltage set by the resistor divider is determined using the following formula : R1 VOUT = 0.8 × 1 + R2 where R1 is the resistor connected from VOUT to FB , and R2 is the resistor connected from FB to GND. The FB pin is also monitored for under voltage events. Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 8 www.anpec.com.tw APW7065C Block Diagram VCC GND BOOT PowerOn-Reset UGATE Sense Low Side Digital Soft Start O.C.P Comparator PHASE 0.29V U.V.P Comparator 50%VREF :2 Error Amp PWM Comparator Gate Control LGATE VREF Sawtooth Wave FOSC 300KHz Oscillator FB COMP Typical Application Circuit 1N4148 12V VIN (12V) 1µH 2.2R 1µF 1µF 5 VCC BOOT 1 UGATE 2 8 PHASE Q3 7 COMP 2N7002 ON/OFF LGATE 33nF 6 4 0.1µF 470µFx2 470µF Q1 APM2510 1µH VOUT (1.2V) Q2 APM2556 470µFx2 FB GND 8.2nF 3 2.7K 1K 2K Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 18R 68nF 9 www.anpec.com.tw APW7065C Function Description Power-On-Reset (POR) Voltage(V) The Power-On-Reset (POR) function of APW7065C con- FB tinually monitors the input supply voltage (VCC) and the COMP pin. The supply voltage (VCC) must exceed its rising POR threshold voltage. The POR function initiates soft-start operation after VCC and COMP voltages exceed 12.5mV their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V 8/Fosc power source must exceed the rising VCC threshold. The POR function inhibits operation at disabled status (VCOMP Time is less than 1.2V). With both input supplies above their POR thresholds, the device initiates a soft-start interval. Figure 2. The Controlled Stepped FB Voltage during Soft Start Soft-Start The APW7065C has a built-in digital soft-start to control Over-Current Protection the output voltage rise and limit the current surge during the start-up. In Figure 1, when VCC exceeds rising POR The over-current protection monitors the output current by using the voltage drop across the lower MOSFET’s RDS(ON) and this voltage drop will be compared with the threshold voltage, the delay time is counted from t1 to t2 and then soft-start will be enabled. During soft-start, an internal 0.29V reference voltage. If the voltage drop across the lower MOSFET’s R DS(ON) is larger than 0.29V, an internal ramp connected to the one of the positive inputs of the Gm amplifier rises up from 0V to 2V to replace the over-current condition is detected. The IC shuts off the converter and initiates a new soft-start process. After two reference voltage (0.8V) until the ramp voltage reaches the reference voltage. The soft-start interval is decided by over-current events are counted, the device turns off both high-side and low-side MOSFETs and the converter's the oscillator frequency (300KHz). The formulation is given by: output is latched to be floating. It requires a POR of VCC to Tsoft − start = t 3 − t 2 = 512/FOSC = 1.7ms restart. The threshold of the over current limit is given by: Figure 2. shows more details of the FB voltage ramp. The FB voltage soft-start ramp is formed with many small ILimit = steps of voltage. The voltage of one step is about 12.5mV in FB, and the period of one step is about 8/FOSC. This method 0.29 RDS( ON ) provides a controlled voltage rise and prevents the large For the over-current is never occurred in the normal operating load range; the variation of all parameters in the peak current to charge output capacitor. above equation should be determined. Voltage (V) - The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer’s datasheet. - The minimum Vocset should be used in the above equation. VCC - Note that the ILIMIT is the current flow through the lower MOSFET; ILIMIT must be greater than maximum output VOUT current and add the half of inductor ripple current. t1 t2 t3 Time Figure 1. Soft Start Interval Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 10 www.anpec.com.tw APW7065C Function Description (Cont.) Shutdown and Enable Pulling the COMP voltage to GND by an open drain transistor, as shown in Typical Application Circuit, shutdowns the APW7065C PWM controller. In shutdown mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively. Under Voltage Protection The FB pin is monitored during converter operation by the internal Under Voltage (UV) comparator. If the FB voltage drops below 50% of the reference voltage (50% of 0.8V = 0.4V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter’s output is latched to be floating. Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 11 www.anpec.com.tw APW7065C Application Information Output Voltage Selection Output Capacitor Selection The output voltage can be programmed with a resistive Higher capacitor value and lower ESR reduce the out- divider. Using 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of put ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by: for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the de- R V OUT = 0.8 × 1 + OUT R GND sired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make where ROUT is the resistor connected from VOUT to FB and RGND is the resistor connected from FB to GND. sure they have been done surge test by the manufactures. If in doubt, consult the capacitors manufacturer. Output Inductor Selection Input Capacitor Selection The inductor value determines the inductor ripple cur- The input capacitor is chosen based on the voltage rat- rent and affects the load transient response. Higher inductor value reduces the inductor’s ripple current and ing and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IRIPPLE = higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, VIN − VOUT V × OUT FS × L VIN where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the ca- ∆VOUT = IRIPPLE × ESR pacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1µF can be connected between the where FS is the switching frequency of the regulator. Although increase of the inductor value reduces the ripple current and voltage, a tradeoff will exist between the drain of upper MOSFET and the source of lower MOSFET. MOSFET Selection inductor’s ripple current and the regulator load transient response time. The selection of the N-channel power MOSFETs are determined by the RDS(ON), which reverses transfer capacitance (CRSS) and maximizes output current requirement. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. The maximum ripple current occurs at the maximum in- There are two components of loss in the MOSFETs: conduction loss and transition loss. For the upper and put voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum out- lower MOSFET, the losses are approximately given by the following: put current. Once the inductance value has been chosen, select an inductor that is capable of carrying the re- 2 PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS quired peak current without going into saturation. In some types of inductors, especially core that is made PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) of ferrite, the ripple current will increase abruptly when Where IOUT is the load current 2 it saturates. This will result in a larger output ripple voltage. TC is the temperature dependency of RDS(ON) FS is the switching frequency Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 12 www.anpec.com.tw APW7065C Application Information (Cont.) MOSFET Selection (Cont.) FLC -40dB/dec GAIN (dB) tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET, including an additional transition loss. The switching internal, tSW , is a function of the reverse FESR -20dB/dec transfer capacitance CRSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be Frequency(Hz) extracted from the “RDS(ON) vs. Temperature” curve of the power MOSFET. Figure 4. The LC Filter GAIN and Frequency PWM Compensation The PWM modulator is shown in Figure 5. The input is The output LC filter of a step down converter introduces a the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modu- double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A lator is given by: compensation network among COMP, FB and VOUT should be added. The compensation network is shown in Fig- GAINPWM = ure 6. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC ΔVOSC 1 + s × ESR × COUT s2 × L × COUT + s × ESR × COUT + 1 Driver PWM Comparator PHASE Output of Error Amplifier The poles and zero of this transfer functions are: FLC = VIN OSC filter is given by: GAINLC = VIN ∆VOSC 1 Driver 2 × π × L × COUT FESR = Figure 5. The PWM Modulator 1 2 × π × ESR × COUT The compensation network is shown in Figure 6. It provides a close loop transfer function with the highest The FLC is the double poles of the LC filter, and FESR is the zero crossover frequency and sufficient phase margin. zero introduced by the ESR of the output capacitor. The transfer function of error amplifier is given by: PHASE L OUTPUT GAINAMP COUT 1 1 s + × s + R2 C2 R1 R3 C3 × ( + ) × R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 × C1× C2 R3 × C3 ESR Figure 3. The Output LC Filter Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 1 1 // R2 + VCOMP sC1 sC2 = = 1 VOUT R1// R3 + sC3 13 www.anpec.com.tw APW7065C Application Information (Cont.) PWM Compensation (Cont.) 3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. The poles and zeros of the transfer function are: FZ1 = 0.75 X FLC 1 FZ1 = 2 × π × R2 × C2 Calculate the C2 by the equation: C2 = FZ2 1 = 2 × π × (R1+ R3) × C3 FP1 = FP2 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR 1 C1× C2 2 × π × R2 × C1 + C2 Calculate the C1 by the equation: C1 = 1 = 2 × π × R3 × C3 C3 R2 C2 LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the VOUT FB R1 C2 2 × π × R2 × C2 × FESR − 1 5.Set the second pole FP2 at the half of the switching frequency and also set the second zero F Z2 at the output C1 R3 1 2 × π × R2 × FLC × 0.75 compensation gain at FP2 with the capabilities of the error amplifier. VCOMP FP2 = 0.5 X FS VREF FZ2 = FLC Figure 6. Compensation Network Combine the two equations will get the following comThe closed loop gain of the converter can be written as: ponent calculations: GAINLC X GAINPWM X GAINAMP R3 = R1 FS −1 2 × FLC C3 = 1 π × R3 × FS Figure 7. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1.Choose a value for R1, usually between 1K and 5K. 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: R2 = ∆VOSC FO × × R1 VIN FLC Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 14 www.anpec.com.tw APW7065C Application Information (Cont.) keep traces to these nodes as short as possible. PWM Compensation (Cont.) - The traces from the gate drivers to the MOSFETs (UG, LG) should be short and wide. GAIN (dB) FZ1 FZ2 FP1 FP2 - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of Compensation Gain 20log (R2/R1) 20log (VIN/ΔVOSC) the node. - Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close their pins. (For example, place the FLC FESR Converter Gain decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk PWM & Filter Gain Frequency(Hz) capacitors are also placed near the drain). Figure 7. Converter Gain and Frequency - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close Layout Consideration In any high switching frequency converter, a correct lay- to the output capacitor GND and the lower MOSFET GND. out is important to ensure proper operation of the regulator. With power devices switching at 300kHz,the - The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is car- APW7065C rying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower VCC MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the BOOT switching interval. In general, using short, wide printed circuit traces should minimize interconnecting im- UGATE VIN L O A D PHASE pedances and the magnitude of voltage spike. In addtion, signal and power grounds are to be kept separate till VOUT LGATE combined using ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold lines Figure 8. Layout Guidelines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 15 www.anpec.com.tw APW7065C Package Information SOP-8 D E E1 SEE VIEW A h X 45 ° c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 3.80 4.00 0.150 0.157 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° E1 e 0.049 1.27 BSC 0.050 BSC 8° Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 16 www.anpec.com.tw APW7065C Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8 A 330.0± 2.00 P0 4.0±0.10 H T1 C d D W E1 F 12.4+2.00 13.0+0.50 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 -0.00 -0.20 P1 P2 D0 D1 T A0 B0 K0 1.5+0.10 0.6+0.00 8.0±0.10 2.0±0.05 6.40±0.20 5.20±0.20 2.10±0.20 1.5 MIN. -0.00 -0.40 (mm) Devices Per Unit Package Type SOP-8 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 Quantity 2500 17 www.anpec.com.tw APW7065C Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 18 www.anpec.com.tw APW7065C Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5°C ≥2.5 mm 225 +0/-5°C 3 Volume mm ≥350 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Mar., 2008 19 www.anpec.com.tw