HT49R30A-1/HT49C30-1/HT49C30L 8-Bit LCD Type MCU Features · Operating voltage: · On-chip crystal, RC and 32768Hz crystal oscillator 2.2V~5.5V for HT49R30A-1/HT49C30-1 1.2V~2.2V for HT49C30L · HALT function and wake-up feature reduce power consumption · 6 input lines · 4-level subroutine nesting · 8 bidirectional I/O lines · Bit manipulation instruction · Two external interrupt input · 14-bit table read instruction · One 8-bit programmable timer/event counter with · Up to 0.5ms instruction cycle with 8MHz system clock PFD (programmable frequency divider) function for HT49R30A-1/HT49C30-1 · LCD driver with 19´2, 19´3 or 18´4 segments · Up to 8ms instruction cycle with 500kHz system clock · 2K´14 program memory ROM for HT49C30L · 96´8 data memory RAM · 63 powerful instructions · Real Time Clock (RTC) · All instructions in 1 or 2 machine cycles · 8-bit prescaler for RTC · Low voltage reset/detector for HT49R30A-1/HT49C30-1 · Watchdog Timer · 48-pin SSOP package · Buzzer output General Description devices are also suitable for use in multiple LCD low power applications such as scales, leisure products, high-level household appliances, hand held LCD products and batteries operated systems in particular. The HT49C30-1 and the HT49C30L are 8-bit high perf o rm a n c e s i n g l e c hi p m i c r o c ont r o l l e r s. T h e HT49R30A-1 is the OTP version of the HT49C30-1. Its single cycle instruction and two-stage pipeline architecture make it suitable for high speed applications. The Rev. 1.10 1 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Block Diagram In te rru p t C ir c u it P ro g ra m M e m o ry P ro g ra m C o u n te r IN T C In s tr u c tio n R e g is te r M M P M T M R C T M R S T A C K X fS U R T C X D A T A M e m o ry M W D T U Y S /4 R T C X O S C O S C 3 O S C 4 W D T O S C M U X In s tr u c tio n D e c o d e r T im in g G e n e r a tio n P O R T B S T A T U S A L U S S P O R T A A C C C 1 D P A P A P A P A P A P A L C D M e m o ry C 3 P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R P B 3 ~ P B 5 P B S h ifte r B P O S R E V D V S O S fS Y S /4 fS Y S R T C O u t P B 2 /T M R P F D T im e B a s e O S C 2 O S C 4 U L C D D R IV E R H A L T 0 /B Z 1 /B Z 2 3 /P F D 4 ~ P A 7 E N /D IS L V D /L V R C O M 0 ~ C O M 2 Rev. 1.10 C O M 3 / S E G 1 8 S E G 0 ~ S E G 1 7 2 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Pin Assignment R E S P A 0 /B Z 1 4 8 P A 1 /B Z 2 4 7 O S C 1 P A 2 3 4 6 O S C 2 P A 3 /P F D 4 4 5 V D D P A 4 5 4 4 O S C 3 P A 5 6 4 3 O S C 4 P A 6 7 4 2 S E G 0 P A 7 8 4 1 S E G 1 P B 0 /IN T 0 9 4 0 S E G 2 P B 1 /IN T 1 1 0 3 9 S E G 3 P B 2 /T M R 1 1 3 8 S E G 4 P B 3 1 2 3 7 S E G 5 P B 4 1 3 3 6 S E G 6 P B 5 1 4 3 5 S E G 7 V S S 1 5 3 4 S E G 8 V L C D 1 6 3 3 S E G 9 V 1 1 7 3 2 S E G 1 0 V 2 1 8 3 1 S E G 1 1 C 1 1 9 3 0 S E G 1 2 C 2 2 0 2 9 S E G 1 3 C O M 0 2 1 2 8 S E G 1 4 C O M 1 2 2 2 7 S E G 1 5 C O M 2 2 3 2 6 S E G 1 6 S E G 1 8 /C O M 3 2 4 2 5 S E G 1 7 H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 /H T 4 9 C 3 0 L 4 8 S S O P -A Pad Assignment HT49C30-1 R E S 4 5 4 4 4 5 4 3 4 2 4 1 4 0 3 9 (0 , 0 ) 6 IN T 1 /P B 1 T M R /P B 2 7 P B 3 8 P B 4 9 P B 5 1 0 3 8 S E G 0 3 7 S E G 1 3 6 S E G 2 3 5 S E G 3 3 4 S E G 4 3 3 S E G 5 3 2 S E G 6 3 1 S E G 7 3 0 S E G 8 2 9 S E G 9 S E G 1 0 S E G 1 1 V S S 1 1 2 8 V L C D 1 2 2 7 C 2 C O M 0 C O M 1 2 1 2 2 2 3 2 4 2 5 2 6 S E G 1 2 C 1 2 0 S E G 1 3 V 2 1 9 S E G 1 4 1 8 S E G 1 5 1 7 S E G 1 6 1 6 S E G 1 7 1 5 S E G 1 8 /C O M 3 1 4 C O M 2 1 3 V 1 Rev. 1.10 T E S T 3 P A 7 IN T 0 /P B 0 4 8 T E S T 2 3 5 0 T E S T 1 P A 6 2 O S C 4 B Z /P A 0 4 6 O S C 3 B Z /P A 1 4 7 V D D P A 2 4 9 O S C 2 P F D /P A 3 5 1 O S C 1 P A 5 P A 4 1 3 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L HT49C30L 4 4 4 3 4 2 4 1 O S C 4 R E S 4 5 V D D B Z /P A 0 4 6 O S C 3 B Z /P A 1 4 7 O S C 2 P A 2 4 8 O S C 1 P A 4 P F D /P A 3 P A 5 1 4 0 3 9 3 8 2 P A 6 P A 7 3 IN T 0 /P B 0 4 (0 ,0 ) 3 7 S E G 0 3 6 S E G 1 3 5 S E G 2 3 4 S E G 3 3 3 S E G 4 3 2 S E G 5 IN T 1 /P B 1 5 T M R /P B 2 6 P B 3 7 3 1 S E G 6 P B 4 8 3 0 S E G 7 P B 5 9 2 9 S E G 8 V S S 1 0 2 8 S E G 9 V L C D 1 1 2 7 S E G 1 0 2 6 S E G 1 1 2 2 2 3 2 4 2 5 S E G 1 2 2 1 S E G 1 4 2 0 S E G 1 3 C 2 1 9 S E G 1 6 C 1 1 8 S E G 1 5 V 2 1 7 C O M 3 /S E G 1 8 V 1 1 6 S E G 1 7 1 5 C O M 2 1 4 C O M 1 1 3 C O M 0 1 2 * The IC substrate should be connected to VSS in the PCB layout artwork. Pad Description Pad Name I/O Options Description I/O Wake-up Pull-high or None CMOS or NMOS PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. Each bit on port can be configured as a wake-up input by options. PA0~PA3 can be configured as a CMOS output or NMOS input/output with or without pull-high resistor by options. PA4~PA7 are always pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by options. PA3 can be set as an I/O pin or as a PFD output also by options. I ¾ PB0~PB5 constitute a 6-bit Schmitt trigger input port. Each bit on port are with pull-high resistor. Of the six bits, PB0 and PB1 can be set as input pins or as external interrupt control pins (INT0) and (INT1) respectively, by software application. PB2 can be set as an input pin or as a timer/event counter input pin TMR also by software application. ¾ ¾ Negative power supply, ground VLCD I ¾ LCD power supply for HT49R30A-1/HT49C30-1. Voltage pump for HT49C30L. V2 I ¾ Voltage pump for HT49R30A-1/HT49C30-1. LCD power supply for HT49C30L. V1,C1,C2 I ¾ Voltage pump SEG18/COM3 COM2~COM0 1/2 or 1/3 or 1/4 SEG18 can be set as a segment or as a common output driver for LCD panel O Duty by options. COM2~COM0 are outputs for LCD panel plate. SEG17~SEG0 O PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/INT0 PB1/INT1 PB2/TMR PB3~PB5 VSS Rev. 1.10 ¾ LCD driver outputs for LCD panel segments 4 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Pad Name I/O OSC4 OSC3 O I VDD ¾ OSC2 OSC1 O I RES I Options Description Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz RTC or crystal oscillator for timing purposes or to a system clock source (depending System Clock on the options). ¾ Positive power supply OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output Crystal or RC terminal for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be floating. ¾ Schmitt trigger reset input, active low Absolute Maximum Ratings Supply Voltage..................................VSS-0.3V to 5.5V* Supply Voltage ................................VSS-0.3V to 2.2V** Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature ...........................-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ²*² For HT49R30A-1/HT49C30-1 ²**² For HT49C30L D.C. Characteristics VDD=1.5V for HT49C30L, VDD=3V & VDD=5V for HT49R30A-1 and HT49C30-1 Symbol VDD Parameter Operating Voltage Test Conditions Min. Typ. Max. Unit for HT49C30L 1.2 ¾ 2.2 V LVR disable (for HT49R30A-1/HT49C30-1) 2.2 ¾ 5.5 V ¾ 60 100 mA ¾ 1 2 mA ¾ 3 5 mA ¾ 50 100 mA ¾ 1 2 mA 5V ¾ 3 5 mA 1.5V ¾ 2.5 4 mA ¾ 0.3 0.6 mA ¾ 2 4 mA ¾ 0.1 0.5 mA ¾ ¾ 1 mA ¾ ¾ 2 mA Conditions VDD ¾ 1.5V No load, fSYS=455kHz IDD1 Operating Current (Crystal OSC) 3V No load, fSYS=4MHz 5V 1.5V No load, fSYS=400kHz IDD2 IDD3 Operating Current (RC OSC) Operating Current (fSYS=32768Hz) 3V 3V No load, fSYS=4MHz No load 5V 1.5V ISTB1 Standby Current (*fS=T1) 3V No load, system HALT, LCD off at HALT 5V Rev. 1.10 Ta=25°C 5 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Symbol Parameter Test Conditions Min. Typ. Max. Unit ¾ 1 2 mA ¾ 2.5 5 mA ¾ 6 10 mA ¾ 0.5 1 mA ¾ 2 5 mA ¾ 6 10 mA ¾ 17 30 mA ¾ 34 60 mA ¾ 13 25 mA ¾ 28 50 mA ¾ 14 25 mA ¾ 26 50 mA ¾ 10 20 mA ¾ 19 40 mA 0 ¾ 0.3VDD V 0 ¾ 0.3VDD V 5V 0 ¾ 0.3VDD V 1.5V 0.7VDD ¾ VDD V 0.7VDD ¾ VDD V 5V 0.7VDD ¾ VDD V 1.5V 0 ¾ 0.4VDD V 0 ¾ 0.4VDD V 5V 0 ¾ 0.4VDD V 3V 0.9VDD ¾ VDD V 0.9VDD ¾ VDD V 5V 0.9VDD ¾ VDD V 1.5V 0.4 0.8 ¾ mA 6 12 ¾ mA 5V 10 25 ¾ mA 1.5V -0.3 -0.6 ¾ mA -2 -4 ¾ mA -5 -8 ¾ mA 210 420 ¾ mA 350 700 ¾ mA -80 -160 ¾ mA -180 -360 ¾ mA Conditions VDD 1.5V ISTB2 Standby Current (*fS=32.768kHz OSC) 3V No load, system HALT, LCD on at HALT, C type 5V 1.5V ISTB3 Standby Current (*fS=WDT RC OSC) 3V No load, system HALT LCD on at HALT, C type 5V ISTB4 ISTB5 ISTB6 ISTB7 Standby Current (*fS=32.768kHz OSC) 3V Standby Current (*fS=32.768kHz OSC) 3V Standby Current (*fS=WDT RC OSC) 3V Standby Current (*fS=WDT RC OSC) 3V 5V 5V 5V 5V No load, system HALT, LCD on at HALT, R type, 1/2 bias No load, system HALT, LCD on at HALT, R type, 1/3 bias No load, system HALT, LCD on at HALT, R type, 1/2 bias No load, system HALT, LCD on at HALT, R type, 1/3 bias 1.5V VIL1 VIH1 VIL2 VIH2 IOL1 IOH1 Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) I/O Port Sink Current I/O Port Source Current ¾ 3V ¾ 3V ¾ 3V ¾ 1.5V 3V 3V VOL=0.1VDD VOH=0.9VDD 5V IOL2 IOH2 Rev. 1.10 LCD Comment and Segment Current LCD Comment and Segment Current 3V VOL=0.1VDD 5V 3V VOH=0.9VDD 5V 6 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Symbol Parameter Test Conditions 1.5V Pull-high Resistance of I/O 3V Ports and INT0, INT1 5V RPH VLVR Low Voltage Reset Voltage ¾ VLVD Low Voltage Detector Voltage ¾ Note: Conditions VDD ¾ ¾ Min. Typ. Max. Unit 75 150 300 kW 40 60 80 kW 10 30 50 kW 2.7 3.2 3.6 V 3.0 3.3 3.6 V tSYS=1/fSYS ²*fS² please refer to the clock option of WDT A.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions 1.5V fSYS1 fSYS2 System Clock (Crystal OSC) System Clock (RC OSC) ¾ 3V Min. Typ. Max. Unit 400 ¾ 500 kHz 4000 kHz 400 5V 400 ¾ 8000 kHz 1.5V 400 ¾ 500 kHz 400 ¾ 4000 kHz 400 ¾ 8000 kHz ¾ 3V 5V fSYS3 System Clock (32768Hz Crystal OSC) ¾ ¾ ¾ 32768 ¾ Hz fRTCOSC RTC Frequency ¾ ¾ ¾ 32768 ¾ Hz 0 ¾ 500 kHz 0 ¾ 4000 kHz 5V 0 ¾ 8000 kHz 1.5V 35 70 140 ms 45 90 180 ms 35 65 130 ms For HT49C30L 10 ¾ ¾ ms For HT49R30A-1/HT49C30-1 1 ¾ ¾ ms Wake-up from HALT ¾ 1024 ¾ tSYS 35 70 140 ms 45 90 180 ms 35 70 140 ms For HT49C30L 10 ¾ ¾ ms For HT49R30A-1/HT49C30-1 1 ¾ ¾ ms 1.5V fTIMER Timer I/P Frequency tWDTOSC Watchdog Oscillator ¾ 3V ¾ 3V 5V tRES tSST External Reset Low Pulse Width System Start-up Timer Period ¾ ¾ 1.5V tOPD Option Load Time During Reset ¾ 3V 5V tINT Interrupt Pulse Width ¾ Note: tSYS=1/fSYS Rev. 1.10 7 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Functional Description Execution flow After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code. The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed with the next instruction. Program counter - PC The program counter (PC) is of 11 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 2048 addresses. S y s te m C lo c k T 1 T 2 T 3 T 4 The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 O S C 2 ( R C o n ly ) P C P C P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution flow Mode Program Counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 0 1 0 0 External Interrupt 1 0 0 0 0 0 0 0 1 0 0 0 Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 1 0 0 Time Base Interrupt 0 0 0 0 0 0 1 0 0 0 0 RTC Interrupt 0 0 0 0 0 0 1 0 1 0 0 Skip PC+2 Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return From Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program counter Note: *10~*0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits Rev. 1.10 @7~@0: PCL bits 8 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L · Location 00CH When a control transfer takes place, an additional dummy cycle is required. Location 00CH is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. Program memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048´14 bits which are addressed by the PC and table pointer. · Location 010H Location 010H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 010H. Certain locations in the ROM are reserved for special usage: · Location 014H · Location 000H Location 014H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H. Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location. · Location 004H · Table location Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H. Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining 2 bit is read as ²0². The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the user¢s requirements. · Location 008H Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H. 0 0 0 H D e v ic e in itia liz a tio n p r o g r a m 0 0 4 H E x te r n a l in te r r u p t 0 s u b r o u tin e 0 0 8 H 0 0 C H E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e 0 1 0 H T im e B a s e In te r r u p t 0 1 4 H P ro g ra m R O M R T C In te rru p t Stack register - STACK n 0 0 H The stack register is a special part of the memory used to save the contents of the PC. The stack is organized into 4 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a commencement of a subroutine call or an interrupt acknowledgment, the contents of the PC is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is L o o k - u p ta b le ( 2 5 6 w o r d s ) n F F H L o o k - u p ta b le ( 2 5 6 w o r d s ) 7 F F H 1 4 b its N o te : n ra n g e s fro m 0 to 7 Program memory Instruction(s) Table Location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table location Note: *10~*0: Table location bits P10~P8: Current program counter bits @7~@0: Table pointer bits Rev. 1.10 9 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent four return addresses are stored). In d ir e c t A d d r e s s in g R e g is te r 0 0 2 H M P 0 In d ir e c t A d d r e s s in g R e g is te r 1 0 3 H M P 1 0 4 H B P A C C P C L 0 5 H 0 6 H 0 7 H 0 8 H T B L P T B L H 0 9 H R T C C 0 A H S T A T U S 0 B H IN T C 0 S p e c ia l P u r p o s e D A T A M E M O R Y 0 C H Data memory - RAM 0 D H The data memory (RAM) is designed with 113´8 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. 0 E H T M R T M R C 0 F H 1 0 H 1 1 H 1 2 H P A 1 3 H Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an A c c u m ul a t o r ( A C C ; 05H ) , a P r o g r am co u n t e r lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a timer/event counter (TMR;0DH), a timer/event counter control register (TMRC;0EH), I/O registers (PA;12H, PB;14H), and Interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 20H to 7FH, is used for data and control information under instruction commands. 1 4 H P B 1 5 H 1 6 H 1 7 H 1 8 H : U n u s e d . 1 9 H 1 A H R e a d a s "0 " 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H IN T C 1 G e n e ra l P u rp o s e D A T A M E M O R Y (9 6 B y te s ) 7 F H The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by ²SET [m].i² and ²CLR [m].i² They are also indirectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H). RAM mapping while MP1 can be applied to data memory and LCD display memory. Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Indirect addressing register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions: The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 (7-bit) and MP1 (7-bit), used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, Rev. 1.10 0 0 H 0 1 H · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ etc.) 10 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. The ALU not only saves the results of a data operation but also changes the status register. Status register - STATUS The status register (0AH) is of 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PD), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PD flags. Operations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the PC onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. External interrupts are triggered by a high to low transition of INT0 or INT1, and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts. Interrupts The device provides two external interrupts, an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Labels The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is Bits Function C 0 C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC 1 AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z 2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV 3 OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD 4 PD is cleared by either a system power-up or executing the ²CLR WDT² instruction. PD is set by executing the ²HALT² instruction. TO 5 TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. ¾ 6 Unused bit, read as ²0² ¾ 7 Unused bit, read as ²0² Status register Rev. 1.10 11 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Register INTC0 (0BH) INTC1 (1EH) Bit No. Label Function 0 EMI Control the master (global) interrupt (1=enabled; 0=disabled) 1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled) 2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled) 3 ETI Control the timer/event counter interrupt (1=enabled; 0=disabled) 4 EIF0 External interrupt 0 request flag (1=active; 0=inactive) 5 EIF1 External interrupt 1 request flag (1=active; 0=inactive) 6 TF Internal timer/event counter request flag (1=active; 0=inactive) 7 ¾ Unused bit, read as ²0² 0 ETBI Control the time base interrupt (1=enabled; 0:disabled) Control the real time clock interrupt (1=enabled; 0:disabled) 1 ERTI 2, 3 ¾ 4 TBF 5 RTF 6, 7 ¾ Unused bit, read as ²0² Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read as ²0² INTC register priorities in the following table apply. These can be masked by resetting the EMI bit. not full, and the TF bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (TF) is reset, and the EMI bit is cleared to disable further interrupts. No. The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 4 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 10H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts. Priority Vector a External interrupt 0 1 04H b External interrupt 1 2 08H c Timer/event counter overflow 3 0CH d Time base interrupt 4 10H e Real time clock interrupt 5 14H The timer/event counter interrupt request flag (TF), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable timer/event counter interrupt bit (ETI), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ETI, ETBI, and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 5 of INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the Rev. 1.10 Interrupt Source 12 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L It is recommended that a program not use the ²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. At this time, if only one stack is left, and enabling the interrupt is not well controlled, operation of the ²call² in the interrupt subroutine may damage the original control sequence. ternal capacitors in OSC1 and OSC2 are required. There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to oscillate quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. Oscillator configuration The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 78ms. The WDT oscillator can be disabled by options to conserve power. The device provides three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signal to conserve power. The 32768Hz crystal oscillator (system oscillator) still runs at HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. Since the (used as system oscillator or oscillator) is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the HALT mode. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 24kW to 1MW for HT49R30A-1/HT49C30-1 and from 560kW to 1MW for HT49C30L. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. The WDT time-out period is fS/215 ~ fS/216. If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the ²HALT² instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by an external logic. When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can stop the system clock. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two ex- The WDT overflow under normal operation initializes a ²chip reset² and sets the status bit ²TO². In the HALT mode, the overflow initializes a ²warm reset², and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., V O S C 3 O S C 4 3 2 7 6 8 H z C r y s ta l/ R T C O s c illa to r D D 4 7 0 p F O S C 1 V O S C 2 C r y s ta l O s c illa to r fS Y S /4 O S C 1 D D O S C 2 R C O s c illa to r System oscillator Rev. 1.10 13 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Time base external reset (a low level to RES), software instruction, and a ²HALT² instruction. There are two types of software instructions; ²CLR WDT² and the other set - ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one type of instruction can be active at a time depending on the options - ²CLR WDT² times selection option . If the ²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the ²CLR WDT² instruction clears the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from /212 to fS/215 selected by options. If time base time-out occurs, the related interrupt request flag (TBF; bit 4 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 10H occurs. Real time clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The real time clock time-out signal also can be applied to be a clock source of timer/event counter for getting a longer time-out period. Multi-function timer The device provides a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of a 8-stage divider and an 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e.., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver circuits, and a selectable frequency signal (ranges from fS/22 to fS/29) for the buzzer output by options. It is recommended to select a near 4kHz signal to LCD driver circuits for proper display. S y s te m C lo c k /4 R T C O S C 3 2 7 6 8 H z O p tio n S e le c t fS D iv id e r D iv id e r C K W D T 1 2 k H z O S C T R C K T R T im e - o u t R e s e t fS /2 1 5 ~ fS /2 1 6 W D T C le a r Watchdog Timer fs D iv id e r P r e s c a le r O p tio n O p tio n T im e B a s e In te r r u p t fS /2 12~ fS /2 15 L C D D r iv e r ( fS /2 2 ~ fS /2 8 ) B u z z e r (fS /2 2~ fS /2 9) Time base fS D iv id e r P r e s c a le r R T 2 R T 1 R T 0 8 to 1 M u x . fS /2 8~ fS /2 15 R T C In te rru p t Real time clock Rev. 1.10 14 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L RT2 RT1 RT0 RTC Clock Divided Factor 0 0 0 28* 0 0 1 29* 0 1 0 210* 0 1 1 211* 1 0 0 212 1 0 1 213 1 1 0 214 1 1 1 215 If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the Wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Note: ²*² not recommended for use Reset Power down operation - HALT There are three ways in which reset may occur. · RES is reset during normal operation The HALT mode is initialized by the ²HALT² instruction and results in the following. · RES is reset during HALT · WDT time-out is reset during normal operation · The system oscillator turns off but the WDT or RTC The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm reset² that resets only the PC and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition² once the reset conditions are met. Examining the PD and TO flags, the program can distinguish between different ²chip resets². oscillator keeps running (if the WDT oscillator or the real time clock is selected). · The contents of the on-chip RAM and of the registers remain unchanged. · The WDT is cleared and start recounting (if the WDT clock source is from the WDT oscillator or the real time clock oscillator). · All I/O ports maintain their original status. V · The PD flag is set but the TO flag is cleared. D D · LCD driver is still running (if the WDT OSC or RTC OSC is selected). The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a ²warm reset². After examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared by system power-up or by executing the ²CLR WDT² instruction, and is set by executing the ²HALT² instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the PC (Program Counter) and SP, and leaves the others at their original state. R E S Reset circuit TO PD RESET Conditions 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES Wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT Wake-up HALT The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. Note: ²u² stands for ²unchanged² When an interrupt request flag is set before entering the ²HALT² status, the system cannot be awaken using that interrupt. An extra option load time delay is added during reset and power on. Rev. 1.10 To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state. Awaking from the HALT state, the SST delay is added. 15 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L The functional unit chip reset status is shown below. PC 000H Interrupt Disabled Prescaler, Divider Cleared V D D R E S tO P D + tS S T S S T T im e - o u t C h ip R e s e t Cleared. After master reset, WDT, RTC, Time Base WDT starts counting Timer/Event Counter Off Input/output Ports Input mode SP Points to the top of the stack Reset timing chart H A L T W D T R e s e t T im e - o u t R e s e t E x te rn a l R E S O S C 1 W a rm W D T C o ld R e s e t S S T 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n Reset configuration The states of the registers are summarized below: Register Reset (Power On) WDT Time-out RES Reset (Norma Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* TMR xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMRC 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- Program Counter 0000H 0000H 0000H 0000H 0000H MP0 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu MP1 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu BP RTCC --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown Rev. 1.10 16 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L low if the TE bit is ²0²), it will start counting until the TMR returns to the original level and resets the TON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be made until the TON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting according not to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. Timer/Event Counter One timer/event counters is implemented in the device. It contains an 8-bit programmable count-up counter. The timer/event counter clock source may come from the system clock or system clock/4 or RTC time-out signal or external source. System clock source or system clock/4 is selected by options. Using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are two registers related to the timer/event counter, i.e., TMR ([0DH]) and TMRC ([0EH]). There are also two physical registers which are mapped to TMR location; writing TMR places the starting value in the timer/event counter preload register, while reading it yields the contents of the timer/event counter. TMRC is a timer/event counter control register used to define some options. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON is automatically cleared after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. The overflow of the Timer/Event Counter is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. No matter what the operation mode is, writing a 0 to ETI disables the related interrupt service. When the PFD function is selected, executing ²CLR [PA].3² instruction to enable PFD output and executing ²SET [PA].3² instruction to disable PFD output. The TN0 and TN1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external TMR pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal TMR, and the counting is based on the internal selected clock source. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (TF; bit 6 of INTC0). When the timer/event counter (reading TMR) is read, the clock is blocked to avoid errors. As this may results in a counting error, blocking of the clock should be taken into account by the programmer. In the pulse width measurement mode with the values of the TON and TE bits equal to one, after the TMR has received a transient from low to high (or high to S y s te m S y s te m C lo c k M O p tio n C lo c k /4 f IN U T X D a ta B u s R T C O u t T N 1 T N 0 T N 2 T M R T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d T E T N 1 T N 0 T O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l O v e r flo w to In te rru p t T im e r /E v e n t C o u n te r T Q P F D P A 3 D a ta C T R L Timer/Event Counter Rev. 1.10 17 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Label (TMR0C) Bits ¾ 0~2 Function Unused bit, read as ²0² TE 3 To define the TMR0 active edge of timer/event counter (0=active on low to high; 1=active on high to low) TON 4 To enable/disable timer counting (0=disabled; 1=enabled) TN2 5 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0=RTC outputs; 1= system clock or system clock/4) 6 7 To define the operating mode (TN1, TN0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TN0 TN1 TMRC register Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. When a PA line is used as an I/O line, the related PA line options should be configured as NMOS with or without pull-high resistor. Once a PA line is selected as a CMOS output, the I/O function cannot be used. It is strongly recommended to load a desired value into the TMR register first, then turn on the related timer/event counter for proper operation, because the initial value of TMR is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. The input state of a PA line is read from the related PA pad. When the PA is configured as NMOS with or without pull-high resistor, one should be careful when applying a read-modify-write instruction to PA. Since the read-modify-write will read the entire port state (pads state) firstly, execute the specified instruction and then write the result to the port data register. When the read operation is executed, a fault pad state (caused by the load effect or floating state) may be read. Errors will then occur. Input/output ports There are a 8-bit bidirectional input/output port, an 6-bit input port in the device, labeled PA, PB which are mapped to [12H], [14H] of the RAM, respectively. PA0~PA3 can be configured as CMOS (output) or NMOS (input/output) with or without pull-high resistor by options. PA4~PA7 are always pull-high and NMOS (input/output). If you choose NMOS (input), each bit on the port (PA0~PA7) can be configured as a wake-up input. PB can only be used for input operation. All the ports for the input operation (PA, PB), are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction ²MOV A, [m]² (m=12H or 14H). There are three function pins that share with the PA port: PA0/BZ, PA1/BZ and PA3/PFD. The BZ and BZ are buzzer driving output pair and the PFD is a programmable frequency divider output. If the user wants to use the BZ/BZ or PFD function, the related PA port should be set as a CMOS output. The buzzer output signals are controlled by PA0 and PA1 data registers and defined in the following table. For PA output operation, all data are latched and remain unchanged until the output latch is rewritten. When the PA structures are open drain NMOS type, it should be noted that, before reading data from the pads, a ²1² should be written to the related bits to disable the NMOS device. That is executing first the instruction ²SET [m].i² (i=0~7 for PA) to disable related NMOS device, and then ²MOV A, [m]² to get stable data. After chip reset, these input lines remain at the high level or are left floating (by options). Each bit of these output latches can be set or cleared by the ²MOV [m], A² (m=12H) instruction. Rev. 1.10 PA1 Data Register PA0 Data Register 0 0 PA0=BZ, PA1=BZ 1 0 PA0=BZ, PA1=0 X 1 PA0=0, PA1=0 PA0/PA1 Pad State Note: ²X² stands for ²unused² 18 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L The PFD output signal function is controlled by the PA3 data register and the timer/event counter state. The PFD output signal frequency is also dependent on the timer/event counter overflow period. The definitions of PFD control signal and PFD output frequency are listed in the following table. Timer Timer Preload Value PA3 Data Register PA3 Pad State PFD Frequency OFF X 0 U X OFF X 1 0 X ON N 0 PFD fINT/[2´(256-N)] ON N 1 0 X Note: ²X² stands for unused ²U² stands for unknown V V D a ta B u s W r ite D D D W e a k P u ll- u p C /N M O S O p tio n (P A 0 ~ P A 3 ) Q C K D D O p tio n (P A 0 ~ P A 3 ) V P A 0 ~ P A 7 Q S D D W e a k P u ll- u p C h ip R e s e t D a ta b u s P B 0 ~ P B 5 R e a d I/O R e a S y W a k (P A d I/O s te m e -u p o n ly ) O p tio n PA Input/output ports PB Input ports memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a ²1² or a ²0² is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device. LCD display memory The device provides an area of embedded data memory for LCD display. This area is located from 40H to 52H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as ²01H², any data written into 40H~52H will effect the LCD display. When the BP is cleared to ²00H², any data written into 40H~52H means to access the general purpose data C O M 4 0 H 4 1 H 4 2 H 4 3 H 5 0 5 1 5 2 B it 0 0 1 1 2 2 3 3 S E G M E N T 0 1 2 3 1 6 1 7 1 8 Display memory Rev. 1.10 19 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L is selected, no external capacitor is required. If the ²C² bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The bias voltage of LCD driver can be 1/2 bias or 1/3 bias by options. LCD driver output The output number of the device LCD driver can be 19´2 or 19´3 or 18´4 by options (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type of LCD driver can be ²R² type (for HT49R30A-1/HT49C30-1) or ²C² type. If the ²R² bias type D u r in g a r e s e t p u ls e V A C O M 0 ,C O M 1 ,C O M 2 A ll L C D V B V S S V A V B V S S d r iv e r o u tp u ts N o r m a l o p e r a tio n m o d e * * * C O M 0 C O M 1 C O M 2 * L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e lig h te d H A L T M o d e S S S S S S S S S S S V A C O M 0 ,C O M 1 ,C O M 2 * V B V S S V A V B V S S A ll L C D d r iv e r o u tp u ts N o te : V A V B V S V A V B V S V A V B V S V A V B V S V A V B V S V A V B V S V A V B V S V A V B V S V A V B V S V A V B V S V A V B V S " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d . V A = V L C D , V B = 1 /2 V L C D fo r H T 4 9 R 3 0 A -1 /H T 4 9 C 3 0 -1 V A = 2 V 2 , V B = V 2 , C ty p e fo r H T 4 9 C 3 0 L LCD driver output (1/3 duty, 1/2 bias, R/C type) Rev. 1.10 20 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L V A V B C O M 0 V C V S S V A V B C O M 1 V C V S S V A V B C O M 2 V C V S S V A V B C O M 3 V C V S S V A V B L C D s e g m e n ts O N C O M 2 s id e lig h te d V C V S S N o te : 1 /4 d u ty , 1 /3 b ia s , C ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D 1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D 1 /3 b ia s o n ly fo r H T 4 9 R 3 0 A - 1 /H T 4 9 C 3 0 - 1 LCD driver output The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT state, LVR is disabled. Low voltage reset/detector functions for HT49R30A-1/HT49C30-1 There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the options of LVD is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled. Register RTCC (09H) Bit No. Label Read/Write The definitions of RTCC register are listed in the following table. Reset Function 8 to 1 multiplexer control inputs to select the real clock prescaler output 0~2 RT0~RT2 R/W 111B 3 LVDC* R/W 0 LVD enable/disable (1/0) 4 QOSC R/W 0 32768Hz OSC quick start-up oscillating 0/1: quickly/slowly start 5 LVDO* R 0 LVD detection output (1/0) 1: low voltage detected 6~7 ¾ ¾ ¾ Unused bit, read as ²0² Note: ²*² For HT49R30A-1/HT49C30-1 Rev. 1.10 21 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system. Options OSC type selection. This option is to determine whether an RC or crystal or 32768Hz crystal oscillator is chosen as system clock. WDT Clock source selection. RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by options. CLR WDT times selection. This option defines how to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the WDT. ²Two times² means that if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, only then will the WDT be cleared. Time Base time-out period selection. The Time Base time-out period ranges from clock/212 to clock/215 ²Clock² means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: Clock/22~Clock/29. ²Clock² means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. Pull-high selection. This option is to decide whether the pull-high resistance is visible or not on the PA0~PA3. (PB and PA4~PA7 are always pull-high) PA0~PA3 CMOS or NMOS selection. The structure of PA0~PA3 4 bits can be selected as CMOS or NMOS individually. When the CMOS is selected, the related pins only can be used for output operations. When the NMOS is selected, the related pins can be used for input or output operations. (PA4~PA7 are always NMOS) Clock source selection of timer/event counter. There are two types of selection: system clock or system clock/4. I/O pins share with other functions selection. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are three types of selection: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin ²SEG18² will be set as a common output. LCD bias power supply selection. There are two types of selection: 1/2 bias or 1/3 bias for HT49R30A-1/HT49C30-1. LCD bias type selection. This option is to determine what kind of bias is selected, R type or C type for HT49R30A-1/HT49C30-1, C type for HT49C30L. LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. ²fS² means the clock source selection by options. LCD ON/OFF at HALT selection LVR selection. LVR has enable or disable options for HT49R30A-1/HT49C30-1 LVD selection. LVD has enable or disable options for HT49R30A-1/HT49C30-1 Rev. 1.10 22 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Application Circuits RC oscillator application V Crystal oscillator application D D C 1 4 7 0 p F O S C 1 O S C 1 2 4 k W ~ 1 M W fS Y S V S E G 0 ~ 1 7 C O M 0 ~ 3 D D L C D P A N E L S E G 0 ~ 1 7 C O M 0 ~ 3 C 2 L C D P A N E L O S C 2 /4 V L C D O S C 2 V L C D P o w e r S u p p ly V L C D V D D C 1 1 0 0 k W 0 .1 m F 0 .1 m F C 2 R E S R E S H T 4 9 R 3 0 A -1 / H T 4 9 C 3 0 -1 0 .1 m F C 1 1 0 0 k W C 2 1 0 k W D D L C D P o w e r S u p p ly V 1 H T 4 9 R 3 0 A -1 / H T 4 9 C 3 0 -1 1 0 k W 0 .1 m F 0 .1 m F V 2 V 2 0 .1 m F O S C 4 P A 0 ~ P A 7 IN T 0 IN T 0 P B 0 ~ P B 5 IN T 1 0 .1 m F 0 .1 m F O S C 3 O S C 3 O S C 4 V 1 P A 0 ~ P A 7 P B 0 ~ P B 5 IN T 1 T M R T M R 32768Hz crystal oscillator application O S C 1 O S C 2 V D D S E G 0 ~ 1 7 C O M 0 ~ 3 V L C D 1 0 0 k W C 1 R E S 1 0 k W L C D P A N E L L C D P o w e r S u p p ly 0 .1 m F C 2 H T 4 9 R 3 0 A -1 / H T 4 9 C 3 0 -1 0 .1 m F O S C 3 V 1 V 2 0 .1 m F 0 .1 m F O S C 4 IN T 0 P A 0 ~ P A 7 IN T 1 T M R Note: P B 0 ~ P B 5 C1=C2=300pF if fSYS < 1MHz, Otherwise, C1=C2=0 The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Rev. 1.10 23 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L RC oscillator application V Crystal oscillator application D D 2 0 0 p F 4 7 0 p F O S C 1 O S C 1 5 6 0 k W ~ 1 M W V S E G 0 ~ 1 7 C O M 0 ~ 3 D D L C D P A N E L S E G 0 ~ 1 7 C O M 0 ~ 3 2 0 0 p F O S C 2 V L C D V L C D fS Y S L C D P A N E L /4 V 0 .1 m F 0 .1 m F O S C 2 V D D C 1 1 0 0 k W 0 .1 m F C 1 1 0 0 k W C 2 0 .1 m F C 2 R E S R E S H T 4 9 C 3 0 L 0 .1 m F D D V 1 O S C 4 IN T 0 IN T 1 0 .1 m F V 2 O S C 3 V H T 4 9 C 3 0 L 0 .1 m F D D P A 0 ~ P A 7 O S C 3 V 2 O S C 4 P A 0 ~ P A 7 IN T 0 P B 0 ~ P B 5 V 1 V 0 .1 m F D D P B 0 ~ P B 5 IN T 1 T M R T M R 32768Hz crystal oscillator application O S C 1 O S C 2 V S E G 0 ~ 1 7 C O M 0 ~ 3 L C D P A N E L V L C D D D 0 .1 m F 1 0 0 k W C 1 R E S 1 0 k W 0 .1 m F C 2 H T 4 9 C 3 0 L 0 .1 m F V 1 0 .1 m F O S C 3 O S C 4 IN T 0 V 2 V D D P A 0 ~ P A 7 IN T 1 T M R Note: P B 0 ~ P B 5 The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Rev. 1.10 24 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Instruction Set Summary Description Instruction Cycle Flag Affected Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Rev. 1.10 25 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Instruction Cycle Flag Affected Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Mnemonic Description Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Ö: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. (3) (1) : (4) Rev. 1.10 and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged. 26 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADCM A,[m] Add the accumulator and carry to data memory Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADD A,[m] Add data memory to the accumulator Description The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. Operation ACC ¬ ACC+[m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADD A,x Add immediate data to the accumulator Description The contents of the accumulator and the specified data are added, leaving the result in the accumulator. Operation ACC ¬ ACC+x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö 27 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ AND A,x Logical AND immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ANDM A,[m] Logical AND data memory with the accumulator Description Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack ¬ PC+1 PC ¬ addr Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] ¬ 00H Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 28 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. Operation WDT ¬ 00H PD and TO ¬ 0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0 0 ¾ ¾ ¾ ¾ CLR WDT1 Preclear Watchdog Timer Description Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. Operation WDT ¬ 00H* PD and TO ¬ 0* Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0* 0* ¾ ¾ ¾ ¾ CLR WDT2 Preclear Watchdog Timer Description Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. Operation WDT ¬ 00H* PD and TO ¬ 0* Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0* 0* ¾ ¾ ¾ ¾ CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 29 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ DAA [m] Decimal-Adjust accumulator for addition Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. Operation If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö DEC [m] Decrement data memory Description Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]-1 Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 30 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. Operation PC ¬ PC+1 PD ¬ 1 TO ¬ 0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ 0 1 ¾ ¾ ¾ ¾ INC [m] Increment data memory Description Data in the specified data memory is incremented by 1 Operation [m] ¬ [m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ INCA [m] Increment data memory and place result in the accumulator Description Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ JMP addr Directly jump Description The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation PC ¬addr Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC ¬ [m] Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 31 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC ¬ x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory Description The contents of the accumulator are copied to the specified data memory (one of the data memories). Operation [m] ¬ACC Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation PC ¬ PC+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ OR A,x Logical OR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ORM A,[m] Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ¬ACC ²OR² [m] Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 32 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation PC ¬ Stack Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation PC ¬ Stack ACC ¬ x Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RETI Return from interrupt Description The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Operation PC ¬ Stack EMI ¬ 1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RL [m] Rotate data memory left Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ [m].7 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RLA [m] Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7 Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 33 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö RLCA [m] Rotate left through carry and place result in the accumulator Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö RR [m] Rotate data memory right Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RRA [m] Rotate right and place result in the accumulator Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ RRC [m] Rotate data memory right through carry Description The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö 34 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SBCM A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SDZ [m] Skip if decrement data memory is 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SDZA [m] Decrement data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1) Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 35 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] ¬ FFH Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SIZ [m] Skip if increment data memory is 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SIZA [m] Increment data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SNZ [m].i Skip if bit i of the data memory is not 0 Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i¹0 Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 36 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SUBM A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SUB A,x Subtract immediate data from the accumulator Description The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+x+1 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ Ö Ö Ö Ö SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. Operation [m].3~[m].0 « [m].7~[m].4 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SWAPA [m] Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0 Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 37 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SZA [m] Move data memory to ACC, skip if 0 Description The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ SZ [m].i Skip if bit i of the data memory is 0 Description If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i=0 Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ TABRDC [m] Move the ROM code (current page) to TBLH and data memory Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ TABRDL [m] Move the ROM code (last page) to TBLH and data memory Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 38 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Rev. 1.10 TC2 TC1 TO PD OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 39 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Package Information 48-pin SSOP (300mil) outline dimensions 4 8 2 5 A B 2 4 1 C C ' G H D E Symbol Rev. 1.10 a F Dimensions in mil Min. Nom. Max. A 395 ¾ 420 B 291 ¾ 299 C 8 ¾ 12 C¢ 613 ¾ 637 D 85 ¾ 99 E ¾ 25 ¾ F 4 ¾ 10 G 25 ¾ 35 H 4 ¾ 12 a 0° ¾ 8° 40 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Product Tape and Reel Specifications Reel dimensions , 6 ) + * 6 SSOP 48W Symbol Description Dimensions in mm A Reel Outer Diameter 330±1.0 B Reel Inner Diameter 100±0.1 C Spindle Hole Diameter 13.0+0.5 -0.2 D Key Slit Width 2.0±0.5 T1 Space Between Flange 32.2+0.3 -0.2 T2 Reel Thickness 38.2±0.2 Rev. 1.10 41 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Carrier tape dimensions P 0 D P 1 t E F W D 1 C B 0 K 1 P K 2 A 0 SSOP 48W Symbol Description Dimensions in mm W Carrier Tape Width 32.0±0.3 P Cavity Pitch 16.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 14.2±0.1 D Perforation Diameter 2.0 Min. D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 12.0±0.1 B0 Cavity Width 16.20±0.1 K1 Cavity Depth 2.4±0.1 K2 Cavity Depth 3.2±0.1 t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 0.35±0.05 25.5 42 September 25, 2002 HT49R30A-1/HT49C30-1/HT49C30L Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 43 September 25, 2002