TI ABT18646 With 18-bit transceiver and register Datasheet

SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
D
D
D
D
Member of the Texas Instruments
Widebus Family
Compatible With IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
Includes D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data
Two Boundary-Scan Cells Per I/O for
Greater Flexibility
D
SCOPE Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions, Optional INTEST, and
P1149.1A CLAMP and HIGHZ
– Parallel Signature Analysis at Inputs
With Masking Option
– Pseudorandom Pattern Generation From
Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
1A2
1A1
1OE
GND
1SAB
1CLKAB
TDO
V CC
TMS
1CLKBA
1SBA
1DIR
GND
1B1
1B2
1B3
PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
VCC
2A1
2A2
2A3
GND
2A4
2A5
2A6
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
1B4
1B5
1B6
GND
1B7
1B8
1B9
VCC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2A7
2A8
2A9
GND
2OE
2SAB
2CLKAB
TDI
VCC
TCK
2CLKBA
2SBA
GND
2DIR
2B9
2B8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
description
This scan test device with a 18-bit bus transceiver and register is a member of the Texas Instruments SCOPE
testability IC family. This device supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex
circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port
(TAP) interface.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and Widebus are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
description (continued)
In the normal mode, this device is an 18-bit bus transceiver and register that allows for multiplexed transmission
of data directly from the input bus or from the internal registers. It can be used either as two 9-bit transceivers
or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data
appearing at the device pins or to perform a self-test on the boundary test cells. Activating the TAP in the normal
mode does not affect the functional operation of the SCOPE bus transceivers and registers.
Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating both
buses.
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively. Figure 1 illustrates the four fundamental bus-management functions that can be
performed with the SN74ABT18646.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can
perform boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform
other testing functions, such as parallel signature analysis on data inputs and pseudorandom pattern generation
from data outputs. All testing and scan operations are synchronized to the TAP interface.
Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each
I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT
instruction is also included to ease the testing of memories and other circuits where a binary count addressing
scheme is useful.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C
LQFP – PM
Tray
SN74ABT18646PM
ABT18646
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
2
POST OFFICE BOX 655303
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SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
FUNCTION TABLE
(normal mode, each 9-bit section)
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1–A9
B1–B9
X
X
↑
X
X
X
Input
Unspecified†
X
X
X
↑
X
X
Unspecified†
Input
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
L
L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
Store A, B unspecified†
Store B, A unspecified†
L
L
X
X
X
H
Output
Input disabled
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
L
X
H
X
Input disabled
Output
Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
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3
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
OE
L
DIR
L
CLKAB CLKBA
X
X
SAB
X
BUS B
BUS A
BUS A
BUS B
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
SBA
L
OE
L
DIR
H
REAL-TIME TRANSFER
BUS B TO BUS A
DIR
X
X
X
CLKAB CLKBA
X
↑
X
↑
↑
↑
SAB
X
X
X
SAB
L
SBA
X
BUS B
BUS A
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
OE
L
L
DIR
L
H
CLKAB
X
L
CLKBA
X
X
SAB
X
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
4
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
BUS A
OE
X
X
H
CLKAB
X
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SBA
H
X
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
functional block diagram
1OE
1DIR
1CLKBA
Boundary-Scan Register
62
53
55
1SBA 54
59
1CLKAB
60
1SAB
C1
1D
1A1
51
63
C1
1D
1B1
1 of 9 Channels
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
21
30
27
28
23
22
C1
1D
2A1
40
10
C1
1D
2B1
1 of 9 Channels
Bypass Register
Boundary-Control
Register
VCC
TDI 24
VCC
TMS
TCK
Identification
Register
58
Instruction
Register
TDO
56
26
TAP
Controller
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5
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–32
mA
Low-level output current
64
mA
∆t/∆v
Input transition rise or fall rate
10
ns/V
High-level input voltage
2
V
0.8
Input voltage
0
V
V
V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
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SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 4)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VOL
VCC = 4.5 V,
VCC = 4.5 V,
IOH = –32 mA
IOL = 64 mA
II
5V
VCC = 5
5.5
V,
VI = VCC or GND
IIH
IIL
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC,
VI = GND,
IOZH‡
IOZL‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
Ioff
ICEX
IO§
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 5.5 V
VO = 5.5 V,
VCC = 5.5 V,
VO = 2.5 V
VOH
ICC
∆ICC#
Ci
Cio
MIN
TYP†
A or B ports
VCC = 5.5 V,
One input at 3.4 V,
VI = 2.5 V or 0.5 V,
VO = 2.5 V or 0.5 V,
UNIT
–1.2
V
2.5
V
2
0.55
±1
CLK, DIR, OE, S, TCK
±100
A or B ports
V
µA
TDI, TMS
10
µA
TDI, TMS
–150
µA
50
µA
Outputs high
–50
Outputs high
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
MAX
Outputs low
–50
µA
±100
µA
50
µA
–200
mA
5.5
38¶
mA
Outputs disabled
5
Other inputs at VCC or GND
2
Control inputs
A or B ports
Co
VO = 2.5 V or 0.5 V,
TDO
NOTE 4: Preliminary specifications based on SPICE analysis
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ If both A and B ports are low, ICCL is 76 mA.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
mA
3
pF
10
pF
8
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
MIN
fclock
tw
Clock frequency
CLKAB or CLKBA
Pulse duration
CLKAB or CLKBA high or low
tsu
th
Setup time
A before CLKAB↑ or B before CLKBA↑
Hold time
A after CLKAB↑ or B after CLKBA↑
MAX
UNIT
100
MHz
4
ns
4.5
ns
0
ns
NOTE 4: Preliminary specifications based on SPICE analysis
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7
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
MIN
fclock
tw
tsu
th
td
tr
Clock frequency
TCK
Pulse duration
TCK high or low
Setup time
UNIT
50
MHz
8
A, B, CLK, DIR, OE, or S before TCK↑
4.5
TDI before TCK↑
7.5
TMS before TCK↑
3
A or B after TCK↑
0.5
CLK, DIR, OE, or S after TCK↑
Hold time
MAX
ns
ns
0
ns
TDI after TCK↑
0.5
TMS after TCK↑
0.5
Delay time
Power up to TCK↑
50
ns
Rise time
VCC power up
1
µs
NOTE 4: Preliminary specifications based on SPICE analysis
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
CLKAB or CLKBA
A or B
B or A
CLKAB or CLKBA
B or A
SAB or SBA
B or A
DIR
B or A
OE
B or A
DIR
B or A
POST OFFICE BOX 655303
MAX
100
B or A
OE
tPLZ
NOTE 4: Preliminary specifications based on SPICE analysis
8
MIN
• DALLAS, TEXAS 75265
UNIT
MHz
2
5.4
2
6.6
2.5
8
2.5
7.4
2
7.5
2
8
2
8
3
9.1
2.5
8.6
3
9.3
3.5
11.1
3
8.8
3.5
10.5
2
8.5
ns
ns
ns
ns
ns
ns
ns
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
TCK
MAX
50
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
TDO
TCK↓
A or B
TCK↓
tPLZ
NOTE 4: Preliminary specifications based on SPICE analysis
POST OFFICE BOX 655303
MIN
TDO
• DALLAS, TEXAS 75265
UNIT
MHz
2.5
13.5
2.5
12.5
2
6.5
2
6.5
4.5
13.8
5
14.5
2
7
3
7.5
4
17
3
16
3
9
3
7.5
ns
ns
ns
ns
ns
ns
9
SN74ABT18646
SCAN TEST DEVICE
WITH 18-BIT TRANSCEIVER AND REGISTER
SCBS131A – AUGUST 1992 – REVISED JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
7V
500 Ω
From Output
Under Test
Open
S1
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
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PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ABT18646PM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74ABT18646PMG4
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
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1
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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