IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 OptiMOS®-T Power-Transistor Product Summary V DS 40 V R DS(on),max (SMD version) 4.5 mΩ ID 80 A Features • N-channel - Enhancement mode • Automotive AEC Q101 qualified PG-TO263-3-2 PG-TO262-3-1 PG-TO220-3-1 • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green package (RoHS compliant) • 100% Avalanche tested Type Package Marking IPB80N04S3-H4 PG-TO263-3-2 3N04H4 IPI80N04S3-H4 PG-TO262-3-1 3N04H4 IPP80N04S3-H4 PG-TO220-3-1 3N04H4 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions T C=25°C, V GS=10V T C=100 °C, V GS=10 V2) Value 80 Unit A 80 Pulsed drain current2) I D,pulse T C=25 °C 320 Avalanche energy, single pulse2) E AS I D=40 A 370 mJ Avalanche current, single pulse I AS - 80 A Gate source voltage V GS - ±20 V Power dissipation P tot T C=25 °C 115 W Operating and storage temperature T j, T stg - -55 ... +175 °C IEC climatic category; DIN IEC 68-1 - - 55/175/56 Rev. 1.0 page 1 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 Parameter Symbol Values Conditions Unit min. typ. max. Thermal characteristics2) Thermal resistance, junction - case R thJC - - - 1.3 Thermal resistance, junction ambient, leaded R thJA - - - 62 SMD version, device on PCB R thJA minimal footprint - - 62 6 cm2 cooling area3) - - 40 K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D= 1 mA 40 - - Gate threshold voltage V GS(th) V DS=V GS, I D=65 µA 2.1 3.0 4.0 Zero gate voltage drain current I DSS V DS=40 V, V GS=0 V, T j=25 °C - - 1 - - 100 V DS=40 V, V GS=0 V, T j=125 °C2) V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - - 100 nA Drain-source on-state resistance RDS(on) V GS=10 V, I D=80 A - 3.9 4.8 mΩ V GS=10 V, I D=80 A, SMD version - 3.6 4.5 Rev. 1.0 page 2 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 Parameter Symbol Values Conditions Unit min. typ. max. - 3000 3900 - 850 1100 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 130 200 Turn-on delay time t d(on) - 20 - Rise time tr - 12 - Turn-off delay time t d(off) - 30 - Fall time tf - 10 - Gate to source charge Q gs - 18 24 Gate to drain charge Q gd - 12 18 Gate charge total Qg - 46 60 Gate plateau voltage V plateau - 5.6 - V - - 80 A - - 320 V GS=0 V, V DS=25 V, f =1 MHz V DD=20 V, V GS=10 V, I D=80 A, R G=3.5 Ω pF ns Gate Charge Characteristics2) V DD=32 V, I D=80 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD V GS=0 V, I F=80 A, T j=25 °C - 0.95 1.3 V Reverse recovery time2) t rr V R=20 V, I F=I S, di F/dt =100 A/µs - 35 - ns Reverse recovery charge2) Q rr - 35 - nC T C=25 °C 1) Current is limited by bondwire; with an R thJC = 1.3K/W the chip is able to carry 119A at 25°C. 2) Defined by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.0 page 3 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 6 V I D = f(T C); V GS ≥ 6 V 120 100 100 80 80 I D [A] P tot [W] 60 60 40 40 20 20 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0; SMD Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 1 µs 10 µs 100 100 0.5 100 µs I D [A] Z thJC [K/W] 1 ms 0.1 10-1 0.05 0.01 10 10-2 10-3 1 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.0 single pulse page 4 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C; SMD R DS(on) = f(I D); T j = 25 °C; SMD parameter: V GS parameter: V GS 20 320 5.5 V 7V 280 18 10 V 16 240 6.5 V 14 160 R DS(on) [mΩ] I D [A] 200 6V 120 12 10 6V 8 5.5 V 80 6.5 V 6 7V 40 4 5V 10 V 2 0 0 2 4 6 0 8 20 40 60 80 100 120 140 180 I D [A] V DS [V] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 6V R DS(on) = f(T j); I D = 80 A; V GS = 10 V; SMD parameter: T j 360 -55 °C 7 25 °C 320 6 280 240 R DS(on) [mΩ] I D [A] 175 °C 200 160 5 4 120 80 3 40 0 2 3 4 5 6 7 8 V GS [V] Rev. 1.0 2 -60 -20 20 60 100 T j [°C] page 5 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 4 3.5 V GS(th) [V] 3 C [pF] Ciss 650µA 65µA 2.5 103 Coss 2 1.5 Crss 102 1 -60 -20 20 60 100 140 0 180 5 10 15 20 25 30 V DS [V] T j [°C] 11 Typical forward diode characteristicis 12 Typ. avalanche characteristics IF = f(VSD) I A S= f(t AV) parameter: T j parameter: T j(start) 100 103 25 °C 100 °C 150 °C I F [A] I AV [A] 102 175 °C 10 25 °C 1 10 100 1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 V SD [V] Rev. 1.0 1 10 100 1000 t AV [µs] page 6 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 13 Typical avalanche energy 14 Typ. drain-source breakdown voltage E AS = f(T j) V BR(DSS) = f(T j); I D = 1 mA parameter: I D 55 800 700 50 600 20 A V BR(DSS) [V] E AS [mJ] 500 400 300 45 40 40 A 200 35 80 A 100 30 0 25 75 125 -60 175 -20 T j [°C] 20 60 100 140 180 T j [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 80 A pulsed parameter: V DD 12 V GS 8V Qg 32 V 10 V GS [V] 8 6 V g s(th) 4 2 Q g (th) Q sw Q gs 0 0 10 20 30 40 Q gate Q gd 50 Q gate [nC] Rev. 1.0 page 7 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2008 All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.0 page 8 2008-08-01 IPB80N04S3-H4 IPI80N04S3-H4, IPP80N04S3-H4 Revision History Version Rev. 1.0 Date Changes page 9 2008-08-01