MSN6504D 650V(D-S) N-Channel Enhancement Mode Power MOS FET General Features ● VDS =650V,ID =4A RDS(ON) <2.5 Ω @ VGS=10V ● High density cell design for ultra low Rdson ● Fully characterized avalanche voltage and current Lead Free ● Good stability and uniformity with high EAS ● Excellent package for good heat dissipation ● Special process technology for high ESD capability Application ● Power switching application ● Hard switched and high frequency circuits ● Uninterruptible power supply Marking and pin assignment PIN Configuration Schematic diagram TO-252-2L top view Package Marking and Ordering Information Device Marking Device MSN6504D MSN6504D Device Package TO-252 Reel Size Tape width Quantity - - 2500PCS Absolute Maximum Ratings (TC=25℃unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS 650 V Gate-Source Voltage VGS ±30 V ID 4 A ID (100℃) 3.?2 A Pulsed Drain Current IDM 16 A Maximum Power Dissipation PD 50 W 0.45 W/℃ 260 mJ Drain Current-Continuous Drain Current-Continuous(TC=100℃) Derating factor Single pulse avalanche energy (Note 5) Operating Junction and Storage Temperature Range MORE Semiconductor Company Limited EAS TJ,TSTG http://www.moresemi.com -55 To 150 ℃ 1/5 MSN6504D Thermal Characteristic Thermal Resistance,Junction-to-Case(Note 2) RθJC ℃/W 2.6 Electrical Characteristics (TC=25℃unless otherwise noted) Parameter Symbol Condition Min Drain-Source Breakdown Voltage BVDSS VGS=0V ID=250μA 650 Zero Gate Voltage Drain Current IDSS VDS=650V,VGS=0V - Gate-Body Leakage Current IGSS VGS=±30V,VDS=0V - Gate Threshold Voltage VGS(th) VDS=VGS,ID=250μA 2 Drain-Source On-State Resistance RDS(ON) VGS=10V, ID=2.0A - VDS=40V,ID=2A Typ Max Unit - V - 10 μA - ±100 nA 4 V 2.1 2.5 Ω - 4.0 - S - 520 - PF - 70 - PF Crss - 8 - PF Turn-on Delay Time td(on) - 13 - nS Turn-on Rise Time tr VDD=325V,ID=4A,RL=25Ω - 45 - nS td(off) VGS=10V,RG=2.5Ω - 25 - nS - 35 - nS - 15 - nC - 3.4 - nC - 7.1 - nC 1.4 V Off Characteristics On Characteristics (Note 3) Forward Transconductance Dynamic Characteristics gFS (Note4) Input Capacitance Clss Output Capacitance Coss Reverse Transfer Capacitance Switching Characteristics VDS=25V,VGS=0V, F=1.0MHz (Note 4) Turn-Off Delay Time Turn-Off Fall Time tf Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd VDS =520V,I D=4A, VGS=10V Drain-Source Diode Characteristics Diode Forward Voltage (Note 3) VSD Diode Forward Current (Note 2) IS Reverse Recovery Time VGS=0V,IS=4.0A trr Reverse Recovery Charge Qrr Forward Turn-On Time ton TJ = 25°C, IF = 4.0A di/dt = 100A/μs (Note3) - - 4.0 A - 300 - nS 1.5 - μC - Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: 1. Repetitive Rating: Pulse width limited by maximum junction temperature. 2. Surface Mounted on FR4 Board, t ≤ 10 sec. 3. Pulse Test: Pulse Width ≤ 300μs, Duty Cycle ≤ 2%. 4. Guaranteed by design, not subject to production 5. EAS condition: j=25℃,VDD=50V,VG=10V,L=0.5mH,Rg=25Ω MORE Semiconductor Company Limited http://www.moresemi.com 2/5 MSN6504D Typical Electrical and Thermal Characteristics (Curves) 9 VGS=10,8,7V 5 ID, Drain Current (A) ID, Drain Current (A) 6 4 VGS=5V 3 2 1 0 0.0 5 15 10 20 25 TJ=125C 1 2 -55 C 3 4 5 6 Figure 1. Output Characteristics Figure 2. Transfer Characteristics RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) Ciss 600 400 Coss 200 Crss 0 5 10 15 20 25 3.0 2.5 ID=2A VGS=10V 2.0 1.5 1.0 0.5 0.0 -100 -50 0 50 100 150 200 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature( C) Figure 3. Capacitance Figure 4. On-Resistance Variation with Temperature VDS=VGS ID=250µA 1.1 1.0 0.9 0.8 0.7 0.6 -50 25 C 1.5 0 IS, Source-drain current (A) C, Capacitance (pF) VTH, Normalized Gate-Source Threshold Voltage 3 VGS, Gate-to-Source Voltage (V) 800 1.2 4.5 VDS, Drain-to-Source Voltage (V) 1000 1.3 6 30 1200 0 7.5 -25 0 25 50 75 100 125 150 VGS=0V 10 1 10 0 10-1 0.4 0.7 1.0 1.3 1.7 2.0 TJ, Junction Temperature( C) VSD, Body Diode Forward Voltage (V) Figure 5. Gate Threshold Variation with Temperature Figure 6. Body Diode Forward Voltage Variation with Source Current MORE Semiconductor Company Limited http://www.moresemi.com 3/5 10 VDS=480V ID=4A 10 8 ID, Drain Current (A) VGS, Gate to Source Voltage (V) MSN6504D 6 4 2 0 0 2 4 8 6 10 0 10 -1 10 10 1 RDS(ON)Limit 100ms 1ms 10ms DC TC=25 C TJ=175 C Single Pulse -2 10 0 10 1 10 2 10 Qg, Total Gate Charge (nC) VDS, Drain-Source Voltage (V) Figure 7. Gate Charge Figure 8. Maximum Safe Operating Area 3 VDD t on RL V IN D td(off) tf 90% 90% VOUT VGS RGEN toff tr td(on) VOUT 10% INVERTED 10% G 90% S VIN 50% 50% 10% PULSE WIDTH Figure 10. Switching Waveforms r(t),Normalized Effective Transient Thermal Impedance Figure 9. Switching Test Circuit 10 0 D=0.5 0.2 10 -1 PDM 0.1 t1 0.05 0.02 0.01 Single Pulse 10 -2 10 -5 t2 1. RθJA (t)=r (t) * RθJA 2. RθJA=See Datasheet 3. TJM-TA = P* RθJC (t) 4. Duty Cycle, D=t1/t2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 Square Wave Pulse Duration (sec) Figure 11. Normalized Thermal Transient Impedance Curve MORE Semiconductor Company Limited http://www.moresemi.com 4/5 MSN6504D TO-252 Package Information Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A 2.200 2.400 0.087 0.094 A1 0.000 0.127 0.000 0.005 b 0.660 0.860 0.026 0.034 c 0.460 0.580 0.018 0.023 D 6.500 6.700 0.256 0.264 D1 5.100 5.460 0.201 0.215 D2 4.830 TYP. 0.190 TYP. E 6.000 6.200 0.236 0.244 e 2.186 2.386 0.086 0.094 L 9.800 10.400 0.386 0.409 L1 L2 2.900 TYP. 1.400 L3 0.114 TYP. 1.700 0.055 1.600 TYP. 0.067 0.063 TYP. L4 0.600 1.000 0.024 0.039 Φ 1.100 1.300 0.043 0.051 θ 0° 8° 0° 8° h 0.000 0.300 0.000 0.012 V 5.350 TYP. MORE Semiconductor Company Limited 0.211 TYP. http://www.moresemi.com 5/5