To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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HD74HC78 Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) REJ03D0553-0200 (Previous ADE-205-425) Rev.2.00 Oct 06, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are independent of the clock and accomplished by a low logic level on the corresponding input. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Ordering Information Part Name Package Code (Previous Code) Package Type Package Abbreviation Taping Abbreviation (Quantity) HD74HC78FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP EL (2,000 pcs/reel) HD74HC78RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Outputs Preset Clear Clock J K Q Q L H X X X H L H L X X X L H L L X X X H*1 H*1 H H L L H H L H L H H H H L H L No change H H H H Toggle H H L X X No change H H H X X No change H H X X No change H: High level L: Low level X: Irrelevant Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go High simultaneously. Rev.2.00, Oct 06, 2005 page 1 of 6 HD74HC78 Pin Arrangement CK 1 1PR 2 1J 3 14 1K K CK J CLR PR Q 13 1Q 12 1Q Q VCC 4 CLR 5 11 GND K CK J CLR PR Q 10 2J Q 2PR 6 9 2Q 2K 7 8 2Q (Top view) Logic Diagram (1/2) To Other FF PR Q CLR J # CK CK K # CK CK CK # CK # CK CK CK CK CK To Other FF Rev.2.00, Oct 06, 2005 page 2 of 6 Q CK # CK HD74HC78 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input / Output voltage VCC Vin, Vout –0.5 to 7.0 –0.5 to VCC +0.5 V V IIK, IOK IO ±20 ±25 mA mA ICC or IGND PT ±50 500 mA mW Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Tstg –65 to +150 °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Symbol VCC Ratings 2 to 6 Unit V Input / Output voltage Operating temperature VIN, VOUT Ta 0 to VCC –40 to 85 V °C tr , tf 0 to 1000 0 to 500 ns Input rise / fall time Note: *1 0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Quiescent supply current Iin ICC Min Ta = 25°C Typ Max Ta = –40 to+85°C Unit Min Max 2.0 4.5 1.5 3.15 — — — — 1.5 3.15 — — 6.0 2.0 4.2 — — — — 0.5 4.2 — — 0.5 4.5 6.0 — — — — 1.35 1.8 — — 1.35 1.8 2.0 4.5 1.9 4.4 2.0 4.5 — — 1.9 4.4 — — 6.0 4.5 5.9 4.18 6.0 — — — 5.9 4.13 — — 6.0 2.0 5.68 — — 0.0 — 0.1 5.63 — — 0.1 4.5 6.0 — — 0.0 0.0 0.1 0.1 — — 0.1 0.1 4.5 6.0 — — — — 0.26 0.26 — — 0.33 0.33 6.0 6.0 — — — — ±0.1 2.0 — — ±1.0 20 Rev.2.00, Oct 06, 2005 page 3 of 6 Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA V IOH = –5.2 mA Vin = VIH or VIL IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC78 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25°C Item Maximum clock frequency Propagation delay time Pulse width Symbol VCC (V) fmax tPLH, tPHL tw Setup time tsu Hold time th Removal time Output rise/fall time Input capacitance trem tTLH, tTHL Cin Ta = –40 to +85°C 2.0 Min — Typ — Max 6 Min — Max 5 4.5 6.0 — — — — 30 35 — — 24 28 2.0 4.5 — — — 20 150 30 — — 190 38 6.0 2.0 — — — — 26 140 — — 33 175 4.5 6.0 — — 18 — 28 24 — — 35 30 2.0 4.5 — — — 18 140 28 — — 175 35 6.0 2.0 — 80 — — 24 — — 100 30 — 4.5 6.0 16 14 8 — — — 20 17 — — 2.0 4.5 100 20 — 2 — — 125 25 — — 6.0 2.0 17 5 — — — — 21 5 — — 4.5 6.0 5 5 –1 — — — 5 5 — — 2.0 4.5 100 20 — 0 — — 125 25 — — 6.0 2.0 17 — — — — 75 21 — — 95 4.5 6.0 — — 5 — 15 13 — — 19 16 — — 5 10 — 10 Unit Test Conditions MHz ns Clock to Q or Q ns Clear to Q or Q ns Preset to Q or Q ns Preset, Clear, Clock ns J or K to Clock ns Clock to J or K ns Preset or Clear to Clock ns pF Test Circuit VCC VCC Pulse generator Zout = 50 Ω Input Pulse generator Zout = 50 Ω See Function Table Output Input Preset Clock Q CL = 50 pF J K Clear Output Q Note: C L includes the probe and jig capacitance. Rev.2.00, Oct 06, 2005 page 4 of 6 CL = 50 pF HD74HC78 Waveforms • Waveform − 1 tr tf t w (L) VCC 90 % Clock 50 % 10 % 50 % 50 % 50 % 10 % t w (H) 0V t TLH t THL VOH 90 % 50 % 90 % 50 % 10 % Q or Q 10 % t PLH t PHL t PHL t PLH 90 % Q or Q 50 % 10 % 50 % 10 % VOL VOH VOL t TLH t THL • Waveform − 2 tf Clear tr VCC 90 % 50 % 10 % 90 % 50 % 10 % 0V t w(clear) tf tr 90 % 50 % 90 % 50 % Preset 10 % t w(preset) t PHL 0V t PLH 90 % 50 % 10 % Q t THL t PLH VOH 50 % VOL t PHL VOH 90 % Q 50 % 10 % VCC 50 % VOL t TLH Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. Rev.2.00, Oct 06, 2005 page 5 of 6 HD74HC78 Package Dimensions JEITA Package Code P-SOP14-3.95x8.65-1.27 RENESAS Code PRSP0014DE-A *1 MASS[Typ.] 0.13g Previous Code FP-14DNV NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 14 8 *2 Index mark c E HE bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 8.65 9.05 E 3.95 A2 A1 7 1 *3 e Z 0.10 0.14 A bp x M bp L1 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 b1 c A c1 A1 θ θ 0° HE 5.80 1.27 e L y Detail F x 0.25 y 0.15 0.635 Z L L JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B *1 Previous Code FP-14DAV D 0.40 0.60 1.27 1.08 1 MASS[Typ.] 0.23g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 14 8° 8 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 Nom Max D 10.06 10.5 E 5.50 A2 7 e A1 bp Dimension in Millimeters Min x M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 1.27 e x 0.12 y 0.15 Z 1.42 0.50 L L Rev.2.00, Oct 06, 2005 page 6 of 6 8° 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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