TI DAC8832IRGYT 16-bit, ultra-low power, voltage-output digital-to-analog converter Datasheet

 DA
C8
®
832
DAC8832
SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
16-Bit, Ultra-Low Power, Voltage-Output
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
16-Bit Resolution
2.7 V to 5.5 V Single-Supply Operation
Very Low Power: 15 µW for 3 V Power
High Accuracy, INL: 1 LSB
Low Glitch: 10 nV-s
Low Noise: 18n V/√Hz
Fast Settling: 1.0 µS
Fast SPI™ Interface, up to 50 MHz
Reset to Mid-Code
Schmitt-Trigger Inputs for Direct Optocoupler
Interface
APPLICATIONS
•
•
•
•
•
Portable Equipment
Automatic Test Equipment
Industrial Process Control
Data Acquisition Systems
Optical Networking
The DAC8832 is a single, 16-bit, serial-input,
voltage-output digital-to-analog converter (DAC)
operating from a single 3 V to 5 V power supply. The
DAC8832 provides excellent linearity (1 LSB INL),
low glitch, low noise, and fast settling (1.0 µS to 1/2
LSB of full-scale output) over the specified
temperature range of –40°C to +85°C. The output is
unbuffered, which reduces the power consumption
and the error introduced by the buffer.
This device features a standard high-speed (clock up
to 50MHz), 3 V or 5 V SPI serial interface to
communicate with the DSP or microprocessors.
The DAC8832 provides unipolar or bipolar output
(±VREF) when working with an external buffer, and is
reset to mid-code after power-up. For optimum
performance, a set of Kelvin connections to the
external reference and the analog ground input are
provided.
The DAC8832 is available in a QFN-14 package,
and is pin-to-pin compatible with the DAC8831IRGY,
which is reset to zero-code after power-up.
Functional Block Diagram
VREF−S
VDD
VREF−F
RINV
RFB
+V
LDAC
CS
SCLK
RFB
INV
Serial
Interface
and
Control
Logic
DAC
VO
+
−V
OPA277
OPA704
OPA727
AGNDF
Input
Register
SDI
VOUT
−
AGNDS
DAC Latch
DAC8832
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
DAC8832
www.ti.com
SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
POWERON
RESET
VALUE
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PACKAGELEAD
PACKAGE
DESIGNATOR
DAC8832IRGY
±4
±1
Mid-Code
–40°C to +85°C
8832I
QFN-14
RGY
±2
±1
Mid-Code
±1
±1
Mid-Code
DAC8832IBRGY
DAC8832ICRGY
(1)
–40°C to +85°C
–40°C to +85°C
8832I
8832I
QFN-14
QFN-14
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
DAC8832IRGYT
Tape and Reel, 250
DAC8832IRGYR
Tape and Reel, 1000
DAC8832IBRGYT
Tape and Reel, 250
DAC8832IBRGYR
Tape and Reel, 1000
RGY
DAC8832ICRGYT
Tape and Reel, 250
DAC8832ICRGYR
Tape and Reel, 1000
RGY
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
DAC8832
UNIT
–0.3 to +7
V
Digital input voltage to DGND
–0.3 to +VDD + 0.3
V
VOUT to AGND
–0.3 to +VDD + 0.3
V
VDD to AGND
AGND, AGNDF, AGNDS to DGND
–0.3 to +0.3
V
Operating temperature range
–40 to +85
°C
Storage temperature range
–65 to +150
°C
+150
°C
(TJ max – TA) / θJA
W
54.9
°C/W
Junction temperature range (TJ max)
Power dissipation
Thermal impedance, θJA
(1)
2
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VDD = +3 V or VDD = +5V, VREF = +2.5 V unless otherwise noted; specifications subject
to change without notice.
DAC8832
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
16
Linearity error
bits
DAC8832ICRGY
±0.5
±1
DAC8832IBRGY
±0.5
±2
DAC8832IRGY
±0.5
±4
±0.5
±1
±1
±5
Differential linearity error
All grades
TA = +25°C
Gain error
±7
TA = –40°C to +85°C
±0.1
Gain drift
Zero code error
±0.25
TA = +25°C
±0.05
Zero code drift
LSB
LSB
ppm/°C
±1
±2
TA = –40°C to +85°C
LSB
LSB
ppm/°C
OUTPUT CHARACTERISTICS
Voltage output
(1)
Unipolar operation
Bipolar operation
Output impedance
To 1/2 LSB of FS, CL = 10 pF
Slew rate (2)
CL = 10 pF
Digital-to-analog glitch
1 LSB change around major carry
Digital feedthrough (3)
Output noise
TA = +25°C
Power-supply rejection
VDD varies ±10%
Bipolar zero error
V
+VREF
V
kΩ
1
µs
25
V/µs
10
nV-s
0.2
nV-s
18
nV/√Hz
±1
1
Ratio error
±0.0015
±0.0076
±0.25
±5
TA = +25°C
±7
TA = –40°C to +85°C
±0.2
LSB
Ω/Ω
RFB / RINV
Bipolar zero drift
(1)
(2)
(3)
+VREF
6.25
Settling time
Bipolar resistor matching
0
–VREF
%
LSB
ppm/°C
See the Bipolar Output Operation section for details.
Slew Rate is measure from 10% to 90% of transition when the output changes from 0 to full-scale.
Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change; CS is held high, while SCLK and DIN signals are toggled.
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SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, VDD = +3 V or VDD = +5V, VREF = +2.5 V unless otherwise noted; specifications subject
to change without notice.
DAC8832
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
REFERENCE INPUT
Reference input voltage range
Reference input impedance (4)
1.25
Unipolar mode
Bipolar mode
Reference –3 dB bandwidth, BW
Code = FFFFh
Reference feedthrough
Code = 0000h, VREF = 1 VPP at 100 kHz
9
Signal-to-noise ratio, SNR
Reference input capacitance
kΩ
7.5
1.3
MHz
1
mV
92
dB
Code = 0000h
75
Code = FFFFh
120
pF
DIGITAL INPUTS
VIL
Input low voltage
VIH
Input high voltage
VDD = 2.7 V
0.6
VDD = 5 V
0.8
VDD = 2.7 V
2.1
VDD = 5 V
2.4
V
V
Input current
±1
µA
Input capacitance
10
pF
Hysteresis voltage
0.4
V
POWER SUPPLY
VDD
IDD
Power-supply voltage
Power-supply current
Power
2.7
5.5
VDD = 3 V
5
20
VDD = 5 V
5
20
VDD = 3 V
15
60
VDD = 5 V
25
100
V
µA
µW
TEMPERATURE RANGE
Specified performance
(4)
4
–40
Reference input resistance is code-dependent, minimum at 8555h.
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+85
°C
DAC8832
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SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
PIN CONFIGURATION (NOT TO SCALE)
VDD
INV
DGND
LDAC
SDI
NC
RGY PACKAGE
QFN-14
(TOP VIEW)
13
12
11
10
9
14
8 SCLK
DAC8832
Thermal Pad(1)
2
3
4
5
6
AGNDS
VREF−S
VREF−F
7 CS
AGNDF
1
VOUT
RFB
NOTE: (1) Exposed thermal pad must be connected to analog ground.
TERMINAL FUNCTIONS
TERMINAL
NO.
DESCRIPTION
NAME
1
RFB
Feedback resistor. Connect to the output of external operational amplifier in bipolar mode.
2
VOUT
Analog output of DAC
3
AGNDF
Analog ground (Force)
4
AGNDS
Analog ground (Sense)
5
VREF-S
Voltage reference input (Sense). Connect to external voltage reference
6
VREF-F
Voltage reference input (Force). Connect to external voltage reference
7
CS
Chip select input (active low). Data is not clocked into SDI unless CS is low.
8
SCLK
Serial clock input.
9
NC
No internal connection
10
SDI
Serial data input. Data is latched into input register on the rising edge of SCLK.
11
LDAC
Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the
content of the input register.
12
DGND
Digital ground
13
INV
Junction point of internal scaling resistors. Connect to external operational amplifier inverting input in bipolar
mode.
14
VDD
Analog power supply, +3 V to +5 V.
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Case1: LDAC tied to LOW
t td
CS
DAC
Updated
t Delay
t sck
t Lead
t wsck
t Lag
t wsck
t DSCLK
SCLK
t su
t ho
SDI
BIT 15 (MSB)
LDAC
BIT 14
BIT 13, . . . ,1
BIT 0
LOW
−−−Don’t Care
Case2: LDAC Active
t td
CS
t Delay
t sck
t Lead
t wsck
t Lag
t wsck
t DSCLK
SCLK
t su
SDI
t ho
BIT 15 (MSB)
BIT 14
BIT 13, . . . ,1
BIT 0
t DLADC
HIGH
LDAC
DAC
Updated
−−−Don’t Care
Figure 1. DAC8832 Timing Diagram
6
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t WLDAC
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SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
TIMING CHARACTERISTICS: VDD = +5 V
(1) (2)
At –40°C to +85°C, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
10
ns
tLead
CS enable lead time
10
ns
tLag
CS enable lag time
10
ns
tDSCLK
Delay from CS high to SCLK high
10
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
µs
(1)
(2)
Assured by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
TIMING CHARACTERISTICS: VDD = +3 V (1) (2)
At –40°C to +85°C, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
10
ns
tLead
CS enable lead time
10
ns
tLag
CS enable lag time
10
ns
tDSCLK
Delay from CS high to SCLK high
10
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
µs
(1)
(2)
Assured by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
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SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, VREF = +2.5 V unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_C
VREF = 2.5 V
0.50
0.50
0.25
0.25
0
−0.25
−0.25
−0.50
−0.75
−0.75
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 3.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = −40_ C
VREF = 2.5 V
0.75
0.50
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = −40_ C
VREF = 2.5 V
0.75
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 4.
Figure 5.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +85_ C
VREF = 2.5 V
0.75
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = +85_ C
VREF = 2.5 V
0.75
0.50
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 6.
8
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 2.
1.00
INL (LSB)
0
−0.50
−1.00
INL (LSB)
TA = +25_ C
VREF = 2.5 V
0.75
DNL (LSB)
INL (LSB)
0.75
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 7.
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SBAS380A – FEBRUARY 2006 – REVISED APRIL 2006
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, VREF = +2.5 V unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_C
VREF = 5 V
TA = +25_C
VREF = 5 V
0.75
0.50
0.50
0.25
0.25
DNL (LSB)
INL (LSB)
0.75
0
−0.25
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 8.
Figure 9.
LINEARITY ERROR
vs REFERENCE VOLTAGE
LINEARITY ERROR
vs SUPPLY VOLTAGE
0.75
0.75
0.50
0.50
0.25
Linearity Error (LSB)
Linearity Error (LSB)
VREF = 2.5 V
DNL
0
INL
−0.25
DNL
0.25
0
INL
−0.25
−0.50
−0.50
0
1
2
3
4
5
6
2.5
3.0
3.5
Reference Voltage (V)
4.0
4.5
5.0
Figure 10.
Figure 11.
GAIN ERROR
vs TEMPERATURE
ZERO-CODE ERROR
vs TEMPERATURE
1.25
VREF = 2.5 V
Zero−Code Error (LSB)
1.00
0.75
Gain Error (LSB)
6.0
0.50
Bipolar Mode
0.50
0.25
0
Unipolar Mode
−0.25
0.25
Bipolar Mode
0
−0.25
−0.50
−0.75
−60
5.5
Supply Voltage (V)
Unipolar Mode
VREF = 2.5 V
−40 −20
0
20
40
60
80
Temperature (_C)
100
120 140
−0.50
−60
Figure 12.
−40 −20
0
20
40
60
80
Temperature (_C)
100
120 140
Figure 13.
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TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, VREF = +2.5 V unless otherwise noted.
REFERENCE CURRENT
vs CODE (UNIPOLAR MODE)
REFERENCE CURRENT
vs CODE (BIPOLAR MODE)
300
300
VREF = 2.5 V
VREF = 2.5 V
250
Reference Current (µA)
Reference Current (µA)
250
200
150
100
200
150
100
50
50
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 14.
Figure 15.
SUPPLY CURRENT
vs DIGITAL INPUT VOLTAGE
SUPPLY CURRENT
vs TEMPERATURE
800
5
VREF = 2.5 V
700
4
600
Supply Current (µA)
Supply Current (µA)
VDD = 5 V
500
400
300
VDD = 3 V
200
VDD = 5 V
VLOGIC = 5 V
3
VDD = 3 V
VLOGIC = 3 V
2
1
100
0
0
1
2
3
Digital Input Voltage (V)
4
0
−60 −40
5
20 40
60
80
Temperature (_C)
100 120 140
Figure 17.
SUPPLY CURRENT
vs SUPPLY VOLTAGE
SUPPLY CURRENT
vs REFERENCE VOLTAGE
5.0
VREF = 2.5 V
4.5
4.5
4.0
Supply Current (µA)
4.0
Supply Current (µA)
0
Figure 16.
5.0
3.5
3.0
2.5
2.0
1.5
3.5
VDD = 5 V
3.0
2.5
2.0
VDD = 3 V
1.5
1.0
1.0
0.5
0.5
0
0
2.7
3.0 3.3
3.6 3.9 4.2 4.5 4.8
Supply Voltage (V)
5.1
5.4
5.7 6.0
0
0.5
Figure 18.
10
−20
1.0
1.5 2.0 2.5 3.0 3.5
Reference Voltage (V)
Figure 19.
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4.0
4.5
5.0
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TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, VREF = +2.5 V unless otherwise noted.
MAJOR-CARRY GLITCH
(FALLING)
MAJOR-CARRY GLITCH
(RISING)
VREF = 2.5 V
5V/div
VREF = 2.5 V
5V/div
LDAC
VOUT
LDAC
VOUT
0.1V/div
0.1V/div
Time (0.5µs/div)
Time (0.5µs/div)
Figure 20.
Figure 21.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
VREF = 2.5 V
5V/div
VREF = 2.5 V
5V/div
LDAC
LDAC
1V/div
VOUT
VOUT
1V/div
Time (0.2µs/div)
Time (0.2µs/div)
Figure 22.
Figure 23.
DIGITAL
FEEDTHROUGH
VREF = 2.5 V
5V/div
20mV/div
SDI
VOUT
Time (50ns/div)
Figure 24.
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TYPICAL CHARACTERISTICS: VDD = +3 V
At TA = +25°C, VREF = +2.5 V unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_C
VREF = 1.5 V
0.50
0.50
0.25
0.25
0
−0.25
−0.25
−0.50
−0.75
−0.75
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 26.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = −40_ C
VREF = 1.5 V
0.75
0.50
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = −40_ C
VREF = 1.5 V
0.75
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 27.
Figure 28.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +85_ C
VREF = 1.5 V
0.75
0.25
0.25
DNL (LSB)
0.50
0
−0.25
TA = +85_ C
VREF = 1.5 V
0.75
0.50
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 29.
12
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 25.
1.00
INL (LSB)
0
−0.50
−1.00
INL (LSB)
TA = +25_ C
VREF = 1.5 V
0.75
DNL (LSB)
INL (LSB)
0.75
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 30.
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TYPICAL CHARACTERISTICS: VDD = +3 V (continued)
At TA = +25°C, VREF = +2.5 V unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25_C
VREF = 3 V
TA = +25_C
VREF = 3 V
0.75
0.50
0.50
0.25
0.25
DNL (LSB)
INL (LSB)
0.75
0
−0.25
0
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
−1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 31.
Figure 32.
LINEARITY ERROR
vs REFERENCE VOLTAGE
GAIN ERROR
vs TEMPERATURE
1.00
0.75
0.75
Bipolar Mode
0.50
Gain Error (LSB)
Linearity Error (LSB)
0.50
DNL
0.25
0
−0.25
1.5
2.0
2.5
3.0
Unipolar Mode
−0.25
−0.50
VDD = 3 V
VREF = 2.5 V
−1.00
−60
−0.50
1.0
0
−0.75
INL
0.5
0.25
3.5
Reference Voltage (V)
20
40
60
80
Temperature (_C)
100
Figure 34.
ZERO-CODE ERROR
vs TEMPERATURE
REFERENCE CURRENT
vs CODE (UNIPOLAR MODE)
VREF = 1.5 V
250
Reference Current (µA)
0.25
0
Unipolar Mode
−0.25
Bipolar Mode
−0.50
120 140
300
VDD = 3 V
VREF = 2.5 V
Zero−Code Error (LSB)
0
Figure 33.
0.50
−0.75
−60
−40 −20
200
150
100
50
0
−40 −20
0
20
40
60
80
Temperature (_C)
100
120 140
0
Figure 35.
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 36.
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TYPICAL CHARACTERISTICS: VDD = +3 V (continued)
At TA = +25°C, VREF = +2.5 V unless otherwise noted.
REFERENCE CURRENT
vs CODE (BIPOLAR MODE)
DIGITAL
FEEDTHROUGH
300
VREF = 2.5 V
VREF = 1.5 V
Reference Current (µA)
250
5V/div
SDI
200
150
20mV/div
VOUT
100
50
0
0
Time (50ns/div)
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 37.
Figure 38.
MAJOR-CARRY GLITCH
(FALLING)
MAJOR-CARRY GLITCH
(RISING)
VREF = 2.5 V
5V/div
VREF = 2.5 V
5V/div
LDAC
VOUT
LDAC
VOUT
0.1V/div
0.1V/div
Time (0.5µs/div)
Time (0.5µs/div)
Figure 39.
Figure 40.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
VREF = 2.5 V
VREF = 2.5 V
5V/div
LDAC
5V/div
1V/div
VOUT
VOUT
1V/div
Time (0.2µs/div)
Time (0.2µs/div)
Figure 41.
14
LDAC
Figure 42.
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THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC8832 is a single, 16-bit, serial-input, voltage-output DAC. It operates from a single supply ranging from
2.7 V to 5 V, and typically consumes 5 µA. Data are written to this device in a 16-bit word format, via an SPI
serial interface. To ensure a known power-up state, the DAC8832 is designed with a power-on reset function.
The DAC8832 is reset to mid-scale code. In unipolar mode, the DAC8832 is reset to 1/2 × VREF, and in bipolar
mode, is reset to 0 V. Kelvin sense connections for the reference and analog ground are also included.
DIGITAL-TO-ANALOG SECTIONS
The DAC architecture consists of two matched DAC sections and is segmented. A simplified circuit diagram is
shown in Figure 43. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each
of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the
data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R
R
VOUT
2R
2R
S0
2R
S1
2R
2R
S11
E1
2R
E2
2R
E15
VREF
12−Bit R−2R Ladder
Four MSBs Decoded into
15 Equal Segments
Figure 43. DAC Architecture
OUTPUT RANGE
The output of the DAC is:
VOUT = (VREF × Code)/65536
Where Code is the decimal data word loaded to the DAC latch.
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THEORY OF OPERATION (continued)
POWER-ON RESET
The DAC8832 has a power-on reset function to ensure the output is at a known state upon power-up. Upon
power-up, the DAC latch and input register contain mid-scale code until new data is loaded from the input serial
shift register. Therefore, after power-up, the output from pin VOUT is 0.5 × VREF in unipolar mode, and 0V in
bipolar mode.
However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially
to the device, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than
16 bits are loaded, the last 16 are kept; if less than 16 are loaded, bits will remain from the previous word. If the
device must be interfaced with data shorter than 16 bits, the data should be padded with 0s at the LSBs.
SERIAL INTERFACE
The digital interface is standard 3-wire connection compatible with SPI, QSPI™, Microwire™, and TI DSP
interfaces, which can operate at speeds up to 50M-bits/sec. The data transfer is framed by CS, the chip select
signal. The DAC works as a bus slave. The bus master generates the synchronize clock, SCLK, and initiates the
transmission. When CS is high, the DAC is not accessed, and the clock SCLK and serial input data SDI are
ignored. The bus master accesses the DAC by driving pin CS low. Immediately following the high-to-low
transition of CS, the serial input data on pin SDI is shifted out from the bus master synchronously on the falling
edge of SCLK, and latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high
transition of CS transfers the contents of the input shift register to the input register. All data registers are 16-bit.
It takes 16 clocks of SCLK to transfer one data word to the parts. To complete a whole data word, CS must go
high immediately after 16 SCLKs are clocked in. If more than 16 SCLKs are applied during the low state of CS,
the last 16 bits are transferred to the input register on the rising edge of CS. However, if CS is not kept low
during the entire 16 SCLK cycles, data is corrupted. In this case, reload the DAC with a new 16-bit word.
The DAC8832 has an LDAC pin allowing the DAC latch to be updated asynchronously by bringing LDAC low
after CS goes high. In this case, LDAC must be maintained high while CS is low. If LDAC is tied permanently
low, the DAC latch is updated immediately after the input register is loaded (caused by the low-to-high transition
of CS).
16
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APPLICATION INFORMATION
UNIPOLAR OUTPUT OPERATION
The DAC8832 is capable of driving unbuffered loads of 60kΩ. Unbuffered operation results in low supply current
(typically 5µA) and a low offset error. The DAC8832 can be configured to output both unipolar and bipolar
voltages. Figure 44 shows a typical unipolar output voltage circuit. The code table for this mode of operation is
shown in Table 1.
+5 V
+2.5 V
0.1 µF
0.1 µF
VDD
+
10 µF
OPA277
OPA704
OPA727
VREF−S VREF−F
RINV
RFB
RFB
+V
CS
SCLK
SDI
Serial Interface
and Control Logic
LDAC
INV
VOUT
DAC
VO = 0 to +VREF
−V
AGNDF
Input
Register
AGNDS
DAC Latch
DAC8832
DGND
Figure 44. Unipolar Output Mode
Table 1. Unipolar Code
DAC LATCH CONTENTS
MSB
LSB
ANALOG OUTPUT
1111 1111 1111 1111
VREF × (65,535/65,536)
1000 0000 0000 0000
VREF × (32,768/65,536) = 1/2 VREF
0000 0000 0000 0001
VREF × (1/65,536)
0000 0000 0000 0000
0V
Assuming a perfect reference, the worst-case output voltage may be calculated in the following equation:
Unipolar Mode Worst-Case Output:
V OUT_UNI + D
216
ǒVREF ) VGEǓ ) V ZSE ) INL
Where:
VOUT_UNI = Unipolar mode worst-case output
D = Code loaded to DAC
VREF = Reference voltage applied to part
VGE = Gain error in volts
VZSE = Zero scale error in volts
INL = Integral nonlinearity in volts
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BIPOLAR OUTPUT OPERATION
With the aid of an external operational amplifier, the DAC8832 may be configured to provide a bipolar voltage
output. A typical circuit of such an operation is shown in Figure 45. The matched bipolar offset resistors RFB and
RINV are connected to an external operational amplifier to achieve this bipolar output swing; typically, RFB = RINV
= 28 kΩ.
+5 V
+2.5 V
0.1 µF
VDD
+
0.1 µF
VREF−S VREF−F
RINV
R FB
RFB
INV
CS
SDI
Serial Interface
and Control Logic
LDAC
SCLK
10 µF
VOUT
DAC
AGNDF
Input
Register
+V
VO = −VREF to +VREF
OPA277
−V OPA704
OPA727
AGNDS
DAC Latch
DAC8832
DGND
Figure 45. Bipolar Output Mode
Table 2 shows the transfer function for this output operating mode. The DAC8832 also provides a set of Kelvin
connections to the analog ground and external reference inputs.
Table 2. Bipolar Code
DAC LATCH CONTENTS
MSB
LSB
ANALOG OUTPUT
1111 1111 1111 1111
+VREF × (32,767/32,768)
1000 0000 0000 0001
+VREF × (1/32,768)
1000 0000 0000 0000
0V
0111 1111 1111 1111
–VREF × (1/32,768)
0000 0000 0000 0000
–VREF × (32,768/32,768) = –VREF
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation:
Bipolar Mode Worst-Case Output:
V OUT_BIP +
ƪǒVOUT_UNI ) VOSǓ (2 ) RD) * VREF(1 ) RD)ƫ
1 ) ǒ2)RDǓ
A
Where:
VOS = External operational amplifier input offset voltage
RD = RFB and RIN resistor matching error
A = Operational amplifier open-loop gain
18
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OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This provides the
±VREF output.
In a single-supply application, selection of a suitable operational amplifier may be more difficult because the
output swing of the amplifier does not usually include the negative rail; in this case, AGND. This output swing
can result in some degradation of the specified performance unless the application does not use codes near 0.
The selected operational amplifier needs to have low-offset voltage (the DAC LSB is 38 µV with a 2.5 V
reference), eliminating the need for output offset trims. Input bias current should also be low because the bias
current multiplied by the DAC output impedance (approximately 6.25 kΩ) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier
should not impede the settling time of the DAC. Output impedance of the DAC is constant and
code-independent, but in order to minimize gain errors the input impedance of the output amplifier should be as
high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds
another time constant to the system, thus increasing the settling time of the output. A higher 3 dB amplifier
bandwidth results in a shorter effective settling time of the combined DAC and amplifier.
REFERENCE AND GROUND
Since the input impedance is code-dependent, the reference pin should be driven from a low impedance source.
The DAC8832 operates with a voltage reference ranging from 1.25 V to VDD. References below 1.25 V result in
reduced accuracy.
The DAC full-scale output voltage is determined by the reference. Table 1 and Table 2 outline the analog output
voltage for particular digital codes.
For optimum performance, Kelvin sense connections are provided. If the application does not require separate
force and sense lines, they should be tied together close to the package to minimize voltage drops between the
package leads and the internal die.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed
with a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor.
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original Revision (February 2006) to A Revision ................................................................................. Page
•
20
Deleted Lead Temperature information from Absolute Maximum Ratings........................................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC8832IBRGYR
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832IBRGYRG4
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832IBRGYT
ACTIVE
QFN
RGY
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832IBRGYTG4
ACTIVE
QFN
RGY
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832ICRGYR
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832ICRGYRG4
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832ICRGYT
ACTIVE
QFN
RGY
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832ICRGYTG4
ACTIVE
QFN
RGY
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832IRGYR
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832IRGYRG4
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832IRGYT
ACTIVE
QFN
RGY
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DAC8832IRGYTG4
ACTIVE
QFN
RGY
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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