Sony CXA1982Q Rf signal processing servo amplifier for cd player Datasheet

CXA1982Q
RF Signal Processing Servo Amplifier for CD players
For the availability of this product, please contact the sales office.
Description
The CXA1982Q is a bipolar IC with built-in RF
signal processing and various servo ICs. A CD
player servo can be configured by using this IC, DSP
and driver.
Features
• Low operating voltage (VCC – VEE = 2.8 to 4.0V)
• Low power consumption (36mW, VCC = 3.0V)
• Supports pickup of either current output, voltage
output
• Supports tracking system balance adjustment
externally
• Single power supply and positive/negative dual
power supplies
Applications
• RF I-V amplifier, RF amplifier
• Focus and tracking error amplifier
• APC circuit
• Mirror detection circuit
• Defect detection and prevention circuits
• Focus servo control
• Tracking servo control
• Sled servo control
48 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
12
V
• Supply voltage
VCC
• Operating temperature Topr
–20 to +75
°C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation
PD
833
mW
Recommended Operating Condition
Operating supply voltage
VCC – VEE
2.8 to 4.0
V
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97215-PS
CXA1982Q
PHD2
PHD1
PD
LD
RF_M
RF_O
RF_I
CP
CB
CC1
CC2
FOK
Block Diagram
36
35
34
33
32
31
30
29
28
27
26
25
APC
LEVEL S
I IL
24 SENS
TTL
23 C.OUT
RF IV AMP1
22 XRST
MIRR
FOK
DFCT
TTL
21 DATA
RF IV AMP2
FE_BIAS 37
•I IL DATA REGISTER •INPUT SHIFT REGISTER
•ADRESS.DECODER
TTL
F 38
FE AMP
I IL
I IL
•OUTPUT DECODER
20 XLT
19 CLK
F IV AMP
E 39
FS1 to 4
TG1 to 2
TM1 to 7
PS1 to 4
FZC COMP
E IV AMP
18 Vcc
EI 40
TE AMP
•TRACKING
PHASE COMPENSATION
•I SET
17 ISET
TM6
VEE 41
16 SL_O
TEO 42
TG1
TM5
15 SL_M
TM4
TZC COMP
NC 43
ATSC 45
TZC 46
•FCS PHASE COMPENSATION
DFCT
TEI 44
TM1
TM2
TM3
FS1
•WINDOW COMP.
13 TA_O
TM7
ATSC
FS2
TDFCT 47
•
•
•
•
•F SET
TG2
DFCT
FEI
FDFCT
FGD
FLB
7
8
9
10
11
12
TA_M
FEO
6
FSET
5
TG2
4
TGU
3
SRCH
2
FE_M
1
FE_O
FS4
VC 48
14 SL_P
The switch state in Block Diagram is for initial resetting.
Switch turns to ° side for 1 and to • side for 0 in Serial Data Truth Table.
DFCT switch turns to ° side when defect signal generates for DEFECT = E in Serial Data Truth Table.
TG1 switch turns to ° side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1.
–2–
CXA1982Q
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
25p
147
1
FEO
O
1
174k
51k
Focus error amplifier output.
Connected internally to the FZC
comparator input.
300µ
10k
2
FEI
I
9k
Focus error input.
147
2
100k
147
3
FDFCT
I
Capacitor connection pin for defect
time constant.
3
68k
147
4
FGD
I
4
130k
5
FLB
I
6
FE_O
O
20µ
Ground this pin through a capacitor
when decreasing the focus servo
high-frequency gain.
External time constant setting pin
for increasing the focus servo lowfrequency.
40k
5
Focus drive output.
6
13
TA_O
O
Tracking drive output.
13
16
16
SL_O
250µ
O
147
7
FE_M
I
Sled drive output.
90k
Focus amplifier inverted input.
7
50k
–3–
CXA1982Q
Pin
No.
Symbol
I/O
Equivalent circuit
Description
147
8
SRCH
I
External time constant setting pin for
generating focus servo waveform.
8
11µ
50k
110k
9
TGU
External time constant setting pin for
switching tracking high-frequency
gain.
20k
I
9
82k
10
TG2
I
External time constant setting pin for
switching tracking high-frequency
gain.
10
470k
2µ
High cut-off frequency setting pin for
focus and tracking phase
compensation amplifier.
147k
11
FSET
I
11
15k
15k
100k
12
TA_M
I
147
Tracking amplifier inverted input.
12
11µ
14
SL_P
I
15
SL_M
I
147
Sled amplifier non-inverted input.
14
147
Sled amplifier inverted input.
15
22µ
–4–
CXA1982Q
Pin
No.
Symbol
I/O
Description
Equivalent circuit
147
17
ISET
I
19
CLK
I
Setting pin for Focus search, Track
jump, and Sled kick current.
17
Serial data transfer clock input from
CPU. (no pull-up resistance)
15µ
20
XLT
I
19
147
Latch input from CPU.
(no pull-up resistance)
1k
20
21
DATA
I
Serial data input from CPU.
(no pull-up resistance)
21
22
22
XRST
I
23
C. OUT
O
Reset input; resets at Low.
(no pull-up resistance)
Track number count signal output.
20k
147
23
24
24
SENS
O
Outputs FZC, DFCT, TZC, gain,
balance, and others according to
the command from CPU.
100k
20k
25
FOK
147
O
Focus OK comparator output.
40k
25
100k
26
CC2
Input for the DEFECT bottom hold
output with capacitance coupled.
I
147
147
27
28
27
CC1
O
DEFECT bottom hold output.
147
26
28
CB
Connection pin for DEFECT bottom
hold capacitor.
I
–5–
CXA1982Q
Pin
No.
Symbol
I/O
Equivalent circuit
Description
147
29
CP
I
Connection pin for MIRR hold
capacitor.
MIRR comparator non-inverted
input.
30
RF_I
I
Input for the RF summing amplifier
output with capacitance coupled.
29
147
30
31
RF_O
RF sunning amplifier output.
Eye-pattern check point.
O
147
147
31
32
32
RF_M
I
RF summing amplifier inverted
input.
The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.
10k
1k
33
LD
O
APC amplifier output.
33
130k
34
PD
I
17µ
100k
APC amplifier input.
34
10k
35
36
PHD1
PHD2
I
I
147
35
36
100µ
–6–
11.6k
RF I-V amplifier inverted input.
Connect these pins to the photo
diode A + C and B + D pins.
CXA1982Q
Pin
No.
Symbol
I/O
Equivalent circuit
Description
32k
164k
37
FE_BIAS
I
Bias adjustment of focus error
amplifier.
37
25p
8µ
12p
260k
38
39
F
E
I
I
147
38
39
513
F I-V and E I-V amplifier inverted
input.
Connect these pins to photo diodes
F and E.
10µ
6.8k
260k
40
EI
—
40
20.3k
I-V amplifier E balance adjustment.
147
42
TEO
O
42
Tracking error amplifier output.
E-F signal is output.
300µ
43
NC
—
–7–
CXA1982Q
Pin
No.
44
Symbol
TEI
I/O
Description
Equivalent circuit
I
Tracking error input.
100k
147
44
147
47
TDFCT
Capacitor connection pin for defect
time constant.
47
I
1k
100k
10k
45
ATSC
I
Window comparator input for ATSC
detection.
45
100k
1k
10k
46
TZC
I
Tracking zero-cross comparator
input.
46
75k
48
VC
O
50
120
(VCC + VEE)/2 DC voltage output.
48
120
VC
–8–
T22
T21
T20
T19
T18
T17
T16
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
O
1
O
9
10
11
12
13
14
15
O
16
17
Center amplifier output
offset
O
8
Output voltage 4
7
O
O
O
6
Output voltage 3
O
O
5
O
O
O
4
Output voltage 2
O
O
3
O
O
O
O
O
2
SW conditions
Output voltage 1
Max. output voltage-Low
Max. output voltage-High
Voltage gain E0
Voltage gain F0
Offset
Max. output voltage-Low
Max. output voltage-High
Voltage gain difference
Voltage gain 1
Voltage gain 1
Offset
Max. output voltage-Low
Max. output voltage-High O
Voltage gain
Offset
Current consumption 2
T2
FE amplifier
TE amplifier
APC
–9–
VC
T3
Current consumption 1
RF amplifier
T1
Item
Electrical Characteristics
18
RST
SD
48
33
42
1
0.8mA sink
–100
–200
350
–400
V2 = 145mV
V2 = 170mV
–900
—
1.2
7.2
7.3
–1.0
–1.33
100
500
1500
900
–300
—
13.2
13.3
25
–1.0
—
3.0
33.0
33.0
120
–0.3
—
31.1
50
–8
18
Max.
1.45
10.2
10.3
0
–1.3
—
–25
1.3
0
30.0
30.0
1.0
–3.0
27.0
27.0
V2 = 120mV
V1 = 1VDC EI: 39kΩ
V1 = 1VDC
V1 = 1kHz EI: 39kΩ
V1 = 1kHz
V1 = 100mVDC
V1 = 100mVDC
V1 = 1kHz I/O ratio
V1 = 1kHz I/O ratio
0
—
–120
–0.9
1.2
V1 = 100mVDC
V1 = –100mVDC
1.3
25.1
28.1
0
–12
12
Typ.
Ratings
1kHz input ratio
–50
31
8
Min.
–18
Measurement conditions
41
18
Measurement pin
mV
mV
mV
mV
mV
V
V
dB
dB
mV
V
V
dB
dB
dB
mV
V
V
dB
mV
mA
mA
Unit
(VCC = 1.5V, VEE = –1.5V, Ta = 25°C)
CXA1982Q
– 10 –
T41
T40
T39
T38
T37
T36
T35
T34
O
O
12
13 14
15
O
16
17 18
13
25
10
24
T31+ T14
Pin 1 threshold
O
ATSC threshold (+)
FOK threshold
TZC threshold
O
38
25
25
25
25
24
–400
–20
7
–25
360
28
Jump output voltage (+)
ATSC threshold (–)
–640
2C
Jump output voltage (–)
1.0
22.9
12.25
185
–356
–330
20
25
15
0
–7
640
–360
–1.0
–39
26.9
17.6
265
–15
500
–500
–1.3
1.3
24.9
14.6
225
500
360
03
00
–360
–500
–640
02
640
–1.0
—
–35
53
24
Max.
–1.3
V1 = –200mVDC
51
49
1.3
21.0
18
1.0
Typ.
Min.
Ratings
—
08
V1 = 200mVDC
08
T23+ T8 (or T9)
Output gain difference between
SD = 00 and SD = 08.
6
00
08
V1 = +0.5VDC
O
O
O
O
10 11
O
9
O
O
8
Max. output voltage-Low
7
V1 = –0.5VDC
O
6
O
5
O
4
Max. output voltage-High
3
Measurement conditions
Output gain difference between
SD = 20 and SD = 25.
TRK total gain
T32
2
Measure-
SD ment pin
O
DC voltage gain
T31
O
1
SW conditions
Feed through
FZC threshold
T30
T33
Search voltage (+)
T29
Max. output voltage-Low
Max. output voltage-High
Feed through
FCS total gain
DC voltage gain
Search voltage (–)
FOK
T28
T27
T26
T25
T24
T23
FCS servo
TRK servo
Item
mV
mV
mV
mV
mV
mV
V
V
dB
dB
dB
mV
mV
mV
V
V
dB
dB
dB
Unit
CXA1982Q
– 11 –
T54
T53
T52
T51
T50
T49
T48
T47
T46
T45
T44
T43
T42
Sled servo
MIRR
DEFECT
9
10
11
12
13
14
15 16
17
18
16
O
O
O
O
O
O
Min. input operating voltage
Max. input operating voltage
O
O
O
O
Min. input operating voltage
Max. input operating voltage
O
O
Max. operating frequency
Min. operating frequency
O
O
10
14
23
Measures at C. OUT pin.
24
Measures at SENS pin.
Measures at SENS pin.
Measures at SENS pin.
Measures at SENS pin.
Measures at C. OUT pin.
Measures at C. OUT pin.
1.8
2.5
1.8
30
600
450
22
Kick voltage (+)
Max. operating frequency
–600
–750
–1.3
1.3
Typ.
23
O
Max. output voltage-Low
1.0
50
Min.
Ratings
Kick voltage (–)
O
Max. output voltage-High
V1 = –0.4VDC
V1 = +0.4VDC
8
25
7
Output gain difference between
SD = 20 and SD = 25.
6
20
5
O
4
Feed through
3
Measurement conditions
25
2
Measure-
SD ment pin
O
1
SW conditions
DC open gain
Item
0.5
1
0.3
750
–450
–1.0
–34
Max.
Vp-p
Vp-p
kHz
kHz
Vp-p
Vp-p
kHz
mV
mV
V
V
dB
dB
Unit
CXA1982Q
CXA1982Q
Electrical Characteristics Measurement Circuit
VEE Vcc
S4
1000p
35
34
33
32
31
30
29
28
27
26
PD
LD
RF_M
RF_O
RF_I
CP
CB
CC1
CC2
FE_BIAS
10k
25
FOK
3000p
10k
S15
S16
S17
36
PD1
10k
3300p
PD2
37
S3
22k
10k
10k
S1
S2
V2
SENS
24
Vcc
10k
38 F
C. OUT 23
39 E
XRST 22
XRST
40 EI
DATA 21
DATA
390k
Vcc
10k
390k
39kΩ S5
VEE
A
41 VEE
XLT 20
XLT
42 TEO
CLK 19
CLK
43 NC
Vcc 18
44 TEI
ISET 17
S18
A
Vcc
S6
SL_O 16
46 TZC
SL_M 15
47 TDFCT
SL_P 14
FE_O
FE_M
SRCH
TGU
TG2
FSET
4
5
6
7
8
9
10
11
S13
47k
100k
510k
10k
S11
– 12 –
10k
13
12
S12
200k
5.1k
100k
FLB
3
TA_O
S14
13k
200k
FGD
2
0.1µ
FDFCT
1
S10
48 VC
FEI
0.1µ
S9
10k
V
FEO
S8
60k
45 ATSC
TA_M
AC
DC
VEE
240k
S7
0.015µ
V1
CXA1982Q
Application Circuit (Dual ±1.5V power supplies)
Vcc
MICROCOMPUTER
10
1µ/6.3V
10µH
A
VEE
100
34
33
32
31
30
29
28
27
PD
LD
RF M
RF O
RF I
CP
CB
CC1
37
VEE FE_BIAS
38 F
F
E
6.8k
35
PD2
47k
36
PD1
Vcc
0.033µ
26
25
CC2
22k 0.01µ
D
FOK
500
B
0.033µ
C
0.01µ
1k
100µ/6.3V
1µ/6.3V
Vcc
SENS
DSP
24
DSP
C. OUT 23
39 E
XRST 22
MICROCOMPUTER
40 EI
DATA 21
DSP
41 VEE
XLT 20
DSP
42 TEO
CLK 19
22k
100k
VEE
DSP
Vcc
43 NC
Vcc 18
44 TEI
ISET 17
45 ATSC
SL O 16
46 TZC
SL M 15
120k
FDFCT
FGD
FLB
FE O
FE M
SRCH
TGU
TG2
FSET
3
4
5
6
7
8
9
10
11
0.015µ
3.3µ
13
22µ 15k
12
4.7µ
0.1µ
100k
Driver
0.015µ
Driver
0.033µ
510k
100k
0.1µ
2200p 0.1µ
22k
TA M
FEI
2
680k
FEO
1
TA O
82k
0.022µ
10µ
Driver
SL P 14
47 TDFCT
0.1µ
48 VC
8.2k 100k
VEE
BPF
Vcc
Application Circuit (Single +3V power supply)
Vcc
MICROCOMPUTER
10
1µ/6.3V
10µH
A
22k 0.01µ
E
6.8k
35
34
33
32
31
30
29
28
27
26
PD
LD
RF M
RF O
RF I
CP
CB
CC1
CC2
25
24
DSP
38 F
C. OUT 23
DSP
39 E
XRST 22
MICROCOMPUTER
40 EI
DATA 21
DSP
41 VEE
XLT 20
DSP
42 TEO
CLK 19
37
47k
F
36
PD1
Vcc
0.033µ
PD2
D
0.01µ
100
500
B
0.033µ
C
FOK
1k
100µ/6.3V
1µ/6.3V
Vcc
FE_BIAS
SENS
22k
100k
43 NC
Vcc 18
44 TEI
ISET 17
45 ATSC
SL O 16
46 TZC
SL M 15
DSP
Vcc
SL P 14
FGD
FLB
FE O
FE M
SRCH
TGU
TG2
FSET
2
3
4
5
6
7
8
9
10
11
TA O
22µ 15k
0.015µ
Vcc
510k
100k
0.033µ
0.015µ
3.3µ
13
12
4.7µ
100k
Driver
22k
0.1µ
FDFCT
1
0.1µ 680k
Vcc
10µ
FEI
10µ
2200p 0.1µ
48 VC
FEO
0.1µ
TA M
47 TDFCT
Driver
82k
0.022µ
BPF
8.2k 100k
120k
Driver
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 13 –
CXA1982Q
Description of Functions
RF Amplifier
The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted via a 58kΩ equivalent
resistor by the PD I-V amplifiers. these signals are added by the RF summing amplifier, and the photo diode
(A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be
performed at this pin.
1k
22k
3.3µ
RF_M
32
A
RF_O
31
58k
C
PD1
iPD1 →
FOK
DEFECT
RF SUMMING AMP
PD1 IV AMP
B
D
10k
VA
35
VC
58k
VC
PD2
iPD2 →
10k
VB
36
PD2 IV AMP
VC
The low frequency component of the RFO output voltage is VRFO = 2.2 × (VA + VB) = 127.6kΩ × (iPD1 + iPD2).
Focus Error Amplifier
The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and
output current-voltage converted voltage of the photo diode (A + C – B – D).
25p
174k
– (B + D)
– (A + C)
VB
32k
1 FEO
VA
FE AMP
32k
25p
87k
164k
VC
FE_BIAS
37
VEE
VCC
47k
The FEO output voltage (low frequency) is VFEO = 5.4 × (VA – VB) = (iPD2 – iPD1) × 315kΩ.
Be aware that the rotation of the focus bias volume has reversed for the usual CD RF IC.
– 14 –
CXA1982Q
Tracking Error Amplifier
The photo diode currents input to E and F pins are each current-voltage converted by the E I-V and F I-V
amplifiers.
1k
RF1
3.3µ
260k
12p
TE AMP
F
30k
VF
13k
RE1
TEO
30k
RF3
96k
F I-V AMP
26k
VC
96k
42
RF2
38
→
iF
VC
VC
VC
E I-V AMP
RE2
VC
RE3
VE
39
6.8k
E
→
iE
20.3k
260k
12p
40
EI
R1
VC
Tracking system balance adjustment is performed by varying the resistance externally attached to EI pin.
This external resistance sets combined feed back resistance of the T-configured E I-V AMP.
F I-V AMP feedback resistance = RF1 + RF2 +
RF1 × RF2
= 403kΩ
RF3
E I-V AMP feedback resistance = RE1 + RE2 +
RE1 × RE2
(Rx = R1//RE3)
Rx
Gain adjustment is performed by adjusting external variable resistor of TEO pin.
– 15 –
CXA1982Q
Center Voltage Generation Circuit
(Single voltage application; Connect to GND when it’s positive/negative dual power supplies.)
Maximum current is approximately ±3mA. Output impedance is approximately 50Ω.
30k
Vcc
VC
VC
50
30k
48
VEE
APC Circuit
When driving a constant current, the optical output by the laser diode possesses large negative temperature
characteristics. Therefore, the current must be controlled with the monitor photo diode to ensure the output
remains constant.
Vcc
130k
60k
100µ
/6.3V
100k
2k
34
1k
PD
33
LD
10µH
80k
1.25V
8k
4k
1µ/6.3V
27k
15k
1SS149
33k
LD
GND
– 16 –
PD
VEE
CXA1982Q
Focus Servo
FE
9k
51k
FEO
10k
22k
FZC
1
2
FEI
2200p
100k
3
0.47µ
DFCT
FS4
68k
FDFCT
FOCUS COIL
FE_O
Focus
100k
phase
Compensation
6
FGD
4
50k
100k
FE_M
7
680k
40k
11µ
22µ
0.1µ
ISET 120k
17
50k
FS2
FLB
5
0.1µ
FSET
11
510k
FS1
SRCH
8
0.01µ
4.7µ
The above figure shows a block diagram of the focus servo.
Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100kΩ resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used,
leave Pin 3 open. The defect switch operation can be enabled and disabled with command.
The capacitor connected between Pin 5 and GND is a time constant to raise the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510Ω is
connected to Pin 11.
The focus search height is approximately ±1.1Vp-p when using the constants indicated in the above figure.
This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing
this resistance also changes the height of the track jump and sled kick as well.
The FZC comparator inverted input is set to 15% of VCC and VC (Pin 48); (VCC – VC) × 15%.
∗ 510kΩ resistance is recommended for Pin 11.
– 17 –
CXA1982Q
Tracking Sled Servo
TE
42
TEO
43 NC
SLED MOTOR
SL_O
16
TM1
44
680k
TG1
SL_M
15
100k
100k
TDFCT
47
66p
TM6 22µA
0.47µ
8.2k
TM5
0.047µ 470k
1k
ATSC
47p
1k
0.022µ
TM4 11µA
TM3
TZC
10
14
TA_M
12
46
0.033µ
22µA
ATSC
100k
TZC
9
SL_P
TM2
3.3µ
45
330k
680k
20k
TGU
TG2
M
0.015µ
DFCT
120k
TEI
TG2
Tracking Phase
Compensation
10k
82k
22µ
100k
15k
11µA
TRACKING
COIL
90k
TA_O
13
TM7
470k
FSET
11
510k
0.01µ
The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 9 and 10 is a time constant to decrease the high-frequency gain when
TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance connected to Pin 11. In the CXA1782, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 ( or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and
VEE. When this resistance is 120kΩ:
TM3 ( or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100kΩ) and the capacitance connected to Pin 47.
– 18 –
CXA1982Q
Focus OK Circuit
RF
VCC
DEFECT
RF_O
C5
31
0.01µ
30
20k
54k
×1
RF_I
25 FOK
VG
92k
15k
0.625V
FOCUS OK
COMPARATOR
FOCUS OK AMP
The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output reverses when VRFI – VRFO ≈ –0.37V.
Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK
amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block error rate
degradation brought about by RF envelope defects caused by scratched discs can be prevented.
DEFECT Circuit
After inversion, RF O signal is bottom held by means of the long and short time constants. The long timeconstant bottom hold keeps the mirror level prior to the defect.
The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1msec, and this is
differentiated and level-shifted through the AC coupling circuit.
The long and short time-constant signals are compared to generate at mirror defect detection signal.
0.033µ
CC1
27
RF
CC2
26
FOK
a
RF_O 31
×2
b
c
e
24 SENS
DEFECT AMP
d
DEFECT SW
DEFECT BOTTOM
HOLD
28
CB
a
RFO
b
DEFECT
AMP
c
e
DEFECT COMPARATOR
0.01µ
BOTTOM
HOLD (1)
solid line
CC1
d
H
DEFECT
L
– 19 –
BOTTOM
HOLD (2)
dotted line
CC2
CXA1982Q
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.
FOK DEFECT
RF_O
31
MIRROR HOLD AMP
RF
0.033µ
29
30
RF_I
×1.4
G
PEAK &
BOTTOM
HOLD
H
CP
×1
I
J
K
MIRROR AMP
20k
LOGIC
MIRROR
COMPARATOR
RF_O
0V
G
(RF_I)
0V
H
(PEAK HOLD)
0V
I
(BOTTOM HOLD)
0V
J
K
(MIRROR HOLD)
H
MIRR
L
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1982Q, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. OUT
output to the MIRR input of the DSP.
– 20 –
CXA1982Q
Commands
The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by
2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F.
Commands for the CXA1982Q can be broadly divided into four groups ranging in value from $0X to $2X.
1. $0X (“FZC” at SENS pin (Pin 24))
These commands are related to focus servo control.
The bit configuration is as shown below.
D7
0
D6
0
D5
0
D4
0
D3
FS4
D2
DEFECT
D1
FS2
D0
FS1
Four focus-servo related switches exist: FS1, FS2, FS4, and DEFECT corresponding to D0 to D3, respectively.
$00
$02
When FS1 = 0, Pin 8 is charged to (22µA – 11µA) × 50kΩ = 0.55V.
If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V.
From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 6. This voltage level is obtained by equation 1 below.
(22µA – 11µA) × 50kΩ ×
$03
resistance between Pins 6 and 7
50kΩ
Equation 1
....
From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as
shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 8 when FS1 gose from 0 → 1
This time constant is obtained with the 50kΩ resistance and an external capacitor.
By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)
$04
When the fact that the RF signal is missing is detected and the scratches on the disc are detected with
DEFECT = 0, DFCT (FS3) is turned ON.
– 21 –
CXA1982Q
1-1. FS4
This switch is provided between the focus error input (Pin 2) and the focus phase compensation, and is in
charge of turning the focus servo ON and OFF.
$00
→ $08
Focus OFF ← Focus ON
1-2. Procedure of focus activation
For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 6) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.
A
t
Fig. 3. S-curve
The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the
turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3.
To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 24) as the point A transit signal. In
addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
(20ms) (200ms)
$02
($00)
$03
$08
Drive voltage
∗ The broken lines in the figure
indicate the voltage assuming
the signal is not in focus.
Focus error
SENS pin
(FZC)
The instant the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart
– 22 –
CXA1982Q
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ↓ ?
Transfer $08
NO
YES
F. OK ?
F. OK ?
NO
NO
YES
YES
Transfer $08
FZC ↓ ?
NO
YES
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences
1-3. SENS pin (Pin 24)
The output of the SENS pin differs depending on the input data as shown below.
$0X: FZC
$1X: DEFECT
$2X: TZC
$3X: PROHIBITED
$4X to 7X: HIGH-Z
2. $1X (“DEFECT” at SENS pin (Pin 24))
These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output.
The bit configuration is as follows
Sled kick height
Relative
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
value
(PS1)
(PS0)
0
0
0
1
TG1, TG2 Break
Sled kick
±1
0
0
circuit
height
±2
0
1
ON/OFF
ON/OFF
±3
1
0
±4
1
1
TG1, TG2
The purpose of these switches is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the occurrence of such frequently occurring phenomena as
extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should
be a 100-track jump to fall back down to a 10-track jump after a 100 or 10-track jump has been performed. To
do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of
the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope
and the tracking error is 180˚out-of-phase to cut the unneeded portion of the tracking error and apply braking.
– 23 –
CXA1982Q
[∗A]
RF_I 30
[∗B]
Envelope Detection
[∗D]
Tracking error
(TZC) 46
D2
Waveform Shaping
(MIRR)
[∗C]
[∗E]
Waveform Shaping
[∗F]
Edge Detection
D Q
[∗G]
BRK
TM7
Low: open
High: make
CK
(Latch)
CXA1982Q
Fig. 6. TMI movement during braking operation
From inner to outer track
From outer to inner track
[∗A]
[∗B]
[∗C]
(“MIRR”)
[∗D]
(“TZC”)
[∗E]
[∗F]
[∗G]
[∗H]
Braking is
applied from
here.
0V
Fig. 7. Internal waveform
3. $2X (“TZC” at SENS pin (Pin 24))
These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Tracking
control
00: OFF
01: Servo ON
10: F-JUMP
11: R-JUMP
↓
TM1, TM3, TM4
– 24 –
Sled
control
00: OFF
01: Servo ON
10: F-FAST FORWARD
11: R-FAST FORWARD
↓
TM2, TM5, TM6
CXA1982Q
CPU Serial Interface Timing Chart
D0
DATA
D1
tWCK
D2
D3
tWCK
tSU
D4
D5
D6
D7
D0
th
CLK
tCD
1/fck
tD
XLT
tWL
(VCC = 3.0V)
Item
Symbol
Min.
Type.
Max.
Unit
1
MHz
Clock frequency
fck
Clock pulse width
fwck
500
ns
Setup time
tsu
th
tD
tWL
tCD
500
ns
500
ns
500
ns
1000
ns
1000
ns
Hold time
Delay time
Latch pulse width
Data transfer interval
System Control
DATA
ADRESS
Item
D7 D6 D5 D4
D3
D2
D1
D0
0
0
0
FS4
FS1
DEFECT (FS3) FS2
0 Focus
Search
Disable = 1
Search
ON = 1, OFF = 0 Enable = 0
ON = 1, OFF = 0 Up = 1, Down = 0
Tracking Control 0
0
0
1
Tracking Mode 0
0
1
TG1, TG2
Brake
Sled
ON = 1, OFF = 0 ON = 1, OFF = 0 Kick + 2
0 Tracking Mode ∗1
Sled Mode ∗2
0
0
1
1
Focus Control
Select
∗1 TRACKING MODE
D2
OFF
0
0
ON
0
FWD JUMP
REV JUMP
FZC
DEFECT
TZC
—
Prohibited
∗2 SLED MODE
D3
Sled
Kick + 1
SENS
output
D1
D0
OFF
0
0
1
ON
0
1
1
0
FWD MOVE
1
0
1
1
REV MOVE
1
1
– 25 –
CXA1982Q
Serial Data Truth Table
Hex
Serial Data
FOCUS CONTROL
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
TRACKING MODE
Hex
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FS = 4321
DEFECT FS2
FS4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Functions
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
E
E
E
E
D
D
D
D
E
E
E
E
D
D
D
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TM = 6 5 4 3 2 1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
– 26 –
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
FS1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DEFECT
E: enable
D: disable
CXA1982Q
Initial State (resetting state)
ADDRESS
Item
DATA
HEXADECIMAL
D7 D6 D5 D4 D3 D2 D1 D0
Focus Control
0
0
0
0
0
0
0
0
$00
Tracking Control
0
0
0
1
0
0
0
0
$10
Tracking Mode
0
0
1
0
0
0
0
0
$20
0
0
1
1
0
1
1
1
$37
Select
1
0
0
0
$38
The above data means the following operation modes.
Focus Control
Tracking Control
Tracking Mode
Focus off, Defect enable, Focus Search off, Focus Search down
TG1 – TG2 off, Brake off, Sled Kick + 2 off, Sled Kick + 1 off
Tracking off, Sled off
– 27 –
CXA1982Q
Notes on Operation
1. FSET pin
The FSET pin determines the fc for the focus and tracking high-frequency phase compensation.
2. ISET pin
ISET current = 1.27V/R
= Focus search current
= Tracking jump current
1
= Sled kick current ($1X: PS1 = PS0 = 0) ×
2
Use the setting resistance within the range of 120kΩ to 240kΩ. If the resistance value is out of this range,
the oscillation may be occurred in the ISET block.
3. FE (focus error)/TE (tracking error) gain changing method
1) High gain: Resistance between FE pins (pins 6 and 7) 100kΩ → Large
Resistance between TE pins (pins 12 and 13) 100kΩ → Large
2) Low gain: A signal, whose resistance is divided between Pins 1 and 2, is input to FE.
The external variable resistor of TEO pin is used for TE.
The anti-shock circuit always operates in the CXA1982Q so that TG1 and TG2 (address 1 : D3) should
be set to 1 for tracking adjustment to prevent this effect.
When the anti-shock function is not used, Pin 45 (ATSC) should be fixed to VC.
4. Input voltage at Pins 19 to 22 of the microcomputer interface should be as follows:
VIH VCC × 90% or more
VIL VCC × 10% or less
5. Focus OK circuit
1) Refer to the “Description of Operation” for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
2) The equivalent circuit of the output pin (FOK) is as shown below.
VCC
20k
FOK
The FOK and comparator output are as follows:
Output voltage High: VFOKH ≈ near VCC
Output voltage Low: VFOKL ≈ Vsat (NPN)
25
40k
RL
100k
VCC
VEE
– 28 –
VEE
CXA1982Q
6. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.
Sled/Tracking internal phase compensation and reference design material
TRK
FCS
Item
SD
1.2kHz gain
08
1.2kHz phase
08
1.2kHz gain
25
1.2kHz phase
25
2.7kHz gain
25→13
2.7kHz phase
25→13
Measurement pin
6
13
Conditions
Typ.
Unit
CFLB = 0.1µF
CFGD = 0.1µF
21.5
dB
63
deg
13
dB
–125
deg
26.5
dB
–130
deg
CTGU = 0.1µF
– 29 –
CXA1982Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
13.5
37
48
+ 0.2
0.1 – 0.1
13
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
SONY CODE
QFP-48P-L04
EIAJ CODE
∗QFP048-P-1212-B
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
– 30 –