Ramtron FM21L16 2mbit f-ram memory Datasheet

Pre-Production
FM21L16
2Mbit F-RAM Memory
Features
2Mbit Ferroelectric Nonvolatile RAM
• Organized as 128Kx16
• Configurable as 256Kx8 Using /UB, /LB
• 1014 Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process
SRAM Compatible
• Industry Std. 128Kx16 SRAM Pinout
• 60 ns Access Time, 110 ns Cycle Time
Advanced Features
• Software Programmable Block Write Protect
Description
The FM21L16 is a 128Kx16 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make the
F-RAM superior to other types of memory.
Superior to Battery-backed SRAM Modules
• No Battery Concerns
• Monolithic Reliability
• True Surface Mount Solution, No Rework Steps
• Superior for Moisture, Shock, and Vibration
Low Power Operation
• 2.7V – 3.6V Power Supply
• Low Current Mode (5µA) using ZZ pin
• Low Active Current (8 mA typ.)
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 44-pin “Green”/RoHS TSOP-II package
The device is available in a 400 mil 44-pin TSOP-II
surface mount package. Device specifications are
guaranteed over industrial temperature range –40°C
to +85°C.
Pin Configuration
In-system operation of the FM21L16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The F-RAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM21L16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM21L16 includes a low voltage monitor that
blocks access to the memory array when VDD drops
below VDD min. The memory is protected against an
inadvertent access and data corruption under this
condition. The device also features softwarecontrolled write protection. The memory array is
divided into 8 uniform blocks, each of which can be
individually write protected.
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change the
specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Rev. 2.0
Apr. 2011
Ordering Information
FM21L16-60-TG
60 ns access, 44-pin
“Green”/RoHS TSOP-II
FM21L16-60-TGTR 60 ns access, 44-pin
“Green”/RoHS TSOP-II,
Tape & Reel
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 15
A(16:0)
A(16:2)
Block & Row Decoder
Address Latch & Write Protect
FM21L16 - 128Kx16 FRAM
16K x 16 block
16K x 16 block
16K x 16 block
16K x 16 block
16K x 16 block
16K x 16 block
16K x 16 block
16K x 16 block
A(1:0)
Column Decoder
CE
I/O Latch & Bus Driver
WE
UB, LB
2
DQ(15:0)
Control
Logic
OE
ZZ
Figure 1. Block Diagram
Pin Description
Pin Name
Type
A(16:0)
Input
/CE
Input
/WE
Input
/OE
Input
/ZZ
Input
DQ(15:0)
/UB
I/O
Input
/LB
Input
VDD
VSS
Rev. 2.0
Apr. 2011
Supply
Supply
Pin Description
Address inputs: The 17 address lines select one of 131,072 words in the F-RAM array. The
lowest two address lines A(1:0) may be used for page mode read and write operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is low
and /ZZ is high. The entire address is latched internally on the falling edge of /CE. Subsequent
changes to the A(1:0) address inputs allow page mode operation when /CE is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21L16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM21L16 drives the data bus when valid read data is
available. Deasserting /OE high tri-states the DQ pins.
Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for normal
read/write operation. If unused, tie /ZZ to VDD.
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z if /UB
is high. If the user does not perform byte writes and the device is not configured as a 256Kx8,
the /UB and /LB pins may be tied to ground.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z if /LB
is high. If the user does not perform byte writes and the device is not configured as a 256Kx8,
the /UB and /LB pins may be tied to ground.
Supply Voltage
Ground
Page 2 of 15
FM21L16 - 128Kx16 FRAM
Functional Truth Table 1,2
/CE
/WE
A(16:2)
X
X
X
H
X
X
H
V
↓
L
H
No Change
L
H
Change
L
V
↓
L
V
↓
L
No Change
↓
X
X
↑
A(1:0)
X
X
V
Change
V
V
V
V
X
/ZZ
L
H
H
H
H
H
H
H
H
Operation
Sleep Mode
Standby/Idle
Read
Page Mode Read
Random Read
/CE-Controlled Write
/WE-Controlled Write 2
Page Mode Write 3
Starts Precharge
Notes:
1)
2)
3)
4)
H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care.
/WE-controlled write cycle begins as a Read cycle and A(16:2) is latched then.
Addresses A(1:0) must remain stable for at least 10 ns during page mode operation.
For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
Byte Select Truth Table
/WE
/OE
/LB
H
H
X
X
H
H
L
H
L
L
L
X
H
L
L
/UB
X
H
L
H
L
L
H
L
Operation
Read; Outputs Disabled
Read upper byte; Hi-Z lower byte
Read lower byte; Hi-Z upper byte
Read both bytes
Write upper byte; Mask lower byte
Write lower byte; Mask upper byte
Write both bytes
Note: Assumes /CE is low and /ZZ is high for all cases. The /UB and /LB pins may be
grounded if 1) the system does not perform byte writes and 2) the device is not
configured as a 256Kx8.
Figure 2. Simplified Sleep/Standby State Diagram
Rev. 2.0
Apr. 2011
Page 3 of 15
FM21L16 - 128Kx16 FRAM
Overview
The FM21L16 is a wordwide F-RAM memory
logically organized as 131,072 x 16 and accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(16:2) changes.
Memory Operation
Users access 131,072 memory locations, each with 16
data bits through a parallel interface. The F-RAM
array is organized as 8 blocks each having 4096 rows.
Each row has 4 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle /CE. When /CE is
deasserted high, a precharge operation begins. Writes
occur immediately at the end of the access with no
delay. The /WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique
to F-RAM called NoDelayTM writes.
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random location (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is tRC. Note that unlike SRAMs, the
FM21L16’s /CE-initiated access time is faster than
the address cycle time.
The FM21L16 will drive the data bus when /OE and
at least one of the byte enables (/UB, /LB) is asserted
low. The upper data byte is driven when /UB is low,
and the lower data byte is driven when /LB is low. If
/OE is asserted after the memory access time has been
satisfied, the data bus will be driven with valid data.
If /OE is asserted prior to completion of the memory
access, the data bus will not be driven until valid data
is available. This feature minimizes supply current in
the system by eliminating transients caused by invalid
data being driven onto the bus. When /OE is
deasserted high, the data bus will remain in a high-Z
state.
Write Operation
Writes occur in the FM21L16 in the same time
interval as reads. The FM21L16 supports both /CERev. 2.0
Apr. 2011
and /WE-controlled write cycles. In both cases, the
address A(16:2) is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM21L16 will not
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is deasserted high. In a /WE-controlled write, the
memory cycle begins on the falling edge of /CE. The
/WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown in the Electrical
Specifications section.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (rising
edge of /WE or /CE).
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The F-RAM array is organized as 8 blocks each
having 4096 rows. Each row has 4 column address
locations. Address inputs A(1:0) define the column
address to be accessed. An access can start on any
column address, and other column locations may be
accessed without the need to toggle the /CE pin. For
fast access reads, once the first data byte is driven
onto the bus, the column address inputs A(1:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins no later than tAAP, which is less
than half the initial read access time. For fast access
writes, the first write pulse defines the first write
access. While /CE is low, a subsequent write pulse
along with a new column address provides a page
mode write access.
Page 4 of 15
FM21L16 - 128Kx16 FRAM
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time tPC.
Precharge is also activated by changing the upper
addess A(16:2). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
the new read data is valid within the tAA address
access time. Refer to the Read Cycle Timing 1
diagram on page 10. Likewise a similar sequence
occurs for write cycles. Refer to the Write Cycle
Timing 3 diagram on page 12. The rate at which
random addresses can be issued is tRC and tWC,
respectively.
Sleep Mode
The device incorporates a sleep mode of operation
which allows the user to achieve the lowest power
supply current condition. It enters a low power sleep
mode by asserting the /ZZ pin low. Read and write
operations must complete prior to the /ZZ pin going
low. Once /ZZ is low, all pins are ignored except the
/ZZ pin. When /ZZ is deasserted high, there is some
time delay (tZZEX) before the user can access the
device.
If Sleep Mode is not used, the /ZZ pin should be tied
to VDD.
Software Write Protection
The 128Kx16 address space is divided into 8 sectors
(blocks) of 16Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
Rev. 2.0
Apr. 2011
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
address is a don’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. The
data byte must be driven to the lower 8-bits of the
data bus, DQ(7:0). Setting a bit to 1 write protects the
corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
Write Protect Sectors – 16K x16 blocks
Sector 7
1FFFFh – 1C000h
Sector 6
1BFFFh – 18000h
Sector 5
17FFFh – 14000h
Sector 4
13FFFh – 10000h
Sector 3
0FFFFh – 0C000h
Sector 2
0BFFFh – 08000h
Sector 1
07FFFh – 04000h
Sector 0
03FFFh – 00000h
The write-protect read address sequence follows:
1.
12555h *
2.
1DAAAh
3.
01333h
4.
0ECCCh
5.
000FFh
6.
1FF00h
7.
1DAAAh
8.
0ECCCh
9.
0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 12555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 1032 chance of randomly accessing
exactly the 1st six addresses. The odds are further
Page 5 of 15
FM21L16 - 128Kx16 FRAM
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write protect operation is shown in
Figure 3. The write-protect settings are nonvolatile.
The factory default: all blocks are unprotected.
Figure 3. Write-Protect State Machine
For example, the following sequence write-protects addresses from 0C000h to 13FFFh (sectors 3 & 4):
Read
Read
Read
Read
Read
Read
Write
Write
Write
Read
Rev. 2.0
Apr. 2011
Address
12555h
1DAAAh
01333h
0ECCCh
000FFh
1FF00h
1DAAAh
0ECCCh
0FF00h
00000h
Data
18h
E7h
-
;
;
;
;
bits 3 & 4 = 1
complement of 18h
Data is don’t care
return to Normal Operation
Page 6 of 15
FM21L16 - 128Kx16 FRAM
Figure 4. Sequence to Set Write-Protect Blocks
Note: This sequence requires tAS ≥ 10ns and address must be stable while /CE is low.
Figure 5. Sequence to Read Write-Protect Settings
Note: This sequence requires tAS ≥ 10ns and address must be stable while /CE is low.
Rev. 2.0
Apr. 2011
Page 7 of 15
FM21L16 - 128Kx16 FRAM
SRAM Drop-In Replacement
The FM21L16 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require /CE to toggle for each new
address. /CE may remain low for as long as 10µs.
While /CE is low, the device automatically detects
address changes and a new access is begun. It also
allows page mode operation at speeds up to 33MHz.
The user must be sure /CE is not low at powerup
or powerdown events. If /CE and /WE are both
low during power cycles, data corruption will
occur. Figure 6 shows a pullup resistor on /CE
which will keep the pin high during power cycles
assuming the MCU/MPU pin is tri-stated during
the system reset. The pullup resistor value should
be chosen to ensure the /CE pin tracks VDD yet a
high enough value that the current drawn when
/CE is low is not an issue. A 10K ohm resistor
draws 330µA when /CE is low and VDD=3.3V.
VDD
R
only during memory accesses. The FM21L16 draws
supply current while /CE is low, even if addresses and
control signals are static. While /CE is high, the
device draws no more than the maximum standby
current ISB.
The FM21L16 is backward compatible with the
1Mbit FM20L08 and 256Kbit FM18L08 devices.
That is, operating the FM21L16 with /CE toggling
low on every address is perfectly acceptable.
The /UB and /LB byte select pins are active for both
read and write cycles. They may be used to allow the
device to be wired as a 256Kx8 memory. The upper
and lower data bytes can be tied together and
controlled with the byte selects. Individual byte
enables or the next higher address line A(17) may be
available from the system processor.
FM21L16
CE
MCU/
MPU
WE
OE
A(16:0)
DQ
Figure 7. FM21L16 Wired as 256Kx8
Figure 6. Use of Pullup Resistor on /CE
For applications that require the lowest power
consumption, the /CE signal should be active (low)
Rev. 2.0
Apr. 2011
Page 8 of 15
FM21L16 - 128Kx16 FRAM
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any signal pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-F)
- Charged Device Model (JEDEC Std JESD22-C101-D)
- Machine Model (JEDEC Std JESD22-A115-A)
Package Moisture Sensitivity Level
Ratings
-1.0V to +4.5V
-1.0V to +4.5V and
VIN < VDD+1V
-55°C to +125°C
260° C
2.5kV
800V
200V
MSL-3
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol Parameter
Min
Typ
Max
Units Notes
VDD
Power Supply
2.7
3.3
3.6
V
IDD
Power Supply Current
8
12
mA
1
ISB
Standby Current
2
@ TA = 25°C
90
150
µA
@ TA = 85°C
270
µA
IZZ
Sleep Mode Current
3
@ TA = 25°C
5
µA
@ TA = 85°C
8
µA
ILI
Input Leakage Current
4
±1
µA
ILO
Output Leakage Current
4
±1
µA
VIH
Input High Voltage
2.2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.6
V
VOH1
Output High Voltage (IOH = -1.0 mA)
2.4
V
VOH2
Output High Voltage (IOH = -100 µA)
VDD-0.2
V
VOL1
Output Low Voltage (IOL = 2.1 mA)
0.4
V
VOL2
Output Low Voltage (IOL = 100 µA)
0.2
V
Notes
1. VDD = 3.6V, /CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or VDD-0.2V), all DQ pins unloaded.
2. VDD = 3.6V, /CE at VDD, All other pins are static and at CMOS levels (0.2V or VDD-0.2V), /ZZ is high.
3. VDD = 3.6V, /ZZ is low, all other inputs at CMOS levels (0.2V or VDD-0.2V).
4. VIN, VOUT between VDD and VSS.
Rev. 2.0
Apr. 2011
Page 9 of 15
FM21L16 - 128Kx16 FRAM
Read Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
tRC
tCE
tAA
tOH
tAAP
tOHP
tCA
tPC
tBA
tAS
tAH
tOE
tHZ
tOHZ
tBHZ
Parameter
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Hold Time
Page Mode Address Access Time
Page Mode Output Hold Time
Chip Enable Active Time
Precharge Time
/UB, /LB Access Time
Address Setup Time (to /CE low)
Address Hold Time (/CE-controlled)
Output Enable Access Time
Chip Enable to Output High-Z
Output Enable High to Output High-Z
/UB, /LB High to Output High-Z
Min
110
20
5
60
50
0
60
-
Max
60
110
25
10,000
20
15
10
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
Write Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
tWC
tCA
tCW
tPC
tPWC
tWP
tAS
tASP
tAHP
tWLC
tBLC
tWLA
tAWH
tDS
tDH
tWZ
tWX
tWS
tWH
Parameter
Write Cycle Time
Chip Enable Active Time
Chip Enable to Write Enable High
Precharge Time
Page Mode Write Enable Cycle Time
Write Enable Pulse Width
Address Setup Time (to /CE low)
Page Mode Address Setup Time (to /WE low)
Page Mode Address Hold Time (to /WE low)
Write Enable Low to /CE High
/UB, /LB Low to /CE High
Write Enable Low to A(16:2) Change
A(16:2) Change to Write Enable High
Data Input Setup Time
Data Input Hold Time
Write Enable Low to Output High Z
Write Enable High to Output Driven
Write Enable to /CE Low Setup Time
Write Enable to /CE High Hold Time
Min
110
60
60
50
25
16
0
8
15
25
25
25
110
14
0
10
0
0
Max
10,000
10
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
2
2
Notes
1. This parameter is characterized but not 100% tested.
2. The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. The parameters tWS and tWH
are not tested.
Capacitance
Symbol
CI/O
CIN
CZZ
Rev. 2.0
Apr. 2011
(TA = 25° C , f=1 MHz, VDD = 3.3V)
Parameter
Input/Output Capacitance (DQ)
Input Capacitance
Input Capacitance of /ZZ pin
Min
-
Max
8
6
8
Units
pF
pF
pF
Notes
Page 10 of 15
FM21L16 - 128Kx16 FRAM
Power Cycle and Sleep Mode Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
tPU
Power Up (after VDD min. is reached) to First Access Time
450
µs
tPD
Last Write (/WE high) to Power Down Time
0
µs
tVR
VDD Rise Time
50
1,2
µs/V
tVF
VDD Fall Time
100
1,2
µs/V
tZZH
/ZZ Active to DQ Hi-Z Time
20
ns
tWEZZ
Last Write to Sleep Mode Entry Time
0
µs
tZZL
/ZZ Active Low Time
1
µs
tZZEN
Sleep Mode Entry Time (/ZZ low to /CE don’t care)
0
µs
tZZEX
Sleep Mode Exit Time (/ZZ high to 1st access after wakeup)
450
µs
Notes
1. Slope measured at any point on VDD waveform.
2. Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Data Retention
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
0 to 3V
3 ns
Min
10
Units
Years
Input and Output Timing Levels
Output Load Capacitance
Notes
1.5V
30pF
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
Rev. 2.0
Apr. 2011
Page 11 of 15
FM21L16 - 128Kx16 FRAM
Page Mode Read Cycle Timing
Although sequential column addressing is shown, it is not required.
Write Cycle Timing 1 (/WE-Controlled) Note: /OE (not shown) is low only to show effect of /WE on DQ pins
Write Cycle Timing 2 (/CE-Controlled)
tCA
tPC
CE
tAS
tBLC
A(17:0)
tWH
WE
tWS
tDS
DQ(15:0)
tDH
D in
UB/LB
Rev. 2.0
Apr. 2011
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FM21L16 - 128Kx16 FRAM
Write Cycle Timing 3 (/CE low) Note: /OE (not shown) is low only to show effect of /WE on DQ pins
Page Mode Write Cycle Timing
Although sequential column addressing is shown, it is not required.
Power Cycle and Sleep Mode Enter/Exit Timing
Rev. 2.0
Apr. 2011
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FM21L16 - 128Kx16 FRAM
Mechanical Drawing
44-pin TSOP-II (Complies with JEDEC Standard MS-024g Var. AC)
Recommended PCB Footprint
Pin 1
0.45
0.30
18.41
BASIC
0.80
BSC
0.8
0.5
1.50
10.16 BSC
11.96
11.56
12.6
1.20 max
0.15
0.05
0.20
0.12
0.10 mm
0°-8°
0.6
0.4
Note: All dimensions in millimeters.
TSOP-II Package Marking Scheme
RAMTRON
XXXXXXX-S-P
LLLLLLL
YYWW
Legend:
XXXXXX= part number, S= speed, P=package
LLLLLL= lot code, YY=year, WW=work week
Examples: FM21L16, 60ns access time, “Green”/RoHS TSOP-II package,
Lot 6340282, Year 2007, Work Week 31
RAMTRON
FM21L16-60-TG
6340282
0731
Rev. 2.0
Apr. 2011
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FM21L16 - 128Kx16 FRAM
Revision History
Revision
1.0
1.1
1.2
Date
9/24/2007
12/12/2007
12/22/2009
2.0
4/4/2011
Rev. 2.0
Apr. 2011
Summary
Initial release.
Added package MSL rating and placeholder for ESD ratings.
Lowered IDD limit. Added UB/LB signals to timing diagrams and added
timing parameters to AC table. Expanded explanation of precharge operation.
Updated lead temperature rating in Abs Max table. Removed VTP spec. Added
tape & reel ordering information.
Pre-Production status. Added ESD ratings. Modified write-protect flow
diagram and added read sequence diagram. Made clarifications to Byte Select
truth table. Added max. CE active time.
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