ON NCV4269CD150R2G 5.0 v micropower 150 ma ldo linear regulator with delay, adjustable reset and sense output Datasheet

NCV4269C
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
The NCV4269C is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 125 mA with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of an
external resistor divider to the RADJ lead. The regulator is protected
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
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MARKING
DIAGRAM
8
8
1
•
•
•
•
•
•
•
5.0 V ± 2.0% Output
Low 125 mA Quiescent Current
Active Reset Output Low Down to VQ = 1.0 V
Adjustable Reset Threshold
150 mA Output Current Capability
Fault Protection
♦ +60 V Peak Transient Voltage
♦ −40 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
Early Warning through SI/SO Leads
Internally Fused Leads in SO−14 Package
Integrated Pullup Resistor at Logic Outputs (To Use External
Resistors, Select the NCV4279C)
Very Low Dropout Voltage
Electrical Parameters Guaranteed Over Entire Temperature Range
AEC−Q100 Grade 1 Qualified and PPAP Capable
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 3
1
4269C5
ALYW
G
1
8
8
1
SO−8
EXPOSED PAD
PD SUFFIX
CASE 751AC
4269C5
ALYW
G
1
14
SO−14
D2 SUFFIX
CASE 751A
14
1
NCV4269C5G
AWLYWW
1
Features
•
•
•
•
•
•
SO−8
D1 SUFFIX
CASE 751
14
1
TSSOP−14 EP
PA SUFFIX
CASE 948AW
A
WL, L
Y
WW, W
G, G
V426
9C50
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb Free
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Publication Order Number:
NCV4269C/D
NCV4269C
I
Q
Error
Amplifier
Current and
Saturation
Control
Reference
and Trim
RSO
RRO
RO
D
or
Reference
SO
RADJ
+
SI
−
GND
Figure 1. Block Diagram
PIN CONNECTIONS
1
I
1
8
SI
RADJ
Q
SO
RO
D
14
RADJ
D
GND
GND
GND
GND
RO
GND
SO−8
SI
I
GND
GND
GND
Q
SO
1
14
RADJ
NC
D
GND
NC
NC
RO
SI
I
NC
Q
NC
NC
SO
TSSOP−14 EP
SO−14
PACKAGE PIN DESCRIPTION
Package Pin Number
SO−8
SO−8 EP
SO−14
TSSOP14
Pin
Symbol
3
3
1
1
RADJ
4
4
2
3
D
5
5
3, 4, 5, 6,
10, 11, 12
4
GND
−
−
−
2, 5, 6, 9,
10, 12
NC
No connection to these pins from the IC.
6
6
7
7
RO
Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor to
Q. Leave Open if Not Used.
7
7
8
8
SO
Sense Output; This Open−Collector Output is Internally Pulled Up by 20 kW
pullup resistor to Q. If not used, keep open.
8
8
9
11
Q
5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 2.5 W.
1
1
13
13
I
Input; Connect to GND Directly at the IC with Ceramic Capacitor.
2
2
14
14
SI
−
EPAD
−
EPAD
EPAD
Function
Reset Threshold Adjust; if not used to connect to GND.
Reset Delay; To Set Time Delay, Connect to GND with Capacitor
Ground
Sense Input; If not used, Connect to Q.
Connect to ground potential or leave unconnected
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2
NCV4269C
MAXIMUM RATINGS (TJ = −40°C to 150°C)
Symbol
Min
Max
Unit
Input to Regulator
VI
II
−40
Internally Limited
45
Internally Limited
V
Input Transient to Regulator (Note 3)
VI
−
60
V
Sense Input
VSI
ISI
−40
−1
45
1
V
mA
VRADJ
IRADJ
−0.3
−10
7
10
V
mA
Reset Delay
VD
ID
−0.3
Internally Limited
7
Internally Limited
V
Ground
Iq
50
−
mA
Reset Output
VRO
IRO
−0.3
Internally Limited
7
Internally Limited
V
Sense Output
VSO
ISO
−0.3
Internally Limited
7
Internally Limited
V
Regulated Output
VQ
IQ
−0.5
−10
7
−
V
mA
TJ
TSTG
−
−50
150
150
°C
°C
VI
TJ
−
−40
45
150
V
°C
Parameter
Reset Threshold Adjust
Junction Temperature
Storage Temperature
Input Voltage Operating Range
Junction Temperature Operating Range
LEAD TEMPERATURE SOLDERING AND MSL
Symbol
Value
MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 4)
MSL
1
MSL, 8−Lead EP, LS Temperature 260°C
MSL
2
Parameter
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 4.0 kV per AEC−Q100−002.
Machine Model (MM) ≤ 200 V per AEC−Q100−003.
2. Latchup tested per AEC−Q100−004.
3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class A according to ISO16750−1.
4. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Values)
Unit
Junction−to−Pin 6 (Y − JL6, YL6)
58.3
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
151.1
°C/W
SO−8 Package (Note 5)
SO−8 EP Package (Note 5)
47
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
131.6
°C/W
Junction−to−Pad (Y − JPad)
16.3
°C/W
Junction−to−Pin 4 (Y − JL4, YL4)
19.5
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
100.9
°C/W
Junction−to−Pin 3 (Y − JL3, YL3)
19.3
°C/W
Junction−to−Ambient Thermal Resistance (RqJA, qJA)
77.3
°C/W
Junction−to−Pad (Y − JPad)
12.6
°C/W
Junction−to−Pin 8 (Y − JL8, YL8)
SO−14 Package (Note 5)
TSSOP−14 EP Package (Note 5)
5. 2 oz copper, 150
mm2
copper area, 1.5 mm thick FR4
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NCV4269C
ELECTRICAL CHARACTERISTICS (TJ = −40°C ≤ TJ ≤ 150°C, VI = 13.5 V unless otherwise specified)
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
VQ
1 mA v IQ v 100 mA 6 V v VI v 16 V
4.90
5.00
5.10
V
Current Limit
IQ
−
150
430
500
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 1 mA, RO, SO High
−
125
250
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 10 mA, RO, SO High
−
230
450
mA
Current Consumption; Iq = II – IQ
Iq
IQ = 50 mA, RO, SO High
−
0.9
3.0
mA
Dropout Voltage
Vdr
VI = 5 V, IQ = 100 mA
−
0.23
0.5
V
Load Regulation
DVQ
IQ = 5 mA to 100 mA
−
1
20
mV
Line Regulation
DVQ
VI = 6 V to 26 V IQ = 1 mA
−
1
30
mV
VRT
−
4.50
4.65
4.80
V
Characteristic
REGULATOR
RESET GENERATOR
Reset Switching Threshold
Reset Adjust Switching Threshold
VRADJ,TH
VQ > 3.5 V
1.26
1.35
1.44
V
Reset Pullup Resistance
RRO,INT
−
10
20
40
kW
Reset Output Saturation Voltage
VRO,SAT
VQ < VRT, RRO, INT
−
0.03
0.4
V
Upper Delay Switching Threshold
VUD
−
1.4
1.8
2.2
V
Lower Delay Switching Threshold
VLD
−
0.3
0.45
0.60
V
VD,SAT
VQ < VRT
−
−
0.1
V
Saturation Voltage on Delay Capacitor
ID,C
VD = 1 V
3.0
6.5
9.5
mA
Delay Time L ³ H
td
CD = 100 nF
17
28
73
ms
Delay Time H ³ L
tRR
CD = 100 nF
−
1.5
−
ms
VSI,High
−
1.24
1.31
1.38
V
Charge Current
INPUT VOLTAGE SENSE
Sense Threshold High
Sense Threshold Low
VSI,Low
−
1.16
1.20
1.28
V
Sense Output Saturation Voltage
VSO,Low
VSI < 1.20 V; VQ > 3 V; RSO,INT
−
0.03
0.4
V
Sense Resistor Pullup
RSO,INT
−
10
20
40
kW
ISI
−
−1.0
0.1
1.0
mA
TSD
Iout = 1 mA
150
−
200
°C
Sense Input Current
THERMAL SHUTDOWN
Thermal Shutdown Temperature (Note 6)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Values based on design and/or characterization.
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NCV4269C
II
I
CI
470 nF
1000 mF
IQ
Q
CQ
22 mF
RADJ1
ISI
VI
SI
D
GND
ID
VSI
RADJ
SO
RO
Iq
VRO
IRADJ
VQ
VSO
VRADJ
VD
CD
100 nF
RADJ2
Figure 2. Measuring Circuit
VI
t
< tRR
VQ
VRT
t
dV
I
+ D
dt
CD
VD
VUD
VLD
t
td
tRR
VRO
VRO,SAT
Power−on−Reset
t
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Figure 3. Reset Timing Diagram
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Secondary
Spike
Overload
at Output
NCV4269C
Sense Input Voltage
VSI,High
VSI,Low
t
Sense Output Voltage
High
Low
t
Figure 4. Sense Timing Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
3.2
VI = 13.5 V
VD = 1.0 V
14
VD, DELAY THRESHOLD(V)
ID,C, CHARGE CURRENT (mA)
16
12
10
8
6
4
2
0
−40
0
40
80
120
2.8
2.4
2.0
VUD
1.6
1.2
0.8
VLD
0.4
0
−40
160
VI = 13.5 V
0
40
80
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Charge Current ID,C vs. Temperature TJ
Figure 6. Switching Voltage VUD and VLD vs.
Temperature TJ
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6
160
NCV4269C
TYPICAL PERFORMANCE CHARACTERISTICS
1.7
400
TJ = 125°C
300
TJ = 25°C
VRADJ,TH, RESET ADJUST
SWITCHING THRESHOLD (V)
Vdr, DROPOUT VOLTAGE (mV)
500
200
TJ = −40°C
100
0
0
30
60
90
120
150
1.5
1.4
1.3
1.2
1.1
1.0
0.9
−40
180
0
80
120
IQ, OUTPUT CURRENT (mA)
Figure 7. Drop Voltage Vdr vs. Output Current IQ
Figure 8. Reset Adjust Switching Threshold,
VRADJ,TH vs. Temperature TJ
160
12
TJ = 25°C
TJ = 25°C
VQ, OUTPUT VOLTAGE (V)
12
10
8
RL = 100 W
6
RL = 33 W
4
RL = 200 W
RL = 50 W
2
0
10
8
6
4
2
0
0
5
15
10
20
25
30
35
40
RL = 50 W
45
0
2
VI, INPUT VOLTAGE (V)
4
6
8
10
VI, INPUT VOLTAGE (V)
Figure 10. Output Voltage VQ vs. Input Voltage VI
Figure 9. Current Consumption Iq vs. Input
Voltage VI
1.6
5.2
VI = 13.5 V
1.5
VQ, OUTPUT VOLTAGE (V)
VSI, SENSE INPUT THRESHOLD (V)
40
TJ, JUNCTION TEMPERATURE (°C)
14
Iq, CURRENT CONSUMPTION (mA)
1.6
1.4
VSI, High
1.3
VSI, Low
1.2
1.1
1.0
−40
0
40
80
120
5.1
VI = 13.5 V
IQ = 1 mA
5.0
4.9
4.8
4.7
4.6
−40
160
TJ, JUNCTION TEMPERATURE (°C)
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Sense Threshold VSI vs. Temperature TJ
Figure 12. Output Voltage VQ vs. Temperature TJ
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NCV4269C
TYPICAL PERFORMANCE CHARACTERISTICS
4.0
350
Iq, CURRENT CONSUMPTION (mA)
IQ, OUTPUT CURRENT (mA)
400
TJ = 125°C
300
TJ = 25°C
250
200
150
VQ = 0 V
100
50
0
0
5
10
15
20
25
30
35
40
45
2.0
1.5
1.0
0.5
0
20
40
80
60
120
100
IQ, OUTPUT CURRENT (mA)
Figure 13. Output Current IQ vs. Input Voltage VI
Figure 14. Current Consumption Iq vs. Output
Current IQ
3.0
Iq, CURRENT CONSUMPTION (mA)
Iq, CURRENT CONSUMPTION (mA)
2.5
VI, INPUT VOLTAGE (V)
VI = 13.5 V
TJ = 25°C
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
20
40
30
TJ = 125°C
2.5
IQ = 100 mA
2.0
1.5
1.0
IQ = 50 mA
0.5
IQ = 10 mA
0
50
6
8
10
14
16
18
20
22
VI, INPUT VOLTAGE (V)
Figure 15. Current Consumption Iq vs.
Output Current IQ
Figure 16. Quiescent Current Iq vs.
Input Voltage VI
24
26
100
TJ = 25°C
Unstable Region
10
ESR (W)
200
150
IQ = 100 mA
1
Stable Region for
2.2 mF to 10 mF
0.1
100
50
6
12
IQ, OUTPUT CURRENT (mA)
250
Iq, CURRENT CONSUMPTION (mA)
VI = 13.5 V
TJ = 25°C
3.0
0
50
1.6
0
3.5
0.01
8
10
12
14
16
18
20
22
24
26
0
25
50
75
100
125
VI, INPUT VOLTAGE (V)
IQ, OUTPUT CURRENT (mA)
Figure 17. Quiescent Current Iq vs. Input Voltage VI
Figure 18. Output Stability, Capacitance ESR
vs. Output Load Current
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150
NCV4269C
TYPICAL THERMAL CHARACTERISTICS
200
180
160
qJA (°C/W)
140
120
100
80
60
40
20
0
0
100
200
300
400
500
600
700
COPPER HEAT−SPREADER AREA (mm2)
SO−8 Std Package NCV4269C, 1.0 oz
SO−8 Std Package NCV4269C, 2.0 oz
TSSOP−14 EP Package NCV4269C, 1.0 oz
TSSOP−14 EP Package NCV4269C, 2.0 oz
SO−8 EP Package NCV4269C, 1.0 oz
SO−8 EP Package NCV4269C, 2.0 oz
SO−14 w/6 Thermal Leads NCV4269C, 1.0 oz
SO−14 w/6 Thermal Leads NCV4269C, 2.0 oz
Figure 19. Junction−to−Ambient Thermal Resistance (qJA) vs. Heat Spreader Area
1000
R(t) (°C/W)
100
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (s)
Single Pulse (SO−8 Std Package) PCB = 150 mm2, 2.0 oz
Single Pulse (TSSOP−14 EP Package) PCB = 150 mm2, 2.0 oz
Single Pulse (SO−8 EP Package) PCB = 150 mm2, 2.0 oz
Single Pulse (SO−14 w/6 TL Package) PCB = 150 mm2, 2.0 oz
Figure 20. R(t) vs. Pulse Time
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1
10
100
1000
NCV4269C
APPLICATION DESCRIPTION
OUTPUT REGULATOR
If the reset adjust option is not needed, the RADJ pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
The output is controlled by a precision trimmed reference.
The PNP output has base drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead D
provides charge current ID,C (typically 6.5 mA) to the
external delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (VRT, reset
threshold voltage) has been violated. When the
delay capacitor discharges to VLD, the reset signal
RO pulls low.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage VQ
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer VD
passes VUD, the reset signal RO goes high. A discharge of
the delay timer VD is started when VQ drops and stays below
the reset threshold voltage VRT. When the voltage of the
delay timer VD drops below the lower threshold voltage VLD
the reset output voltage VRO is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor
with an internal 20 kW pullup resistor connected to the
output Q, controlled by a low voltage detection circuit. The
circuit is functionally independent of the rest of the IC,
thereby guaranteeing that RO is valid for VQ as low as 1.0 V.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of VDSAT to
the higher level VUD. The time delay follows the equation:
td + [CD (VUD * VD, SAT)]ńID, C
Example:
Using CD = 100 nF.
Use the typical value for VD,SAT = 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.
RESET ADJUST (RADJ)
The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 21. The resistor divider keeps the voltage
above the VRADJ,TH (typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
VBAT
(eq. 1)
I
CI*
td + [100 nF (1.8 * 0.1 V)] ń 6.5 mA + 26.2 ms
Q
VDD
RADJ1
0.1 mF
RADJ
RADJ2
NCV4269C
RSI1
CQ**
10 mF
(2.2 mF)
Microprocessor
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) ń RADJ2
SI
RSI2
D
CD
RO
SO
(eq. 2)
GND
I/O
I/O
*CI required if regulator is located far from the power supply filter.
** CQ − minimum cap required for stability is 2.2 mF while higher over/under−shoots may be
expected. Cap must operate at minimum temperature expected.
Figure 21. Application Diagram
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10
(eq. 3)
NCV4269C
SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE
MONITOR
(−25°C to −40°C), both the value and ESR of the capacitor
will vary considerably. The capacitor manufacturer’s data
sheet usually provides this information.
The 10 mF output capacitor CQ shown in Figure 21 should
work for most applications; however, it is not necessarily the
optimized solution. Stability is guaranteed at CQ is min
2.2 mF and max ESR is 2.5 W. There is no min ESR limit
which was proved with MURATA’s ceramic caps
GRM31MR71A225KA01 (2.2 mF, 10 V, X7R, 1206) and
GRM31CR71A106KA01 (10 mF, 10 V, X7R, 1206) directly
soldered between output and ground pins.
An on−chip comparator is available to provide early
warning to the microprocessor of a possible reset signal
(Figure 4). The output is from an open collector driver with
an internal 20 kW pull up resistor to output Q. The reset signal
typically turns the microprocessor off instantaneously. This
can cause unpredictable results with the microprocessor. The
signal received from the SO pin will allow the microprocessor
time to complete its present task before shutting down. This
function is performed by a comparator referenced to the band
gap voltage. The actual trip point can be programmed
externally using a resistor divider to the input monitor SI
(Figure 21). The values for RSI1 and RSI2 are selected for a
typical threshold of 1.20 V on the SI Pin.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 21) is:
SIGNAL OUTPUT
PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max) Iq (eq. 4)
Figure 22 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 21. As the output
voltage (VQ) falls, the monitor threshold (VSI,Low), is
crossed. This causes the voltage on the SO output to go low
sending a warning signal to the microprocessor that a reset
signal may occur in a short period of time. TWARNING is the
time the microprocessor has to complete the function it is
currently working on and get ready for the reset
shutdown signal. When the voltage on the SO goes low and
the RO stays high the current consumption is typically
530 mA at 1 mA load current.
where:
VI(max) is the maximum input voltage,
VQ(min) is the minimum output voltage,
IQ(max) is the maximum output current for the application,
and Iq is the quiescent current the regulator consumes at
IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA = (150°C – TA) / PD
(eq. 5)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heatsink will be required. The current
flow and voltages are shown in the Measurement Circuit
Diagram.
VQ
SI
VSI,Low
HEATSINKS
VRO
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
SO
TWARNING
Figure 22. SO Warning Waveform Time Diagram
RqJA + RqJC ) RqCS ) RqSA
(eq. 6)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heat sink thermal resistance, and
RqSA = the heat sink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in data sheets of
heatsink manufacturers. Thermal, mounting, and
heatsinking considerations are discussed in the
ON Semiconductor application note AN1040/D, available
on the ON Semiconductor website.
STABILITY CONSIDERATIONS
The input capacitor CI in Figure 21 is necessary for
compensating input line reactance. Possible oscillations caused
by input inductance and input capacitance can be damped by
using a resistor of approximately 1.0 W in series with CI.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. The
aluminum electrolytic capacitor is the least expensive
solution, but, if the circuit operates at low temperatures
www.onsemi.com
11
NCV4269C
ORDERING INFORMATION
Package
Shipping†
NCV4269CD150R2G
SO−8
(Pb−Free)
2500 / Tape & Reel
NCV4269CPD50R2G
SO−8 EP
(Pb−Free)
2500 / Tape & Reel
NCV4269CD250R2G
SO−14
(Pb−Free)
2500 / Tape & Reel
NCV4269CPA50R2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
Device
Output Voltage
5.0 V
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
12
NCV4269C
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
13
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCV4269C
PACKAGE DIMENSIONS
SOIC−8 EP
CASE 751AC
ISSUE B
2X
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
0.10 C A-B
D
8
E1
2X
0.10 C D
1
F
EXPOSED
PAD
5
ÉÉÉ
ÉÉÉ
PIN ONE
LOCATION
DETAIL A
D
A
5
8
G
E
h
2X
4
4
0.20 C
e
8X b
0.25 C A-B D
B
1
BOTTOM VIEW
A
END VIEW
TOP VIEW
0.10 C
A2
b1
GAUGE
PLANE
0.10 C
L
SEATING
PLANE
C
SIDE VIEW
ÉÉ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
c
H
A
8X
A
A1
0.25
(L1)
DETAIL A
q
c1
(b)
SECTION A−A
SOLDERING FOOTPRINT*
2.72
0.107
1.52
0.060
7.0
0.275
Exposed
Pad
4.0
0.155
2.03
0.08
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
14
DIM
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
F
G
h
q
MILLIMETERS
MIN
MAX
1.35
1.75
0.00
0.10
1.35
1.65
0.31
0.51
0.28
0.48
0.17
0.25
0.17
0.23
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.40
1.27
1.04 REF
2.24
3.20
1.55
2.51
0.25
0.50
0_
8_
NCV4269C
PACKAGE DIMENSIONS
TSSOP−14 EP
CASE 948AW
ISSUE C
B
NOTE 6
14
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
ÇÇÇ
b
8
b1
E1
c1
E
NOTE 5
SECTION B−B
c
NOTE 8
PIN 1
REFERENCE
1
7
0.20 C B A
e
2X 14 TIPS
TOP VIEW
NOTE 6
A
0.05 C
0.10 C
14X
D
A2
NOTE 4
A
DETAIL A
B
M
14X b
0.10 C B
S
A
S
C
SEATING
PLANE c
B
NOTE 3
END VIEW
SIDE VIEW
D2
H
E2
L2
A1
L
NOTE 7
C
GAUGE
PLANE
DETAIL A
BOTTOM VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.07 mm MAX. AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 mm PER SIDE. DIMENSION D IS DETERMINED AT
DATUM H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. DIMENSION E1 IS DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM
THE SEATING PLANE TO THE LOWEST POINT ON THE
PACKAGE BODY.
8. SECTION B−B TO BE DETERMINED AT 0.10 TO 0.25 mm
FROM THE LEAD TIP.
DIM
A
A1
A2
b
b1
c
c1
D
D2
E
E1
E2
e
L
L2
M
MILLIMETERS
MIN
MAX
−−−−
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.19
0.25
0.09
0.20
0.09
0.16
4.90
5.10
3.09
3.62
6.40 BSC
4.30
4.50
2.69
3.22
0.65 BSC
0.45
0.75
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
3.40
14X
1.15
3.06
6.70
1
14X
0.65
PITCH
0.42
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
15
NCV4269C
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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16
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NCV4269C/D