FMS6243 Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control Features Description ■ Three Fourth-Order 8MHz (SD) Filters The FMS6243 Low-Cost Video Filter (LCVF) is intended to replace passive LC filters and drivers with a low-cost integrated device. Three fourth-order filters provide improved image quality compared to typical second- or third-order passive solutions. ■ External Delay Control ■ Transparent Input Clamping ■ Dual-Video Load Drive (2Vpp, 75Ω) ■ AC- or DC-Coupled Inputs ■ AC- or DC-Coupled Outputs ■ Lead-Free Package: TSSOP-14 The FMS6243 can be directly driven by a DC-coupled DAC output or an AC-coupled signal. Internal diode clamps and bias circuitry can be used if AC-coupled inputs are required (see the Applications section for details). Applications Delay for each channel can be independently controlled with an external capacitor. ■ DC-Coupled Outputs Eliminate AC-Coupling Capacitors ■ 5V Only ■ Cable Set-Top Boxes The outputs can drive AC- or DC-coupled single (150Ω) or dual (75Ω) loads. DC coupling the outputs removes the need for output coupling capacitors. The input DC levels are offset approximately +280mV at the output (see the Applications section for details). ■ Satellite Set-Top Boxes ■ DVD Players ■ HDTV ■ Personal Video Recorders (PVR) ■ Video On Demand (VOD) Ordering Information Operating Temperature Range Packing Method Part Number Package PbFree FMS6243MTC14 14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide Yes -40°C to 85°C Tube FMS6243MTC14X 14-Lead TSSOP, JEDEC MO-153, 4.4mm Wide Yes -40°C to 85°C Tape and Reel IN1 Transparent Clamp 2X OUT1 Transparent Clamp 2X OUT2 Transparent Clamp 2X OUT3 Del1 IN2 Del2 IN3 Del3 8MHz, 4th-order Figure 1. Functional Block Diagram © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 www.fairchildsemi.com FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control March 2007 DCap1 1 14 VCC GND 2 13 GND IN1 3 12 OUT1 IN2 4 11 OUT2 IN3 5 10 OUT3 GND 6 9 DCap3 DCap2 7 8 GND Figure 2. Pin Configuration Pin Definitions Pin # Name Type Description 1 DCap1 INPUT External Group Delay and Chroma/Luma Delay Adjustment for Channel 1 2 GND INPUT Must be tied to ground, do not float 3 IN1 INPUT Video input channel 1 4 IN2 INPUT Video input channel 2 5 IN3 INPUT Video input channel 3 6 GND INPUT Must be tied to ground, do not float 7 DCap2 INPUT External Group Delay and Chroma/Luma Delay Adjustment for Channel 2 8 GND INPUT Must be tied to ground, do not float 9 DCap3 INPUT External Group Delay and Chroma/Luma Delay Adjustment for Channel 3 10 OUT3 OUTPUT Filtered output for channel 3 11 OUT2 OUTPUT Filtered output for channel 2 12 OUT1 OUTPUT Filtered output for channel 1 13 GND INPUT Must be tied to ground, do not float 14 VCC INPUT +5V supply, do not float © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 www.fairchildsemi.com 2 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control Pin Assignments Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Units VCC DC Supply Voltage -0.3 6.0 V VI/O Analog and Digital I/O -0.3 VCC +0.3 V IOUT Output Current Any One Channel, Do Not Exceed 50 mA Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbols TA VCC Parameter Min. Operating Temperature Range -40 VCC Range 4.75 Typ. 5.00 Max. Units 85 °C 5.25 V Value Units Electrostatic Discharge Conditions Symbols Parameter HBM Human Body Model 8 kV CDM Charged Device Model 2 kV Max. Units 150 °C 150 °C 260 °C Reliability Information Symbol TJ TSTG TL ΘJA Parameter Min. Junction Temperature Storage Temperature Range -65 Reflow Temperature (Soldering) Thermal Resistance, Still Air JEDEC Standard Multi-Layer Test Boards, © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 Typ. 100 °C/W www.fairchildsemi.com 3 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control Absolute Maximum Ratings TA = 25°C, VCC = 5.0V, RS = 37.5Ω; all inputs are AC coupled with 0.1μF; all outputs are AC coupled with 220μF into 150Ω loads; unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units ICC Supply Current(1) No Load 24 VIN Video Input Voltage Range Referenced to GND if DC-coupled 1.4 Vpp 48 dB PSRR Power Supply Rejection Ratio DC (All Channels) 34 mA Note: 1. 100% tested at 25°C. AC Electrical Specifications TA = 25°C, VIN = 1VPP, VCC = 5.0V, RS = 37.5Ω; all inputs are AC coupled with 0.1µF; all outputs are AC coupled with 220µF into 150Ω loads; unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units AV Channel Gain(1) All Channels 5.6 6.0 f1dB -1dB Bandwidth(1) All Channels 5.5 6.5 MHz fC -3dB Bandwidth All Channels 8.0 MHz fSB Attenuation (Stopband Reject) All Channels at f = 27MHz 44 dB DG Differential Gain All Channels 0.3 % DP Differential Phase All Channels 0.6 ° 6.6 dB THD Output Distortion (All Channels) VOUT = 1.8Vpp, 1MHz 0.4 % XTALK Crosstalk (Channel-to-Channel) f = 1MHz -70 dB 75 dB SNR Signal-to-Noise Ratio All Channels, Chroma Weighting; 5MHz Low Pass Note: 1. 100% tested at 25°C. © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 www.fairchildsemi.com 4 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control DC Specifications I/O Configurations The FMS6243 Low-Cost Video Filter (LCVF) provides 6dB gain from input to output. In addition, the input is slightly offset to optimize the output driver performance. The offset is held to the minimum required value to decrease the standing DC current into the load. Typical voltage levels are shown in the diagram below: For DC-coupled DAC drive with DC-coupled outputs, use this configuration: Figure 5. DC-Coupled Inputs and Outputs Alternatively, if the DAC’s average DC output level causes the signal to exceed the range of 0V to 1.4V, it can be AC-coupled as follows: Figure 6. AC-Coupled Inputs, DC-Coupled Outputs When driven by an unknown external source or a SCART switch with its own clamping circuitry, the inputs should be AC-coupled like this: Figure 3. Typical Voltage Levels The FMS6243 provides an internal diode clamp to support AC-coupled input signals. If the input signal does not go below ground, the input clamp does not operate. This allows DAC outputs to directly drive the FMS6243 without an AC coupling capacitor. When the input is AC-coupled, the diode clamp sets the sync tip (or lowest voltage) just below ground. The worst-case sync tip compression due to the clamp can not exceed 7mV. The input level set by the clamp combined with the internal DC offset keeps the output within its acceptable range. For symmetric signals like Chroma, U, V, Pb, and Pr, the average DC bias is fairly constant and the inputs can be AC-coupled with the addition of a pull-up resistor to set the DC input voltage. DAC outputs can also drive these signals without the AC-coupling capacitor. A conceptual illustration of the input clamp circuit is shown below: Figure 7. SCART with DC-Coupled Outputs The same method can be used for biased signals with the addition of a pull-up resistor to make sure the clamp never operates. The internal pull-down resistance is 800kΩ ±20% so the external resistance should be 7.5MΩ to set the DC level to 500mV. Figure 4. Input Clamp Circuit Figure 8. Biased SCART with DC-Coupled Outputs © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 www.fairchildsemi.com 5 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control Application Information where: VO = 2Vin + 0.280V ICH = (ICC / 3) + (VO/RL) VIN = RMS value of input signal ICC = 24mA Vs = 5V RL = channel load resistance 0V - 1.4V DVD or STB SoC DAC Output LCVF Clamp Inactive 75Ω Board layout can also affect thermal characteristics. Refer to the Layout Considerations section for more information. The FMS6243 is specified to operate with output currents typically less than 50mA, more than sufficient for a dual (75Ω) video load. Internal amplifiers are current limited to a maximum of 100mA and should withstand briefduration, short-circuit conditions; however, this capability is not guaranteed. Figure 9. DC-Coupled Inputs, AC-Coupled Outputs External video source must be AC coupled 0V - 1.4V 0.1μ LCVF Clamp Active 75Ω 220μ Group Delay Adjustment 75Ω The FMS6243 has the ability to independently adjust each channel for Sin X/X group delay and Chroma/Luma delay. This is accomplished by placing a capacitor from the device delay adjust pin to ground. The group delay can be adjusted from the nominal of +10ns to -80ns. This means that, under a nominal situation, a video system may have an overall group delay measurement of +50ns. If the system specification is +40ns, the FMS6243 could be used to decrease this group delay to fall well within specification with a guard band to allow for system variation. Figure 10. AC-coupled Inputs and Outputs External video source must be AC coupled 75Ω 7.5MΩ 0.1μ LCVF Bias Input 75Ω Adding a 50pF capacitor to the desired channel DCap pin (see Figure 15) generates a -20ns delay through the FMS6243, which, when summed with the +50ns of the system, gives a new system overall group delay of +30ns. It now meets the system specification with a +10ns guard band for system group delay variation. 500mV +/-350mV Figure 11. Biased AC-Coupled Inputs with AC-Coupled Outputs Figure 12 shows the effect on group delay by adding capacitance to the FMS6243 DCap pins. The correct capacitor can be chosen by determining the format of the video system (NTSC 3.58 or PAL 4.43), then choosing the desired group delay to sum with overall system delay. The desired delay and format line intersection is the delay capacitor needed for the DCap pins. NOTE: The video tilt or line time distortion is dominated by the AC-coupling capacitor. The value may need to be increased beyond 220µF to obtain satisfactory operation in some applications. Power Dissipation 40 400kHz Ref The output drive configuration must be considered when calculating overall power dissipation. Care must be taken not to exceed the maximum die junction temperature. The following example can be used to calculate power dissipation and internal temperature rise: 4.43MHz 3.58MHz 20 10pF Group Delay (ns) 0 20pF 30pF -20 40pF 50pF -40 60pF 70pF -60 Tj = TA + Pd • ΘJA where: Pd = PCH1 + PCH2 + PCH3 and PCHx = Vs • ICH - (VO2/RL) -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency (MHz) Figure 12. Group Delay vs. Delay Cap. Value © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 80pF -80 www.fairchildsemi.com 6 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control The same circuits can be used with AC-coupled outputs if desired. Here is the DC-coupled input with an AC-coupled output. Group Delay and Peaking Adjustment Simultaneously The peaking of a video input signal can be adjusted by placing a peaking capacitor across the series-75ohm resistor on the output of the FMS6243. Where the input video signal to the FMS6243 has a soft roll-off, meaning the input video signal is attenuated at 4Mhz by -0.5dB, the Chroma/Luma gain is approximately -5% and fails a system specification of +- 2.5%. This attenuation can be adjusted by adding a 150pF capacitor across the series75ohm resistor on the output (see Figure 15). This brings the attenuation at 4.0Mhz to approximately 0dB, giving a Chroma/Luma gain of 0%. Figure 13 shows the peaking effect of adding a peaking capacitor across the series75ohm resistor. The graph shows a 10pF delay capacitor with a 10pF, 50pF, and 100pF peaking capacitor. If both a group delay adjustment and a peaking adjustment need to be incorporated into the system design, the following methodology should be followed. Address the group delay adjustment first, then the peaking adjusment, because the group delay adjustment causes a video signal attenuation at 4Mhz. 6.35 3.58MHz 400KHz 4.43MHz 6.30 6.25 6.20 10pF 40pF Gain (dB) 6.15 6.40 80pF 6.10 6.05 6.35 10pF10pF 6.30 5.95 10pF100pF 6.20 Gain (dB) 6.00 10pF50pF 6.25 5.90 6.15 0.0 0.5 6.10 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency (MHz) 6.05 Figure 14. Frequency Response vs. Delay Cap. Value 6.00 5.95 5.90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency (MHz) Figure 13. Frequency Response Delay Capacitor vs. Peaking Capacitor VCC + peaking Delay Cap In1 In2 In3 3 4 5 6 7 VCC GND1 GND4 IN1 OUT1 IN2 IN3 OUT2 OUT3 GND2 DCAP3 DCAP2 GND3 14 75 13 12 peaking 11 75 10 Out2 220μF Delay Cap 9 peaking 8 Delay Cap 75 Figure 15. Out3 220μF Schematic © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 Out1 220μF + 2 DCAP1 + 1 www.fairchildsemi.com 7 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control Signal Peaking Adjustment Thermal Considerations It is critical that the delay capacitor pins (1, 7, and 9) have the delay capacitor placed as close to the device pin as possible. The ground connection should be as short as possible, ideally a direct connect to the adjacent ground pin. These layout considerations create the best environment for the device and reduce noise. Since the interior of most systems, such as set-top boxes, TVs, and DVD players, are at +70°C; consideration must be given to providing an adequate heat sink for the device package for maximum heat dissipation. When designing a system board, determine how much power each device dissipates. Ensure that devices of high power are not placed in the same location, such as directly above (top plane) or below (bottom plane), each other on the PCB. General layout and supply bypassing play a major role in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board to guide layout and aid device evaluation. The demo board is a fourlayer board with full power and ground planes. Following this layout configuration provides optimum performance and thermal characteristics for the device. For the best results, follow the steps and recommended routing rules listed below. PCB Thermal Layout Considerations ■ Understand the system power requirements and environmental conditions. ■ Maximize thermal performance of the PCB. Recommended Routing / Layout Rules ■ Consider using 70μm of copper for high-power ■ Do not run analog and digital signals in parallel. ■ Make the PCB as thin as possible by reducing FR4 designs. ■ Use separate analog and digital power planes to ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ thickness. supply power. Traces should run on top of the ground plane at all times. No trace should run over ground / power splits. Avoid routing at 90-degree angles. Minimize clock and video data trace length differences. Include 10μF and 0.1μF ceramic power supply bypass capacitors. Place the 0.1μF capacitor within 0.1 inches of the device power pin. Place the 10μF capacitor within 0.75 inches of the device power pin. For multi-layer boards, use a large ground plane to help dissipate heat. For two-layer boards, use a ground plane that extends beyond the device body at least 0.5 inches on all sides. Include a metal paddle under the device on the top layer. Minimize all trace lengths to reduce series inductance. ■ Use vias in the power pad to tie adjacent layers together. ■ Remember that baseline temperature is a function of board area, not copper thickness. ■ Modeling techniques provide first-order approximation. © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 www.fairchildsemi.com 8 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control Layout Considerations FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control Mechanical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 16. 14-Lead, Thin-Shrink Small Outline Package (TSSOP) © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 www.fairchildsemi.com 9 The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx® Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ E2CMOS™ EcoSPARK® EnSigna™ FACT Quiet Series™ FACT® FAST® FASTr™ FPS™ FRFET® Power247® PowerEdge™ PowerSaver™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 GlobalOptoisolator™ GTO™ HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR® PACMAN™ POP™ Power220® SyncFET™ TCM™ The Power Franchise® ™ TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ UHC® UniFET™ VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 2. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I24 © 2007 Fairchild Semiconductor Corporation FMS6243 Rev. 1.0.0 www.fairchildsemi.com 10 FMS6243 — Low-Cost, 3-Channel, SD Video Filter Drivers with External Delay Control TRADEMARKS