RoHS Compliant Value Added Compact Flash Series Ⅲ Specification for Industrial CF Mar 8, 2011 Version 1.0 Apacer Technology Inc. th 4 Fl., 75 Hsin Tai Wu Rd., Sec.1, Hsichih, New Taipei City, Taiwan 221 Tel: +886-2-2698-2888 www.apacer.com Fax: +886-2-2698-2889 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Features: Compact Flash Association Specification Revision 3.0 Standard Interface – ATA command set compatible – ATA mode support for up to: PIO Mode-6 Multiword DMA Mode-4 Ultra DMA Mode-4 – Connector Type 50 pins female – – – Low power consumption (typical) Supply voltage: 3.3V & 5V Active mode: 80 mA/95 mA (3.3V/5.0V) Sleep mode: 700 µA/900 µA (3.3V/5.0V) – – Temperature ranges Operation: Standard: 0°C to 70°C ET*: -40°C to 85°C – Storage: -40°C to 100°C – Flash management – Intelligent endurance design Advanced wear-leveling algorithms S.M.A.R.T. Technology Built-in Hardware ECC Enhanced Data Integrity – Intelligent power failure recovery RoHS compliant Performance** Sustained read: 30 MB/sec Sustained write: Standard: 5 MB/sec High Speed: 15 MB/sec Capacity Standard: 128, 256, 512 MB 1, 2, 16 GB – High Speed: 256, 512 MB 1, 2, 4, 8 GB – NAND Flash Type: SLC *Extended Temperature **Performance varies with flash configurations 1 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Table of Contents 1. GENERAL DESCRIPTION ......................................................................................... 3 1.1 PERFORMANCE-OPTIMIZED CONTROLLER ............................................................................................... 3 1.1.1 Power Management Unit (PMU)................................................................................................... 3 1.1.2 SRAM Buffer ................................................................................................................................. 3 2. FUNCTIONAL BLOCK ............................................................................................... 4 3. PIN ASSIGNMENTS ................................................................................................... 5 4. CAPACITY SPECIFICATION ..................................................................................... 7 4.1 PERFORMANCE SPECIFICATION .............................................................................................................. 7 4.2 ENVIRONMENTAL SPECIFICATIONS .......................................................................................................... 8 5. FLASH MANAGEMENT ............................................................................................. 9 5.1 INTELLIGENT ENDURANCE DESIGN .......................................................................................................... 9 5.1.1 Advanced wear-leveling algorithms .............................................................................................. 9 5.1.2 S.M.A.R.T. technology.................................................................................................................. 9 5.1.3 Built-in hardware ECC .................................................................................................................. 9 5.1.4 Enhanced data integrity ................................................................................................................ 9 5.2 INTELLIGENT POWER FAILURE RECOVERY ............................................................................................. 10 6. SOFTWARE INTERFACE ....................................................................................... 11 6.1 COMMAND SET .................................................................................................................................... 11 7. ELECTRICAL SPECIFICATION .............................................................................. 13 7.1 DC CHARACTERISTICS ......................................................................................................................... 14 7.2 AC CHARACTERISTICS ......................................................................................................................... 15 7.2.1 Attribute Memory Read Timing Specification ............................................................................. 16 7.2.2 Configuration Register (Attribute Memory) Write Specification .................................................. 17 7.2.3 Common Memory Read Timing Specification ............................................................................ 18 7.2.4 Common Memory Write Timing Specification ............................................................................ 19 7.2.5 I/O Input (Read) Timing Specification......................................................................................... 20 7.2.6 I/O Output (Write) Timing Specification ...................................................................................... 21 7.2.7 Ultra DMA Mode Data Transfer Input/Output (Read/Write) Timing............................................ 22 7.2.8 Media Side Interface I/O Timing Specifications.......................................................................... 34 8. PHYSICAL CHARACTERISTICS ............................................................................ 37 8.1 DIMENSION .......................................................................................................................................... 37 9. PRODUCT ORDERING INFORMATION ................................................................. 38 9.1 PRODUCT CODE DESIGNATIONS ........................................................................................................... 38 9.2 VALID COMBINATIONS .......................................................................................................................... 39 2 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 1. General Description Apacer’s Industrial Compact Flash Card (CFC) offers the most reliable and high performance storage which is compatible with CF Type I and Type II devise. Unlike the ordinary consumer Compact Flash cards, Apacer Industrial Compact Flash card provides solid traceability to ensure all products HW/SW are the same as you qualified. Apacer’s CFC provides complete PCMCIA - ATA functionality and compatibility. Apacer ‘s Compact Flash technology is designed for use in Point of Sale (POS) terminals, telecom, IP-STB, medical instruments, surveillance systems, industrial PCs and handheld applications. Featuring technologies as Advanced Wear-leveling algorithms, S.M.A.R.T, Enhanced Data Integrity, Builtin Hardware ECC, and Intelligent Power Failure Recovery, Apacer’s Industrial Compact Flash Card assures users of a versatile device on data storage. 1.1 Performance-Optimized Controller The Compact Flash Card Controller translates standard CF signals into flash media data and control signals. 1.1.1 Power Management Unit (PMU) The power management unit (PMU) controls the power consumption of the Compact Flash card controller. It reduces the power consumption of the Compact Flash Card Controller by putting circuitry not in operation into sleep mode. The PMU has zero wake-up latency. 1.1.2 SRAM Buffer The Compact Flash Card Controller performs as an SRAM buffer to optimize the host’s data transfer to and from the flash media. 3 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 2. Functional Block The Compact Flash Card (CFC) includes a controller and flash media, as well as the Compact Flash standard interface. Figure 2-1 shows the functional block diagram. Flash Array Flash Media Compact Flash Interface Flash Media Compact Flash Controller Flash Media Flash Media Figure 2-1: Functional block diagram 4 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 3. Pin Assignments Table 3-1 lists the pin assignments with respective signal names for the 50-pin configuration. A “#” suffix indicates the active low signal. The pin type can be input, output or input/output. Table 3-1: Pin assignments (1 of 2) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Memory card mode Signal name GND D3 D4 D5 D6 D7 #CE1 A10 #OE A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP #CD2 #CD1 D11 D12 D13 D14 D15 #CE2 #VS1 #IORD #IOWR #WE RDY/-BSY VCC #CSEL #VS2 RESET Pin I/O type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I I/O card mode Signal name GND D3 D4 D5 D6 D7 #CE1 A10 #OE A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 #IOIS16 #CD2 #CD1 D11 D12 D13 D14 D15 #CE2 #VS1 #IORD #IOWR #WE #IREQ VCC #CSEL #VS2 RESET Pin I/O type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I True IDE mode Signal name GND D3 D4 D5 D6 D7 #CS0 1 A10 #ATA SEL 1 A9 1 A8 1 A7 VCC 1 A6 1 A5 1 A4 1 A3 A2 A1 A0 D0 D1 D2 #IOCS16 #CD2 #CD1 D11 D12 D13 D14 D15 #CS1 #VS1 #IORD #IOWR #WE INTRQ VCC #CSEL #VS2 #RESET Pin I/O type I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I 5 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Table 3-1: Pin assignments (2 of 2) Pin No. 42 43 44 45 46 47 48 49 50 Memory card mode Signal name #WAIT #INPACK #REG BVD2 BVD1 D8 D9 D10 GND Pin I/O type O O I O O I/O I/O I/O - I/O card mode Signal name #WAIT #INPACK #REG #SPKR #STSCHG D8 D9 D10 GND Pin I/O type O O I O O I/O I/O I/O - True IDE mode Signal name IORDY 2 DMARQ 2 DMACK #DASP #PDIAG D8 D9 D10 GND Pin I/O type O O I O O I/O I/O I/O - 1. The signal should be grounded by the host. 2. Connection required when UDMA is in use. 6 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 4. Capacity Specification Capacity specification of the Compact Flash Card series (CFC) is available as shown in Table 4-1. It lists the specific capacity and the default numbers of heads, sectors and cylinders for each product line. Table 4-1: Capacity specifications Capacity Total bytes* Cylinders Heads Sectors Max LBA 128 MB 128,450,560 980 8 32 250,880 256 MB 256,901,120 980 16 32 501,760 512 MB 512,483,328 993 16 63 1,000,944 1GB 1,024,966,656 1,986 16 63 2,001,888 2GB 2,048,901,120 3,970 16 63 4,001,760 4GB 4,110,188,544 7,964 16 63 8,027,712 8GB 8,195,604,480 15,880 16 63 16,007,040 16GB 16,391,208,960 16,383** 16 63 32,014,080 *Display of total bytes varies from file systems. **Cylinders, heads or sectors are not applicable for these capacities. Only LBA addressing applies 4.1 Performance Specification Performances of the Standard and High Speed ATA-Flash Disk are listed in Table 4-2 and Table 4-3. Table 4-2: Standard Performance specifications Capacity 128 MB / 256 MB Performance 2 GB 16 GB 512 MB / 1 GB Sustained read (MB/s) 15 20 20 Sustained write (MB/s) 5 5 5 Table 4-3: High Speed Performance specifications Capacity 256 MB 512 MB 1 GB 2 GB 4 GB 8 GB Sustained read (MB/s) 25 25 25 25 30 30 Sustained write (MB/s) 5 5 5 5 10 15 Performance Note: Performance varies from flash configurations. 7 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 4.2 Environmental Specifications Environmental specification of the Compact Flash Card series (CFC) which follows the MIL-STD-810F standards is available as shown in Table 4-4. Table 4-4: Environmental specifications Environment Temperature Specification Operation 0°C to 70 ℃ (Standard) ; -40°C to 85 ℃ (Extended Temperature) Storage -40℃ to 100℃ Humidity Vibration (Non-Operation) Shock (Non-Operation) 5% to 95% RH (Non-condensing) Sine wave: 10~2000Hz, 15G (X, Y, Z axes) Half sine wave, Peak acceleration 50 G, 11 ms (X, Y, Z ; All 6 axes) 8 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 5. Flash Management 5.1 Intelligent Endurance Design 5.1.1 Advanced wear-leveling algorithms The NAND flash devices are limited by a certain number of write cycles. When using a file system, frequent file table updates is mandatory. If some area on the flash wears out faster than others, it would significantly reduce the lifetime of the whole device, even if the erase counts of others are far from the write cycle limit. Thus, if the write cycles can be distributed evenly across the media, the lifetime of the media can be prolonged significantly. The scheme is achieved both via buffer management and Apacerspecific advanced wear leveling to ensure that the lifetime of the flash media can be increased, and the disk access performance is optimized as well. 5.1.2 S.M.A.R.T. technology S.M.A.R.T. is an acronym for Self-Monitoring, Analysis and Reporting Technology, an open standard allowing disk drives to automatically monitor their own health and report potential problems. It protects the user from unscheduled downtime by monitoring and storing critical drive performance and calibration parameters. Ideally, this should allow taking proactive actions to prevent impending drive failure. Apacer SMART feature adopts the standard SMART command B0h to read data from the drive. When the Apacer SMART Utility running on the host, it analyzes and reports the disk status to the host before the device is in critical condition. 5.1.3 Built-in hardware ECC The ATA-Disk Module uses BCH Error Detection Code (EDC) and Error Correction Code (ECC) algorithms which correct up to eight random single-bit errors for each 512-byte block of data. High performance is fulfilled through hardware-based error detection and correction. 5.1.4 Enhanced data integrity The properties of NAND flash memory make it ideal for applications that require high integrity while operating in challenging environments. The integrity of data to NAND flash memory is generally maintained through ECC algorithms and bad block management. Flash controllers can support up to 8 bits ECC capability for accuracy of data transactions, and bad block management is a preventive mechanism from loss of data by retiring unusable media blocks and relocating the data to the other blocks, along with the integration of advanced wear leveling algorithms, so that the lifespan of device can be expanded. 9 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 5.2 Intelligent Power Failure Recovery The Low Power Detection on the controller initiates cached data saving before the power supply to the device is too low. This feature prevents the device from crash and ensures data integrity during an unexpected blackout. Once power was failure before cached data writing back into flash, data in the cache will lost. The next time the power is on, the controller will check these fragmented data segment, and, if necessary, replace them with old data kept in flash until programmed successfully. 10 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 6. Software Interface 6.1 Command Set Table 6-1 summarizes the command set with the paragraphs that follow describing the individual commands and the task file for each. Table 6-1: Command set (1 of 2) Command 1 2 3 4 5 FR SC SN CY E5H or 98H - - - - D 8 - Execute-Drive-Diagnostic 90H - - - - D - Erase Sector(s) C0H - Y Y Y Y Y Flush-Cache E7H - - - - D - 8 Check-Power-Mode 7 DH 6 Code LBA Format Track 50H - Y - Y Y Y Identify-Drive ECH - - - - D - Idle E3H or 97H - Y - - D - Idle-Immediate E1H or 95H - - - - D - Initialize-Drive-Parameters 91H - Y - - Y - NOP 00H - - - - D - Read-Buffer E4H - - - - D - Read-DMA C8H or C9H - Y Y Y Y Y C4H - Y Y Y Y Y Read-Sector(s) 20H or 21H - Y Y Y Y Y Read-Verify-Sector(s) 40H or 41H - Y Y Y Y Y Recalibrate 1XH - - - - D - Request-Sense 03H - - - - D - Seek 7XH - - Y Y Y Y - - - D - Read-Multiple Set-Features 7 Y EFH 11 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Table 6-1: Command set (2 of 2) Command 1 2 3 4 5 FR SC SN CY SMART B0H Y Y Y Y D Set-Multiple-Mode C6H - Y - - D - Set-Sleep-Mode E6H or 99H - - - - D - Standby E2H or 96H - - - - D - Standby-lmmediate E0H or 94H - - - - D - Translate-Sector 87H - Y Y Y Y Y Write-Buffer E8H - - - - D - Write-DMA CAH or CBH - Y Y Y Y Y Write-Multiple C5H - Y Y Y Y Y Write-Multiple-Without-Erase CDH - Y Y Y Y Y 30H or 31H - Y Y Y Y Y Write-Sector-Without-Erase 38H - Y Y Y Y Y Write-Verify 3CH - Y Y Y Y Y Write-Sector(s) DH 6 Code LBA 1. FR - Features register 2. SC - Sector Count register 3. SN - Sector Number register 4. CY - Cylinder registers 5. DH - Drive/Head register 6. LBA - Logical Block Address mode supported (see command descriptions for use) 7. Y - The register contains a valid parameter for this command 8. For the Drive/Head register: Y means both the CFC and Head parameters are used D means only the CFC parameter is valid and not the Head parameter 12 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7. Electrical Specification Caution: Absolute Maximum Stress Ratings – Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Table 7-1: Operating range Range Ambient Temperature 3.3V 5V Standard Extended Temperature 0°C to +70°C -40°C to +85°C 3.135-3.465V 4.75-5.25V Table 7-2: Absolute maximum power pin stress ratings Parameter Symbol Input Power Voltage on any pin except VDD with respect to GND VDD V Conditions -0.3V min. to 6.5V max. -0.5V min. to VDD + 0.5V max. Table 7-3: Recommended system power-up timing Symbol Parameter 1 TPU-READY 1 TPU-WRITE Power-up to Ready Operation Power-up to Write Operation Typical Maximum Units 200 200 1000 1000 ms ms 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 13 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.1 DC Characteristics Table 7-4: DC Characteristics Symbol Type VIH1 VIL1 IIL1 I1Z IU1 I1U VT+2 VT-2 I1 Min 2.0V Max Units V 0.8V Input Leakage Current -10 10 μA Input Pull-Up Current -110 -1 μA 2.0 V Input Voltage Schmitt Trigger I2 IIL2 I2Z IU2 I2U VOH1 VOL1 IOH1 IOL1 VOH2 VOL2 IOH2 IOL2 IOH2 IOL2 VOH6 VOL6 IOH6 IOL6 IOH6 IOL6 Parameter Input Voltage Input Leakage Current 0.8 -10 10 μA Input Pull-Up Current -110 -1 μA Output Voltage 2.4 V 0.4 O1 Output Current Output Current -4 Output Voltage 2.4 4 mA mA V 0.4 O2 Output Current Output Current -6 Output Current Output Current -8 Output Voltage for DASP# pin 2.4 IDD1,2 PWR IDD1,2 PWR ISP PWR ISP PWR Output Current for DASP# pin Output Current for DASP# pin -3 Output Current for DASP# pin Output Current for DASP# pin -3 Power supply current (Ta = 0°C to +70°C) Power supply current (Ta= -40°C to +85°C) Sleep/Standby/Idle current (Ta = 0°C to +70°C) Sleep/Standby/Idle current (Ta = -40°C to +85°C) VIN=GND to VDDQ VDDQ= VDDQ Max VOUT=GND, VDDQ= VDDQ Max VDDQ=VDDQ Max VDDQ=VDDQ Min VIN=GND to VDDQ VDDQ= VDDQ Max VOUT=GND, VDDQ= VDDQ Max IOH1=IOH1 Min IOL1=IOL1 Max VDDQ=VDDQ Min VDDQ=VDDQ Min IOH2=IOH2 Min IOL2=IOL2 Max 6 mA mA VDDQ=3.135V-3.465V VDDQ=3.135V-3.465V 8 mA mA VDDQ=4.5V-5.5V VDDQ=4.5V-5.5V V 0.4 O6 Conditions VDDQ=VDDQ Max VDDQ=VDDQ Min IOH6=IOH6 Min IOL6=IOL6 Max 8 mA mA VDDQ=3.135V-3.465V VDDQ=3.135V-3.465V 12 mA mA VDDQ=4.5V-5.5V VDDQ=4.5V-5.5V 50 mA 75 mA 75 μA VDD=VDD Max VDDQ=VDDQ Max VDD=VDD Max VDDQ=VDDQ Max VDD=VDD Max VDDQ=VDDQ Max 200 μA VDD=VDD Max VDDQ=VDDQ Max 14 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2 AC Characteristics Figure 7-1: AC Input/Output Reference Waveforms AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT- VINPUT LOW Test 15 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.1 Attribute Memory Read Timing Specification The Attribute Memory access time is defined as 100 ns. Detailed timing specifications are shown in the table below. Table 7-5: Attribute Memory Read Timing Specification Speed Version Item Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from CE# Output Disable Time from OE# Address Setup Time Output Enable Time from CE# Output Enable Time from OE# Data Valid from Address Change Symbol TC(R) TA(A) TA(CE) TA(OE) TDIS(CE) TDIS(OE) TSU(A) TEN(CE) TEN(OE) TV(A) IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAVGL tELQNZ tGLQNZ tAXQZ Min* 100 100 ns Max* 100 100 50 50 50 10 5 5 0 Units ns ns ns ns ns ns ns ns ns ns *DOUT signifies data provided by the Compact Flash card to the system. The CE# signal or both the OE# signal and the WE# signal must be de-asserted between consecutive cycle operations. All AC specifications are guaranteed by design. Figure 7-2: Attribute Memory Read Timing Diagram 16 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.2 Configuration Register (Attribute Memory) Write Specification The card configuration write access time is defined as 100 ns. Detailed timing specifications are shown in the table below. Table 7-6: Configuration Register (Attribute Memory) Write Timing Speed Version Item Write Cycle Time Write Pulse Width Address Setup Time Write Recover Time Data Setup Time for WE Data Hold Time Symbol TC(W) TW(WE) TSU(A) TREC(WE) TSU(DWE#H) TH(D) IEEE Symbol tAVAV tWLWH tAVWL tWMAX tDVWH tWMDX Min* 100 60 10 15 40 15 100 ns Max* Units ns ns ns ns ns ns *DIN signifies data provided by the system to the Compact Flash card. All AC specifications are guaranteed by design. Figure 7-3: Configuration Register (Attribute Memory) Write Timing Diagram 17 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.3 Common Memory Read Timing Specification Table 7-7: Common Memory Read Timing Item Output Enable Access Time Output Disable Time from OE Address Setup Time Address Hold Time CE Setup before OE CE Hold following OE Symbol TA(OE) TDIS(OE) TSU(A) TREC(WE) TSU(CE) TH(CE) IEEE Symbol tGLQV tGHQZ tAVGL tGHAX tELGL tGHEH Min* 10 15 0 15 Max* 50 50 Units ns ns ns ns ns ns *All AC specifications are guaranteed by design. Figure 7-4: Common Memory Read Timing Diagram 18 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.4 Common Memory Write Timing Specification Table 7-8: Common Memory Write Timing Item Data Setup before WE Data Hold following WE WE Pulse Width Address Setup Time CE Setup before WE Write Recovery Time Address Hold Time CE Hold following WE Symbol TSU(DWE#H) TH(D) TW(WE) TSU(A) TSU(CE) TREC(WE) TH(A) TH(CE) IEEE Symbol tDVWH tWMDX tWLWH tAVWL tELWL tWMAX tGHAX tGHEH Min* 40 15 60 10 0 15 15 15 Max* Units ns ns ns ns ns ns ns ns *All AC specifications are guaranteed by design. Figure 7-5: Common Memory Write Timing Diagram 19 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.5 I/O Input (Read) Timing Specification Table 7-9: I/O Read Timing Item Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD REG Setup before IORD REG Hold following IORD INPACK Delay Falling from IORD INPACK Delay Rising from IORD IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Symbol TD(IORD) TH(IORD) TW(IORD) TSUA(IORD) THA(IORD) TSUCE(IORD) THCE(IORD) TSUREG(IORD) THREG(IORD) TDFINPACK(IORD) TDRINPACK(IORD) TDFIOIS16(ARD) TDRIOIS16(ADR) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tRGLIGL tlGHRGH tlGLIAL tlGHIAH tAVISL tAVISH Min* 0 165 70 20 5 20 5 0 0 Max* 100 45 45 35 35 Units ns ns ns ns ns ns ns ns ns ns ns ns ns *All AC specifications are guaranteed by design. Note: The maximum load on –INPACK and IOIS16# is 1 LSTTL with 50pF total load. Figure 7-6: I/O Read Timing Diagram 20 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.6 I/O Output (Write) Timing Specification Table 7-10: I/O Write Timing Item Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR REG Setup before IOWR REG Hold following IOWR IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Symbol TSU(IOWR) TH(IOWR) TW(IOWR) TSUA(IOWR) THA(IOWR) TSUCE(IOWR) THCE(IOWR) TSUREG(IOWR) THREG(IOWR) TDFIOIS16(ARD) TDRIOIS16(ADR) IEEE Symbol tDVIWH tlWHDX tlWLIWH tAVIWL tlWHAX tELIWL tlWHEH tRGLIWL tlWHRGH tAVISL tAVISH Min* 60 30 165 70 20 5 20 5 0 Max* 35 35 Units ns ns ns ns ns ns ns ns ns ns ns *All AC specifications are guaranteed by design. Note: The maximum load on –INPACK and IOIS16# is 1 LSTTL with 50pF total load. Figure 7-7: I/O Write Timing Diagram 21 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.7 Ultra DMA Mode Data Transfer Input/Output (Read/Write) Timing Table 7-11: Ultra DMA Data Burst Timing Specifications Name Descriptions T2CYCTYP T CYC Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) Data setup time at recipient (from data valid until 4,5 STROBE edge) Data hold time at Recipient (from STROBE edge 1,2 until data becomes invalid) Data valid setup time for Sender (from data valid 6 until STROBE edge) Data valid hold time at Sender (from STROBE 3 edge until data becomes invalid) 1 CRC word setup time at device 1 CRC word hold time at device CRC word valid setup time at host (from CRC 3 valid until DMACK negation) CRC word valid hold time at Sender (from 3 DMACK negation until CRC becomes invalid) Time from STROBE output released-to-driving until the first transition of critical timing Time from data output released-to-driving until the first transition of critical timing First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) 7 Limited interlock time 4 Interlock time with minimum 4 Unlimited interlock time Maximum time allowed for output drivers to release (from asserted to negated) Minimum delay time required for output Drivers to assert or negate (from released) Envelope time (from DMACK# to STOP and HDMARDY# during data in burst initiation and from DMACK to STOP during data our burst initiation) Ready-to-final STROBE time (no STROBE edge are sent this long after negation of DMARDY) Ready-to-pause time (Recipient waits to pause until after negating DMARDY) Maximum time before releasing IORDY 10 Minimum time before driving IORDY T 2CYC T DS T DH T DVS T DVH T CS T CH T CVS T CVH T ZFS T DZFS T FS T LI T MLI T UI T AZ T ZAH T ZAD T ENV T RFS T RP T IORDYZ T ZIORDY T ACK T SS Mode 4 Min Max 60 25 1 ns ns Measurement 2 Location Sender 3 Note 57 ns Sender 5.0 ns Recipient 5.0 ns Recipient 6.0 ns Sender 6.0 ns Sender 5.0 5.0 6.7 ns ns ns Device Device Host 6.2 ns Host 0 ns Device 6.7 ns Sender 120 ns Device 100 10 ns ns ns ns Note Host Host 9 Note 55 ns ns ns Host Device Host 60 ns Sender ns Recipient ns ns ns ns Device Device Host Sender 0 20 0 20 0 20 100 20 0 20 50 Unit 8 22 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 1. All timing measurement switching points (low-to-high and high-to-low) are taken at 1.5V. 2. All signal transitions for a timing parameter are measured at the connector specified in the measurement location column. For example, in the case of TRFS, both STROBE and DMARDY Transitions are measured at the Sender connector. 3. The parameter TCYC is measured at the recipient’s connector farthest from the Sender. 4. 80-Conductor cabling is required in order to meet sup (TDS, TCS) and hold (TDH, TCH) times in modes greater than two. 5. The parameters TDS and TDH for Mode 5 are defined for a Recipient at the end of the cable only in a configuration with a single device located at the end of the cable. This could result in the minimum values for TDS and TDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively. 6. Timing for TDVS, TDVH, TCVS, and TCVH are met for lumped capacitive loads of 15 and 50 pf at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system. 7. The parameters TUI, TMLI, and TLI indicate Sender-to-Recipient or Recipient-to-Sender interlocks. For example, one agent (either Sender or Recipient) is waiting for the other agent to respond with a signal before proceeding; TUI is an unlimited interlock that has no maximum time value, TMLI is a limited time-out that has a defined minimum, and TLI is a limited time-out that has a defined maximum. 8. The parameter TLI is measured at the connector of the Sender or Recipient that is responding to an incoming transition from the Recipient or Sender respectively. Both the incoming signal and the outgoing response are measured at the same connector. 9. The parameter TAZ is measured at the connector of the Sender or Recipient that is driving the bus but must release the bus that allow for a bus turnaround. 10. For all modes the parameter TZIORDY may be greater than TENV because the host has a pull-on IORDY giving it a known state when released. 23 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Table 7-12: Ultra DMA Sender and Recipient IC Timing Specifications Name TDSIC T DHIC T DVSIC T DVHIC 1. 2. 3. Descriptions 2 Recipient IC data setup time (from data valid until STROBE edge) Recipient IC data hold time (from STROBE edge until data becomes 1 invalid) 3 Sender IC data valid setup time (from data valid until STROBE edge) 1 Mode 4 Min Max 4.8 4.8 9.5 9.0 Unit ns ns ns ns All timing measurement switching point (low-to-high and high-to-low) The correct data value is captured by the Recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at TDSIC and TDHIC timing (as measured through 1.5 V). The parameters TDVSIC and TDVHIC are met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values. Figure 7-8: Initiating an Ultra DMA Data-In Burst Notes: 1. The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE, and IORDY:DDRARDY-: DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. 24 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-9: Sustained Ultra DMA Data-In Burst Notes: 1. DD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay will not allow the data signals to be considered stable at the host until some time after they are driven by the device. 25 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-10: Sustained Ultra DMA Data-In Burst Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than TRP after HDMARDY# is negated. 2. After negating HDMARDY#, the host may receive zero, one, two, or three more data words from the device. 26 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-11: Device Terminating and Ultra DMA Data-In Burst Notes: 1. The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 27 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-12: Host Terminating and Ultra DMA Data-In Burst Notes: 1. The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 28 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-13: Initiating an Ultra DMA Data-Out Burst Notes: 1. The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 29 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-14: Sustained Ultra DMA Data-Out Burst Notes: 1. DD(15:0) and HSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay will not allow the data signals to be considered stable at the host until some time after they are driven by the host. 30 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-15: Device Pausing and Ultra DMA Data-Out Burst Notes: 1. The host may negate DMARQ to request termination of the Ultra DMA burst no sooner than TRP after DDMARDY# is negated. 2. After negating DDMARDY#, the host may receive zero, one, two, or three more data words from the host. 31 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-16: Host Terminating and Ultra DMA Data-Out Burst Notes: 1. The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 32 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-17: Device Terminating and Ultra DMA Data-Out Burst Notes: 1. The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 33 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 7.2.8 Media Side Interface I/O Timing Specifications Table 7-13: Timing Parameter Symbol TCLS TCLH TCS TCH TCHR TWP TWH TWC TALS TALH TDS TDH TRP TRR TRES TRC TREH TRHZ Parameter FCLE Setup Time FCLE Hold Time FCE# Setup Time FCE# Hold Time for Command/Data Write Cycle FCE# Hold Time for Sequential Read Last Cycle FWE# Pulse Width FWE# High Hold Time Write Cycle Time FALE Setup Time FALE Hold Time FAD[15:0] Setup Time FAD[15:0] Hold Time FRE# Pulse Width Ready to FRE# Low FRE# Data Setup Access Time Read Cycle Time FRE# High Hold Time FRE# High to Data Hi-Z Min 20 40 40 40 20 20 40 20 40 20 20 20 40 20 40 20 5 Max 40 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: All AC specifications are guaranteed by design. 34 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-18: Media Command Latch Cycle Figure 7-19: Media Access Latch Cycle 35 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Figure 7-20: Media Data Loading Latch Cycle Figure 7-21: Media Data Read Cycle 36 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 8. Physical Characteristics 8.1 Dimension TABLE 8-1: Type I CFC physical specification Length: Width: Thickness (Including Label Area): 36.40 +/- 0.15mm (1.433+/- 0.06 in.) 42.80 +/- 0.10mm (1.685+/- 0.04 in.) 3.3mm+/-0.10mm (0.130+/-0.04in.) Unit: mm FIGURE 8-1: Physical dimension 37 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 9. Product Ordering Information 9.1 Product Code Designations A P – C F x x x x E 3 X R – XXXXXXK Specification NR: Non-Removable Setting NDNR: Non-DMA + Non-Removable ETNR: Ext. Temp. + Non-Removable ETNDNR: Ext. Temp + Non-DMA + Non-Removable K: Value Added Ⅲ RoHS Compliant Configuration E: Standard F: High Speed Controller Type CFC Type Capacity: 128M: 256M: 512M: 001G: 002G: 004G: 008G: 016G: 128MB 256MB 512MB 1GB 2GB 4GB 8GB 16GB Model Name Apacer Product Code 38 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK 9.2 Valid Combinations Standard Temperature Non-Removable Standard Capacity High Speed Model Number Capacity Model Number 128MB AP-CF128ME3ER-NRK 256MB AP-CF256ME3FR-NRK 256MB AP-CF256ME3ER-NRK 512MB AP-CF512ME3FR-NRK 512MB AP-CF512ME3ER-NRK 1GB AP-CF001GE3FR-NRK 1GB AP-CF001GE3ER-NRK 2GB AP-CF002GE3FR-NRK 2GB AP-CF002GE3ER-NRK 4GB AP-CF004GE3FR-NRK 16GB AP-CF016GE3ER-NRK 8GB AP-CF008GE3FR-NRK Non-DMA & Non-Removable Standard Capacity Model Number High Speed Capacity Model Number 128MB AP-CF128ME3ER-NDNRK 256MB AP-CF256ME3FR-NDNRK 256MB AP-CF256ME3ER-NDNRK 512MB AP-CF512ME3FR-NDNRK 512MB AP-CF512ME3ER-NDNRK 1GB AP-CF001GE3FR-NDNRK 1GB AP-CF001GE3ER-NDNRK 2GB AP-CF002GE3FR-NDNRK 2GB AP-CF002GE3ER-NDNRK 4GB AP-CF004GE3FR-NDNRK 16GB AP-CF016GE3ER-NDNRK 8GB AP-CF008GE3FR-NDNRK 39 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Extended Temperature Non-Removable Standard Capacity High Speed Model Number Capacity Model Number 128MB AP-CF128ME3ER-ETNRK 256MB AP-CF256ME3FR-ETNRK 256MB AP-CF256ME3ER-ETNRK 512MB AP-CF512ME3FR-ETNRK 512MB AP-CF512ME3ER-ETNRK 1GB AP-CF001GE3FR-ETNRK 1GB AP-CF001GE3ER-ETNRK 2GB AP-CF002GE3FR-ETNRK 2GB AP-CF002GE3ER-ETNRK 4GB AP-CF004GE3FR-ETNRK 16GB AP-CF016GE3ER-ETNRK 8GB AP-CF008GE3FR-ETNRK Non-DMA & Non-Removable Standard High Speed Capacity Model Number Capacity Model Number 128MB AP-CF128ME3ER-ETNDNRK 256MB AP-CF256ME3FR-ETNDNRK 256MB AP-CF256ME3ER-ETNDNRK 512MB AP-CF512ME3FR-ETNDNRK 512MB AP-CF512ME3ER-ETNDNRK 1GB AP-CF001GE3FR-ETNDNRK 1GB AP-CF001GE3ER-ETNDNRK 2GB AP-CF002GE3FR-ETNDNRK 2GB AP-CF002GE3ER-ETNDNRK 4GB AP-CF004GE3FR-ETNDNRK 16GB AP-CF016GE3ER-ETNDNRK 8GB AP-CF008GE3FR-ETNDNRK 40 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Revision History Revision 1.0 Description Official release Date Mar 8, 2011 41 © 2011 Apacer Technology Inc. Rev. 1.0 Value Added Compact Flash Ⅲ series AP-CFxxxxE3XR-XXXXXXK Global Presence Taiwan (Headquarters) Apacer Technology Inc. th th 4 Fl, 75 Xintai 5 Rd., Sec.1 Hsichih, New Taipei City Taiwan 221 R.O.C. Tel: +886-2-2698-2888 Fax: +886-2-2698-2889 [email protected] U.S.A. Apacer Memory America, Inc. 386 Fairview Way, Suite102, Milpitas, CA 95035 Tel: 1-408-518-8699 Fax: 1-408-935-9611 [email protected] Japan Apacer Technology Corp. 5F, Matsura Bldg., Shiba, Minato-Ku Tokyo, 105-0014, Japan Tel: 81-3-5419-2668 Fax: 81-3-5419-0018 [email protected] Europe Apacer Technology B.V. Aziëlaan 22, 5232 BA 's-Hertogenbosch, The Netherlands Tel: 31-73-645-9620 Fax: 31-73-645-9629 [email protected] China Apacer Electronic (Shanghai) Co., Ltd 1301, No.251,Xiaomuqiao Road, Shanghai, 200032, China Tel: 86-21-5529-0222 Fax: 86-21-5206-6939 [email protected] India Apacer Technologies Pvt Ltd, #1064, 1st Floor, 7th ‘A’ Main, 3rd Block Koramangala, Bangalore – 560 034 Tel: +91 80 4152 9061/62/63 Fax: +91 80 4170 0215 [email protected] 42 © 2011 Apacer Technology Inc. Rev. 1.0 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Apacer: AP-CF001GE3FR-ETNDNRK AP-CF001GE3FR-ETNRK AP-CF001GE3FR-NDNRK AP-CF001GE3FR-NRK APCF001GH4FR-ETNDNRK AP-CF001GH4FR-ETNRK AP-CF001GH4FR-NDNRK AP-CF001GH4FR-NRK APCF002GE3FR-ETNDNRK AP-CF002GE3FR-ETNRK AP-CF002GE3FR-NDNRK AP-CF002GE3FR-NRK APCF002GH4FR-ETNDNRK AP-CF002GH4FR-ETNRK AP-CF002GH4FR-NDNRK AP-CF002GH4FR-NRK APCF004GE3FR-ETNDNRK AP-CF004GE3FR-ETNRK AP-CF004GE3FR-NDNRK AP-CF004GE3FR-NRK APCF004GH4FR-ETNDNRK AP-CF004GH4FR-ETNRK AP-CF004GH4FR-NDNRK AP-CF004GH4FR-NRK APCF008GE3FR-ETNDNRK AP-CF008GE3FR-ETNRK AP-CF008GE3FR-NDNRK AP-CF008GE3FR-NRK APCF008GH4FR-ETNDNRK AP-CF008GH4FR-ETNRK AP-CF008GH4FR-NDNRK AP-CF128ME3ER-ETNDNRK APCF128ME3ER-ETNRK AP-CF128ME3ER-NDNRK AP-CF128ME3ER-NRK AP-CF128MH4ER-ETNDNRK APCF128MH4ER-ETNRK AP-CF128MH4ER-NDNRK AP-CF128MH4ER-NRK AP-CF256ME3FR-NDNRK APCF256ME3FR-NRK AP-CF256MH4FR-ETNDNRK AP-CF256MH4FR-ETNRK AP-CF256MH4FR-NDNRK APCF256MH4FR-NRK AP-CF512ME3FR-ETNDNRK AP-CF512ME3FR-ETNRK AP-CF512ME3FR-NDNRK APCF512ME3FR-NRK AP-CF512MH4FR-ETNDNRK AP-CF512MH4FR-ETNRK AP-CF512MH4FR-NDNRK APCF512MH4FR-NRK